Transmitting / receiving device of a participant station of a serial bus system and method of communication by differential signals in a serial bus system

Abstract

Title: Transmitting / receiving device for a participant station of a serial bus system and method for communication by differential signals in a serial bus system The transmitting / receiving device (22B) has a transmitting / receiving block (220) for sending a digital transmitting signal in the form of an analog differential signal (CAN_H, CAN_L) on a bus (40) in order to send a message to at least one other participant station and / or to receive an analog signal (CAN_H, CAN_L, VDIF) from the bus (40), a transformer block (225) for providing a voltage as voltage supply for the transmitting / receiving block and a terminal (43) for an external voltage source (25), the transformer block (225) is connected between the terminal (43) and the transmitting / receiving block (220) and is designed to transform a supply voltage applied to the terminal (43) into a voltage (U_A) which has a higher value than the voltage applied to terminal (43).Figure for abstract: Fig. 10.

Description

Title of the invention: Transmitting / receiving device of a participant station of a serial bus system and method of communication by differential signals in a serial bus system

[0001] The present invention relates to a transmitting / receiving device of a participant station of a serial bus system and a method of communication by differential signals in a serial bus system. State of the art

[0002] For communication in serial bus systems by differential signals, for example, CAN bus systems are used. Nowadays, Classical CAN and / or CAN FD are used for communication of devices in vehicles and / or other technical devices, both of which are standardized in the international standard ISO11898-1:2015. The devices form participant stations on the bus, which are also called nodes. Each participant station has at least one transmitting / receiving device, also called a transmitter / receiver.

[0003] CAN FD is now often used at data bit rates of 2 Mbit / s and at arbitration bit rates of 500 kbit / s. So-called CAN SIC transmitter / receiver devices make it possible to use CAN FD with up to 8 Mbit / s. For higher data rates, nowadays up to 20 Mbit / s, CAN XL is currently available.

[0004] Nowadays in CAN bus systems a voltage source of Vcc = 5 V is used for the transmitting / receiving devices (transceiver) in order to produce the different voltage levels for the differential signals on the bus. The signals indicate the data to be exchanged serially.

[0005] In order to reduce costs, it is considered to use a voltage source of Vcc = 3.3 V for the transmitting / receiving devices. Such a lowering of the supply voltage would be advantageous, since the voltage of 3.3 V is used in many micro-control units today. In addition, many other modules could also be powered by this voltage.

[0006] The problem, however, is that there are already a number of devices that can be used on the CAN bus with a 5 V voltage supply. Lowering the supply voltage from 5 V to 3.3 V therefore only offers the desired advantage if not all devices that can be used on the CAN bus with a 5 V voltage supply have to be replaced. In particular, mixed operation on the bus must be possible. 5 V participant stations (5 V node) and 3.3V participants (3.3V nodes) must be able to communicate in any number simultaneously on a bus.

[0007] It must be taken into account in this respect that the current CAN bus has, due to the differential CAN_H, CAN_L signals, on average a voltage of Vcc / 2, i.e. 2.5 V. This is achieved by the fact that each bus participant station strives via a standardized resistance network, by means of a current source, to maintain the bus more or less exactly at 2.5 V. The bus voltage substantially follows the lowest node voltage (voltage at the participant station), thus typically being slightly lower than 2.5 V.

[0008] When transmitting, a CAN participant station (node) can connect its transmitting / receiving device exactly between a dominant state and a recessive state. For the dominant state, it excites the CAN_H level to about 3.5 V (Vcc-diode voltage losses) and the CAN_L level to about 1.5 V. The difference between the CAN_H level and the CAN_L level is then in a range of 2 V. A minimum of 1.5 V is required by the international standard ISO11898-1:2015. The transition from the recessive state to the dominant state or vice versa is carried out as symmetrically as possible around the virtual line 0, which is at Vcc / 2. The sum of the CAN_H and CAN_L levels remains as much as possible at 5 V.

[0009] A serious problem is that small deviations in the mV range result in already significant electromagnetic emissions, which cause EMV disturbances (EMV = electromagnetic compatibility) of other electrical devices. There are therefore maximum permissible electromagnetic emission requirements, which must be met by each transmitting / receiving device (transmitter / receiver). But these requirements on electromagnetic emissions represent a very big challenge.

[0010] The challenges in mixed operation are all the greater when there is on the bus at least one participant station having a transmitting / receiving device (transmitter / receiver), which in the dominant state excites other voltage levels for CAN_H and CAN_L than transmitting / receiving devices (transmitter / receiver) of other participant stations. The reasons for this are as follows.

[0011] A 3.3 V CAN bus operates exactly like the 5 V CAN bus except that the voltages on the bus are different. A 3.3 V node (participant station) can, for the dominant state on the bus, bring the CAN_H signal to approximately 3 V and the CAN_L signal significantly below 1 V by eliminating the voltage of a diode of the transmitting / receiving device (transmitter / receiver) in circuit technology. The specified minimum level difference of 1.5 V can thus be exceeded even for a 3.3 V CAN bus system.

[0012] A peculiarity in the mixed operation is that a 5 V node puts the bus on 2.5 V in the recessive phase, while a 3 V node aims on the bus about 1.65 V. By raising the CAN_L voltage in the CAN to 3.3 V in the direction of 1 V, the voltage in the recessive state can be raised to about 1.9 V. But there remains a difference of about 500 to 600 mV between the 5 V node and the 3.3 V node. In a configuration of this kind, the bus takes any voltage between 1.9 V and 2.5 V and it constantly passes a current in the directions of the 3.3 V node, but which is in the range below the microampere.

[0013] If then however a participant station (node) starts to transmit and goes into the dominant state, the participant station (node) takes the operation not of "its" zero line, but of the mixed operation. As a result the sum of the levels of CAN_H and CAN_L changes during switching and again during reconnection.

[0014] This predictably leads to large EMV emissions. Mixed operation is therefore not possible so simply. Statement of the invention

[0015] The present invention therefore aims at a transmission / reception device for a participant station of a serial bus system and a method of communication by differential signals in a serial bus system, which solve the problems mentioned above. It is sought in particular that a transmission / reception device of a participant station of a serial bus system and a method of communication by differential signals in a serial bus system are as uncomplicated as possible and therefore inexpensive and allow reliable communication as much as possible without error and with little transmission on a bus to which transmission / reception devices can also be connected, which produce on the bus the voltage level other than the transmission / reception device given by the invention.

[0016] This is achieved by a transmitting / receiving device for a participant station of a serial bus system comprising a transmitting / receiving device of a participant station of a serial bus system, comprising a transmitting / receiving block for transmitting a digital transmit signal as an analog differential signal on a bus of the bus system, in order to send a message to at least one other participant station of the bus system and / or to receive an analog signal from the bus, a transformer block for providing a voltage as a voltage supply to the transmitting / receiving block and a terminal for an external voltage source, in which the transformer block is connected between the terminal for the external voltage source and the transmitting / receiving block and in which the transformer block is designed to transforming a supply voltage applied to the terminal into a voltage, which has a higher voltage value than the supply voltage applied to the terminal.

[0017] The transmitting / receiving device can, by means of the transformation block, transform a voltage, which is given by an external voltage source for the voltage supply, into a voltage having another voltage value. A transmitting / receiving block, by means of which the transmitting / receiving device is connected to the bus, can therefore be designed for a voltage supply having a voltage value other than that given by the external voltage supply.

[0018] Thus, for example, the described transmitting / receiving device can be supplied with a voltage of approximately 3.3 V, at least 3.0 V, by which a zero line of approximately 1.9 V can be produced for differential signals on the bus. The described transmitting / receiving device can, however, use a transmitting / receiving block which, based on a voltage supply of approximately 5.0 V, can produce a zero line of approximately 2.5 V for differential signals on the bus.

[0019] The described transmitting / receiving device thus solves the problem that even conventional transmitting / receiving blocks can be excited in a system, which only provides an external voltage supply having a voltage of about 3.3 V, at least 3.0 V.

[0020] The described transmitting / receiving device ensures that the zero line on the bus is set to the level required in the bus system or to be used before the transmission of a dominant state. This applies, of course, not only to the zero line before the transmission of a dominant state, but also between such states. Emissions, which pose a problem with regard to electromagnetic compatibility (EMC), can thus be significantly reduced in the phase, and in the best case minimized, in which the participant station, more precisely its transmitting / receiving device, transmits.

[0021] The described transmitting / receiving device thus makes possible in a system having a voltage supply with a voltage of approximately 3.3 V, at least 3.0 V, a mixed operation of transmitting / receiving devices, which can be excited at different voltages, in particular of transmitting / receiving devices at 3.3 V and transmitting / receiving blocks at 5 V or transmitting / receiving devices at 5 V.

[0022] It follows that the described transmitting / receiving device offers resource conservation and cost savings for the bus system and yet makes possible low-transmission and error-free operation of the bus system.

[0023] The described transmitting / receiving device can thus, overall, even at a voltage supply of approximately 3.3 V, not only realize communication in the bus system between other transmitting / receiving devices at 5 V with the (high) bit rates required for the respective communication standard, but also contribute also that the bit rate that can be transmitted is not lowered by errors in communication.

[0024] The supply voltage applied to the terminal may be a direct voltage.

[0025] Optionally, the supply voltage applied to the terminal is a voltage having a voltage value of about 3.3 V, at least 3.0 V, wherein the voltage given by the transformation block is optionally a voltage having a voltage value of about 5.0 V.

[0026] According to an exemplary embodiment, the transformation block has a first and a second transistor, the drain terminals of which are connected to each other and a first and a second diode, which are connected in series between an input of the transformation block and its output, in which the source terminal of the first transistor is connected to the anode of the first diode, in which to the cathode of the first diode is connected a first capacitor, which is connected by its other terminal to the drain terminals of the first and second transistor and in which to the cathode of the second diode is connected a capacitor, which by its other terminal is connected to the source terminal of the second transistor and to a ground terminal.

[0027] The transmitting / receiving device may further have a clock block for controlling the transformation block by a clock signal for transforming the supply voltage applied to the terminal into the voltage, which has a higher voltage value than the supply voltage applied to the terminal.

[0028] It is also possible to consider that the gate terminals of the first and second transistors are connected.

[0029] The clock block is connected to the gate terminals of the first and second transistors, in order to control the first and second transistors by the clock signal.

[0030] According to another exemplary embodiment, the transformation block further has a third and a fourth transistor, in which the third transistor shunts the first diode and in which the fourth transistor shunts the second diode.

[0031] In one embodiment, the transmit / receive block, the transformation block, the clock block and the terminal for an external voltage source are arranged monolithically on a semiconductor chip.

[0032] According to an exemplary embodiment, the transmitting / receiving device further has a first adjustment block for adjusting the voltage ripple given by the transformation block to a minimum value.

[0033] According to yet another embodiment, the transmission / reception device further has a second adjustment block for adjusting to a voltage value determined in advance the voltage (U_A) given by the transformation block (225).

[0034] Optionally the second adjustment block has a transformer, a capacitor and an operational amplifier, in which the transistor is connected between the output of the transformer block and the transmission / reception block, in which the output of the operational amplifier is connected to the gate terminal of the transistor and in which the capacitor is connected by one of its terminals to the drain terminal of the transistor and by its other terminal to a ground terminal.

[0035] The transmitting / receiving device may be configured to produce the analog differential signal in a first phase of communication of the message by a physical layer other than in a second phase of communication.

[0036] The transmitting / receiving device described above may be part of a participant station in a serial bus system, which further has a communication control device for controlling a communication in the serial bus system and for generating the transmission signal, in which the participant station is configured for communication in a serial bus system, in which at least occasionally exclusive and collision-free access of a participant station to the bus of the bus system is ensured.

[0037] Optionally, the bus system has a bus and at least two participant stations, which communicate via the bus so as to be able to communicate with each other in series and at least one of the participant stations is a participant station described above.

[0038] The above-mentioned problem is further solved by a method for communication by differential signals in a serial bus system according to the invention. This is a method for communication by differential signals in a serial bus system, in which the method is carried out by a transmitting / receiving device of a participant station of the serial bus system, which has a transmitting / receiving block, a transformer block and a terminal for an external voltage source, in which the transformer block is connected between the terminal for the external voltage source and the transmitting / receiving block and in which the method has steps, applying, by the transformer block, a voltage as a voltage supply to the transmitting / receiving block and sending a digital transmitting signal as an analog differential signal on a bus of the bus system using the voltage given by the transformer block,in order to send a message to at least one other participant station of the bus system and / or receiving an analog signal from the bus using the voltage given by the transformation block, wherein the transformation block is configured to transform a supply voltage applying to the terminal into a voltage which has a higher voltage value than the supply voltage applying to the terminal. The method provides the , same advantages as those mentioned previously about the transmitting / receiving device.

[0039] Other possible implementations of the invention also include combinations which have not been explicitly mentioned of features or embodiments described in the following with reference to the exemplary embodiments. The person skilled in the art will add individual facets as improvements or supplements to the respective basic form of the invention. Description of the drawings

[0040] The invention will be explained in a more precise manner with reference to the attached drawing and with the aid of exemplary embodiments. In the drawing:

[0041] [Fig. 1] is a block diagram of a bus system according to a first exemplary embodiment;

[0042] [Fig.2] is a diagram illustrating the structure of a message, which is sent from a first participant station of the bus system according to the first exemplary embodiment;

[0043] [Fig. 3] is a time-dependent curve of a digital transmission signal in operation of the bus system in the first and / or second participant station, which is connected to at least one first participant station on the same bus of the bus system;

[0044] [Fig.4] is a curve as a function of time of CAN_H and CAN_L bus signals at the second participant station according to the first embodiment example;

[0045] [Fig.5] is a curve as a function of time of a differential VDIFF voltage of the CAN_H and CAN_L bus signals at the first and second participant stations according to the first exemplary embodiment;

[0046] [Fig. 6] is a time-dependent curve of a digital reception signal that the first or second participant station produces from a signal received from the bus, which is based on the transmission signal of [Fig. 3];

[0047] [Fig.7] is a time-dependent curve of CAN_H and CAN_L bus signals, which can be produced on the bus by the first participant station according to the first embodiment example from the transmission signal of [Fig.3];

[0048] [Fig.8] is an example of a time-dependent curve of a digital transmission signal, which is to be transformed in an arbitration phase (SIC operating type of a transmission module) into bus signals CAN_H, CAN_L for a bus of the bus system of [Fig.l];

[0049] [Fig.9] is the time curve of the CAN_H, CAN_L bus signals when changing between a recessive bus state and a dominant bus state and back in the recessive bus state, which are sent to the bus in the arbitration phase (SIC operation type) based on the transmit signal of [Fig.8];

[0050] [Fig. 10] is a diagram of a transmission module for a participant station of the bus system according to the first embodiment example;

[0051] [Fig. 11] is a diagram of a transmitting / receiving device of a participant station of the bus system according to a second exemplary embodiment; and

[0052] [Fig. 12] is a diagram of a transmitting / receiving device of a participant station of the bus system according to a third exemplary embodiment;

[0053] [Fig. 13] is a diagram of a transmitting / receiving device of a participant station of the bus system according to a fourth exemplary embodiment.

[0054] In the figures, similar elements or elements having the same function are, unless otherwise indicated, provided with the same references.

[0055] Description of the examples of embodiment

[0056] [Fig.l] represents a bus system 1, which can be for example at least in places, a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can find application in a vehicle, in particular in a motor vehicle, an airplane, etc., or in a hospital, etc.

[0057] Although the bus system 1 is described in the following using CAN bus systems, the bus system 1 is not limited to CAN bus systems.

[0058] In [Fig.l] the bus system 1 has a plurality of participant stations 10, 20, 30, which are respectively connected to a bus 40 or to a bus line by a first bus strand 41 and by a second bus strand 42. The bus strands 41, 42 can be referred to in a CAN bus system also as CANH and CANL for conducting CAN_H, CAN_L signals on the bus 40.

[0059] Via the bus 40, messages 45, 46, 47 can be transmitted in the form of signals between the various participant stations 10, 20, 30. The participant stations 10, 20, 30 are, for example, control devices or display devices of a motor vehicle.

[0060] As shown in [Fig.l], the participant stations 10, 30 each have a communication control device 11 and a transmission / reception device 12. The transmission / reception device 12 has a transmission module 121 and a reception module 122. At least one of the participant stations 10, 20, 30 uses a supply voltage of 3.3 V, at least 3.0 V. At least one of the participant stations 10, 20, 30 uses a supply voltage of 5 V. By way of illustration, the following embodiments represent an example of a network or bus system 1, in which all the participant stations 10, 20, 30 are supplied with an electrical supply voltage of approximately 3 V, at least 3.0 V. The participant stations 10, 30 are, by way of example, configured in such a way as to send to the bus signals with an average bus voltage of 1.9 V or 2.5 V. Furthermore, the participant station 20 is designed to send signals with an average bus voltage of 2.5 V to the bus. Alternatively, any other possibility can be considered.

[0061] The participant station 20 has a communication control device 21 and a transmission / reception device 22. The transmission / reception device 22 has a transmission module 221 and a reception module 222.

[0062] The transmitting / receiving devices 12 of the participant stations 10, 30 and the transmitting / receiving device 22 of the participant station 20 are respectively connected directly to the bus 40, even if this is not shown in [Fig.l].

[0063] The communication control devices 11, 21 respectively serve to control a communication of the respective participant station 10, 20, 30 via the bus 40 with at least one other participant station among the participant stations 10, 20, 30, which are connected to the bus 40.

[0064] The communication control device 11 creates and reads first messages 45, 47, which are, for example, modified CAN messages 45, 47. In this respect, the modified CAN messages 45, 47 are created, for example, on the basis of the CAN XL format. The transmitting / receiving device 12 serves to transmit and receive messages 45, 47 via the bus 40. The transmitting module 121 receives a digital transmit TxD signal created by the communication control device 11 for one of the messages 45, 47 and transforms this into signals on the bus 40 as described in more detail with reference to [Fig. 3], [Fig. 4] and [Fig. 7]. The digital transmit TxD signal may be, at least occasionally or in some places, a pulse-width modulated signal. The receiving module 122 receives signals sent on the bus 40 in accordance with messages 45 to 47 and produces a digital receive RxD signal, an example of which is shown in [Fig.6].The receiving module 122 sends the receiving RxD signal to the communication control device 11.

[0065] Furthermore, the communication control device 11 may optionally be configured for the production and reading of second messages 46, which are, for example, CAN FD messages 46 or CAN-SIC messages. The transmission / reception device 12 may be configured accordingly.

[0066] The communication control device 21 can, like a conventional CAN control unit, be implemented according to ISO 11898-1:2015, i.e. as a Classical CAN control unit tolerant to CAN FD or a CAN FD control unit or a CAN SIC control unit. The communication control device 21 produces and reads second messages 46, for example CAN FD messages or CAN SIC messages. The transmitting / receiving device 22 serves to send and receive the messages 46 via the bus 40. The transmitting module 221 receives a digital transmit signal TxD produced by the communication control device 21. communication and transforms this into signals for a message 46 on the bus 40 as described in more detail with reference to [Fig. 3] and [Fig. 4]. The receiving module 222 receives signals sent on the bus 40 in accordance with messages 45 to 47 and thus produces a digital receive signal RxD, an example of which is shown in [Fig. 6]. The transmitting / receiving device 22 is implemented as a conventional CAN FD transceiver or a conventional CAN-SIC transceiver, if necessary.

[0067] For sending messages 45, 46, 47 by CAN SIC or CAN XL, proven properties are taken into account, which provide the robustness and ease of use of CAN and CAN FD, in particular a frame structure with identifier and arbitration according to the known CSMA / CR method, as will be described in more detail below.

[0068] Via the two participant stations 10, 30, it is possible to carry out training and then transmission of messages 45, 46, 47 having different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format as well as the reception of messages 45, 46, 47 of this type. This will be described in more detail in the following for a message 45.

[0069] [Fig.2] represents for message 45 a frame 450, which is in particular a CAN XL frame as given by the communication control device 11 to the transmitting / receiving device 12 for sending on the bus 40. In this regard, the communication control device 11 produces the frame 450 in the present embodiment as compatible with CAN FD. Alternatively, the frame 450 is compatible with any standard to be followed for CAN FD.

[0070] According to [Fig. 2] the frame 450 for CAN communication on the bus 40 is subdivided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start SOF bit, an arbitration field 453, a control field 454, a first switching field 455, a data field 456, a checksum field 457, a second switching field 458 and an end of frame field 459, in which there is an EOF marking (EOF = End of Frame). The checksum field 457, the second switching field 458 and the end-of-frame field 459 form an end-of-frame phase 457, 458, 459 of the frame 450. In the end-of-frame field 459 there may be a confirmation field (ACK = Acknowledge), which contains at least one ACK bit and which is not shown in the figures.

[0071] Unlike frame 450 of [Fig.2] there is no switching field 455, 458 in a CAN FD frame, which the participant station 20 uses for the second message 46.

[0072] For all the CAN versions mentioned above, it is ensured that in the arbitration phase 451, by means of an identifier (ID) in the bit-by-bit arbitration field 453 between the participant stations 10, 20, 30, the participant station 10, 20, 30 wishing to send the message 45, 46, 47 having the highest priority and therefore for the immediately following time obtains exclusive access to the bus 40 of the bus system 1 for sending connected data in phase 452. In the arbitration phase 451, a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0073] During phase 451, the known CSMA / CR method is used, which allows simultaneous access of the participant stations 10, 20, 30 to the bus 40, without the message 45, 46, 47 having the highest priority being disturbed. In this way, further bus participant stations 10, 20, 30 can be added to the bus system 1 in a relatively simple manner, which is very advantageous.

[0074] The CSMA / CR method results in the bus 40 being given so-called recessive states, which can be overridden by other participant stations 10, 20, 30 having dominant levels or dominant states on the bus 40. In the recessive state, high-ohmic relationships prevail at the various participant stations 10, 20, 30, which, in combination with the bus circuitry interference, results in rather long time constants. This results in a limitation of the maximum bit rate of the current CAN-FD physical layer to currently about 2 megabits per second in actual vehicle use.

[0075] At the end of the arbitration phase 451, we move to the data phase 452. In CAN XL, switching is carried out using the first switching field 455 of [Fig.2],

[0076] In the data phase 452, the useful data of the CAN-XL frame 450 and respectively the message 45 composed of the data field 456 as well as the checksum field 457 and a part of the second switching field 458 are sent in CAN XL alongside a part of the first switching field 455. In CAN FD, the useful data of the CAN-FD frame and respectively the message 46 composed of the data field 456 as well as the checksum field 457 are sent.

[0077] At the end of the data phase 452, we return to the arbitration phase 451. In CAN XL, switching is carried out using the second switching field 458 of [Fig.2],

[0078] A transmitter of message 45 begins a transmission of bits of phase 452 of data on bus 40, only if and only if the station 10 of participant as transmitter won the arbitration and participant station 10 as transmitter thus has exclusive access to bus 40 of bus system 1 for the transmission.

[0079] In the end-of-frame EOF field, a bit sequence is provided, which marks the end of frame 450. The bit sequence of the end-of-frame (EOF) field thus serves to characterize the end of frame 450. The end-of-frame (EOF) field serves to send a number of 7 recessive bits at the end of frame 450. Together with an ACK delimiter possibly present in the confirmation field not shown, a number of 8 recessive bits is sent at the end of frame 450. The mentioned bit sequence of recessive bits is a bit sequence which cannot occur within frame 450. The end of frame 450 can thus be identified reliably by the participant stations 10, 30.

[0080] The participant station 10 carries out, from an instant or time tl, starting more precisely with time tl, for a duration T_M1 of time, a detection of the bus potential or the bus voltage, which applies to the bus 40. The detection is carried out after the occurrence of an event EL. The event El is that a predetermined number of recessive bits directly following one another has appeared at the end of the frame 450, more precisely in the end field (EOF).

[0081] Optionally, the participant station can, from a time t2, starting more precisely at time t2, for a duration T_M2, perform a detection of the bus potential or the bus voltage, which applies to the bus 40. The detection is performed after an event E2 has occurred. The event E2 is that at the end of the first communication phase the participant station is determined, which has, in the following second communication phase, exclusive access to the bus and thus can send its message.

[0082] This detection or these detections or this measurement or these measurements are described in the following using the figures.

[0083] After the end field (EOF), which has 7 bits, comes in frame 450 an Inter Frame Space (IFS), which is not shown in [Fig.2]. This Inter Frame Space (IFS) is conformed in CAN FD according to ISO 11898-1:2015. The Inter Frame Space (IFS) has at least 3 bits.

[0084] Furthermore the fields and bits mentioned are known from ISO 11898-1:2015 and will therefore not be described here in a more precise manner.

[0085] The participant stations 10, 30 thus use in the arbitration phase 451 as the first communication phase in part, in particular up to the FDF bit (inclusive), a known format of CAN / CAN-FD according to ISO 11898-1:2015. It is possible, however, compared to CAN or CAN FD in the data phase 452 as the second communication phase, to have an increase in the net data transmission rate, in particular up to beyond 10 megabits per second. besides an increase in the size of the useful data per frame, in particular up to about 2kbytes or some other value.

[0086] [Fig. 3], [Fig. 5], [Fig. 6] illustrate by way of example the signals, which are produced at the participant stations 10, 20, 30, when the bus system 1 is in operation. [Fig. 4] illustrates by way of example the signals, which are sent from the participant stations 20 to the bus 40, when the bus system 1 is in operation. As already mentioned, the participant station 20 produces at a supply voltage of approximately 3.3 V, at least 3.0 V, an average bus voltage of approximately 2.5 V.

[0087] [Fig. 7] shows the bus signals, which each of the participant stations 10, 30 can produce instead of the bus signals, which are shown in [Fig. 4]. As already mentioned, the participant stations 10, 30 can produce the signals of [Fig. 7], i.e. with an average bus voltage Vcm of approximately 1.9 V as shown in [Fig. 7]. Furthermore, the participant stations 10, 30 can be shaped to produce alternating signals, which are known from CAN XL.

[0088] When the bus system 1 is in operation, each of the modules 121, 221 of [Fig. 1] can transform a transmission TxD signal of the communication control device 11, which belongs to it, in series into corresponding CAN_H, CAN_L signals for CAN or CAN FD for the bus strands 41, 42 and send these signals to the terminals for CAN_H and CAN_L on the bus 40. The respective communication control device 11, 21 sends the transmission TxD signal of [Fig. 3] as a function of time t (serial) to the transmission modules 121, 221 belonging to it, as shown in [Fig. 1].

[0089] As shown exemplarily in [Fig. 3], the transmit TxD signal has voltage states H (High = High) and L (Low = Low) with a corresponding voltage U. The various bits of the TxD signal have a bit time t_bt 1, as shown in [Fig. 3] for the arbitration phase 451. In CAN FD and CAN XL the bits of the TxD signal can be sent in the data phase 452 with a shorter bit time t_bt2, as shown in [Fig. 4].

[0090] The sequence of states H, L of the transmit signal TxD of [Fig.3] and states 401, 402, which follow for the signals CAN_H, CAN_L in [Fig.4] as well as the resulting curve of the voltage VDIFF of [Fig.5] only serves to illustrate the operation of the participant station 10. The sequence of data states for the bus states 401, 402 can be chosen as required.

[0091] Following the example of [Fig.4] the signals CAN_H and CAN_L have at least in the arbitration phase 451 the dominant and recessive bus level or bus states 401, 402, as is known from CAN. Since the participant station 20, the embodiment of which is shown in the following in [Fig.10], excites for the dominant state 401 the CAN_H level to about 3.5 V and the CAN_L level to about 1.5 V, as shown in [Fig.4], the recessive 402 state settles at 2.5 V, which is equal to the average bus voltage Vcm = 2.5 V.

[0092] As shown in [Fig.5] for the difference voltage VDIFF = CAN_H -CAN_L on the bus 40, the difference between the CAN_H level and the CAN_L level for the dominant state 401 is then in a range of 2 V.

[0093] The receiving modules 122, 222 form, from the signals CAN_H and CAN_L, received from the bus 40, which are shown in [Fig. 4], and respectively from the difference voltage VDIFF of [Fig. 5], a receiving signal RxD. For the production of the digital receiving signal RxD of [Fig. 6], the respective receiving module 122, 222 uses the signal VDIFF received from the bus 40 or at least one of the signals CAN_H, CAN_L having reception thresholds as is known. The receiving signal RxD is shown in [Fig. 6] without travel time delay. The receiving module 122 routes this receiving signal RxD to the communication control device 11, 21 belonging to it, as shown in [Fig. 1].

[0094] In contrast to [Fig. 4], [Fig. 7] shows the signals CAN_H and CAN_L, which the participant stations 10, 30 can produce as an alternative to the known signals CAN XL in the arbitration phase 451 and the data phase 452 on the bus 40. At least in the arbitration phase 451, the dominant and recessive bus levels or bus states 401, 402 are used as already shown in [Fig. 4]. If the participant stations 10, 30 are to produce an average bus voltage of 1.9 V, they excite the CAN_H level to about 2.9 V and the CAN_L level to about 0.9 V for the dominant state 401 as shown in [Fig. 7]. The recessive 402 state is established at 1.9 V, which is equal to the average bus voltage Vcm = 1.9 V. In the data phase 452 it can be used for CAN XL a physical 452_P layer other than the physical 451_P layer in the arbitration phase 451. It follows that the CAN_H levels are excited to values ​​for the states L0, Ll, as shown in [Fig.7]. In the arbitration phase 451 a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0095] The transmission module 121 produces, for the transmission signal TxD of [Fig.3], the signals CAN_H, CAN_L of [Fig.7] for the bus strands 41, 42, so that the state L0 forms a state LW (Low = Low). In addition, the state L1 is formed for a state HI (High = High).

[0096] If the participant stations 10, 30 are to produce an average bus voltage of 2.5 V, as is known from CAN XL, the signals of [Fig. 7] have an average bus voltage Vcm of approximately 2.5 V as well as voltage values ​​for the signals CAN_H, CAN_L in the arbitration phase 451, as shown in [Fig. 4] and described previously and in phase 452 data values ​​of 1 V and -1 V for states LO, Ll.

[0097] To increase the bit rate for CAN XL, the transmitting / receiving devices 12 can be configured for CAN SIC.

[0098] As shown more precisely in [Fig.8] and [Fig.9], the transmit module 121 produces in CAN SIC for the transmit signal TxD of [Fig.8] the signals CAN_H, CAN_L according to [Fig.9] for the bus strands 41, 42 with an average bus voltage Vcm_sic = 1.9 V and in such a way that, in addition, there is a state 403 (sic). Alternatively, an average bus voltage Vcm of approximately 2.5 V and voltage values ​​for the signals CAN_H, CAN_L are produced in the arbitration phase 451, as shown in [Fig.4].

[0099] State 403 (SIC) may have a different length as shown with state 403_0 (sic) when transitioning from state 402 (rec) to state 401 (dom) and with state 403_l (sic) when transitioning from state 401 (dom) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_l (sic). To produce signals according to [Fig.9], the transmission module 121 is put into a SIC operating type (SIC-Mode).

[0100] The transition from the short sic 403_0 state in the CiA610-3 is not required and the state depends on the type of implementation. The duration in time of the "long" 403_l (sic) state is specified for CAN-SIC as well as also for the SIC operation type in CAN-XL as t_sic < 530ns, starting with the rising edge of the transmit TxD signal of [Fig.5].

[0101] The participant station 10 carries out, from the instant or a time t3, more precisely starting with the instant t3, after the occurrence of an event E3, for a duration T_M3, a detection of the bus potential or the bus voltage, which applies to the bus 40. The event E3 is, that one leaves the state 401 (dom) and respectively one passes from the state 401 (dom) to the state 403 (sic). Depending on the result of the detection, the participant station 10 then sets itself to send the signals CAN_H, CAN_L, with an average bus voltage Vcm = 1.9 V or Vcm = 2.5 V on the bus 40.

[0102] The transmission module 121 must adapt as well as possible in the "long" state 403_l (sic) the impedance between the bus strands 41 (CANH) and 42 (CANL) to the inductance Zw characteristic of the bus line used. In this respect, we have Zw = 1000 Ohm or 1200 hm. This adaptation prevents reflections and thus allows operation at fairly high bit rates. For the sake of simplification, we will always refer to the state 403 (sic) or the sic state 403 in the following.

[0103] [Fig. 10] shows the transmitting / receiving device 22 of the participant station 20 of [Fig.l] to the bus 40 in more detail. The transmitting / receiving device 22 has a transmitting / receiving block 220, which has the transmitting module 221 and the receiving module 222. In addition, the transmitting / receiving device 22 has a transformation block 225 and a clock block 227.

[0104] The transmitting / receiving device 22 has a terminal 43 for a voltage supply VCC and a terminal 44 for ground GND or CAN-GND. Terminal 44 is connected to a system ground S_GND. In addition, the transmitting / receiving device 22 has terminals for lines 41, 42 of the bus 40. The transmitting / receiving device 22 has further terminals, such as terminals TXD for a transmit signal, RXD for a receive signal, VIO, STB even if these are not shown in [Fig. 10] for the sake of simplification.

[0105] The transmission / reception block 220 has an input VCC2 for an output voltage U_A of the transformation block 225.

[0106] In [Fig. 10], a voltage source 15 is connected between the terminals 43, 44. The voltage source 15 is arranged outside the transmitting / receiving device 22. The voltage source 25 may be a part of the participant station 20. The voltage source 25 supplies the transmitting / receiving device 22 with a direct voltage, which has a voltage value of approximately 3.3 V, but at least 3.0 V.

[0107] The transmission / reception device 22 gives, in transmission operation, at its output differential voltages U_H = 3.5 V and U_L = 1.5 V for the signals CAN_H, CAN_L as described previously with reference to [Fig.4].

[0108] According to [Fig.10], the transformation block 225 has an electrical circuit two diodes D1, D2, two transistors TRI, TR2 and two capacitors Cl, C2. The capacitor Cl has the function of a pump capacitor. The capacitor C2 has the function of an intermediate accumulator or buffer accumulator. The capacitor C2 can also be designated as a buffer accumulator capacitor. At the input of the transformation block 225 an electrical voltage U_IN is applied. At the output of the transformation block 225 an electrical voltage U_A is given.

[0109] The transistors TRI, TR2 are respectively CMOS transistors. The transistor TRI is in particular an NMOS transistor. The transistor TR2 is in particular a PMOS transistor. The abbreviation "CMOS" designates a semiconductor element, in which both a p-channel and an n-channel MOSFET are used on a common substrate. The abbreviation CMOS is the English designation "complementary metal-oxide semiconductor" which translates to "complementing / complementing metal-oxide-semiconductor". The abbreviation "MOSFET" designates a metal-oxide field effect transistor.

[0110] The clock generator 227 is connected to the gate terminals of the two transistors TRI, TR2. The input of the transformation block 225 is connected to the source terminal of the first transistor TRI and to the anode of the first diode DL. The drain terminal of the first transistor TRI is connected to the drain terminal of the second transistor TR2. The source terminal of the second transistor TR2 is connected to the ground terminal 44 GND. The cathode of the first diode DI is connected to the anode of the second diode D2 and to one terminal of the first capacitor CL. The other terminal of capacitor Cl is connected to the drain terminals of the first and second transistor TR2. The cathode of the second diode DI is connected to the output of the transformer block 225 and to one terminal of the second capacitor C2. The other terminal of the second capacitor C2 is connected to the ground terminal 43 GND and to the source terminal of the second transistor TR2. The diodes DI and D2 are connected in series between the input and output of the transformer block 225.

[0111] The clock generator 227 gives a clock signal CLK to the gate terminals of the two transistors TRI, TR2, in order to activate the transformation block 225. The clock signal CLK is set for example in a fixed manner.

[0112] The transmitting / receiving device 22 is a closed device in itself, in which a transmitting / receiving block 222, which is designed for a voltage supply of typically 5 V at its terminal VCC2, is monolithically supplemented by the transformer block 225 and by the clock block 227. The transformer block 225 is connected upstream of the transmitting / receiving block 222. The transformer block 225 works as a charge pump, in particular as a single-stage charge pump. For a charge pump of this type, the following equations (1) to (3) apply:

[0113] U_A0 = (U_IN - U_D) * 2 ...(1)

[0114] U_A = U_A0 - R_i * I_L .. .(2)

[0115] R_i = 1 / (f*Cl) ...(3)

[0116] U_A0 is in this respect the output voltage of the uncharged charge pump U_IN, U_IN the input voltage of the uncharged charge pump U_D, U_D the voltage across the diodes DI and D2, U_A the output voltage of the charged charge pump R_i, R_i the internal resistance of the charge pump, I_L the electric current flowing into the charge pump load, in other words, the electric current, which is drawn by the charged charge pump, f the frequency of the clock CLK and Cl the value of the capacitance Cl or the capacitance of the pump.

[0117] It is thus possible to apply exclusively the voltage at 3.3 V to terminal 43 (VCC). This voltage is then transformed by the transformation block 225 mounted on the same chip into a higher voltage and is sent to terminal VCC2 for the voltage supply of the transmission / reception block 222 designed for 5 V. It is thus advantageous to implement the 5 V supply in the system plane, i.e. outside the transmission / reception device 22 (transmitter / receiver). All other terminals of the transmission / reception device 22, in particular the terminals CANH, CANL, VIO, TXD, RXD, GND, STB of the block 220 having the 8 terminals behave exactly like the others terminals of block 220, which has the 8 terminals 5VCAN, CANH, CANL, VIO, TXD, RXD, GND, STB.

[0118] [Fig. 11] represents a transmission / reception device 22A according to a second example of embodiment of the participant station 20 of [Fig. 1].

[0119] The transmitting / receiving device 22A is implemented largely in the same way as the transmitting / receiving device 22 of the previous embodiment. Therefore, only the differences from the transmitting / receiving device 22 of the previous embodiment will be described in the following.

[0120] Unlike the transmission / reception device 22 of the previous embodiment, the transmission / reception device 22A of [Fig. 1 1] also has an adjustment block 228. The input of the adjustment block 228 is connected to the output of the transformation block 225. The output of the adjustment block 228 is connected to the input of the clock block 227.

[0121] The adjustment block 228 has an adjustment circuit 2281 for minimizing a ripple in the output voltage U_A of the transformation block 225. The adjustment block 228, in particular the adjustment circuit 2281, adjusts the clock frequency CLK in the clock block 227 so that the transformation block 225 has as small a ripple as possible in the output voltage U_A.

[0122] The aim of adjustment is to reduce the ripple so as to reduce the variation as a function of the load of the output voltage (see equation (2) above). By the adjustment block 228, more precisely by its adjustment circuit 2281, intervention is made in the clock block 227 so as to modify, by an adaptation of the switching frequency f, the internal resistance R_i of the transformation block 225, so that the output voltage U_A remains approximately constant.

[0123] Alternatively, the adjustment block 228, more precisely its adjustment circuit 2281, can be configured as a voltage comparator with hysteresis, which, when a first predetermined voltage value is exceeded, stops the switching frequency f and, if it falls below a second predetermined voltage level, restarts the switching frequency f. In this respect, the second predetermined voltage level (higher time level) is higher than the first predetermined voltage level (lower voltage level). The resulting ripple of the output voltage U_A is thus given by the difference between the high and low voltage level (hysteresis).

[0124] Adjusting the adjustment block 228, in particular the adjustment circuit 2281, provides an improvement in EMV behavior.

[0125] For the rest, the function of the transmission / reception device 22A is the same as that described in the previous embodiment.

[0126] [Fig. 12] represents a transmission / reception device 22B according to a third embodiment example for the participant station 20 of [Fig. 1].

[0127] The transmitting / receiving device 22B is implemented in much the same way as the transmitting / receiving device 22 of [Fig. 10]. Therefore, only the differences from the transmitting / receiving device 22 of [Fig. 10] will be described in the following.

[0128] Unlike the transmission / reception device 22 of [Fig. 10], the transmission / reception device 22B of [Fig. 12] further has an adjustment block 229. The input of the adjustment block 229 is connected to the output of the transformation block 225. The output of the adjustment block 229 is connected to the input VCC2 of the transmission / reception block 220.

[0129] The adjustment block 229 has a transistor TRR, an operational amplifier 2291 and a capacitor CR. The transistor TRR is a CMOS transistor.

[0130] The source terminal of transistor TRR is connected to the input of adjustment block 229. The gate terminal of transistor TRR is connected to the output of operational amplifier 2291 or is connected to it. The drain terminal of transistor TRR is connected to the output of adjustment block 229 and has one terminal of capacitor CR or to it. Capacitor CR is connected by its other terminal to ground terminal 44 (GND) or is connected to it. Capacitor CR is thus connected between the output of adjustment block 229 and ground terminal 44 (GND). Furthermore, operational amplifier 2291 is connected to ground terminal 44 (GND) or to it.

[0131] An input voltage UR_IN of the adjustment block 229 is equal to the output voltage U_A of the transformation block 225. A reference voltage U4 is applied to the input of the operational amplifier 2291. The adjustment block 229 gives an output voltage UR_A to the input VCC2 of the transmission / reception block 220.

[0132] The adjustment block 229 is a linear regulator, which adjusts the output voltage U_A of the transformation block 225 to a given output voltage UR_A in advance.

[0133] The output voltage U_A of the transformation block 225 can thus be set to a very precise setpoint value, in particular to 5 V, for the input VCC2 of the transmission / reception block 220.

[0134] For the rest, the function of the transmission / reception device 22B is the same as that described in the first example embodiment.

[0135] [Fig. 13] represents a transformation block 225A according to a fourth exemplary embodiment, which can be used in at least one of the transmission / reception devices 22, 22A, 22B of the preceding exemplary embodiments for the participant station 20 of [Fig. 1].

[0136] The transformation block 225A is largely made in the same way than the transformation block 225 of [Fig. 10]. Therefore, only the differences with respect to the transformation block 225 of [Fig. 10] will be described below.

[0137] The transformation block 225A further has a transformer TR3 and a transformer TR4. The source terminal of transistor TR3 is connected to the anode of diode DI. The drain terminal of transistor TR3 is connected to the cathode of diode DI. The source terminal of transistor TR4 is connected to the anode of diode D3. The drain terminal of transistor TR3 is connected to the cathode of diode DI. The gate terminal of transistor TR3 is controlled by clock generator 227 by a signal S_CTRL1. The gate terminal of transistor TR4 is controlled by clock generator 227 by a signal S_CTRL3. Transistors TR3, TR4 are respectively CMOS transistors. The signals S_CTRL1, S_CRTL2 for controlling transistors TR3 and TR4 are controlled from clock block 227 so that transistor TR3 supports the function of diode DI and transistor TR4 supports the function of diode D2.

[0138] The expression "supporting the function of diode DI" means in this specification that transistor TR3 is in the conduction state, if diode DI is biased in the forward direction in order to reduce the losses of diode DI and that transistor TR3 is in the non-conduction state, if diode DI is biased in the reverse direction. The same applies to the expression "supporting diode D2" with respect to transistor TR4 to diode D2.

[0139] In the transformation block 225A, the diodes D1, D2 are thus shunted respectively by a transistor, namely either by the transistor TR3 or by the transistor TR4. The shunting results in a higher output voltage U_A of the transformation block 225A, since the losses created by the forward voltage of the diodes D1, D2 are thus eliminated.

[0140] The circuit of [Fig. 13] can be designed using the previously mentioned equations (2) and (3) of the charge pump for example in the following way.

[0141] According to the equation (2) mentioned above, we obtain for the output voltage the unloaded charge pump: U_A0 = 3.3 V * 2 = 6.6 V, in which for the voltage across the diode D1 with the transistor TR3 in the conduction state and the diode D2 with the transistor TR4 in the conduction state of [Fig. 13], we have: Vdio=0V. If we start from an electric current flowing through the charge pump load I_L = 80mA and if we have as goal: U_A_min = 5.0 V, it follows as design goal for the inner resistor R_I:

[0142] R_i = (6.6 V - 5.0 V) / 80mA = 200hm

[0143] Switching transistors must have a switch-on resistance Ron less than 20hm, so as not to significantly worsen the internal resistance R_i of the charge pump. We thus have: switch-on resistance Ron little different from 1 / 10 of R_i.

[0144] Following the formula (3) (R_i = 1 / (f * Cl)) gives the following values ​​for the capacity Cl of the pump as a function of the switching frequency f of the charge pump:

[0145] f= 150 kHz Cl = 470 nF

[0146] f= 10 MHz Cl =5 nF

[0147] f = 50 MHz —> Cl = InF

[0148] The gate charge required for all charge pump switches is in total of approximately 400pC. We obtain for the capacitance Cl of the pump at the various switching frequencies f, the following average current absorptions I_cp_avg:

[0149] f = 150 kHz —> I_cp_avg = 50 pA

[0150] f = 10MHz —> I_cp_avg = 4 mA

[0151] f = 50MHz —> I_cp_avg = 20 mA

[0152] The capacitors C1, C2 and CR could only be integrated monolithically with an immense cost in Si surface. This is generally avoided for cost reasons. The capacitors can be made, for example, according to the following technologies in the same package with a transmitter / receiver chip, which characterizes a transmission / reception device 22 without a package (plastic or ceramic material). The technologies are Flip-Chip or Stacked-Die or Chip-to-Chip or Silicon Caps. Of course, other values ​​are possible for the design of the charge pump.

[0153] All the embodiments described above, of the transmitting / receiving devices 12, 22 of the stations 10, 20, 30 of participants of the bus system 1 and of the method implemented therein according to the exemplary embodiment or its modifications can be used individually or in all possible combinations. The following modifications can also be considered in particular.

[0154] The bus system 1 described above is described using a bus system based on the CAN protocol. The following embodiment of the bus system 1 may, however, alternatively be another type of communication network, in which the signals are transmitted in the form of differential signals.

[0155] It is advantageous, but not a mandatory prerequisite, that in the bus system 1, at least for certain periods of time, exclusive and collision-free access of a participant station 10, 20, 30 to the bus 40 is ensured.

[0156] The bus system 1 according to the exemplary embodiment and its modifications is, in particular, a bus system, in which communication can be carried out between at least two of the participant stations 10, 20, 30 according to two different CAN standards, such as for example CAN-HS or CAN FD or CAN SIC or CAN XL. The functionality of the exemplary embodiment described above can thus be used, for example, in transmitting / receiving devices 12, 22, which are to operate in a bus system of this kind.

[0157] It is possible that the transmitting / receiving device 22A of [Fig. 11] has not only an adjustment block 228, but also an adjustment block 229, as described for the transmitting / receiving device 22A of [Fig. 12].

[0158] The number and arrangement of the participant stations 10, 20, 30 in the bus system 1 according to the embodiment example and its modifications can be selected at will. In particular, there may be only participant stations 20.

[0159] It is possible in particular that the participant station 10 has a bus voltage supply of 3.3 V and that the participant station 20 has a bus voltage supply of 5.0 V. The number and arrangement of the participant stations 10, 20, 30 in such a bus system 1 can be chosen as desired, in particular there can be only participant stations 10.

[0160] Furthermore, the bus voltage supply of one of the participant stations 10, 20, 30 is not limited to 3.3 V. The bus voltage supply may have a value other than 3.3 V. In this case, the previously described principle of the bus system 1 having participant stations 10, 20, 30 can be applied in mixed operation. If necessary, said voltages of the devices 22, 22A, 22B and / or of the block 220 are adapted accordingly for this purpose.

Claims

Claims

1. Transmitting / receiving device (22; 22A; 22B) of a participant station (20; 10; 30) of a serial bus system (1), comprising a transmitting / receiving block (220) for transmitting a digital transmit signal (TxD) as an analog differential signal (CAN_H, CAN_L) on a bus (40) of the bus system (1), in order to send a message (45; 46; 47) to at least one other participant station (10; 20; 30) of the bus system (1) and / or to receive an analog signal (CAN_H, CAN_L; VDIFF) from the bus (40), a transformation block (225; 225A) for providing a voltage (U_A) as a voltage supply to the transmitting / receiving block (220) and a terminal (43) for an external source (25) voltage, in which the transformation block (225; 225A) is mounted between the terminal (43) for the external voltage source (25) and the transmission / reception block (220) and in which the block (225;225A) transformation is configured to transform a supply voltage (VCC) applied to the terminal (43) into a voltage (U_A), which has a higher voltage value than the supply voltage (VCC) applied to the terminal (43).;

2. Transmitting / receiving device (22; 22A; 22B) according to claim 1, wherein the supply voltage (VCC) applied to the terminal (43) is a direct voltage.

3. Transmitting / receiving device (22; 22A; 22B) according to claim 1 or 2, wherein the supply voltage (VCC) applied to the terminal (43) is a voltage having a voltage value of approximately 3.3 V, at least 3.0 V and wherein the voltage (U_A) given by the transformation block (225; 225A) is a voltage having a voltage value of approximately 5.0 V.

4. Transmitting / receiving device (22; 22A; 22B) according to one of the preceding claims in which the transformation block (225; 225A) has a first and a second transistor (TR1, TR2) whose drain terminals are connected to each other and a first and a second diode (Dl, D2), which are connected in series between an input of the transformation block (225; 225A) and its output, wherein the source terminal of the first transistor (TRI) is connected to the anode of the first diode (Dl), wherein to the cathode of the first diode (Dl) is connected a first capacitor (Cl), which is connected by its other terminal to the drain terminals of the first and second transistors (TRI, TR2) and wherein to the cathode of the second diode (D2) is connected a capacitor (C2), which by its other terminal is connected to the source terminal of the second transistor (TR2) and to a ground terminal (43).

5. Transmitting / receiving device (22; 22A; 22B) according to one of the preceding claims, further comprising a clock block (227) for controlling the transformation block (225) by a clock signal (CLK) for transforming the supply voltage (VCC) applied to the terminal (43) into the voltage (U_A), which has a higher voltage value than the supply voltage (VCC) applied to the terminal (43).

6. Transmitting / receiving device (22; 22A; 22B) according to claim 4 or 5, wherein the gate terminals of the first and second transistors (TR1, TR2) are connected.

7. A transmitting / receiving device (22; 22A; 22B) according to claim 5 or 6, wherein the clock block (227) is connected to the gate terminals of the first and second transistors (TRI, TR2), in order to control the first and second transistors (TRI, TR2) by the clock signal (CLK).

8. Transmitting / receiving device (22; 22A; 22B) according to one of the preceding claims, wherein the transformation block (225A) further has a third and a fourth transistor (TR3, TR4), wherein the third transistor (TR3) shunts the first diode (D1) and wherein the fourth transistor (TR3) shunts the second diode (D2).

9. Transmitting / receiving device (22; 22A; 22B) according to one of the preceding claims, in which the transmitting / receiving block (220), the transformation block (225; 225A), the block (227) clock and the strip (43) for an external voltage source (25) are arranged monolithically on a semiconductor chip.

10. Transmitting / receiving device (22A) according to one of the preceding claims, further comprising a first adjustment block (228) for adjusting to a minimum value the ripple of the voltage (U_A) given by the transformation block (225).

11. Transmitting / receiving device (22B) according to one of the preceding claims, further comprising a second adjustment block (229) for adjusting to a voltage value determined in advance the voltage (U_A) given by the transformation block (225).

12. A transmitting / receiving device (22B) according to claim 11, wherein the second adjustment block (229) has a transformer (TRR), a capacitor (CR) and an operational amplifier (2291) and wherein the transistor (TRR) is connected between the output of the transformer block (225) and the transmitting / receiving block (220), wherein the output of the operational amplifier (2291) is connected to the gate terminal of the transistor (TRR) and wherein the capacitor (CR) is connected by one of its terminals to the drain terminal of the transistor (TRR) and by its other terminal to a ground terminal (43).

13. Transmitting / receiving device (22; 22A; 22B) according to one of the preceding claims, in which the transmitting / receiving device (22; 22A; 22B) is configured to produce the analog differential signal (CAN_H, CAN_L) in a first phase (451) of communication of the message (45) by a physical layer (451_P) other than in a second phase (452) of communication.

14. A participant station (20; 10; 30) for a serial bus system (1), comprising a transmitting / receiving device (22; 22A; 22B) according to one of the preceding claims and a communication control device (21) for controlling a communication in the serial bus system (1) and for generating the transmission signal (TXD), in which the participant station (20; 10; 30) is designed for communication in a bus system (1), in which at least from time to time, exclusive collision-free access of a participant station (10, 20, 30) to the bus (40) of the bus system (1) is ensured.

15. Bus system (1) comprising a bus (40) and at least two participant stations (10, 20; 10, 30; 20, 30), which communicate with each other via the bus (40) in such a way that they can communicate with each other in series and of which at least one of the participant stations (10, 20; 10, 30; 20, 30) is a participant station (10; 30) according to one of the preceding claims.

16. Method for communication by differential signals (CAN_H, CAN_L) in a serial bus system (1), in which the method is carried out by a transmitting / receiving device (22; 22A; 22B) of a participant station (20; 10; 30) of the serial bus system (1), which has a transmitting / receiving block (220), a transformer block (225; 225A) and a terminal (43) for an external voltage source (25), in which the transformer block (225; 225A) is connected between the terminal (43) for the external voltage source (25) and the transmitting / receiving block (220) and in which the method has steps of applying, by the transformer block (225; 225A), a voltage (U_A) as a voltage supply to the block (220) transmitting / receiving and sending a digital transmission signal (TxD) as an analog differential signal (CAN_H, CAN_L) on a bus (40) of the bus system (1) using the voltage (U_A) given by the block (225;225A) transformation block, in order to send a message (45; 46; 47) to at least one other station (10; 20; 30) of participant of the bus system (1) and / or reception of an analog signal (CAN_H, CAN_L; VDIFF) of the bus (40) using the voltage (U_A) given by the transformation block (225; 225A), in which the transformation block (225; 225A) is shaped to transform a supply voltage (VCC) applying to the terminal (43) into a voltage (U_A) which has a higher voltage value than the supply voltage (VCC) applying to the terminal (43).;

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