Memory device comprising a memory cell with an optimized active area

Abstract

Memory device comprising an optimized active area memory cell. Memory device (100) comprising a memory cell having: - a first selection transistor (110) comprising an active area formed in a first semiconductor layer (134); - several interconnection levels (138, 140) superimposed on the first semiconductor layer; - a bipolar memory dot (102) disposed in one of the interconnection levels; - a second selection transistor (112) comprising an active area formed in a second semiconductor layer (136) disposed in another of the interconnection levels arranged between that including the memory dot and the first semiconductor layer; and wherein: - drain regions (114, 116) of the first and second transistors are connected to a first electrode (106) of the memory dot;- Source regions (128, 132) of the first and second transistors are connected respectively to first and second connecting elements (160, 162) that are distinct and independent of each other. Figure for the abbreviation: Fig. 2;

Description

Title of the invention: Memory device comprising a memory cell with an optimized active area. Technical field

[0001] This description relates generally to the field of electronic memory cell devices, in particular to resistive memory cells (called RRAM or ReRAM for "Resistive Random-Access Memory" in English) based on oxide (OxRAM for "Oxide-based Random-Access Memory" in English) or metallic electrolyte (CBRAM or "Conductive-Bridging Random-Access Memory" in English), or to magnetoresistive memory cells (called MRAM for "Magnetoresistive Random-Access Memory" in English). Previous technique

[0002] The main block of a memory is generally formed of an array of memory cells, or "bitcells". Each memory cell includes at least one selection transistor for selecting and electrically accessing the memory cell and at least one memory location where information for the memory cell is stored. The memory cells are electrically coupled to electrical connection elements formed in superimposed interconnection levels of the BEOL ("Back End Of Line") portion of the circuit comprising the memory.

[0003] In an RRAM-type memory cell, each memory point comprises a portion of metallic oxide or electrolyte arranged between two electrodes, generally arranged in a vertical stack. The paper P. Polakowski et al., "Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications", 2014 IEEE 6th International Memory Workshop (IMW), Taipei, Taiwan, 2014, pp. 1-4, describes such a configuration of an OxRAM-type memory cell.

[0004] Programming a memory cell can be achieved using a single transistor coupled to one of the two electrodes of the memory cell. Such a transistor forms a unipolar selector for the memory cell and can be of the PMOS or NMOS type. Such a 1T1R type memory cell has the advantage of occupying a small semiconductor area (or "footprint") since only one transistor is implemented in the semiconductor layer for this memory cell. However, such a unipolar selector cannot perform operations of different polarities (write and erase operations, involving current flows in different directions) on the memory cell in the same way, given The asymmetrical electrical properties of a transistor depend on its conductivity type (N or P). Write and erase operations performed in such a memory cell are therefore highly unbalanced. For example, the selector switch might be well-suited for writing but heavily overpowered during erasing the memory cell.

[0005] The document J.-M. Portai et al., “Design and simulation of a 128 kb embedded nonvolatile memory based on a hybrid RRAM (HfO2) / 28 nm FDSOI CMOS technology,” IEEE Trans. Nanotechnol., vol. 16, no. 4, pp. 677-686, Jul. 2017, describes an example of a 2T1R type memory cell comprising two transistors for programming the memory location, one being of the NMOS type and the other of the PMOS type. Such a memory cell makes it possible to resolve the imbalance problems related to the polarity of the operations to be performed in the memory location, since these operations are implemented with one or the other of the transistors depending on the polarity of the operation. On the other hand, such a memory cell occupies a large semiconductor area (approximately three times larger than that of a 1T1R type memory cell) due to the two transistors that must be manufactured.

[0006] The document A. Levisse et al., “Resistive Switching Memory Architecture Based on Polarity Controllable Selectors,” IEEE Transactions on Nanotechnology, vol. 18, pp. 183–194, 2019, describes the implementation of a 1T1R type memory cell in which the transistor's polarity is controllable according to the operation to be performed. Such a memory cell makes it possible to resolve the imbalance problems related to the polarity of the operations to be performed thanks to the programmability of the transistor's polarity. However, such a memory cell requires a large semiconductor area (approximately twice that required for a 1T1R type memory cell comprising a transistor with non-controllable polarity) due to the area occupied by the controllable-polarity transistor. Summary of the invention

[0007] There is therefore a need to propose a memory device comprising at least one memory cell not exhibiting the problems of asymmetry or imbalance of a memory cell with a unipolar selector and requiring a smaller semiconductor surface than those of known 2T1R or 1T1R type memory cells with a controllable polarity transistor.

[0008] An embodiment proposes a solution to all or part of the drawbacks of known solutions and proposes a memory device comprising at least one memory cell including:

[0009] - a first selection transistor comprising an active region formed in a first semiconductor layer;

[0010] - several levels of interconnections superimposed on the first semi-layer driver;

[0011] - a bipolar memory point disposed in one of the interconnection levels;

[0012] - a second selection transistor comprising an active region formed in a second semiconductor layer arranged in another of the interconnection levels arranged between the one including the memory point and the first semiconductor layer;

[0013] and in which:

[0014] - drain regions of the first and second selection transistors are connected to a first electrode of the memory point;

[0015] - source regions of the first and second selection transistors are connected respectively to first and second connection elements that are distinct and independent of each other.

[0016] According to a particular embodiment, the memory point comprises a resistive portion and the memory cell is of the OxRAM type, or the memory point comprises a solid electrolyte and the memory cell is of the CBRAM type, or the memory point comprises a magnetoresistive stack and the memory cell is of the MRAM type.

[0017] According to a particular embodiment, the active area of ​​the second selection transistor is at least partly arranged directly above the active area of ​​the first selection transistor.

[0018] According to a particular embodiment, one of the first and second selection transistors is of type P and the other of the first and second selection transistors is of type N.

[0019] According to a particular embodiment, the memory device comprises several memory cells arranged in a matrix and addressed by word lines, bit lines, and source lines, and, in each memory cell:

[0020] - separate word lines are coupled to the grids of the first and second memory cell selection transistors;

[0021] - one of the bit lines is coupled to a second electrode of the memory point of the memory cell;

[0022] - separate source lines are coupled to the source regions of the first and second memory cell selection transistors via the first and second connection elements.

[0023] According to a particular embodiment:

[0024] - when the second selection transistor is of type N, the second semi-layer conductive contains semiconducting oxide, or

[0025] - when the second selection transistor is of type P, the second semi-layer conductive contains carbon nanotubes.

[0026] According to a particular embodiment, the second semiconductor layer comprises a crystalline semiconductor material.

[0027] According to a particular embodiment, the memory device is made in the form of an integrated circuit in which the first semiconductor layer is included in the FEOL part of the integrated circuit, and the interconnection levels are included in the BEOL part of the integrated circuit.

[0028] According to a particular embodiment, the first connecting element passes through at least a first dielectric layer covering the first selection transistor and the interconnection levels including the memory point and the second selection transistor, and the second connecting element passes through at least the interconnection levels including the memory point and the second selection transistor.

[0029] According to a particular embodiment, the drain region of the second selector transistor is connected to the first electrode of the memory point by at least one third connecting element traversing at least the level of interconnections including the second selector transistor, and the drain region of the first selector transistor is connected to the first electrode of the memory point by at least one fourth connecting element traversing at least the first dielectric layer and by the third connecting element.

[0030] A method for implementing a memory device comprising at least one memory cell, including at least:

[0031] - realization of a first selection transistor comprising an active region formed in a first semiconductor layer;

[0032] - implementation of several levels of interconnections superimposed on the first layer semiconductor, including at least: • realization of a bipolar memory point in one of the interconnection levels; • realization of a second selection transistor comprising an active area formed in a second semiconductor layer disposed in another of the interconnection levels arranged between that including the memory point and the first semiconductor layer;

[0033] in which drain regions of the first and second selection transistors are connected to a first electrode of the memory spot;

[0034] and further comprising an embodiment of first and second connection elements distinct and independent of each other, and connected to source regions of the first and second selection transistors respectively.

[0035] According to a particular embodiment, the method further comprises, between the realization of the first selection transistor and the realization of the interconnection levels, the realization of a first dielectric layer covering at least the first selection transistor, and the first connection element is made through at least the first dielectric layer and the interconnection levels including the memory point and the second selection transistor, and the second connection element is made through at least the interconnection levels including the memory point and the second selection transistor.

[0036] According to a particular embodiment, the method further comprises an embodiment of at least a third connection element through the interconnection level including the second selection transistor and connecting the drain region of the second selection transistor to the first electrode of the memory point, and an embodiment of at least a fourth connection element through the first dielectric layer and connecting, with the third connection element, the drain region of the first selection transistor to the first electrode of the memory point.

[0037] According to a particular embodiment, the memory device is made in the form of an integrated circuit in which the first semiconductor layer is included in the FEOL part of the integrated circuit and the first selection transistor is made during the realization of the FEOL part of the integrated circuit, and the interconnection levels are included in the BEOL part of the integrated circuit and the memory point and the second selection transistor are made during the realization of the BEOL part of the integrated circuit. Brief description of the drawings

[0038] These features and advantages, as well as others, will be described in detail in the following description of specific examples and embodiments, given by way of non-limiting agreement, in connection with the accompanying figures, among which:

[0039] - Fig. 1 shows an electrical diagram of an example of a memory device according to a particular embodiment;

[0040] - [Fig. 2] represents a cross-sectional view of an example of a memory device according to a particular method of implementation;

[0041] - Figures [Fig. 3] and [Fig. 4] represent steps in an example of a process of creation of a memory device. Description of the implementation methods

[0042] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0043] For the sake of clarity, only the steps and elements useful for understanding the described embodiment examples have been shown and are detailed. In particular, various elements (read circuit, row decoder, column decoder, etc.) of the memory device are not detailed. A detailed implementation of these elements is within the capabilities of a person skilled in the art using the functional description given below.

[0044] In the different figures, the visible elements are not represented at the same scale relative to each other to facilitate understanding of these figures.

[0045] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intervening elements other than conductors, and when referring to two elements connected or coupled, this means that these two elements can be connected or linked via one or more other elements. Furthermore, the term "coupled" is used to denote electrical coupling between elements.

[0046] In the following description, when reference is made to absolute position qualifiers, such as "front," "back," "top," "bottom," "left," "right," etc., or relative position qualifiers, such as "above," "below," "superior," "inferior," etc., or to orientation qualifiers, such as "horizontal," "vertical," etc., unless otherwise specified, reference is made to the orientation of the figures in a normal operating position of the device. However, these terms do not imply the actual position and orientation of the device during its use.

[0047] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0048] The description below of oxide-based resistive bipolar memory cells (OxRAM) can be similarly applied to other types of resistive bipolar memory cells (RRAM), particularly CBRAM, by replacing the constituent elements of these OxRAM memory cells with their CBRAM equivalents, namely, the lower and upper electrodes with a chemically inert and a chemically active electrode, respectively, and the resistive layer with a solid electrolyte. It can also be applied to other types of bipolar memory cells, particularly MRAM, by replacing the resistive layer with a magnetoresistive stack comprising a tunnel oxide layer, for example based on MgO, arranged between two magnetic layers, for example based on cobalt.

[0049] An example of a memory device 100 according to a particular embodiment is described below in relation to Figures 1 and 2. On these figures, an electrical diagram ([Fig.1]) and a cross-sectional view ([Fig.2]) of a memory cell of the memory device 100 are shown.

[0050] In the example described, the memory device 100 comprises several memory cells arranged side by side in the form of a matrix. In Figures 1 and 2, only one memory cell is shown.

[0051] Each memory cell of the device 100 comprises a bipolar memory point 102 in which information is intended to be stored. In the example described, the memory point 102 is of the OxRAM type and comprises a resistive portion 104 including an oxide whose resistance varies according to the information stored in the memory cell. For example, the resistive portion 104 may include HfO2 or any other suitable oxide for storing information by forming conductive filaments within it.

[0052] The resistive portion 104 is disposed between a first electrode 106 and a second electrode 108 of the memory point 102. According to one embodiment, each of the first and second electrodes 106, 108 of the memory point 102 may comprise a first part including, for example, Ti, TiN or TaN and disposed against the resistive portion 104, and at least a second part including, for example, tungsten, TiN, copper or cobalt and serving for the electrical interconnection of the memory point 102. In this example, each of the first and second electrodes 106, 108 has its first part disposed between the resistive portion 104 and its second part. The examples of materials mentioned above for the realization of the first part of the electrodes 106, 108 of the memory point 102 have the advantage of being chemically stable, thus providing electrochemical neutrality to the electrodes 106, 108.

[0053] According to one embodiment, the memory point 102 may optionally include a portion of getter material based on titanium, tantalum, hafnium, or any other material having an electrochemical affinity for oxygen when the memory point 102 is of the OxRAM type. Such a portion of getter material may contribute to the creation of one or more electrically conductive filaments in the resistive portion 104.

[0054] Alternatively, the memory point 102 may be of another type, for example CB RAM or MRAM. In this case, the resistive portion 104 may be replaced by another type of material portion(s) in which information is intended to be stored.

[0055] The memory cell also includes a first selector transistor 110 and a second selector transistor 112 for controlling the memory location 102 during write, erase, and read operations of the memory location 102. In the example described, transistors 110 and 112 are of the MOS type, but other types of transistors are possible. Furthermore, in the example described, the first transistor 110 is of the P-type and the second transistor 112 is of the N-type. Alternatively, it is It is possible that the first transistor 110 is of type N and that the second transistor 112 is of type P.

[0056] A drain region 114, 116 of each of the first and second transistors 110, 112 is connected to the first electrode 106 of the memory point 102.

[0057] The memory cells of the device 100 are addressed by word lines, bit lines, and source lines. Each word line and source line is, for example, coupled to the memory cells arranged on the same row of the memory cell matrix of the device 100, and each bit line is, for example, coupled to the memory cells arranged on the same column of the memory cell matrix of the device 100. Other configurations are possible, however, such as having the source lines coupled to the memory cells perpendicular or parallel to the bit lines, having both the source and bit lines coupled to the memory cells perpendicular to the word lines, etc.

[0058] In the example described, the word lines are coupled to the gates of the memory cell selection transistors. In the example of [Fig. 1], a first word line 118.1 is coupled to the gate 120 of the first transistor 110, and a second word line 118.2 intended for the transmission of a signal complementary to that transmitted by the first word line 118.1 (because the first and second transistors 110, 112 are of opposite types in this example) is coupled to the gate 122 of the second transistor 112.

[0059] In the particular embodiment described here, the bit lines and source lines are coupled to source regions of the first and second transistors 110, 112 and to electrodes of the memory points 102 of the memory cells. In the particular embodiment described with reference to Figures 1 and 2, one of the bit lines 124 is coupled to the second electrode 108 of the memory point 102, a first source line 126 is coupled to a source region 128 of the first transistor 110, and a second source line 130, separate from the first source line 128, is coupled to a source region 132 of the second transistor 112.

[0060] The first transistor 110 comprises an active region (region including the channel, source, and drain of the transistor) formed in a first semiconductor layer 134. In the embodiment shown in Figures 1 and 2, the first semiconductor layer 134 is part of a substrate from which the device 100 is fabricated. This substrate may, for example, be a bulk substrate or a SOI substrate (in which case the first semiconductor layer 134 corresponds to the surface semiconductor layer of the SOI substrate). The first transistor 110 may, for example, be of the bulk type, FDSOI (“Fully- Depleted Silicon On Insulator in English, or totally deserted silicon on insulator type), or FinFET (“Fin Field-Effect Transistor” in English, or finned field-effect transistor).

[0061] In the example described, the device 100 is implemented as an integrated circuit that may include other electronic circuits. The first semiconductor layer 134 is included in the FEOL (Front End-Of-Line) portion of the integrated circuit. Various levels of interconnections are formed above the first semiconductor layer 134, and more specifically above the gates and contacts made on the first semiconductor layer 134, and are part of the BEOL (Back End-Of-Line) portion of the integrated circuit. In [Fig. 1], the boundary between the FEOL and BEOL portions of the integrated circuit is symbolized by a dashed line.

[0062] The second transistor 112 includes an active region formed in a second semiconductor layer 136 which is located in one of the interconnection levels superimposed on the first semiconductor layer 134, and therefore in the BEOL portion of the integrated circuit. Similarly, the memory dot 102 is formed in another of these interconnection levels, and therefore also in the BEOL portion of the integrated circuit.

[0063] The second transistor 112 and the second semiconductor layer 136 are located in an interconnection level disposed between the first semiconductor layer 134 and the interconnection level in which the memory point 102 is formed. For example, the second transistor 112 is disposed in the interconnection level M1 or Metal 1, designated by reference 138, located immediately above the BEOL part of the circuit, and the memory point 102 is disposed in the interconnection level M2 or Metal 2, designated by reference 140, of the integrated circuit.

[0064] According to one embodiment, memory point 102 can be realized in the form of a stack of planar layers or in the form of a 3D structure.

[0065] The active area of ​​the second transistor 112 can be at least partly arranged directly above the active area of ​​the first transistor 110. In the embodiment shown in [Fig.2], the active areas of the first and second transistors 110, 112 are aligned one above the other.

[0066] On [Fig.2], the gate dielectrics of the first and second transistors 110, 112, comprising for example an oxide, are designated respectively by references 142, 144, and the gate spacers, comprising for example a nitride, are designated by references 146 and 148 respectively for the first and second transistors 110, 112.

[0067] In the described embodiment, the first semiconductor layer 132 comprises, for example, silicon. A first dielectric layer 150, of the type PMD (“Pre-Metal Dielectric” in English) and comprising for example a semiconductor oxide such as SiO2, is arranged on the first semiconductor layer 134 and covers in particular the gate 120 of the first transistor 110 as well as the spacers 146.

[0068] The second semiconductor layer 136 is disposed on the first dielectric layer 150. A nitride layer 152, comprising for example silicon nitride, covers parts of the second semiconductor layer 136 not covered by the gate 122 and the spacers 148. The nitride layer 152 also covers parts of the first dielectric layer 150 not covered by the second semiconductor layer 136. The interface between the second semiconductor layer 136 and the first dielectric layer 150, and between the nitride layer 152 and the first dielectric layer 150 for the parts of the first dielectric layer 150 not covered by the second semiconductor layer 136, can be seen as forming the separation between the FEOL and BEOL parts of the integrated circuit.

[0069] The interconnection level 138, including the second transistor 112, also comprises a second dielectric layer 154, of the IMD type (Inter-Metal Dielectric, and more specifically IMD1 when referring to the interconnection level M1), and comprising, for example, a semiconductor oxide such as SiO2. The second dielectric layer 154 is disposed on the nitride layer 152 and also on the second transistor 112, covering it.

[0070] The interconnection level 140, which includes the memory point 102, also comprises a third dielectric layer 156, of the IMD type (Inter-Metal Dielectric, and more specifically IMD2 when referring to the interconnection level M2), and comprising, for example, a semiconductor oxide such as SiO2. The elements of the memory point 102 (resistive portion 104, electrodes 106, 108) are arranged within this third dielectric layer 156.

[0071] Another dielectric layer 158, comprising for example semiconductor nitride such as silicon nitride, is disposed between the second and third dielectric layers 154, 156. The interface between the second dielectric layer 154 and this layer 158 can be seen as forming the separation between the interconnection levels 138, 140 of the integrated circuit.

[0072] When the second transistor 112 is of type N, the second semiconductor layer 136 comprises, for example, a semiconductor oxide such as indium tin oxide (ITO), indium(III) oxide (In2O3), IGZO, indium tungsten oxide (IWO), or polysilicon. When the second transistor 112 is of type P, the second semiconductor layer 136 comprises, for example carbon nanotubes (CNTs). Their thickness is, for example, between 1 monolayer and a few nanometers.

[0073] Alternatively, it is possible that the second semiconductor layer 136 corresponds to a layer of crystalline semiconductor material, for example crystalline silicon.

[0074] In each memory cell of the device 100, connecting elements are present and make the connections between the memory point 102, the selection transistors 110, 112 and the word, bit and source lines.

[0075] In the embodiment described in connection with Figures 1 and 2, a first connecting element 160 couples the source region 128 of the first transistor 110 to the source line 126. This first connecting element 160 passes through the first dielectric layer 150 as well as the different layers of the interconnection levels 138, 140 (without however passing through the second semiconductor layer 136).

[0076] In the embodiment described in connection with Figures 1 and 2, a second connecting element 162 couples the source region 132 of the second transistor 112 to the source line 130. This second connecting element 162 passes through the different dielectric layers of the interconnection levels 138, 140.

[0077] The first and second connecting elements 160, 162 are distinct and independent of each other so that, in the particular embodiment described here, the source regions 128, 132 of the first and second transistors 110, 112 are coupled to different source lines 126, 130.

[0078] In the embodiment described in connection with Figures 1 and 2, a third connecting element 164 connects the drain region 116 of the second selector transistor 112 to the first electrode 106 of the memory point 102. This third connecting element 164 passes through the different layers of the interconnection levels 138, 140 until it reaches the first electrode 106 of the memory point 102.

[0079] In addition, a fourth connecting element 166 passes through the first dielectric layer 150 and allows the drain region 114 of the first selection transistor 110 to be connected, also by means of the third connecting element 164, to the first electrode 106 of the memory point 102.

[0080] For example, the various connection elements present in the memory cell and making the connections between the memory point 102, the selection transistors 110, 112 and the word, bit and source lines, may include tungsten, cobalt or a Ti / TiN stack.

[0081] The interconnection levels 138, 140 may include other metallic interconnection portions not visible in [Fig.1].

[0082] In the embodiment described above, the first and second transistors 110, 112 are single-gate transistors. Alternatively, the gate 122 of the second transistor 112 may be located on the opposite side of the second semiconductor layer 134, i.e., the side of the second semiconductor layer 134 facing the first selector transistor 110. According to another embodiment, the first transistor 110 and / or the second transistor 112 may be double-gate transistors.

[0083] An advantageous configuration of the device 100 corresponds to that in which the first transistor 110 is of type P and has an active area comprising silicon, and in which the second transistor 112 is of type N and has an active area comprising indium oxide.

[0084] In the device 100, the memory cell or each of the memory cells made as described above does not present a problem of polarity asymmetry since the memory point 102 of the cell is accessible, from its first electrode 106, through two separate transistors coupled to different source lines 126, 130 and whose polarity can be adapted to the direction of current flow through the memory point 102. For example, one of the two transistors 110, 112 has a polarity well suited for carrying out a write operation in the memory point 102, and the other of the two transistors 110, 112 has a polarity well suited for carrying out an erase operation in the memory point.

[0085] Furthermore, the footprint, and more specifically the semiconductor surface area occupied by the memory cell or each of the memory cells of the device 100, is limited by the fact that only the first transistor 110 is implemented in the first semiconductor layer 134 of the substrate, and that the memory point 102 and the second transistor 112 are implemented in the interconnection layers 138, 140 superimposed on the first semiconductor layer. This footprint is advantageously optimized when the active areas of the first and second transistors 110, 112 are aligned and positioned directly above each other.

[0086] A method for carrying out the device 100 according to a particular embodiment is described below in relation to figures 3 and 4.

[0087] As shown in [Fig.3], the first transistor 110 is first made from the first semiconductor layer 134. The steps implemented for the realization of this first transistor 110 are not detailed here and correspond to classic steps in the field of integrated circuit realization.

[0088] The first dielectric layer 150 is then made on the first transistor 110 and the first semiconductor layer 134, then the fourth connecting element 166 and the part of the first connecting element 160 located in the The first dielectric layer 150 is then produced. For example, the first dielectric layer 150 can first be deposited to the desired thickness. The connecting elements can then be produced by engraving holes through the first dielectric layer 150, thus creating access points to the desired areas. One or more metals can then be deposited in these holes. The metal parts deposited on the first dielectric layer 150 can then be removed, for example, by implementing CMP (chemical-mechanical polishing). These steps can also form the first line of word 118.1. The structure obtained at this stage of the process is shown in [Fig. 3].

[0089] The first level of interconnections 138 is then fabricated on the resulting structure. To this end, the second semiconductor layer 136 is first fabricated on the previously fabricated structure, and therefore on the first dielectric layer 150 and the fourth connecting element 166. The technique(s) used to fabricate the second semiconductor layer 136 depend on the nature of the material(s) of this layer. When the second semiconductor layer 136 comprises a semiconductor oxide, the steps enabling its fabrication can be carried out at temperatures below approximately 400°C. When the second semiconductor layer 136 comprises a crystalline semiconductor material, this layer can be transferred by implementing a low-temperature transfer step, as described, for example, in the document by M. Vinet et al., “3D monolithic integration: Technological challenges and electrical results”, Microelectronic Engineering, Volume 88, Issue 4, 2011, pages 331-335. .

[0090] The second transistor 112 is then fabricated from the second semiconductor layer 136, followed by the nitride layer 152 and the second dielectric layer 154. The connecting elements (the third connecting element 164) and the portions of the connecting elements located in the second interconnection level 138 (portions of the first and second connecting elements 160, 162) are then fabricated in the second interconnection level 138. The structure obtained at this stage of the process is shown in [Fig. 4].

[0091] The nitride layer 158 is then made on the structure previously made, and therefore on the second dielectric layer 154 and the various parts and connecting elements previously made in the second dielectric layer 154.

[0092] The memory point 102 and the second level of interconnections 140 are then made on the nitride layer 158. The third dielectric layer 156 can in particular be made by implementing several steps of deposition of the dielectric material desired for this layer, with in particular between these deposition steps the implementation of steps forming the different elements of the memory point 102. The memory cell obtained at the end of this process corresponds to the one visible in [Fig.2],

[0093] In the process described above, only the fabrication of the elements of a single memory cell of the device 100 is described. However, these steps are generally implemented for the simultaneous fabrication of several memory cells. Furthermore, when the device 100 is fabricated as an integrated circuit, other components and elements are fabricated during the fabrication of the FEOL and BEOL portions of the integrated circuit.

[0094] Various embodiments and variants have been described. A person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to a person skilled in the art.

[0095] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. For example, the precise nature of the deposition and engraving steps implemented can be chosen according to, in particular, the material(s) to be deposited or engraved, as well as the thicknesses of the material to be deposited or engraved.

Claims

Demands

1. A memory device (100) comprising at least one memory cell having: - a first selection transistor (110) having an active region formed in a first semiconductor layer (134); - several interconnection levels (138, 140) superimposed on the first semiconductor layer (134); - a bipolar memory dot (102) disposed in one of the interconnection levels (140); - a second selection transistor (112) having an active region formed in a second semiconductor layer (136) disposed in another of the interconnection levels (138) arranged between the one including the memory dot (102) and the first semiconductor layer (134); and wherein: - drain regions (114, 116) of the first and second selection transistors (110, 112) are connected to a first electrode (106) of the memory dot (102);- source regions (128, 132) of the first and second selection transistors (110, 112) are connected respectively to first and second connecting elements (160, 162) that are separate and independent of each other.;

2. Memory device (100) according to claim 1, wherein the memory point (102) comprises a resistive portion (104) and the memory cell is of the OxRAM type, or wherein the memory point (102) comprises a solid electrolyte and the memory cell is of the CB RAM type, or wherein the memory point (102) comprises a magnetoresistive stack and the memory cell is of the MRAM type.

3. Memory device (100) according to any one of the preceding claims, wherein the active area of ​​the second selection transistor (112) is at least partly disposed directly above the active area of ​​the first selection transistor (110).

4. Memory device (100) according to any one of the preceding claims, wherein one of the first and second selector transistors (110, 112) is of type P and the other of the first and second selector transistors (110, 112) is of type N.

5. Memory device (100) according to any one of the preceding claims, comprising several memory cells arranged in a matrix and addressed by word lines (118.1, 118.2), bit lines (124) and source lines (126, 130), and wherein, in each memory cell: - distinct word lines (118.1, 118.2) are coupled to the gates (120, 122) of the first and second select transistors (110, 112) of the memory cell; - one of the bit lines (124) is coupled to a second electrode (108) of the memory point (102) of the memory cell; - separate source lines (126, 130) are coupled to the source regions (128, 132) of the first and second selection transistors (110, 112) of the memory cell via the first and second connecting elements (160, 162).

6. Memory device (100) according to any one of the preceding claims, wherein: - when the second selector transistor (112) is of type N, the second semiconductor layer (136) comprises semiconductor oxide, or - when the second selector transistor (112) is of type P, the second semiconductor layer (136) comprises carbon nanotubes.

7. Memory device (100) according to any one of claims 1 to 5, wherein the second semiconductor layer (136) comprises a crystalline semiconductor material.

8. Memory device (100) according to any one of the preceding claims, realized in the form of an integrated circuit in which the first semiconductor layer (134) is included in the FEOL part of the integrated circuit, and in which the interconnection levels (138, 140) are included in the BEOL part of the integrated circuit.

9. Memory device (100) according to any one of the preceding claims, wherein the first connecting element (160) passes through at least one first dielectric layer (150) covering the first selection transistor (110) and the interconnection levels (138, 140) including the memory point (102) and the second selection transistor (112), and wherein the second connection element (162) passes through at least the interconnection levels (138, 140) including the memory point (102) and the second selection transistor (112).

10. Memory device (100) according to claim 9, wherein the drain region (116) of the second selector transistor (112) is connected to the first electrode (106) of the memory point (102) by at least one third connecting element (164) passing through at least the interconnection level (138) including the second selector transistor (112), and wherein the drain region (114) of the first selector transistor (110) is connected to the first electrode (106) of the memory point (102) by at least one fourth connecting element (166) passing through at least the first dielectric layer (150) and by the third connecting element (164).

11. Method for making a memory device (100) comprising at least one memory cell, comprising at least: - realization of a first selection transistor (110) comprising an active region formed in a first semiconductor layer (134); - implementation of several levels of interconnections (138, 140) superimposed on the first semiconductor layer (134), including at least: • realization of a bipolar memory point (102) in one of the interconnection levels (140); • realization of a second selection transistor (112) comprising an active area formed in a second semiconductor layer (136) disposed in another of the interconnection levels (138) arranged between that including the memory point (102) and the first semiconductor layer (134); in which drain regions (114, 116) of the first and second selector transistors (110, 112) are connected to a first electrode (106) of the memory point (102); and further comprising an embodiment of first and second connecting elements (160, 162) distinct and independent of each other the other, and connected to source regions (128, 132) of the first and second selection transistors (110, 112) respectively.

12. A method for making a memory device (100) according to claim 11, further comprising, between the realization of the first selection transistor (110) and the realization of the interconnection levels (138, 140), a realization of a first dielectric layer (150) covering at least the first selection transistor (110), and in which the first connection element (160) is made through at least the first dielectric layer (150) and the interconnection levels (138, 140) including the memory point (102) and the second selection transistor (112), and the second connection element (162) is made through at least the interconnection levels (138, 140) including the memory point (102) and the second selection transistor (112).

13. A method for making a memory device (100) according to claim 12, further comprising an embodiment of at least one third connection element (164) through the interconnection level (138) including the second selection transistor (112) and connecting the drain region (116) of the second selection transistor (112) to the first electrode (106) of the memory point (102), and an embodiment of at least one fourth connection element (166) through the first dielectric layer (150) and connecting, with the third connection element (164), the drain region (114) of the first selection transistor (110) to the first electrode (106) of the memory point (102).

14. A method for making a memory device (100) according to any one of claims 11 to 13, wherein the memory device (100) is made in the form of an integrated circuit in which the first semiconductor layer (134) is included in the FEOL part of the integrated circuit and the first selector transistor (110) is made during the realization of the FEOL part of the integrated circuit, and wherein the interconnection levels (138, 140) are included in the BEOL part of the integrated circuit and the memory point (102) and the second selector transistor (112) are made during the realization of the BEOL part of the integrated circuit.