Signal generation device with phase adjustment
The signal generation device addresses PVT sensitivity and phase shift limitations in ILOs by using a pulsed oscillator and feedback loops to dynamically control phase shifts, enhancing stability and reducing power consumption in radar systems.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Filing Date
- 2024-12-10
- Publication Date
- 2026-06-12
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Abstract
Description
Title of the invention: Signal generation device with phase adjustment. Technical field
[0001] This description relates generally to the field of signal generation, for example for communication systems or for radar and / or detection systems. Previous technique
[0002] The generation of modulated and / or continuous wave (CW) signals in radio frequency (RF) circuits is generally implemented using a phase-locked loop (PLL) that incorporates a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO) in a feedback loop. In this loop, the phase of an external reference signal applied to the input of the PLL is compared to that of a signal similar to the one delivered at the output of the oscillator, but whose frequency is divided by that of the signal delivered at the output of the oscillator.
[0003] The loop formed by the PLL allows the oscillator frequency to be set to an integer multiple or an integer fraction of the reference signal frequency. This multiplication or division factor corresponds to the ratio between the desired oscillator frequency and the reference signal frequency. The generated output signal, which corresponds to the oscillator output signal, is generally called the local oscillator (LO) signal.
[0004] This LO signal can be used to drive other circuits in order, for example, to modulate a communication signal.
[0005] The multiplication factor, or division ratio, of the PLL can also be dynamically modified to implement frequency modulation directly on the PLL output signal. An example of this technique is the generation of a frequency-modulated continuous wave (FMCW) signal, used particularly in radars, which forms a frequency ramp varying linearly over time between two extreme frequencies fmin and fmax.
[0006] In certain applications such as multistatic or phase-controlled phase-array radar transceivers, several antennas transmit or receive the same modulated signal with different phase adjustments between them in order to implement beamforming or angle-of-arrival detection of the signals. One way to obtain these different phase values for each antenna path is to insert a controllable phase shifter in series in the signal path between the antenna and the transmitting or receiving amplifiers. Another way is to insert a controllable phase shifter in the LO signal path, so that the phase shift introduced in the various LO signals used in the transmitter or receiver connected to the antennas is applied to the modulated signal during mixing with the LO signal.
[0007] The document by Kanoun, M. et al., “A 5.8 GHz fully integrated BiCMOS SiGe:C injection-locked-oscillator-based active phase shifter for energy beamforming”, Analog Integr Cire Sig Process 106, 363-374 (2021), describes an implementation of phase shifting on a LO signal using an injection-locked oscillator (ILO). In this document, a combination of a first fine phase shift and a second phase shift larger than the first is performed on an input signal with a frequency of approximately 5 GHz. The first phase shift is obtained by adjusting the control voltage Vtune applied to the ILO, which varies the self-oscillation frequency f0 of the ILO and allows a frequency difference to be introduced relative to the frequency of the injection signal applied to the input of the ILO.If this frequency difference remains within the ILO's locking band, the ILO locks onto the injection frequency, with a phase shift proportional to this frequency difference. This first phase shift can cover a range of values from -45° to +45°. The second phase shift is implemented using a polyphase filter comprising different selectable connection paths between the filter's input and output, each applying different fixed phase shift values, for example, multiples of 90°. These two phase shifts are added together to obtain an output phase shift ranging from -180° to +180°.
[0008] One drawback of this solution is that precisely adjusting the first phase shift requires knowing the exact value of the ILO's self-oscillation frequency f0. However, the ILO's self-oscillation frequency f0 is sensitive to the PVT (Process, Voltage, Temperature variations) experienced by the ILO. Furthermore, this solution requires the ILO to be frequency-locked to the input signal, which necessitates a mechanism to detect whether this condition is met, as well as a calibration method in case this condition is not met, in order to adjust the ILO under the correct locking conditions. Finally, this type of LO signal phase shifting uses ILOs locked to the same input frequency as the desired frequency for the LO signal. In the case where these ILOs are integrated into a A PLL is used to synchronize the output with an integer or fractional multiple of a reference signal. The PLL's operation will affect the phase value of the resulting output signal. The ILO could be placed after the PLL's oscillator, but this would require separate circuits for frequency generation and phase shifting, increasing power consumption.
[0009] EP 3 624 343 A1 describes a technique for detecting the unlock range and configuring an ILO to facilitate its locking onto an input signal, within the framework of an LO signal generation architecture whose frequency is equal to an integer multiple of the input signal. In the described system, the injection signal applied to the ILO input comes from a pulsed oscillator driven by a reference signal. The lock detection implemented is based on subsampling the ILO output signal using the same reference signal that drives the pulsed oscillator, followed by analog processing that measures the spectral content of the subsampled signal using filtering and integration operations. This technique can be used to tune the ILO so that its self-oscillation frequency is equal to the desired output frequency.However, this adjustment is made only once, before the ILO is used, i.e., when it is not yet part of the communication system. Calibration requires setting the ILO to its locking range, and sometimes the ILO is not locked onto the input signal. Once the optimal point is found, the ILO is configured to operate normally. However, temperature or voltage variations, known as VT variations, can cause the ILO's self-oscillation frequency to drift and affect the accuracy of the phase shift. To stabilize the ILO's self-oscillation frequency, a tracking mechanism is necessary to continuously compensate for the impact of VT variations on the ILO.
[0010] The document by Yoo, Seyeon et al., “A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers.” IEEE Journal of Solid-State Circuits 53 (2018): 375-388, describes the implementation of continuous tracking and compensation of the self-oscillation frequency of an ILO. The circuit that implements this function is called the FTL (Frequency Tracking Loop) and compares the areas of regions under two complementary output signals of the ILO by integrating them during a short pulse from the ILO's synchronization input. When the area of the two regions is the same, it means that the pulse is phase-aligned with the output signals. If the self-oscillation frequency of the ILO drifts in either direction from the expected optimal value, the phase difference between the input pulse and the two output signals Complementary signals of the ILO generate areas of different sizes under these two signals. This technique can be used to obtain a voltage proportional to the phase difference (including the sign), which is then used in a feedback loop to adjust the ILO so that its self-oscillation frequency returns to optimal.
[0011] This technique requires that the frequency of the injection signal applied to the input of the ILO be equal to the self-oscillation frequency of the ILO. No pulsed oscillator is present at the input of the ILO, so the frequency multiplication factor that can be obtained is limited to a very small integer value, generally less than or equal to 3. The FTL circuit comprises a pair of switches, a low-pass integrator consisting of a series resistor and a parallel capacitor, and an error amplifier, corresponding to a voltage-to-current conversion differential amplifier, or voltage-to-current converter (V-to-I converter, or transconductance differential amplifier), driven by two integrating signals. The error signal obtained at the output of the amplifier is a current used to charge or discharge the loop capacitor.The loop is active once the lock-up is achieved and the capacitor is charged to the optimal setting voltage. If the self-oscillation frequency of the ILO deviates from the desired value, the loop compensates for the deviation and adjusts the ILO control voltage to maintain the error signal at zero.
[0012] US patent 2023 / 224138 A1 describes the use of an FTL circuit in a PLL using a second VCO that receives output signals from a pulsed oscillator at its injection input. The circuit uses the pulsed oscillator to implement a frequency-multiplying phase detector, but does not directly inject a signal into the VCO in the PLL. An FTL circuit is used to adjust the self-oscillation frequency of the pulsed oscillator so that the output signal of the phase detector is phase-aligned with the signal from the PLL's VCO, both signals having the same frequency.
[0013] The paper by L.-Y. Chen et al., "A Ka-Band 256-QAM Ninefold Sub-Harmonically Injection-Locked CMOS I / Q Modulator Using Pulsed Oscillator", 2024 IEEE / MTT-S International Microwave Symposium - IMS 2024, Washington, DC, USA, 2024, pp. 50-53, describes the use of an FTL circuit to maintain optimal injection conditions for an ILO. The input of such an ILO is coupled to the output of a pulsed oscillator. This circuit is used to track and adjust the value of the ILO's self-oscillation frequency so that the sensitivity curve is aligned with the integer multiple of the reference frequency.
[0014] In all the structures described above, a circuit is used to align the input and output phases of an ILO so that its self-oscillation frequency or a lower harmonic is exactly aligned on a multiple of the frequency of the reference signal applied to the input. However, none of these structures allows signal generation with control of the phase shift between the output signal and the input signal to a desired value other than zero. Summary of the invention
[0015] There is a need to propose a signal generation device that does not present at least some of the disadvantages of known structures.
[0016] One embodiment overcomes all or part of the drawbacks of known solutions and proposes a signal generation device, comprising at least: - a pulsed oscillator configured to receive as input a periodic signal of frequency FRef and generate on an output a TORP signal corresponding to a train of oscillations of frequency equal to M.FRef, of duration less than TRef = l / FRef and repeated periodically at the frequency FRef, with M an integer greater than 1; - a first injection-locked oscillator comprising at least one injection input coupled to the output of the pulsed oscillator and comprising at least two outputs on which periodic signals Vout+ and V„ul of frequency equal to N.FRef, with N an integer greater than 1, and phase-shifted by 180° relative to each other are intended to be delivered; - a first sampler configured to sample the Vout+ and V„ul signals at the FRef frequency; - a first integrator configured to deliver output signals Vo + and V„ each resulting from an integration of one of the signals Vout+ and V„ul sampled at the frequency FRef; - a first conversion circuit comprising at least one control input configured to receive at least one offset voltage Voff, and configured to deliver an output signal of value proportional to the voltage difference (Voff + Vo+) - (Voff + V„) and intended to be applied to a control input of the first injection-locked oscillator.
[0017] According to a particular embodiment, the first conversion circuit includes at least one voltage-to-current amplifier.
[0018] According to a particular embodiment, the first conversion circuit has two control inputs configured to receive each one of the offset voltages Voff+ and Voff., and is configured to deliver the output signal with a value proportional to the voltage difference (Voff+ + Vo+) - (Voff. + Vo_).
[0019] According to a particular embodiment, the first sampler comprises at least two switches configured to be controlled at the FRef frequency and each receive as input one of the signals Vout+ and Vout_.
[0020] According to a particular embodiment, the first integrator comprises at least two electrical capacitors, each comprising a first electrode on which one of the sampled signals Vout+ and V„ul is intended to be applied and a second electrode on which a reference electrical potential is intended to be applied.
[0021] According to a particular embodiment, the signal generation device further comprises a first circuit for storing a control voltage of the first injection-locked oscillator, configured to apply said control voltage to the control input of the first injection-locked oscillator.
[0022] According to a particular embodiment, the first storage circuit includes at least one electrical capacity.
[0023] According to a particular embodiment, the signal generation device further comprises a first circuit for initializing the value of the control voltage stored in the first storage circuit.
[0024] According to a particular embodiment, the first initialization circuit is configured to implement a calibration phase of the signal generation device during which the following steps are implemented: - disconnect the first storage circuit from an output of the first conversion circuit, and disconnect the outputs of the first injection-locked oscillator from inputs of the first sampler; - to couple a first control circuit between the outputs of the first injection-locked oscillator and the first storage circuit; - calculate and store, in the first storage circuit, an initialization voltage value such that its application to the control input of the first injection-locked oscillator causes the first injection-locked oscillator to lock onto the frequency N.FRef and that a phase shift between the periodic signals Vout+ and V„ul and the TORP signal is zero.
[0025] According to a particular embodiment, the first control circuit comprises at least: - an integrator filter configured to perform high-pass or band-pass filtering of the signals Vout+ and V<)Ul; - a comparator configured to compare an output signal from the integrator filter with a threshold value; - a control device configured to determine maximum and minimum values of the control voltage of the first injection-locked oscillator for which the first injection-locked oscillator can frequency lock, and to determine the value of the initialization voltage which is between these maximum and minimum values.
[0026] According to a particular embodiment, the signal generation device further comprises a signal shaping circuit configured to receive as input a sinusoidal signal of frequency FRef and to deliver on the input of the pulsed oscillator the periodic signal of frequency FRef in the form of a square signal.
[0027] According to a particular embodiment, the signal generation device further comprises a controlled delay line coupled to the input of the pulsed oscillator and configured to apply to the periodic signal of frequency FRef a phase shift equal to 0° or 90° or 180° or 270°.
[0028] According to a particular embodiment, the signal generation device includes at least one second injection-locked oscillator having at least two injection inputs coupled to the outputs of the first injection-locked oscillator.
[0029] According to a particular embodiment: - the first injection-locked oscillator is multi-phase and has several outputs on which signals are delivered with phase shifts that are multiples of 90°, or - the second injection-locked oscillator is part of a feedback loop comprising at least a second sampler, a second integrator, and a second conversion circuit, coupled together in a manner analogous to the first sampler, the first integrator and the first conversion circuit with the first injection-locked oscillator.
[0030] A multi-signal generation device is also proposed comprising at least several signal generation devices configured to receive as input the same periodic signal of frequency FRef and different offset voltages Voff each intended for one of the signal generation devices. Brief description of the drawings
[0031] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0032] - Fig. 1 represents an example of a signal generation device according to a first embodiment;
[0033] - [Fig.2] represents a variant embodiment of a conversion circuit of a signal generation device;
[0034] - [Fig. 3] represents a phase shift value obtained in an ILO of the device signal generation as a function of the value of the control voltage applied to the input of this ILO;
[0035] - Fig. 4 represents an example of a signal generation device according to a second embodiment;
[0036] - Fig. 5 represents an example of a signal generation device according to a third embodiment;
[0037] - Figure 6 represents an example of a signal generation device according to a fourth embodiment;
[0038] - Figure 7 represents an example of a multi-signal generation device according to a a particular method of implementation. Description of the implementation methods
[0039] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional, and material properties. In the figures, to facilitate their reading, the different elements are not represented at the same scale relative to each other.
[0040] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, various elements (pulsed oscillator, ILOs, conversion circuit, amplifier, ILO control voltage initialization circuit, integrator filter, comparator, control system, signal shaping circuit, controlled delay line, etc.) are not detailed. A person skilled in the art will be able to implement these elements in detail from the functional description given here.
[0041] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intervening elements other than conductors, and when referring to two elements connected or coupled, this means that these two elements can be connected or linked via one or more other elements. Furthermore, the terms "coupled," "linked," and "connected" are used here to denote electrical couplings, links, or connections.
[0042] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.
[0043] Unless otherwise indicated, the ranges of values shown include the limits of these ranges.
[0044] A signal generation device 100 according to a first embodiment is described below in relation to [Fig.1].
[0045] The device 100 includes a pulsed oscillator 102 configured to receive as input a periodic reference signal "Ref" of frequency FR ef and generate on a output a "TORP" signal corresponding to a train of oscillations of frequency equal to M.Fr ef, of duration less than TR ef = 1 / FR ef, and repeated periodically at the frequency FR ef, with M an integer greater than 1. As an example, the value of the frequency FR ef can be between a few hundred MHz and a few GHz, and the value of M is for example between 15 and 50.
[0046] According to an embodiment corresponding to that shown in [Fig. 1], the pulsed oscillator 102 may include a voltage-controlled VCO oscillator 104 (not visible in [Fig. 1]), and controlled power supply means 106 that supply power to the oscillator 104 and are controlled by the reference signal Ref. These means 106 correspond, for example, to a controlled current source operating as a switch that periodically interrupts the power supply to the oscillator 104 with a period equal to TRef. This controlled current source may correspond to a MOS transistor having a gate to which the reference signal Ref is applied. Generally, these means 106 may include a switch connected to a power supply input of the oscillator 104 and capable of being controlled by the reference signal Ref.
[0047] Details of the embodiment of such a pulsed oscillator 102 and variant embodiments thereof are described for example in document WO 2013 / 079685 A1. Other variant embodiments of such a pulsed oscillator 102 are possible.
[0048] The device 100 further comprises a first ILO 108 including at least one injection input coupled to the output of the pulsed oscillator 102 and to which the TORP signal is applied. The first ILO 108 also includes two outputs to which periodic signals Vout+ and V„ul of frequency equal to N.Fref, where N is an integer greater than 1, and phase-shifted by 180° with respect to each other, are intended to be delivered. By way of example, the value of N can be between 15 and 50.
[0049] The device 100 further comprises a first sampler 110 configured to sample the signals Vout+ and V„ul at the frequency Fref. According to an embodiment corresponding to that shown in [Fig. 1], the first sampler 110 comprises at least two switches 112, configured to be controlled at the frequency Fref and each receiving as input one of the signals Vout+ and V„ul. The input of each of the switches 112 is, in this example, coupled to one of the outputs of the first ILO 108. Other embodiments of the first sampler 110 are possible.
[0050] The device 100 further comprises a first integrator 114 configured to deliver output signals Vo+ and V„, each resulting from the integration of one of the signals Vout+ and V„ul sampled at the frequency Fref. According to an exemplary embodiment Corresponding to that shown in [Fig. 1], the first integrator 114 comprises at least two electrical capacitors 116, each including a first electrode to which one of the sampled signals Vout+ and V„ul is intended to be applied, and a second electrode to which a reference electrical potential, for example, the ground of the device 100, is intended to be applied. The first integrator 114 can also be viewed as a low-pass filter applied to the sampled signals Vout+ and V„ul. Alternatively, the first integrator 114 can also include at least two electrical resistors, each including a first electrode coupled to one of the switches 112 and a second electrode coupled to the first electrode of one of the capacitors 116. Other embodiments of the first integrator 114 are possible.
[0051] The device 100 further includes a first conversion circuit 118 comprising at least one control input configured to receive the Vo+ and V„ signals as voltages and at least one offset voltage, Voff, and to deliver an output current proportional to the voltage difference (Voff + Vo+) - (Voff + Vo.). This output current is intended to be converted into a control voltage Vtune which will be applied to a control input of the first ILO 108. According to an embodiment corresponding to that shown in [Fig. 1], the first conversion circuit 118 includes at least one current-voltage differential amplifier 120, or transconductance amplifier. This amplifier 120 has at least two differential inputs coupled to the outputs of the first integrator 114, to which the Vo+ and V„ signals are delivered.
[0052] In one embodiment, the first conversion circuit 118 has two control inputs configured to receive one of the offset voltages, Voff+ and Voff., and is configured to deliver the output current proportional to the voltage difference (Voff+ + Vo+) - (Voff. + VJ. Figure 2 schematically represents such a variant, in which the amplifier 120 has, in addition to the two differential inputs to which the voltages Vo+ and V„ are applied, two control inputs to which the offset voltages Voff+ and Voff_ are applied.
[0053] Other embodiments of the first conversion circuit 118 are possible.
[0054] In the described embodiment, the device 100 further comprises a first storage circuit 122 for the control voltage Vtune of the first ILO 108, configured to apply, during operation of the device 100, the control voltage Vtune to the control input of the first ILO 108. According to an embodiment corresponding to that shown in [Fig. 1], the first storage circuit 122 comprises at least one electrical capacitor 124 across which the voltage of The Vtune command is stored. In the example of [Fig. 1], a first electrode of capacitor 124 is coupled to the output of the first conversion circuit 118, i.e., the output of amplifier 120 in this example. A reference electrical potential, for example, the ground of device 100, is applied to a second electrode of capacitor 124. Other embodiments of the first storage circuit 122 are possible.
[0055] In the described embodiment, the device 100 further comprises a generator 128 that generates the reference signal Ref and delivers it to the input of the pulsed oscillator 102. In the example shown in [Fig. 1], the generator 128 includes a sinusoidal signal source 130 of frequency Fref, for example, a PLL or any other sinusoidal signal generation circuit. In the described embodiment, the source 130 also serves to provide control signals of frequency Fref with different on / off durations, such as the switching control signals for the switches 112. Alternatively, the switching of the switches 112 can be controlled by control signals of frequency Fref provided by a circuit other than the generator 128.
[0056] The generator 128 also includes a signal-shaping circuit 132 configured to receive as input the sinusoidal signal of frequency Fref delivered by the source 130 and to deliver as output from the generator 128 the reference signal Ref. In the described embodiment, the circuit 132 is configured to deliver the reference signal Ref as a square wave signal of frequency Fref. According to a particular embodiment, the circuit 132 can be configured to allow setting the duty cycle of this square wave signal. For example, the circuit 132 can be configured such that the duty cycle of the reference signal Ref is between 10% and 90%.
[0057] Other embodiments of generator 128 are possible.
[0058] In the device 100, the pulsed oscillator 102 coupled to the first ILO 108 can be used to generate a sustained-wave signal by implementing frequency multiplication by a high-order integer. The pulsed oscillator 102 generates the TORP signal, which contains harmonics that are integer multiples of the frequency of the reference signal Ref, i.e., the frequencies (..., M-2, M1, M, M+1, M+2, ...).FR ef. The pulsed oscillator 102 is synchronized with the reference signal Ref applied to its input. The frequency M.FR ef corresponds to the highest amplitude line in the spectrum of the reference signal Ref, and this spectrum is centered on the self-oscillation frequency f0 of the oscillator 104. The harmonics of maximum amplitude are located around the self-oscillation frequency f0. One of these harmonic terms (the one with frequency N.Fr ef in the example described) is selected by the first ILO 108, depending on the value of the control voltage VtUne applied to the control input of the first ILO 108. In a particular configuration, the harmonic selected by the first ILO 108 corresponds to the line of greatest amplitude of the spectrum of the TORP signal, that is such that N = M.
[0059] The first ILO 108 has its own self-oscillation frequency f0. This frequency f0 defines the center of the sensitivity curve of the first ILO 108. The amplitude of this sensitivity curve has a minimum value when the frequency of the injection signal received by the first ILO 108 is equal to the frequency f0, and increases as the frequency of the injection signal moves away from the value f0. Locking of the first ILO 108 is only possible within a certain frequency range centered on f0. If the amplitude of the injection signal applied to the input of the first ILO 108 exceeds the amplitude of this sensitivity curve of the first ILO 108 at the frequency of the injection signal, the first ILO 108 then locks onto the received injection signal and oscillates at the frequency of this injection signal and not at its own self-oscillation frequency f0. When the first ILO 108 is locked onto the frequency N.FR ef, the output signals of the first ILO 108 Vout+ and V„ul oscillate at the frequency N.FR ef. .
[0060] The phase difference between the injection signal applied to the input of the first ILO 108 and the output signal of the first ILO 108 depends on the difference between the frequencies f0 and N.FR ef. By adjusting the value of the self-oscillation frequency f0 of the first ILO 108, a controllable phase shift can be introduced between the injection signal and the output signal of the first ILO 108.
[0061] In order to adjust the phase of the signal obtained at the output of device 100, the first sampler 110, the first integrator 114, the first conversion circuit 118, and the first storage circuit 122 form, within device 100, a frequency tracking loop used to define the phase shift with respect to the reference signal Ref applied to the input of the pulsed oscillator 102. The signals Vout+ and Vout_ obtained at the output of the first ILO 108 are sampled and integrated such that the signals Vo+ and V„ correspond to, or the surface of, the signals Vout+ and V„ul, respectively. In the embodiment described in connection with [Fig. 1], in which the first sampler 110 includes switches 112 and the first integrator 114 includes electrical capacitors 116, this amounts to performing an integral function on the signals Vout+ and Vout_ during the closing time of the switches 112.The capacitors 116 allow the output signals Vo+ and V„ to be provided in the form of voltages proportional to the area under the curves of the signals Vout+ and V„ul during the closing time of the switches 112. .
[0062] These two signals Vo+ and V„ are compared to each other by applying to each of them the offset signal Voff or one of the two offset signals Voff+ and Voff. The first conversion circuit 118. The error current obtained at the output of the first conversion circuit 118 is used to define the voltage value stored in the first storage circuit 122, which is used to control the first ILO 108. The offset signal Voff, or the offset signals Voff+ and Voff., allow the output to be obtained From the first conversion circuit 118, an error current such that the phase shift between the reference signal Ref and the output signals of the first ILO 108 depends on the value of the offset signal(s). The offset signal(s) are therefore used to define a balance condition for the feedback loop, with a phase shift between the input and output of this loop that is variable in value.
[0063] In the first ILO 108, the phase difference, called a, between the signal applied to its input and the signal obtained at the output depends on various parameters of the first ILO 108: the quality factor Q of the oscillator of the first ILO 108, the ratio between the amplitude E of the output signal of the first ILO 108 and that Einj of the injection signal (TORP signal) applied to the input of the first ILO 108, and the relative difference between the self-oscillation frequency f0 of the first ILO 108 and that of the injection signal of the first ILO 108, i.e. the ratio Aco0 / coo, with co0 = 2nf o and Aco0 = 2k(N . FR ef-fo )■ These parameters are related to each other by the equation:
[0064] [Math.l] sif^)=2Q^
[0065] The form of the function defining the phase difference a as a function of these parameters therefore corresponds to an arcsine function. Figure 3 represents the phase shift value obtained in the first ILO 108 as a function of the internal capacitance value, which depends on the control voltage VtUne applied to the input of the first ILO 108. This internal capacitance value determines the self-oscillation frequency f0 of the first ILO 108. In this figure, reference numerals 10 and 12 designate The limiting values beyond which the locking of the first ILO 108 is no longer achieved. Beyond these values, the phase rotates asynchronously.
[0066] If Acüo = 0, then a = 0°. Consequently, when the self-oscillation frequency f0 of the first ILO 108 is strictly equal to the latching frequency of the first ILO 108 (N.Fref), the phase difference between the input and output signals of the first ILO 108 is zero. In the device 100, the value of the control voltage Vtune applied to the control input of the first ILO 108 can be chosen such that the self-oscillation frequency f0 of the first ILO 108 is different from the latching frequency of the first ILO 108 and allows the desired phase shift to be obtained at the output relative to the input signal.
[0067] As previously stated, the phase shift obtained also depends on the quality factor Q of the first ILO 108 and the E / Einj ratio. These parameters are kept constant so that the phase shift obtained is controlled by changing the value of f0.
[0068] The phase shift a that can be obtained can be between -90° and +90°, or preferably between approximately -45° and +45° in order to limit the risks of losing the frequency lock of the first ILO 108 and to remain in a region of linear variation of the phase shift as a function of the control voltage Vtune applied to the first ILO 108.
[0069] In the described embodiment, the device 100 further includes a circuit for initializing the control voltage value stored in the circuit 122. This circuit can be configured to implement a calibration phase of the device 100 during which the following steps are carried out:
[0070] - disconnect the first storage circuit 122 from an output of the first conversion circuit 118, and disconnect the outputs of the first ILO 108 from the inputs of the first sampler 110;
[0071] - to couple a first control circuit 136 between the outputs of the first ILO 108 and the first storage circuit 122;
[0072] - calculate and store, in the first storage circuit 122, a voltage value initialization such that its application on the control input of the first ILO 108 causes the first ILO 108 to lock onto the frequency N.FR ef and that a phase shift between the periodic signals Vout+ and V„ul and the TORP signal is zero.
[0073] In the embodiment shown in [Fig. 1], the decoupling and coupling steps indicated above are implemented by means of:
[0074] - to the switches 112 which are left in the open state during the calibration phase, And
[0075] - to a switch 138 interposed between the input of the first control circuit 136 and one of the outputs of the first ILO 108, which is closed during the calibration phase, and
[0076] - to a switch 140 interposed between the output of the first conversion circuit 118 and the input of the first storage circuit 122 (i.e., between the output of the amplifier 120 and the first electrode of the capacitor 124 in the example described) and which is set to the open state during the calibration phase, and
[0077] - to a switch 142 interposed between the output of the first control circuit 136 and the first storage circuit 122 (the first electrode of the capacitance 124 in the example described) which is put in the closed state during the calibration phase.
[0078] In the described embodiment, the first control circuit 136 comprises at least:
[0079] - an integrating filter 144 configured to perform high-pass or high-pass filtering band of one of the signals Vout+ and V„ul;
[0080] - a comparator 146 configured to compare an output signal from the filter integrator 144 with a threshold value (corresponding, in the example of [Fig.1], to a value of a reference electrical potential corresponding to the mass of the device 100);
[0081] - a control device 148 configured to determine maximum values and minimum of the control voltage of the first ILO 108 for which the first ILO 108 can lock (corresponding to the control voltage values for points 10 and 12 of the curve shown in [Fig. 3]), and to determine the initialization value of VtUne-
[0082] In the described embodiment, the first storage circuit 122 is initialized by the circuit 136 with an output value from the first conversion circuit 118 after the first ILO 108 is locked to the frequency N.Fref. During this calibration, or initialization, phase, switches 112 and 140 are opened during a phase of lock acquisition by the first ILO 108. After this phase, these switches are closed to form a feedback loop that stabilizes the self-oscillation frequency of the first ILO 108 so that the error current obtained at the output of the first conversion circuit 118 is zero for a desired phase shift of the output signal relative to the reference signal, which has been defined by selecting the offset voltage(s) applied to the first conversion circuit 118.
[0083] By way of example, the control device 148 can implement, to calculate the initialization voltage value to be stored in the first storage circuit 122, an algorithm comprising the following steps: - initialization of the first storage circuit 122 to a minimum voltage value and disconnection of the phase shift and calibration tracking circuits (first sampler 110, first integrator 114 and first conversion circuit 118); - increase of the control voltage value of the first ILO 108 (using for example a digital-to-analog converter) until a latch detection signal is activated, and storage of this value which corresponds to the minimum value of VtUne allowing frequency latching of the first ILO 108 (i.e. the voltage value at point 10 of [Fig.3]); - increasing the control voltage value of the first ILO 108 until the lock detection signal is deactivated, and storing this value which corresponds to the maximum Vtune value allowing locking in frequency of the first ILO 108 (i.e. the value of the voltage at point 12 of [Fig.3]); - calculation and storage, in the first storage circuit 122, of the initialization value from the maximum and minimum values of Vtune, for example such that it is equal to the average of these two values, and disconnection of the first control circuit 136 from the other elements of the device 100; - reconnection of the phase shift and calibration circuits previously disconnected for the calibration phase.
[0084] After the calibration phase, the device 100 is used by disconnecting the first control circuit 136 from the other elements of the device 100. The voltage stored in the first storage circuit 122 allows the sensitivity curve of the first ILO 108 to be fixed, which is centered on the self-oscillation frequency of the first ILO 108, exactly at the frequency N.Fref, i.e., aligned with the frequency of the input signal of the first ILO 108. The loop formed stabilizes with the control voltage stored in the first storage circuit 122, which is applied to the control input of the first ILO 108, corresponding to the desired phase difference between the input and output of the first ILO 108.
[0085] Thus, by setting the offset voltage(s) applied to the first conversion circuit 118, different phase or phase shift values can be applied between the input signal and the output signal of the device 100. The signals of interest provided by the device 100, having the desired frequency and phase, correspond to the Vout+ and V„ul signals obtained at the output of the first ILO 108.
[0086] Figure [Fig.4] schematically represents device 100 according to a second embodiment.
[0087] In this second embodiment, the device 100 includes at least a second ILO 150 having at least two injection inlets coupled to the outputs of the first ILO 108.
[0088] The device 100 according to the second embodiment also includes a second sampler 152, for example, similar to the first sampler 110 and coupled to the outputs of the second ILO 150; a second integrator 154, for example, similar to the first integrator 114 and coupled to the outputs of the second sampler 152; a second conversion circuit 156, for example, similar to the first conversion circuit 118 and coupled to the outputs of the second integrator 154; a second storage circuit 158, for example, similar to the first storage circuit 122 and coupled to the output of the second conversion circuit 156; and an initialization circuit for the value stored in the second storage circuit 158, for example, similar to the initialization circuit for the value stored in the first storage circuit 122 and comprising a second control circuit 160, for example, similar to the first control circuit 136. In this second embodiment, the second ILO 150 is part of a loop comprising the second sampler 152, the second integrator 154, the second conversion circuit 156 and the second storage circuit 158, coupled together in a manner analogous to the first sampler 110, the first integrator 114, the first conversion circuit 118 and the first storage circuit 122 with the first ILO 108.
[0089] During operation of the device 100 according to this second embodiment, the phase control and tracking loop of the signal delivered by the first ILO 108 can be activated first so that the first ILO 108 is in a state where the output signal of the first ILO 108 is in phase with the reference signal (which corresponds to a zero offset voltage Voff applied to the amplifier 120). Then, the phase control and tracking loop of the second ILO 150 can be activated so as to obtain the desired phase shift at the output of the second ILO 150.
[0090] In the example above, the two phase control and frequency tracking loops of each of the ILOs 108, 150 are activated one after the other. Alternatively, these control loops can operate simultaneously.
[0091] During the calibration phase, the steps of the algorithm implemented by the first control device 148 can be implemented for the first ILO 108, then analogous steps can be implemented by the second control device of the second control circuit 160 for the second ILO 150. The phase shifting and calibration tracking circuits can operate in the background for both ILOs 108, 150 simultaneously.
[0092] The use of several ILOs in the device 100 makes it possible to suppress spurious signals that may appear at the output around the N.Fref frequency. In the example described in relation to [Fig. 4], two ILOs are used in cascade. Alternatively, a larger number of cascaded ILOs can be used.
[0093] In this second embodiment, each of the ILOs 108, 150 can introduce a different phase shift between its input and its output, and the overall phase shift between the output of the second ILO 150 and the reference signal corresponds to the cumulative phase shift over the entire chain formed in the device 100. The phase control and monitoring mechanism described previously for the first embodiment can be applied to each of the ILOs 108, 150 of the device 100 according to the second embodiment.
[0094] In the device 100 according to the second embodiment, the signals of interest having the desired frequency and phase correspond to the signals obtained at the output of the second ILO 150.
[0095] The various examples and variants previously described for the first embodiment can be applied to this second embodiment.
[0096] Figure [Fig. 5] schematically represents device 100 according to a third embodiment.
[0097] Compared to the device 100 according to the first embodiment previously described, the device 100 according to this third embodiment further comprises a controlled delay line 162, or VCDL (“Voltage Controlled Delay Line” in English) coupled to the input of the pulsed oscillator 102, and more particularly between the input of the pulsed oscillator 102 and the output of the generator 128. This VCDL 162 is configured to apply to the reference signal REF a delay equivalent to a phase shift equal to 0° or 90° or 180° or 270° at the frequency N.FR ef.
[0098] The VCDL 162 allows a large, fixed-value phase shift to be applied to the reference signal Ref, thus selecting the quadrant in which the phase shift generated by the other elements of the device 100 is applied. The phase shift applied by the VCDL 162 to the reference signal Ref is multiplied by N at the output of the device 100. Therefore, to select a phase shift of 0°, 90°, 180°, or 270°, the reference signal Ref is phase-shifted by [0°, 90°, 180°, or 270°] / N by the VCDL 162. This can be implemented, for example, by using a VCDL 162 applying a selectable delay value corresponding to 0 seconds for a phase shift of 0°, to _1--L Fref '4^ seconds for a phase shift of 90°, at -1— _L seconds for a phase shift of 180°, and at Fref-2N _L_ JL second for a phase shift of 270°. Fref4N
[0099] Furthermore, although not shown in [Fig.5], the device 100 according to the third embodiment includes a control circuit for example similar to the first control circuit 136 previously described.
[0100] Compared to the first and second embodiments described, the device 100 according to the third embodiment makes it possible to generate a phase shift covering the four quadrants (0 to 90°, 90° to 180°, 180° to 270°, and 270° to 0°) or located within one of these four quadrants. The signals of interest provided by the device 100, having the desired frequency and phase, correspond to the signals Vout+ and V,^ obtained at the output of the first ILO 108.
[0101] Such a VCDL 162 can be used within the device 100 according to the first or second embodiment described above.
[0102] Alternatively, the use of a different delay circuit than the VCDL 162 can be envisaged, such as several polyphase filters that can be switched.
[0103] The various examples and variants previously described for the first and second embodiments can be applied to this third embodiment. Furthermore, device 100 according to this third embodiment can include several cascaded coupled ILOs as previously described in connection with the second embodiment.
[0104] Figure [Fig.6] schematically represents device 100 according to a fourth embodiment.
[0105] Compared to device 100 according to the first embodiment described above, device 100 according to the fourth embodiment includes a second ILO 164. Furthermore, the first ILO 108 is multi-phase and has several outputs on which signals are delivered with phase shifts that are multiples of 90°. For example, such a first ILO 108 may include an I / Q differential oscillator. In the example of [Fig. 6], the first ILO 108 has four outputs on which the phase shifts obtained are 0°, 90°, 180°, and 270°.Device 100 further includes a selection circuit 166 for selecting one of the outputs of the first ILO 108 and coupling it to the injection input of the second ILO 164, thus choosing the quadrant in which the second ILO 164, coupled to the other elements of device 100, will apply a controlled phase shift of the desired value via the application of the control voltage to the second ILO 164, as previously described for the first ILO 108 of device 100 according to the first embodiment. In this fourth embodiment, the signals of interest provided by device 100, having the desired frequency and phase, correspond to the Vout+ and V„ul signals obtained at the output of the second ILO 164.
[0106] Furthermore, although not shown in [Fig.6], the device 100 according to the fourth embodiment includes a control circuit for example similar to the first control circuit 136 previously described.
[0107] The various examples and variants previously described for the first and second embodiments can be applied to this fourth embodiment.
[0108] Figure 7 schematically represents a multi-signal generation device 200 according to a particular embodiment.
[0109] The architecture of the device 100 described above can be used within a multi-signal generation device 200 comprising several signal generation devices 100 as described above and configured to receive as input the same reference signal Ref, with different offset voltages applied to the ILOs of these devices 100. In the example of [Fig. 7], the device 200 comprises two devices 100, each similar to the one described above in connection with [Fig. 6], and sharing the same source 130. Since the devices 100 here share the same periodic signal emitted by the source 130, the phase shift generated at the output of each device 100 is aligned to the same reference. This makes it possible to generate a stable and precise relative phase shift between the different branches signal generation. This is also true if the devices 100 are integrated into separate integrated circuits, because the signal from the common source 130, of much lower frequency, can be distributed easily and accurately to all the separate integrated circuits, thus ensuring phase coherence between them.
[0110] Although not shown in [Fig.7], each of the devices 100 includes a control circuit, for example, similar to the first control circuit 136 previously described.
[0111] Such a device 200 can form a MIMO architecture or analog phased networks with phase shift of the output LO signal. In the example described here, the signals of interest having the desired frequency and phase correspond to the Vout+ and V„ul signals obtained at the output of the second ILO 164 of each of the devices 100.
[0112] Alternatively, the device 200 may include devices 100 according to one of the other embodiments previously described.
[0113] In all embodiments, the calibration phase can be implemented, for example, at each start-up of device 100 or 200, or at different time intervals, regular or not.
[0114] Devices 100 and 200 are particularly well-suited to high-speed wireless, wired, or waveguide applications requiring beamforming or precise phase tuning of the LO signal, as well as radar applications. The use of a low-frequency reference signal that sets the phase reference allows for the distribution and synchronization of much higher-frequency, widely separated LO signal generators, ensuring phase coherence across the entire system. The phase control and tracking loop provides a stabilization mechanism against VT variations and device aging. High integer frequency multiplication N enables very good phase noise performance.The phase-locking and phase-tracking acquisition circuits used in device 100 stabilize the locking state of one or more ILOs at the center of their sensitivity curve, resulting in optimal phase noise performance.
[0115] In all modes, variants, and embodiments, the device 100 enables the generation of a LO signal by directly introducing a controlled and calibrated phase shift onto this LO signal at the time of its generation. The signal generation implemented by the device 100 can be based on frequency multiplication by a high-order integer. The device 100 can be used, for example, to generate a modulated or continuous-wave signal in the millimeter wave (mmW) or sub-THz range, with phase adjustment and control of the generated signal relative to a reference input signal whose frequency is much lower and from which the output signal is generated. The resulting phase shift is controlled, stable, and precise.
[0116] In all embodiments, the phase shift obtained is not or very little impacted by the VT variations undergone by the device 100 or 200.
[0117] In all embodiments, the device 100 or 200 does not require continuous monitoring of the frequency locking of the ILO(s).
[0118] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0119] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. Signal generation device (100), comprising at least: - a pulsed oscillator (102) configured to receive as input a periodic signal of frequency FRef and to generate on an output a TORP signal corresponding to a train of oscillations of frequency equal to M.FRef, of duration less than TRef = l / FRef and repeated periodically at the frequency FRef, with M an integer greater than 1; - a first injection-locked oscillator (108) comprising at least one injection input coupled to the output of the pulsed oscillator (102) and comprising at least two outputs on which periodic signals Vout+ and V„ul of frequency equal to N.FRef, with N an integer greater than 1, and phase-shifted by 180° relative to each other are intended to be delivered; - a first sampler (110) configured to sample the signals Vout+ and V„ul at the frequency FRef; - a first integrator (114) configured to deliver at output signals Vo+ and V„ each resulting from an integration of one of the signals Vout+ and V„ul sampled at the frequency FRef; - a first conversion circuit (118) comprising at least one control input configured to receive at least one offset voltage Voff, and configured to deliver an output signal of value proportional to the voltage difference (Voff + Vo+) - (Voff + V„) and intended to be applied to a control input of the first injection-locked oscillator (108).
2. Signal generation device (100) according to claim 1, wherein the first conversion circuit (118) comprises at least one voltage-to-current amplifier (120).
3. A signal generation device (100) according to any one of claims 1 or 2, wherein the first conversion circuit (118) has two control inputs configured to each receive one of the offset voltages Voff+ and Voff_, and is configured to deliver the output signal with a value proportional to the voltage difference (Voff+ + Vo+) - (Voff. + Vo_).
4. Signal generation device (100) according to any one of the preceding claims, wherein the first sampler (110) has at least two switches (112) configured to be controlled at the FRef frequency and each receive as input one of the signals Vout+ and V„ul.
5. Signal generation device (100) according to any one of the preceding claims, wherein the first integrator (114) comprises at least two electrical capacitors (116) each comprising a first electrode to which one of the sampled Vout+ and V„ul signals is intended to be applied and a second electrode to which a reference electrical potential is intended to be applied.
6. Signal generation device (100) according to any one of the preceding claims, further comprising a first storage circuit (122) for a control voltage of the first injection-locked oscillator (108), configured to apply said control voltage to the control input of the first injection-locked oscillator (108).
7. Signal generation device (100) according to claim 6, wherein the first storage circuit (122) comprises at least one electrical capacitance.
8. Signal generation device (100) according to any one of claims 6 or 7, further comprising a first circuit for initializing the value of the control voltage stored in the first storage circuit (122).
9. Signal generation device (100) according to claim 8, wherein the first initialization circuit is configured to implement a calibration phase of the signal generation device (100) during which the following steps are implemented: - disconnect the first storage circuit (122) from an output of the first conversion circuit (118), and disconnect the outputs of the first injection-locked oscillator (108) from inputs of the first sampler (110); - to couple a first control circuit (136) between the outputs of the first injection-locked oscillator (108) and the first storage circuit (122); - to calculate and store, in the first storage circuit (122), an initialization voltage value such that its application to the control input of the first injection-locked oscillator (108) causes the first injection-locked oscillator (108) to lock onto the frequency N.FRef and that a phase shift between the periodic signals Vout+ and Vout. and the TORP signal is zero.
10. Signal generation device (100) according to claim 9, wherein the first control circuit (136) comprises at least: - an integrator filter (144) configured to perform high-pass or band-pass filtering of the Vout+ and V„ul signals; - a comparator (146) configured to compare an output signal of the integrator filter (144) with a threshold value; - a control device (148) configured to determine maximum and minimum values of the control voltage of the first injection-locked oscillator (108) for which the first injection-locked oscillator (108) can lock in frequency, and to determine the value of the initialization voltage which is between these maximum and minimum values.
11. Signal generation device (100) according to any one of the preceding claims, further comprising a signal shaping circuit (132) configured to receive as input a sinusoidal signal of frequency FRef and to deliver on the input of the pulsed oscillator (102) the periodic signal of frequency FRef in the form of a square wave signal.
12. Signal generation device (100) according to any one of the preceding claims, further comprising a controlled delay line (162) coupled to the input of the pulsed oscillator (102) and configured to apply to the periodic signal of frequency FRef a phase shift of 0° or 90° or 180° or 270°.
13. Signal generation device (100) according to any one of the preceding claims, comprising at least one second injection-locked oscillator (150, 164) having at two injection inputs coupled to the outputs of the first injection-locked oscillator (108).
14. Signal generation device (100) according to claim 13, wherein: - the first injection-locked oscillator (108) is multi-phase and has several outputs on which signals are delivered with phase shifts that are multiples of 90°, or - the second injection-locked oscillator (150) is part of a feedback loop comprising at least a second sampler (152), a second integrator (154), and a second conversion circuit (156), coupled together in a manner analogous to the first sampler (110), the first integrator (114) and the first conversion circuit (118) with the first injection-locked oscillator (108).
15. Multi-signal generation device (200) comprising at least several signal generation devices (100) according to any one of the preceding claims, and configured to receive as input the same periodic signal of frequency FRef and different offset voltages Voff each intended for one of the signal generation devices (100).