Quantum device and method for realizing a quantum device

Abstract

Quantum device and method for realizing a quantum device. Method for realizing a quantum device (100), comprising: - supplying and realizing, on one face of a substrate: o of semiconductor portions and a central semiconductor region arranged between the portions and separated from each of the portions by dielectric regions, then o deposition of a grid stack, then o deposition of a hard mask covering a grid conductor, then structuring of the hard mask forming an opening above the central region; - realization of a mask comprising a pattern defining grids and a pattern comprising a coupling electrode (140) extending in the central region, between the dielectric regions; then, - etching the grid stack and the central region according to the pattern of the mask, the remaining portions of the grid stack forming the grids and a remaining portion of the central region forming the coupling electrode.Figure for the abridged version: Fig. 14.

Description

Title of the invention: Quantum device and method for implementing a quantum device. Technical field

[0001] This description relates generally to the field of quantum information and quantum electronic devices, and in particular to the fabrication or realization of a quantum device with quantum bits (also called "quantum bits" or qubits). Prior art

[0002] In the approach considered, qubits are formed by quantum dots that confine elementary charges (electrons or holes) within a semiconductor. Quantum information is, for example, encoded on the spin of these charges. The confinement of the elementary charges is achieved, within the semiconductor, in the three spatial dimensions (length, width, and height) of the quantum dots. This confinement can be achieved structurally, for example, by alternating materials along at least one spatial dimension, and / or electrostatically, for example, by applying an electric potential to the portion of conductive material in which the quantum dots are to be formed.

[0003] Charge detection can be achieved by capacitive coupling between the information-containing quantum dot and another detection quantum dot formed in the same semiconductor region. Tunneling coupling between the two quantum dots is unavoidable in this configuration. Such detection can be implemented by two grids arranged directly opposite each other and covering the same semiconductor region in which the quantum dots are formed. In this case, the grids must be positioned relative to each other with a distance that is neither too great to prevent detection from occurring, nor too small to avoid unwanted charge exchange between the quantum dots. The realization of such grids is therefore challenging.

[0004] Alternatively, non-invasive charge detection can be achieved by realizing the detection quantum dot in a portion of semiconductor separate from that in which the information-containing quantum dot is realized, these semiconductor portions being separated from each other by a dielectric material. A drawback of such a solution is that, in the presence of this dielectric, the capacitive coupling between the quantum dots can drop significantly if the quantum dots are too far apart, thus reducing In this case, the detection sensitivity obtained. Obtaining strong capacitive coupling between quantum dots therefore requires a small distance between the quantum dots, which is difficult to achieve in the presence of the dielectric between the semiconductor portions.

[0005] US patent 2023 / 0177376 A1 proposes a suitable structure for implementing non-invasive charge detection in which the capacitive coupling between two quantum dots formed in two neighboring semiconductor nanowires is enhanced by the presence of a coupling element between these nanowires, the electrical potential of this coupling element being left floating. In this patent, the coupling element partially covers the nanowires, which can lead to the formation of parasitic quantum dots in the portions of the nanowires covered by the coupling element. Furthermore, the alignment between the gates and the coupling element is difficult to achieve. Summary of the invention

[0006] There is a need to propose a quantum device, as well as a method for realizing such a quantum device, suitable for implementing non-invasive charge detection and not presenting at least some of the disadvantages of existing methods.

[0007] An embodiment overcomes all or part of the drawbacks of known methods for implementing a quantum device and proposes a method for implementing a quantum device, comprising at least: - provision of a substrate comprising one face, then creation on the face of the substrate: • of at least two semiconductor portions and at least one central semiconductor region disposed between the portions and separated from each of the portions by dielectric insulating regions, then • deposition of a grid stack comprising at least one grid dielectric covered by at least one grid conductor, then • application of at least one hard mask covering the grid conductor, then structuring of the hard mask to form at least one opening directly above the central region; - creation of a mask comprising a pattern defining at least two grids and a pattern comprising at least one coupling electrode extending in the central region, between the dielectric isolation regions; Then, - engraving of the grid stack and central region according to the pattern of the mask such that remaining portions of the grid stack form the grids and at least a remaining portion of the central region forms the coupling electrode.

[0008] According to a particular embodiment, the portions and the central region are made by etching a semiconducting layer of the substrate, or by oxidizing parts of the semiconducting layer of the substrate such that unoxidized parts of the semiconducting layer form the portions and the central region.

[0009] According to a particular embodiment, the substrate is of the SOI type and the semiconductor layer corresponds to the surface semiconductor layer of the substrate, or in which the semiconductor layer forms a semiconductor heterostructure.

[0010] According to a particular embodiment, the central region has a rectangular shape in a plane parallel to the face of the substrate, and / or the portions form nanowires.

[0011] According to a particular embodiment, the structuring of the hard mask is implemented according to an engraving pattern whose edges are arranged vertically above the dielectric insulation regions next to which the central region is arranged.

[0012] According to a particular embodiment, the pattern of the mask used for engraving the grid stack and the central region defines, on parts of each of the portions, several grids intended to be arranged parallel to each other.

[0013] According to a particular embodiment, the pattern of the mask used for the etching of the grid stack and the central region comprises at least one part defining the coupling electrode and which is aligned with at least one other part of the mask defining at least one pair of grids, or the pattern of the mask used for the etching of the grid stack and the central region comprises several parts defining several coupling electrodes and which are each aligned with other parts of the mask defining pairs of grids.

[0014] According to a particular embodiment, the pattern of the mask used for the engraving of the grid stack and the central region defines several distinct coupling electrodes spaced apart from each other.

[0015] According to a particular embodiment, the method further comprises, after the etching of the grid stack and the central region, the creation of dielectric spacers against the lateral walls of the grids.

[0016] According to a particular embodiment, the method further comprises, after the etching of the grid stack and the central region, a semiconductor epitaxy at least from the semiconductor of the coupling electrode.

[0017] According to a particular embodiment, the process further comprises, after the etching of the grid stack and the central region, at least a silicification of at least a part of the grids and the coupling electrode.

[0018] According to a particular embodiment, the process further comprises, after the silicification of the grids and the coupling electrode, the creation of electrical contacts coupled to the grids.

[0019] According to a particular embodiment, at least one of the grids covers at least a part of one of the semiconductor portions, or at least one of the grids does not cover the semiconductor portions.

[0020] According to a particular embodiment, the coupling electrode is arranged opposite lateral faces of the semiconductor portions.

[0021] According to a particular embodiment, the grid stack is etched such that the same number of grids cover at least part of each of the semiconductor portions.

[0022] A quantum device is also proposed, comprising at least: - a substrate, - two semiconductor portions arranged on one face of the substrate, - grids configured to electrostatically control quantum dots formed in semiconductor portions, - at least one coupling electrode disposed on the substrate face, electrically isolated from each of the semiconductor portions by dielectric isolation regions, extending into a central region disposed between the dielectric isolation regions, and configured so that its electrical potential is floating, and in which the coupling electrode is arranged opposite the lateral faces of the semiconductor portions.

[0023] According to a particular embodiment, the semiconductor portions are arranged, with respect to the face of the substrate, at the same level as the coupling electrode.

[0024] According to a particular embodiment, the coupling electrode extends parallel to an elongation direction of each of the grids, and preferably in a manner aligned with respect to one of the grids.

[0025] According to a particular embodiment, the coupling electrode extends opposite parts of the semiconductor portions intended to form several pairs of quantum dots.

[0026] According to a particular embodiment, the quantum device further comprises at least one semiconductor charge carrier reservoir connected to at least one end of the semiconductor portions.

[0027] According to a particular embodiment, the coupling electrode does not cover the upper faces of the semiconductor portions.

[0028] According to a particular embodiment, the coupling electrode comprises at least one conductive material, for example at least one of the following materials: metal, silicide, doped semiconductor.

[0029] According to a particular embodiment, the charge carrier reservoir is part of at least one semiconductor portion extending perpendicularly to a direction of elongation of the semiconductor portions.

[0030] According to a particular embodiment, a portion of the dielectric spacers is arranged directly above the dielectric insulation regions.

[0031] According to a particular embodiment, at least one of the grids is configured to form, in at least one of the semiconductor portions, quantum dots for information storage. In a particular configuration, at least one other of the grids is configured to form, in the other of the semiconductor portions, quantum dots for charge detection.

[0032] According to a particular embodiment, the coupling electrode is configured to increase the capacitive coupling between at least one pair of quantum dots, each formed in one of the semiconductor portions. Brief description of the drawings

[0033] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0034] - [Fig.l], [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7], [Fig.8], Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 and Fig. 14 represent steps in an example of a process for realizing a quantum device according to a particular embodiment;

[0035] - [Fig. 15] and [Fig. 16] represent examples of variants of a device quantum obtained by implementing a realization process according to a particular embodiment. Description of the implementation methods

[0036] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional, and material properties. In the figures, to facilitate their reading, the different elements and the different material layers are not shown at the same scale relative to each other.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, various elements of the quantum device peripheral to those described below are not detailed.

[0038] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected or coupled (in English "coupled") to each other, it means that these two elements can be connected or linked through one or more other elements.

[0039] In the following description, when reference is made to absolute position qualifiers, such as "front," "back," "top," "bottom," "left," "right," etc., or relative position qualifiers, such as "above," "below," "superior," "inferior," etc., or to orientation qualifiers, such as "horizontal," "vertical," etc., reference is made, unless otherwise specified, to the orientation of the figures. However, these terms do not imply anything about the actual position and orientation of the quantum device when it is used.

[0040] Unless otherwise indicated, the ranges of values ​​shown include the limits of these ranges.

[0041] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0042] An example of a method for realizing a quantum device 100 is described below in relation to figures 1 to 14.

[0043] The device 100 is made from a semiconductor substrate 102. In the described embodiment, the substrate 102 is a silicon-on-insulator (SOI) substrate. In this example, the substrate 102 comprises a support layer 103, for example, of silicon, a buried dielectric layer 104, or BOX (Buried Oxide), for example, of SiO2, and a semiconducting surface layer 106, for example, of silicon. The thickness of the surface layer 106 is, for example, between 5 nm and 20 nm. In [Fig. 1], view a) is a perspective view of the substrate 102 and view b) is a cross-sectional view parallel to the axis AA visible in view a).

[0044] Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate in which the semiconducting surface layer 106 comprises a semiconductor other than silicon. According to another embodiment, the substrate 102 may be a bulk substrate comprising a thick layer of semiconductor.

[0045] According to another embodiment, the surface layer 106 may correspond to a semiconductor heterostructure comprising, for example, a SiGe layer arranged between two silicon layers. Other types of semiconductor heterostructures are possible.

[0046] At least two semiconductor portions 108 and at least one central semiconductor region 110, disposed between the portions 108 and separated from the portions 108 by dielectric insulating regions 112, are made at a face 114 of substrate 102. In the described embodiment example, portions 108 and region 110 are derived from surface layer 106. Furthermore, face 114 of substrate 102 corresponds, in this example, to the main face of substrate 102 formed by surface layer 106.

[0047] According to a first example, the portions 108 and the region 110 are formed by engraving the surface layer 106 according to the pattern corresponding to the portions 108 and the region 110. According to a second example corresponding to that shown in [Fig. 2], the portions 108 and the region 110 can be formed by carrying out an oxidation of parts of the layer 106 such that the unoxidized parts of the layer 106 form the portions 108 and the region 110. The dielectric insulation regions 112 correspond to oxidized parts of the layer 106.

[0048] In the described embodiment, each of the portions 108 forms a semiconductor nanowire. These nanowires extend along a principal direction such that they are oriented parallel to each other. Each nanowire has, for example, a length (dimension parallel to the principal direction of the nanowire, and parallel to the X-axis in [Fig. 2]) between 100 nm and 2000 nm, and a width (dimension perpendicular to the length of the nanowire and parallel to the plane formed by the face 114 of the substrate 102, and parallel to the Y-axis in [Fig. 2]) between 20 nm and 100 nm. Alternatively, other shapes, dimensions, and arrangements of the portions 108 are possible. Furthermore, the device 100 may comprise more than two portions 108.

[0049] In the described embodiment, the region 110 has a rectangular shape in a plane parallel to the face 114. Alternatively, this shape of the region 110 may be non-rectangular. Furthermore, a length of the region 110 parallel to the length of the nanowires formed by the portions 108 may be equal to that of each nanowire, and a width (dimension parallel to the width of the nanowires) of the region 110 may be between 20 nm and 2000 nm.

[0050] In the described embodiment, the insulating dielectric regions 112 extend along a principal direction parallel to the nanowires formed by the portions 108. Each of the insulating dielectric regions 112 has, for example, a length (dimension parallel to the principal direction of the insulating dielectric region 112, and parallel to the X-axis in [Fig. 2]) equal to that of the nanowire formed by the portion against which the region 112 is positioned, for example, between 20 nm and 2000 nm, and a width (dimension perpendicular to the length of the insulating dielectric region 112 and parallel to the plane formed by the face 114 of the substrate 102, and parallel to the Y-axis in [Fig. 2]) between 2 nm and 50 nm. Alternatively, other shapes, dimensions, and arrangements of the insulating dielectric regions 112 are possible. Furthermore, the device 100 may include more than two dielectric isolation regions 112.

[0051] In the described example, the step(s) implemented to produce the portions 108, the central region 110 and the dielectric insulation regions 112 also produce reservoirs of semiconductor charge carriers 116 connected to the ends of the nanowires formed by the portions 108. For this purpose, the pattern of the etching or oxidation implemented includes that of the reservoirs 116 so that remaining portions of the layer 106 (unetched or unoxidized portions) form these reservoirs 116. In the device 100 obtained at the end of the fabrication process, the reservoirs 116 serve as charge carrier reservoirs for the quantum dots formed in the portions 108, both for those used for information storage and those used for charge detection.

[0052] In one embodiment, it is possible that only one reservoir 116 is made and connected to only one end of the nanowires formed by the portions 108.

[0053] On [Fig.2], view a) corresponds to a perspective view of the assembly obtained at the end of this stage of realization of the portions 108, the regions 110 and the reservoirs 116, and view b) corresponds to a cross-sectional view parallel to the axis AA visible on view a).

[0054] Alternatively, the ends of the nanowires formed by the portions 108 can be free, i.e., not connected to charge carrier reservoirs. An example of portions 108 forming nanowires and of the central region 110 obtained according to such an alternative is shown in [Fig. 3], which represents a top view of the face 114 of the substrate 102 at which the portions 108 and the region 110 are formed.

[0055] A grid stack 118 comprising at least one grid dielectric 120 covered by at least one grid conductor 122, and at least one hard mask 124 covering the grid conductor 122, is deposited on the side of the face 114 of the substrate 102, covering in particular the portions 108, the central region 110, the insulating dielectric regions 112 and any reservoirs 116. According to one embodiment, the grid dielectric 120 comprises, for example, SiO2 or a high permittivity dielectric such as HfO2, the grid conductor 122 comprises a TiN / polysilicon bilayer, and the hard mask 124 comprises a semiconductor nitride such as Si3N4 or a SiO2 / Si3N4 bilayer. The thicknesses of the layers of the grid stack 118 are for example: - grid dielectric 120: between 2 nm and 40 nm, or between 2 nm and 10 nm, and for example equal to 5 nm; - TiN of grid conductor 122: between 2 nm and 20 nm, for example equal to 5 nm; - polysilicon of grid conductor 122: between 5 nm and 50 nm, for example equal to 25 nm; - hard mask 124: between 20 nm and 50 nm, for example equal to 40 nm.

[0056] On [Fig.4], view a) corresponds to a perspective view of the assembly obtained after the deposition of the grid stack 118 and view b) corresponds to a cross-sectional view parallel to the axis AA visible on view a).

[0057] The hard mask 124 is then structured. In the example described, a first portion of the hard mask 124, positioned directly above the central region 110, is etched. A first mask 126 is then created on the grid stack 118. In the example shown in [Fig. 5], the first mask 126 is created by depositing layers 128, 130, and 132 comprising SiOC (layer 128), SiARC (layer 130), and a resin (layer 132). The pattern of the first mask 126 is defined in layer 132 and is such that edges 134 of this pattern are positioned directly above edges of the insulating dielectric regions 112, next to which the central region 110 is located.In other words, remaining portions of layer 132 are arranged above the dielectric insulation regions 112, portions 108 (and reservoirs 116 in the example described) as well as the regions of substrate 102 located outside the part in which the central region 110 is arranged. On [Fig.5], view a) corresponds to a perspective view of the assembly obtained after the realization of the first mask 126 and view b) corresponds to a cross-sectional view parallel to the axis AA visible on view a).

[0058] An engraving is then carried out such that the pattern of the first mask 126 is engraved, or transferred, into the hard mask 124. As a result of this engraving, the layers of the first mask 126 have been consumed or selectively removed, and the first part of the hard mask 124 disposed above the region 110 is removed, forming an opening 127 through the hard mask 124 above the central region 110. In this example, edges 129 of the opening 127 are disposed above edges of the dielectric insulation regions 112 next to which the central region 110 is disposed. This engraving is stopped on the grid conductor 122. On [Fig.6], view a) corresponds to a perspective view of the assembly obtained at the end of the engraving of the first part of the hard mask 124 and view b) corresponds to a cross-sectional view parallel to the axis AA visible on view a).

[0059] A second mask 136 comprising an etched pattern defining at least two grids 138, each covering, for example, at least a portion of one of the sections 108, and at least one coupling electrode 140 extending in the central region 110, between the dielectric regions 112, is then produced. The coupling electrode(s) 140 are described as floating because their electrical potential is intended to be floating during the use of the device 100. In the described embodiment, the material layers 131, 133, and 135 used to produce the second mask 136 are of a similar nature to the layers 128, 130, and 132 used to produce the first mask 126. As can be seen in [Fig. 6], the material of layer 131 fills the volume of the opening 127 formed by the previous engraving in the hard mask 124. The pattern of the second mask 136 is defined in layer 135. In [Fig. 7], view a) corresponds to a perspective view of the assembly obtained at the end of this step, view b) corresponds to a sectional view along the axis AA visible in view a), view c) corresponds to a sectional view along the axis BB visible in view a), view d) corresponds to a sectional view along the axis CC visible in view a) and view e) corresponds to a sectional view along the axis DD visible in view a) of a part of the assembly obtained.

[0060] In the described embodiment, the pattern of the second mask 136 comprises, on portions of each of the sections 108, the patterns of several grids 138 intended to be arranged parallel to one another (one pattern defining eight grids on each section 108 in the example of [Fig. 7]). Furthermore, in the described example, the pattern of the second mask 136 also comprises the patterns of several distinct coupling electrodes 140 spaced apart from one another (one pattern defining two coupling electrodes in the example of [Fig. 7]). In addition, in the described example, the pattern of the second mask 136 defines the pattern of each of the coupling electrodes 140 such that it is aligned with the pattern of one of the grids 138 covering each of the sections 108.

[0061] In the example of [Fig.7], two straight portions of the layer 135 each define the pattern of two grids 138 and of one of the coupling electrodes 140 aligned with these grids 138. Each of the other remaining portions of the layer 135 defines the pattern of one of the other grids 138 such that the ends of these other grids are arranged vertically above the edges of the dielectric regions 112 next to which the region 110 is arranged.

[0062] An engraving of the grid stack 118 and the central region 110 according to the pattern of the second mask 136 is then implemented such that remaining portions of the grid stack 128 form the grids 138 and one or more remaining portions of the region 110 form the coupling electrode(s) 140 in the central region 110 and extending between the dielectric insulation regions 112.

[0063] Figure 8 represents the structure obtained after the first part of this etching, during which the materials of layers 131, 133, and 135 are consumed or selectively removed during this first part of the etching of the hard mask 124, and which is stopped on the grid conductor 122 except in the regions where the hard mask 124 had already been etched (previous etching carried out according to the pattern of the first mask 126) and which are not covered by the second mask 136. In these regions, the grid conductor 122 is partially, or totally consumed by this engraving. In [Fig.8], the different views are similar to those in [Fig.7].

[0064] Figure 9 represents the structure obtained at the end of this etching process, during which the grid conductor 122 not protected by the hard mask 124 is etched, and which is stopped on the grid dielectric 120 for regions that have not been previously etched, and on the grid dielectric 120 or on the semiconductor of layer 106 for regions included in the pattern of the first mask 126 or the second mask 136 only (i.e. on the coupling electrodes 140 and, in this example, on the reservoirs 116), or on the buried dielectric 104 of the substrate 102 for regions included in the pattern of the first mask 126 and in the pattern of the second mask 136. This second part of the etching process allows the patterns of the masks 126 and 136 to be transferred into the grid conductor 122.

[0065] As an alternative to the steps described above, the second mask 136 can be such that the grids 138 obtained do not cover the semiconductor portions 108.

[0066] Removing the grid dielectric 120 is optional, depending on its thickness. If the thickness is sufficiently small, the sub-ideal selectivity of the spacer etching and / or the surface preparation chemistry performed before epitaxy may consume the grid dielectric 120.

[0067] In [Fig.9], the different views are similar to those in Figures 7 and 8. In this example, the grid engraving can be completed so as to consume layer 120.

[0068] Thus, the previous etching steps are implemented in the presence of four types of regions: those exposed through the pattern of the first mask 126 only, those exposed through the pattern of the second mask 136 only, those exposed through the patterns of the first and second masks 126, 136, and those which are not exposed by the patterns of the first and second masks 126, 136. In the example described, at the end of these etchings, the coupling electrode(s) 140 are found to be arranged opposite lateral faces of the semiconductor portions 108.

[0069] Dielectric spacers 142 are then made against the lateral sides of the grids 138. For example, these dielectric spacers 142 are obtained by implementing one or more conformal deposits of dielectric materials, followed by an anisotropic etching step removing the deposited materials except against the lateral walls of the grids 138. In the example of [Fig. 10] (with view a) corresponding to a perspective view of the assembly obtained at the end of this step and view b) corresponding to a cross-sectional view along the CC axis visible in view a), these dielectric spacers 142 fill the spaces between the grids 138.

[0070] Selective semiconductor epitaxy is then implemented from the semiconductor parts not covered by another material, i.e. the semi conductor of the coupling electrode(s) 140 and, in this example, that of the reservoirs 116. On [Fig. 11], view a) corresponds to a perspective view of the assembly obtained at the end of this step, view b) corresponds to a cross-sectional view along the axis CC visible on view a), and view c) corresponds to a cross-sectional view along the axis DD visible on view a).

[0071] The remaining portions of the hard mask 124, which are present here on the grids 138, are then removed. This removal is achieved, for example, by engraving the hard mask 124. In [Fig. 12], view a) corresponds to a perspective view of the assembly obtained at the end of this step and view b) corresponds to a cross-sectional view along the axis CC visible in view a).

[0072] A silicification of the grids 138 and of the coupling electrode(s) 140 is then carried out. In the example described, this silicification is also performed on the semiconductor of the reservoirs 116. In [Fig. 13], the silicide portions are designated by reference numeral 144. In [Fig. 13], the different views are similar to those of Figures 7 to 9.

[0073] The device 100 is completed by making electrical contacts 146 coupled to the grids 138 and, in the example described, to the reservoirs 116. These electrical contacts 146 are made on the silicide portions 144 of the grids 138 and the reservoirs 116.

[0074] In the device 100, no electrical contact is made on the coupling electrode(s) 140 whose electrical potential is intended to be floating, i.e. undefined by applying an electrical potential on the coupling electrode(s) 140.

[0075] In the embodiment described above in connection with Figures 1 to 14, two coupling electrodes 140 are made to increase the capacitive coupling between two quantum dots formed in one of the portions 108 and two other quantum dots formed in the other of the portions 108, i.e. two pairs of quantum dots.

[0076] Alternatively, it is possible that only one of the two coupling electrodes 140 previously described is made, or that a larger number of coupling electrodes 140 are made.

[0077] According to another embodiment, it is possible for all the quantum dots to have their capacitive coupling with another quantum dot enhanced by the coupling electrodes 140. In such an embodiment, each of the quantum dots to be formed in the portions 108 is aligned with one of the coupling electrodes 140. Such a configuration is shown schematically in [Fig. 15] for three pairs of quantum dots symbolically designated by the reference numeral 148, and for which one of the coupling electrodes is arranged between each pair of quantum dots. In this configuration, as in the embodiment example As previously described, the coupling electrodes 140 do indeed rest on an insulator, corresponding to the buried dielectric 104 in this example.

[0078] In the embodiment described above in connection with Figures 1 to 14, the first mask 126 and the etching used to form the aperture 127 are made before the second mask 136 and the etching forming the grids 138 and the coupling electrode(s) 140. Alternatively, the second mask 136 and the etching forming the grids 138 and the coupling electrode(s) 140 can be made before the first mask 126 and the etching used to form the aperture 127. According to another embodiment, the second mask 136 can be made before the structuring of the hard mask 124.

[0079] In the examples described above, each of the coupling electrodes 140 has a rectangular shape in a plane parallel to plane 114.

[0080] In the examples described above, each coupling electrode 140 is used to increase the capacitive coupling between a pair of quantum dots 148, each formed in one of the portions 108. Alternatively, the coupling electrode 140 or one of the coupling electrodes 140 may be common to several pairs of quantum dots 148. An example of such a variant is shown schematically in [Fig. 16], in which the coupling electrode 140 shown is common to three pairs of quantum dots 148 controlled by six separate grids 138.

[0081] In the examples described above, the shape of the coupling electrode 140 or of each of the coupling electrodes 140 is the same at the level of each of the dielectric insulation regions 112. Alternatively, it is possible to have several coupling electrodes 140 whose cross-sections are of different dimensions along the axis parallel to the length of the nanowires formed by the portions 108.

[0082] In the previously described embodiment, the portions 108 are coupled to regions 116 forming load-carrier reservoirs, or source and drain regions, common to both portions 108. Alternatively, these load-carrier reservoirs can be formed by elements other than the regions 116, common or not to the portions 108.

[0083] In the embodiment described above, the coupling element(s) whose electrical potential is left floating do not cross the portions 108, i.e. are not made on a part of the portions 108, thus avoiding any risk of formation of parasitic quantum dot in the portions 108 by the coupling electrode(s) 140.

[0084] In all embodiments, the presence of one or more coupling electrodes 140, whose electrical potential is floating, between the quantum dots 148, in their vicinity, allows for better capacitive coupling between the quantum dots 148 compared to a configuration in which the dots The quantum elements would be separated by the same distance but without the presence of this metallic element. The coupling electrode(s) 140 are not connected to the nanowires 108, which allows the device 100 to implement non-invasive charge detection.

[0085] In the various embodiments, one of the portions 108 can be used to form quantum dots 148 for information storage, and the other portion 108 can be used to form quantum dots used for charge detection. Alternatively, both portions 108 can be used to form quantum dots 148 for information storage.

[0086] In all embodiments, the two lithography-engravings implemented make it possible to create an over-engraving in the semiconductor layer 106 where the patterns of the two masks used overlap, and thus precisely define the portions 108, the coupling electrode(s) 140, the dielectric isolation regions 112 and any reservoirs 116.

[0087] In the described process, self-alignment between the grids and the coupling electrode is obtained.

[0088] With the described process, the quantum device 100 can be realized in a single semiconductor nanowire.

[0089] With the described process, it is possible to choose the number of dielectric isolation regions formed in the quantum device 100.

[0090] The process described above allows the realization of at least one coupling electrode disposed opposite the lateral sides of the semiconductor portions and which does not cover the upper faces of the semiconductor portions, thus avoiding the formation of parasitic quantum dots.

[0091] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0092] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. For example, the precise nature of the deposition and engraving steps implemented can be chosen according to, in particular, the material(s) to be deposited or engraved, as well as the thicknesses of the material to be deposited or engraved.

Claims

1.

2. Demands Method for making a quantum device (100), comprising at least: - provision of a substrate (102) comprising a face (114), then fabrication on face (114) of the substrate (102): • of at least two semiconductor portions (108) and at least one central semiconductor region (110) disposed between the portions (108) and separated from each of the portions (108) by dielectric insulating regions (112), then • deposition of a grid stack (118) comprising at least one grid dielectric (120) covered by at least one grid conductor (122), then • deposition of at least one hard mask (124) covering the grid conductor (122), then structuring of the hard mask (124) to form at least one opening (127) directly above the central region (110); - production of a mask (136) comprising a pattern defining at least two grids (138) and a pattern comprising at least one coupling electrode (140) extending in the central region (110), between the dielectric isolation regions (112); Then, - engraving of the grid stack (118) and of the central region (110) according to the pattern of the mask (136) such that remaining portions of the grid stack (118) form the grids (138) and at least a remaining portion of the central region (110) forms the coupling electrode (140). A method according to claim 1, wherein the portions (108) and the central region (110) are made by etching a semiconducting layer (106) of the substrate (102), or by oxidizing parts of the semiconducting layer (106) of the substrate (102) such that unoxidized parts of the semiconducting layer (106) form the portions (108) and the central region (110).

3. Method according to claim 2, wherein the substrate (102) is of the SOI type and the semiconductor layer (106) corresponds to the semiconductor surface layer of the substrate (102), or wherein the semiconductor layer (106) forms a semiconductor heterostructure.

4. A method according to any one of the preceding claims, wherein the central region (110) has a rectangular shape in a plane parallel to the face (114) of the substrate (102), and / or wherein the portions (108) form nanowires.

5. A method according to any one of the preceding claims, wherein the hard mask structuring (124) is implemented according to an etching pattern of which edges (134) are arranged vertically above the dielectric insulation regions (112) next to which the central region (110) is disposed.

6. A method according to any one of the preceding claims, wherein the pattern of the mask (136) used for engraving the grid stack (118) and the central region (110) defines, on parts of each of the portions (108), several grids (138) intended to be arranged parallel to each other.

7. A method according to claim 6, wherein the pattern of the mask (136) used for etching the grid stack (118) and the central region (110) comprises at least one part defining the coupling electrode (140) and which is aligned with at least one other part of the mask (136) defining at least one pair of grids (138), or wherein the pattern of the mask (136) used for etching the grid stack (118) and the central region (110) comprises several parts defining several coupling electrodes (140) and which are each aligned with other parts of the mask (136) defining pairs of grids (138).

8. A method according to any one of the preceding claims, wherein the pattern of the mask (136) used for etching the grid stack (118) and the central region (110) defines several distinct coupling electrodes (140) spaced apart from each other.

9. A method according to any one of the preceding claims, further comprising, after the engraving of the grid stack (118) and the central region (110), an embodiment of dielectric spacers (142) against side walls of the grids (138).

10. A method according to any one of the preceding claims, further comprising, after etching the grid stack (118) and the central region (110), a semiconductor epitaxy at least from the coupling electrode semiconductor (140).

11. A method according to any one of the preceding claims, further comprising, after the etching of the grid stack (118) and the central region (110), at least a silicification of at least a part of the grids (138) and the coupling electrode (140).

12. A method according to claim 11, further comprising, after the silicification of the grids (138) and the coupling electrode (140), the making of electrical contacts (146) coupled to the grids (138).

13. A method according to any one of the preceding claims, wherein at least one of the grids (138) covers at least a part of one of the semiconductor portions (108), or wherein at least one of the grids (138) does not cover the semiconductor portions (108).

14. A method according to any one of the preceding claims, wherein the coupling electrode (140) is arranged opposite lateral faces of the semiconducting portions (108).

15. A method according to any one of the preceding claims, wherein the grid stack (118) is etched such that the same number of grids (138) cover at least part of each of the semiconductor portions (108).

16. Quantum device (100), comprising at least: - a substrate (102), - two semiconductor portions (108) disposed on one face (114) of the substrate (102), - grids (138) configured to electrostatically control quantum dots formed in the semiconductor portions (108), - at least one coupling electrode (140) disposed on the face (114) of the substrate, electrically isolated from each of the semiconductor portions (108) by dielectric isolation regions (112), extending into a central region (110) disposed between the dielectric isolation regions (112), and configured so that its electrical potential is floating, and in which the coupling electrode (140) is arranged opposite lateral faces of the semiconducting portions (108).

17. Quantum device (100) according to claim 16, wherein the semiconductor portions (108) are arranged, with respect to the face (114) of the substrate (102), at the same level as the coupling electrode (140).

18. Quantum device (100) according to any one of claims 16 or 17, wherein the coupling electrode (140) extends parallel to an elongation direction of each of the grids (138), and preferably in a manner aligned with respect to one of the grids (138).

19. Quantum device (100) according to any one of claims 16 to 18, wherein the coupling electrode (140) extends opposite portions of the semiconductor portions (108) intended to form several pairs of quantum dots.

20. Quantum device (100) according to any one of claims 16 to 19, further comprising at least one semiconductor charge carrier reservoir (116) connected to at least one end of the semiconductor portions (108).

21. Quantum device (100) according to any one of claims 16 to 20, wherein the coupling electrode (140) does not cover the upper faces of the semiconductor portions (108).

22. Quantum device (100) according to any one of claims 16 to 21, wherein the coupling electrode (140) comprises at least one conductive material, for example at least one of the following materials: metal, silicide, doped semiconductor.

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