Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a substrate and a driving circuit layer, wherein the driving circuit layer comprises: pixel circuits (P) arranged in an array, a plurality of first scanning signal lines (G1) and a plurality of second scanning signal lines (G2); the driving circuit layer comprises: a plurality of first discharge structures (E1) and / or a plurality of second discharge structures (E2); at least one first discharge structure (E1) is electrically connected to a first scanning signal line (G1) and a second scanning signal line (G2), respectively; the first scanning signal line (G1) and the second scanning signal line (G2) electrically connected to the first discharge structure (E1) are connected to the same row of pixel circuits (P); at least one second discharge structure (E2) is electrically connected to a first scanning signal line (G1) and a second scanning signal line (G2), respectively; and the first scanning signal line (G1) and the second scanning signal line (G2) electrically connected to the second discharge structure (E2) are connected to adjacent rows of pixel circuits (P) and are located between adjacent rows of pixel circuits (P).

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a display panel, comprising: a substrate and a driving circuit layer disposed on the substrate, wherein the substrate comprises: a display area and a non-display area, the driving circuit layer comprising: a pixel circuit arranged in an array in the display area, and a plurality of first scanning signal lines and a plurality of second scanning signal lines at least partially located in the display area, at least one pixel circuit being electrically connected to the first scanning signal line and the second scanning signal line, respectively, the first scanning signal line and the second scanning signal line electrically connected to the pixel circuit being located on either side of the pixel circuit and extending at least partially along a first direction;

[0006] The driving circuit layer includes: multiple first discharge structures and / or multiple second discharge structures, at least one first discharge structure is electrically connected to a first scanning signal line and a second scanning signal line, respectively, the first scanning signal line and the second scanning signal line electrically connected to the first discharge structure are connected to the same row of pixel circuits, at least one second discharge structure is electrically connected to the first scanning signal line and the second scanning signal line, respectively, the first scanning signal line and the second scanning signal line electrically connected to the second discharge structure are connected to adjacent rows of pixel circuits, and are located between adjacent rows of pixel circuits.

[0007] In an exemplary embodiment, the driving circuit layer further includes: a gate driving circuit located in a non-display area, a first low-level power line and a second low-level power line extending along a second direction, and a plurality of first scan output lines and a plurality of second scan output lines extending at least partially along the first direction, the first direction and the second direction intersect, the first low-level power line and the second low-level power line are arranged in the same layer, the first scan output line and the second scan output line are arranged in the same layer, and the first low-level power line is located on a side of the first scan output line close to the substrate;

[0008] The first scan output line is electrically connected to the first scan signal line, the second scan output line is electrically connected to the second scan signal line, and the gate drive circuit is electrically connected to the first low-level power line, the second low-level power line, the plurality of first scan output lines, and the plurality of second scan output lines, respectively;

[0009] The first low level power line and the second low level power line are located on a side of the gate driving circuit close to the display area, and the first low level power line is located on a side of the second low level power line away from the display area.

[0010] In an exemplary embodiment, the driving circuit layer further includes: a plurality of data signal lines at least partially located in the display area, and a plurality of electrostatic discharge circuits and a plurality of electrostatic release lines located in the non-display area, wherein the data signal lines and the electrostatic release lines at least partially extend along the second direction, and the data signal lines and the electrostatic release lines are arranged in the same layer;

[0011] The pixel circuit is electrically connected to the data signal line, and at least one electrostatic release circuit is electrically connected to the data signal line and the electrostatic release line respectively.

[0012] In an exemplary embodiment, the driving circuit layer further includes: a first power supply line at least partially located in the display area, and a first power supply line, a second power supply line, and a second power supply line located in the non-display area, the first power supply line providing a high-level signal, and the second power supply line providing a low-level signal;

[0013] The first power supply line and the second power supply line are arranged in the same layer, the first power supply line is located on a side of the first power supply line away from the substrate, the second power supply line is located on a side of the second power supply line close to the substrate, the first power supply line is located on a side of the second power supply line away from the display area, and the second power supply line partially surrounds the first power supply line, and the second power supply line is arranged on a side of the first power supply line away from the display area and surrounds at least one side of the display area;

[0014] The pixel circuit is electrically connected to the first power line, the orthographic projection of the first power supply line on the substrate partially overlaps with the orthographic projections of the first power line and the second power line on the substrate, and is electrically connected to the first power line, the orthographic projection of the second power line on the substrate partially overlaps with the multiple electrostatic release lines and the orthographic projection of the first power line on the substrate, and is electrically connected to the multiple electrostatic release lines and the second power supply line respectively.

[0015] In an exemplary embodiment, the driving circuit layer further includes: a first signal connection line and a second signal connection line, the first signal connection line and the second signal connection line at least partially extending along a first direction, the first signal connection line and the second signal connection line being electrically connected to different electrostatic discharge circuits, respectively;

[0016] The pixel circuit includes: a first pixel circuit and a second pixel circuit, wherein the second pixel circuit is located on a side of the first pixel circuit close to the second power supply line;

[0017] An orthographic projection of a first scan signal line electrically connected to the first pixel circuit on the substrate partially overlaps with an orthographic projection of the first scan output line on the substrate, and the first pixel circuit is electrically connected to the first scan output line; an orthographic projection of a second scan signal line electrically connected to the first pixel circuit on the substrate partially overlaps with an orthographic projection of the second scan output line on the substrate, and the first pixel circuit is electrically connected to the second scan output line;

[0018] The orthographic projection of the second scanning signal line electrically connected to the second pixel circuit on the substrate partially overlaps with the orthographic projection of the first signal connection line on the substrate, and is electrically connected to the first signal connection line. The orthographic projection of the first scanning signal line electrically connected to the second pixel circuit on the substrate partially overlaps with the orthographic projection of the second signal connection line on the substrate, and is electrically connected to the second signal connection line.

[0019] In an exemplary embodiment, the driving circuit layer further includes: a plurality of first low-level connection portions arranged at intervals and a plurality of second low-level connection portions arranged at intervals, the first low-level connection portions and the second low-level connection portions are arranged on the same layer, and the first low-level connection portions are located on a side of the first low-level power line away from the substrate.

[0020] In an exemplary embodiment, when the display panel includes the first discharge structure, the first scan signal line is provided with a first protrusion extending along the second direction, the first protrusion being located on a side of the first scan signal line close to an electrically connected pixel circuit, the first protrusion including: a first tip;

[0021] The second scanning signal line is provided with a second protrusion extending along the second direction, the second protrusion is located on a side of the second scanning signal line close to the electrically connected pixel circuit, and the second protrusion includes: a second tip;

[0022] A first tip of a first scanning signal line electrically connected to the first discharge structure and a second tip of a second scanning signal line electrically connected to the first discharge structure are arranged opposite to each other, and an orthographic projection of the first discharge structure on the substrate at least partially overlaps with an orthographic projection of the first tip of the first scanning signal line electrically connected to the first discharge structure and an orthographic projection of the second tip of the second scanning signal line electrically connected to the first discharge structure on the substrate.

[0023] In an exemplary embodiment, when the display panel includes: the second discharge structure, the first scan signal line is provided with a third protrusion extending at least partially along the second direction, the third protrusion is located on a side of the first scan signal line close to the gate driving circuit, and the third protrusion includes: a third tip;

[0024] The second scanning signal line is further provided with a fourth protrusion extending at least partially along the second direction, the fourth protrusion being located on a side of the second scanning signal line close to the gate driving circuit, the fourth protrusion comprising: a fourth tip;

[0025] The third tip of the first scan signal line electrically connected to the second discharge structure is arranged opposite to the fourth tip of the second scan signal line electrically connected to the second discharge structure, and an orthographic projection of the second discharge structure on the substrate at least partially overlaps with an orthographic projection of the third tip of the first scan signal line electrically connected to the second discharge structure and an orthographic projection of the fourth tip of the second scan signal line electrically connected to the second discharge structure on the substrate.

[0026] In an exemplary embodiment, when the display panel includes: a second discharge structure, the second discharge structure is electrically connected to the first scan signal line through the first signal line, and is electrically connected to the second scan signal line through the second scan output line;

[0027] The first signal line includes: a first scan output line or a second signal connection line. When the pixel circuit electrically connected to the first scan signal line is a first pixel circuit, the first signal line is a first scan output line. When the pixel circuit electrically connected to the first scan signal line is a second pixel circuit, the first signal line is a second signal connection line.

[0028] In an exemplary embodiment, the first signal line electrically connected to the second discharge structure is provided with a fifth protrusion extending at least partially along the second direction, the fifth protrusion being located on a side of the first signal line close to the gate driving circuit, the fifth protrusion comprising: a fifth tip;

[0029] The second scan output line electrically connected to the second scan signal line is provided with a sixth protrusion extending at least partially along the second direction, the sixth protrusion being located on a side of the second scan output line close to the gate driving circuit, the sixth protrusion comprising: a sixth tip;

[0030] The fifth tip of the first signal line electrically connected to the second discharge structure and the sixth tip of the second scan output line electrically connected to the second discharge structure are arranged opposite to each other, and an orthographic projection of the second discharge structure on the substrate at least partially overlaps with an orthographic projection of the fifth tip of the first signal line electrically connected to the second discharge structure and an orthographic projection of the sixth tip of the second scan output line electrically connected to the second discharge structure on the substrate.

[0031] In an exemplary embodiment, the second discharge structure is further electrically connected to a second low-level power line or a second low-level connection portion.

[0032] In an exemplary embodiment, when the second discharge structure is electrically connected to the second low-level power line, the second low-level power line is provided with a seventh protrusion extending along the first direction, the seventh protrusion including: a seventh tip;

[0033] A virtual straight line passing through the seventh tip and extending along the first direction is located between the other two tips at least partially overlapping with the second discharge structure on the substrate;

[0034] The orthographic projection of the second discharge structure on the substrate also partially overlaps with the orthographic projection of the seventh tip of the electrically connected second low-level power line on the substrate.

[0035] In an exemplary embodiment, when the second discharge structure is electrically connected to the second low-level connection portion, the second low-level connection portion is provided with an eighth protrusion extending along the first direction, the eighth protrusion including: an eighth tip;

[0036] A virtual straight line passing through the eighth tip and extending along the first direction is located between the other two tips at least partially overlapping with the second discharge structure on the substrate;

[0037] The orthographic projection of the second discharge structure on the substrate also partially overlaps with the orthographic projection of the eighth tip of the electrically connected second low-level connection portion on the substrate.

[0038] In an exemplary embodiment, the driving circuit layer further includes: at least one discharge structure among a third discharge structure, a fourth discharge structure, a fifth discharge structure, and a sixth discharge structure;

[0039] The third discharge structure is electrically connected to a scan signal line close to a non-display area and an electrostatic release line close to a gate drive circuit, respectively. The fourth discharge structure is electrically connected to a second low-level power line and an electrostatic release line close to a gate drive circuit, respectively. The fifth discharge structure is electrically connected to a first low-level power line and a second low-level power line, respectively. The sixth discharge structure is electrically connected to a first power supply line and a second power supply line, respectively. The scan signal line is a first scan signal line or a second scan signal line.

[0040] In an exemplary embodiment, the first discharge structure, the second discharge structure, the third discharge structure, the fourth discharge structure, the fifth discharge structure, and the sixth discharge structure are disposed in the same layer.

[0041] In an exemplary embodiment, when the driving circuit layer includes: the third discharge structure or the fourth discharge structure, the electrostatic release line close to the gate driving circuit includes: a first connecting line extending along the first direction and a second connecting line extending along the second direction, and the first connecting line is electrically connected to the second connecting line.

[0042] In an exemplary embodiment, the scanning signal line electrically connected to the third discharge structure is provided with a ninth protrusion extending along the second direction, the ninth protrusion being located on a side of the scanning signal line close to the electrostatic discharge circuit, the ninth protrusion including: a ninth tip;

[0043] The first connection line of the electrostatic discharge line electrically connected to the third discharge structure is provided with a tenth protrusion, the tenth protrusion is located on a side of the first connection line close to the electrostatic discharge circuit, and the tenth protrusion includes: a tenth tip;

[0044] The ninth tip of the scanning signal line electrically connected to the third discharge structure and the tenth tip of the electrostatic release line electrically connected to the third discharge structure are arranged opposite to each other.

[0045] The orthographic projection of the third discharge structure on the substrate at least partially overlaps with the orthographic projections of the ninth tip of the scan signal line electrically connected thereto and the tenth tip of the electrostatic discharge line electrically connected thereto.

[0046] In an exemplary embodiment, the third discharge structure is electrically connected to the scan signal line through the first signal connection line.

[0047] In an exemplary embodiment, the first signal connection line electrically connected to the third discharge structure is provided with an eleventh protrusion extending along the second direction, the eleventh protrusion is located on a side of the first signal connection line close to the electrostatic discharge circuit, and the eleventh protrusion includes: an eleventh tip;

[0048] The first connection line of the electrostatic release line electrically connected to the third discharge structure is provided with a tenth protrusion, the tenth protrusion is located on a side of the first connection line of the electrostatic release line close to the electrostatic release circuit, the tenth protrusion includes: a tenth tip;

[0049] The eleventh tip of the first signal connection line electrically connected to the third discharge structure and the tenth tip of the electrostatic release line electrically connected to the third discharge structure are arranged opposite to each other.

[0050] The orthographic projection of the third discharge structure on the substrate at least partially overlaps with the orthographic projections of the eleventh tip of the electrically connected first signal connection line and the tenth tip of the electrically connected electrostatic discharge line on the substrate.

[0051] In an exemplary embodiment, the electrostatic release line electrically connected to the fourth discharge structure includes: a twelfth protrusion, the twelfth protrusion is located on a side of the first connection line of the electrostatic release line close to the gate driving circuit, the twelfth protrusion includes: a twelfth tip;

[0052] The second low-level power line is further provided with a thirteenth protrusion extending along the first direction, the thirteenth protrusion is located on a side of the second low-level power line close to the display area, and the thirteenth protrusion includes a thirteenth tip;

[0053] The twelfth tip of the electrostatic discharge line electrically connected to the fourth discharge structure is arranged opposite to the thirteenth tip of the second low-level power line;

[0054] The orthographic projection of the fourth discharge structure on the substrate at least partially overlaps with the orthographic projection of the twelfth tip of the electrically connected electrostatic discharge line on the substrate and the orthographic projection of the thirteenth tip of the second low-level power line on the substrate.

[0055] In an exemplary embodiment, the first low-level power supply line is provided with a fourteenth protrusion, the fourteenth protrusion being located on a side of the first low-level power supply line close to the second power supply line, the fourteenth protrusion comprising: a fourteenth tip;

[0056] The second low-level power line is provided with a fifteenth protrusion, the fifteenth protrusion is located on a side of the second low-level power line close to the second power supply line, and the fifteenth protrusion includes: a fifteenth tip;

[0057] The fourteenth tip of the first low-level power line is arranged opposite to the fifteenth tip of the second low-level power line;

[0058] The orthographic projection of the fifth discharge structure on the substrate at least partially overlaps with the orthographic projection of the fourteenth tip of the first low-level power line on the substrate and the orthographic projection of the fifteenth tip of the second low-level power line on the substrate.

[0059] In an exemplary embodiment, the first power supply line is provided with a sixteenth protrusion extending along the second direction, the sixteenth protrusion is located on a side of the first power supply line close to the second power supply line, and the sixteenth protrusion includes a sixteenth tip;

[0060] The second power supply line is provided with a seventeenth protrusion extending along the second direction, the seventeenth protrusion being located on a side of the second power supply line close to the first power supply line, and the seventeenth protrusion including a seventeenth tip; the sixteenth tip of the first power supply line is disposed opposite to the seventeenth tip of the second power supply line;

[0061] An orthographic projection of the sixth discharge structure on the substrate at least partially overlaps with an orthographic projection of the sixteenth tip of the first power supply line on the substrate and an orthographic projection of the seventeenth tip of the second power supply line on the substrate.

[0062] In an exemplary embodiment, the driving circuit layer further includes: a plurality of first scan connection portions, a plurality of second scan connection portions, a plurality of data connection portions, a plurality of power connection portions, a plurality of sensing signal lines, a plurality of sensing connection portions, and a power connection line;

[0063] The first scan connection portion is electrically connected to the first scan signal line, the second scan connection portion is electrically connected to the second scan signal line, the data connection portion is electrically connected to the data signal line, the power connection portion is electrically connected to the first power line, the sensing signal line is electrically connected to the pixel circuit and the sensing connection portion, and the power connection line is electrically connected to the second power line and the second power supply line respectively.

[0064] In an exemplary embodiment, the driving circuit layer includes: a blocking layer, a semiconductor layer, a first conductive layer, and a second conductive layer;

[0065] The shielding layer at least includes: a second power line;

[0066] The semiconductor layer at least includes: one or more of the first discharge structure to the sixth discharge structure;

[0067] The first conductive layer at least includes: a first power supply line, a second power supply line, a first low-level power line, a second low-level power line, a first scan signal line, a second scan signal line, a data connection part, a power connection part and a sensing connection part.

[0068] The second conductive layer includes at least: a data signal line, a first power line, a first signal connection line, a second signal connection line, an electrostatic release line, a first scan output line, a second scan output line, a first scan connection part, a second scan connection part, a power connection line, a first low-level connection part and a second low-level connection part.

[0069] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display panel.

[0070] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0072] FIG1 is a structural block diagram of a display panel;

[0073] FIG2 is a schematic structural diagram of a display panel;

[0074] FIG3 is a schematic diagram of an equivalent circuit of a pixel circuit;

[0075] FIG4 is an enlarged view of area C in the display panel provided in FIG1 ;

[0076] FIG5 is a second enlarged view of area C in the display panel provided in FIG1 ;

[0077] FIG6 is a third enlarged view of area C in the display panel provided in FIG1 ;

[0078] FIG7 is a fourth enlarged view of area C in the display panel provided in FIG1 ;

[0079] FIG8 is a fifth enlarged view of area C in the display panel provided in FIG1 ;

[0080] FIG9 is an enlarged view of area C in the display panel provided in FIG1 ;

[0081] FIG10 is an enlarged view of the area C1 in the display panel provided in FIG4 to FIG9;

[0082] FIG11 is an equivalent circuit diagram of a shift register;

[0083] FIG12 is an enlarged view of area C2 in the display panel provided in FIG4 to FIG9;

[0084] FIG13 is an enlarged view of area C3 in the display panel provided in FIG4 to FIG9;

[0085] FIG14 is an enlarged view of area C4 in the display panel provided in FIG4 ;

[0086] FIG15 is an enlarged view of area C4 in the display panel provided in FIG5 ;

[0087] FIG16 is an enlarged view of area C4 in the display panel provided in FIG6 and FIG8;

[0088] FIG17 is an enlarged view of area C4 in the display panel provided in FIG7 and FIG9;

[0089] FIG18 is an enlarged view of area C5 in the display panel provided in FIG4 ;

[0090] FIG19 is an enlarged view of area C5 in the display panel provided in FIG5 ;

[0091] FIG20 is an enlarged view of area C5 in the display panel provided in FIG6 and FIG8;

[0092] FIG21 is an enlarged view of area C5 in the display panel provided in FIG7 and FIG9;

[0093] FIG22 is an enlarged view of area C6 in the display panel provided in FIG8 and FIG9;

[0094] FIG23 is an enlarged view of area C7 in the display panel provided in FIG8 and FIG9;

[0095] FIG24 is a schematic diagram of a pixel circuit in a shielding layer;

[0096] FIG25 is a schematic diagram of a pixel circuit after a semiconductor layer is formed;

[0097] FIG26 is a schematic diagram of a pixel circuit after forming a first conductive layer;

[0098] FIG27 is a schematic diagram of a pixel circuit after forming a second conductive layer;

[0099] FIG28 is a schematic diagram of an electrostatic discharge circuit in a semiconductor layer;

[0100] FIG29 is a schematic diagram of an electrostatic discharge circuit after forming a first conductive layer;

[0101] FIG30 is a schematic diagram of an electrostatic discharge circuit after forming a second conductive layer;

[0102] FIG31 is an equivalent circuit diagram of an electrostatic discharge circuit. DETAILED DESCRIPTION

[0103] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0104] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are only structural schematics, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the figures.

[0105] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0106] In this specification, for convenience, terms such as "center," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to describe the positional relationships of components with reference to the accompanying drawings. This is intended solely to facilitate the description of this specification and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of the components may vary depending on the direction in which the components are described. Therefore, the terms are not limited to those described in this specification and may be appropriately replaced as appropriate.

[0107] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0108] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0109] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0110] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0111] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0112] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0113] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0114] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0115] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0116] In the display industry, display panels are often manufactured using an oxide process to achieve high uniformity. However, ultra-large display panels are prone to generating transient high static electricity during use due to their large size, which can damage the panel and reduce its reliability.

[0117] Figure 1 is a block diagram of the structure of a display panel, and Figure 2 is a schematic diagram of the structure of a display panel. As shown in Figures 1 and 2, the display panel includes a display area AA and a non-display area AA' located on at least one side of the display area. The display panel may include a timing controller, a data signal driver, and a scan signal driver located in the non-display area, and a pixel array located in the display area. The pixel array may include multiple first scan signal lines G1 and multiple second scan signal lines G2, multiple data signal lines Data, and multiple sub-pixels.

[0118] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, and may provide clock signals, scan start signals, etc. suitable for the specifications of the scan signal driver to the scan signal driver.

[0119] In an exemplary embodiment, the data signal driver may generate a data voltage to be provided to the data signal line Data using a grayscale value and a control signal received from the timing controller. For example, the data signal driver may sample a grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal line Data in units of sub-pixel rows.

[0120] In an exemplary embodiment, the scan signal driver may generate scan signals to be provided to the plurality of first scan signal lines G1 and the plurality of second scan signal lines G2 by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide scan signals having on-level pulses to the plurality of first scan signal lines G1 and the plurality of second scan signal lines G2. For example, the scan signal driver may be configured in the form of a shift register and may generate scan signals in such a manner that the scan start signal provided in the form of on-level pulses is sequentially transmitted to the next stage circuit under the control of a clock signal.

[0121] In an exemplary embodiment, the sub-pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding first scan signal line and a second scan signal line, where i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th first scan signal line and the i-th second scan signal line and is connected to the j-th data signal line.

[0122] In an exemplary embodiment, a display panel may include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units including a first subpixel that emits light of a first color, a second subpixel that emits light of a second color, and a third subpixel that emits light of a third color. The first, second, and third subpixels each include a pixel circuit and a light-emitting device. The pixel circuits in the first, second, and third subpixels are respectively connected to a scan signal line and a data signal line. The pixel circuits are configured to receive a data voltage transmitted by the data signal line under the control of the first and second scan signal lines and output a corresponding current to the light-emitting device. The light-emitting devices in the first, second, and third subpixels are respectively connected to the pixel circuits of their respective subpixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel circuits of their respective subpixels.

[0123] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0124] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

[0125] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the sub-pixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0126] In other exemplary embodiments, a pixel unit may include four sub-pixels. In an exemplary embodiment, the first sub-pixel may be a red sub-pixel that emits red (R) light, the second sub-pixel may be a blue sub-pixel that emits blue (B) light, the third sub-pixel P3 may be a green sub-pixel that emits green (G) light, and the fourth sub-pixel may be a white sub-pixel that emits white (W) light. In an exemplary embodiment, the shape of the sub-pixels in a pixel unit may be rectangular, diamond, pentagonal, or hexagonal, and may be arranged horizontally, vertically, in a square, or diamond shape, etc., which is not limited in this disclosure.

[0127] In an exemplary embodiment, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 3 is a schematic diagram of an equivalent circuit of a pixel circuit. As shown in Figure 3, the pixel circuit has a 3T1C structure and may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3), a capacitor C, and six signal lines (a data signal line Data, a first scan signal line G1, a second scan signal line G2, a sense signal line Sense, a first power line VDD, and a second power line VSS). In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a sensing transistor. The gate electrode of the first transistor T1 is coupled to the first scan signal line G1, the first electrode of the first transistor T1 is coupled to the data signal line Data, and the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2. The first transistor T1 is configured to receive a data signal transmitted by the data signal line Data under the control of the first scan signal line G1, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1. The first electrode of the second transistor T2 is coupled to the first power line VDD. The second electrode of the second transistor T2 is coupled to the first electrode of the light-emitting device OLED. The second transistor T2 is configured to generate a corresponding current at its second electrode under control of the data signal received at its gate electrode. The gate electrode of the third transistor T3 is coupled to the second scan signal line G2. The first electrode of the third transistor T3 is coupled to the sense signal line Sense. The second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2. The third transistor T3 is configured to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. The first electrode of the light-emitting device OLED is coupled to the second electrode of the second transistor T2. The second electrode of the light-emitting device OLED is coupled to the second electrode of the second transistor T2. The second electrode of the light-emitting device OLED is coupled to the second power line VSS. The light-emitting device OLED is configured to emit light of a corresponding brightness in response to the current flowing in the second electrode of the second transistor T2.

[0128] In an exemplary embodiment, the third transistor T3 may extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the sensing timing.

[0129] In an exemplary embodiment, the capacitor C includes: a first plate C1 and a second plate C2, the second plate C2 of the capacitor C is coupled to the gate electrode of the second transistor T2, the first plate of the capacitor C is coupled to the second electrode of the second transistor T2, and the capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0130] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.

[0131] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0132] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0133] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel to form a low-temperature polycrystalline oxide (LTPO) display panel can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0134] Figure 4 is an enlarged first view of region C in the display panel provided in Figure 1 , Figure 5 is an enlarged second view of region C in the display panel provided in Figure 1 , Figure 6 is an enlarged third view of region C in the display panel provided in Figure 1 , Figure 7 is an enlarged fourth view of region C in the display panel provided in Figure 1 , Figure 8 is an enlarged fifth view of region C in the display panel provided in Figure 1 , and Figure 9 is an enlarged sixth view of region C in the display panel provided in Figure 1 As shown in Figures 4 to 9 , the display panel provided in the embodiments of the present disclosure may include: a substrate and a drive circuit layer disposed on the substrate. The substrate may include: a display area and a non-display area. The drive circuit layer includes: pixel circuits P arranged in an array in the display area, and a plurality of first scan signal lines G1 and a plurality of second scan signal lines G2 located at least partially in the display area. At least one pixel circuit P is electrically connected to the first scan signal line G1 and the second scan signal line G2, respectively. The first scan signal lines G1 and the second scan signal lines G2 electrically connected to the pixel circuit P are located on either side of the pixel circuit, and extend at least partially along a first direction D1.

[0135] In exemplary embodiments, as shown in Figures 4 to 9 , the driving circuit layer may further include: a plurality of first discharge structures E1 and / or a plurality of second discharge structures E2. At least one first discharge structure E1 is electrically connected to a first scan signal line G1 and a second scan signal line G2, respectively. The first scan signal line G1 and the second scan signal line G2 electrically connected by the first discharge structure are connected to the same row of pixel circuits. At least one second discharge structure E2 is electrically connected to the first scan signal line G1 and the second scan signal line G2, respectively. The first scan signal line G1 and the second scan signal line G2 electrically connected by the second discharge structure E2 are connected to adjacent rows of pixel circuits and are located between adjacent rows of pixel circuits. Figures 4 to 9 illustrate a display panel including the first discharge structure E1 and the plurality of second discharge structures E2.

[0136] The present disclosure can connect the first scan signal lines and the second scan signal lines electrically connected to all pixel circuits to form a discharge path by providing a first discharge structure and / or a second discharge structure. When static electricity is generated, the static electricity can be discharged to the first scan signal line and the second scan signal line to avoid damage to the display panel caused by instantaneous high static electricity, thereby improving the reliability of the display panel.

[0137] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. In an exemplary embodiment, the rigid substrate may be made of a material such as glass or quartz, and the flexible substrate may be made of a material such as polyimide (PI). The flexible substrate may have a single-layer structure or a laminated structure composed of an inorganic material layer and a flexible material layer, which is not limited in this disclosure.

[0138] In an exemplary embodiment, the display panel may further include: a light-emitting structure layer disposed on a side of the drive circuit layer away from the substrate; and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. Exemplarily, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0139] In an exemplary embodiment, the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the driving transistor through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding color under the drive of the anode and the cathode.

[0140] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0141] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0142] In an exemplary embodiment, the display panel of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and the present disclosure is not limited here.

[0143] In an exemplary embodiment, as shown in Figures 4 to 9, the driving circuit layer may further include: a gate driving circuit located in the non-display area, a first low-level power line VGL1 and a second low-level power line VGL2 extending along the second direction D2, and a plurality of first scan output lines OUTL1 and a plurality of second scan output lines OUTL2 extending at least partially along the first direction D1, and the first direction D1 and the second direction D2 intersecting.

[0144] In an exemplary embodiment, the gate driving circuit may be located in the scan signal driver.

[0145] In an exemplary embodiment, as shown in Figures 4 to 9, the first low-level power line VGL1 and the second low-level power line VGL2 can be arranged on the same layer, the first scan output line OUTL1 and the second scan output line OUTL2 can be arranged on the same layer, and the first low-level power line VGL1 can be located on a side of the first scan output line OUTL1 close to the substrate.

[0146] In an exemplary embodiment, as shown in Figures 4 to 9, the first scan output line OUTL1 is electrically connected to the first scan signal line G1, the second scan output line OUTL2 is electrically connected to the second scan signal line G2, and the gate driving circuit is electrically connected to the first low-level power line VGL1, the second low-level power line VGL2, the plurality of first scan output lines OUTL1, and the plurality of second scan output lines OUTL2, respectively.

[0147] 4 to 9 , the first low-level power line VGL1 and the second low-level power line VGL2 are located on a side of the gate driving circuit close to the display area, and the first low-level power line VGL1 is located on a side of the second low-level power line VGL2 away from the display area.

[0148] In an exemplary embodiment, as shown in Figures 4 to 9, the driving circuit layer may further include: a plurality of data signal lines Data at least partially located in the display area and a plurality of electrostatic release circuits ESD and a plurality of electrostatic release lines ESDL located in the non-display area, the data signal lines Data and the electrostatic release lines ESDL at least partially extending along the second direction D2, and the data signal lines Data and the electrostatic release lines ESDL are arranged in the same layer; the pixel circuit is electrically connected to the data signal line Data, and at least one electrostatic release circuit ESD is electrically connected to the data signal line Data and the electrostatic release line ESDL, respectively.

[0149] In an exemplary embodiment, as shown in FIG. 4 to FIG. 9 , a plurality of electrostatic discharge circuits are arranged along a first direction D1 .

[0150] In an exemplary embodiment, as shown in Figures 4 to 9, the driving circuit layer may further include: a first power supply line VDD at least partially located in the display area, and a first power supply line VDDL, a second power supply line VSS, and a second power supply line VSSL located in the non-display area, the first power supply line VDDL providing a high-level signal, and the second power supply line VSSL providing a low-level signal.

[0151] In an exemplary embodiment, as shown in Figures 4 to 9, the first power supply line VDDL and the second power supply line VSSL may be provided on the same layer, the first power supply line VDD is located on a side of the first power supply line VDDL away from the substrate, and the second power supply line VSS is located on a side of the second power supply line VSSL close to the substrate.

[0152] In exemplary embodiments, as shown in FIG. 4 to FIG. 9 , the first power supply line VDDL may be located on a side of the second power line VSS away from the display area, and the second power line VSS may partially surround the first power supply line VDDL.

[0153] In an exemplary embodiment, as shown in Figures 1 and 4 to 9, the second power supply line VSSL is disposed on a side of the first power supply line VDDL away from the display area and surrounds at least one side of the display area. Figure 1 illustrates an example where the second power supply line VSSL surrounds the display area.

[0154] In an exemplary embodiment, as shown in Figures 4 to 9, the pixel circuit is electrically connected to the first power line VDD, the orthographic projection of the first power supply line VDDL on the substrate partially overlaps with the orthographic projections of the first power line VDD and the second power line VSS on the substrate, and is electrically connected to the first power line VDD, and the orthographic projection of the second power line VSS on the substrate partially overlaps with the multiple electrostatic release lines ESDL and the orthographic projections of the first power line VDD on the substrate, and is electrically connected to the multiple electrostatic release lines ESDL and the second power supply line VSSL, respectively.

[0155] In an exemplary embodiment, as shown in Figures 4 to 9 , the driving circuit layer further includes a first signal connection line DL1 and a second signal connection line DL2. The first signal connection line DL1 and the second signal connection line DL2 extend at least partially along a first direction D1, and the first signal connection line DL1 and the second signal connection line DL2 are electrically connected to different electrostatic discharge circuits ESD, respectively. Figures 4 to 9 illustrate the first signal connection line DL1 being electrically connected to a first electrostatic discharge circuit ESD, and the second signal connection line DL2 being electrically connected to a second electrostatic discharge circuit ESD.

[0156] In an exemplary embodiment, as shown in FIG4 to FIG9 , a pixel circuit may include: a first pixel circuit and a second pixel circuit, wherein the second pixel circuit is located on a side of the first pixel circuit closer to the second power supply line VSSL. The first pixel circuit is electrically connected to a first scan signal line G1, whose orthographic projection on the substrate partially overlaps with the orthographic projection on the substrate of the first scan output line OUTL1, and is electrically connected to the first scan output line OUTL1; the first pixel circuit is electrically connected to a second scan signal line G2, whose orthographic projection on the substrate partially overlaps with the orthographic projection on the substrate of the second scan output line OUTL2, and is electrically connected to the second scan output line OUTL2; the second pixel circuit is electrically connected to a second scan signal line G2, whose orthographic projection on the substrate partially overlaps with the orthographic projection on the substrate of the first signal connection line DL1, and is electrically connected to the first signal connection line DL1; and the second pixel circuit is electrically connected to a first scan signal line G1, whose orthographic projection on the substrate partially overlaps with the orthographic projection on the substrate of the second signal connection line DL2, and is electrically connected to the second signal connection line DL2. 4 to 9 are described by taking the pixel circuits in the first row as the second pixel circuits and all pixel circuits except the pixel circuits in the first row as the first pixel circuits as an example.

[0157] In an exemplary embodiment, as shown in Figures 4 to 9, the driving circuit layer further includes: a plurality of first low-level connection portions VGL1_CL arranged at intervals and a plurality of second low-level connection portions VGL2_CL arranged at intervals, the first low-level connection portions VGL1_CL and the second low-level connection portions VGL2_CL are arranged on the same layer, and the first low-level connection portions VGL1_CL are located on a side of the first low-level power line VGL1 away from the substrate.

[0158] Figure 10 is an enlarged view of area C1 in the display panel shown in Figures 4 to 9. Figure 10 illustrates four pixel circuits P1 to P4 as an example. As shown in Figure 10 , the four pixel circuits P1 to P4 are connected to two first power lines VDD, four data signal lines Data, and one sensing signal line Sense. Figure 10 illustrates the pixel circuit as including first to third transistors T1 to T3, but this disclosure does not impose any limitations on this.

[0159] In an exemplary embodiment, as shown in FIG10 , four pixel circuits P1 to P4 are connected to two first power lines VDD located on a side of the first pixel circuit P1 away from the second pixel circuit P2 and a side of the fourth pixel circuit P4 away from the third pixel circuit P3 .

[0160] In an exemplary embodiment, as shown in FIG10 , the data signal line Data connected to the first pixel circuit P1 and the data signal line Data connected to the second pixel circuit P2 are located between the first pixel circuit P1 and the second pixel circuit P2, and the data signal line Data connected to the first pixel circuit P1 is located on a side of the data signal line Data connected to the second pixel circuit P2 that is closer to the first pixel circuit P1. The data signal line Data connected to the third pixel circuit P1 and the data signal line Data connected to the fourth pixel circuit P4 are located between the third pixel circuit P3 and the fourth pixel circuit P4, and the data signal line Data connected to the third pixel circuit P3 is located on a side of the data signal line Data connected to the fourth pixel circuit P4 that is closer to the third pixel circuit P3.

[0161] In an exemplary embodiment, as shown in FIG. 10 , the sensing signal line Sense connected to the four pixel circuits P1 to P4 is located between the third pixel circuit P3 and the fourth pixel circuit P4 .

[0162] Figure 11 is an equivalent circuit diagram of an electrostatic discharge circuit. As shown in Figure 11, the electrostatic discharge circuit may include an electrostatic discharge transistor ET, a first electrostatic discharge capacitor EC1, and a second electrostatic discharge capacitor EC2. The first electrostatic discharge capacitor EC1 and the second electrostatic discharge capacitor EC2 each include two plates: a first plate and a second plate.

[0163] In an exemplary embodiment, as shown in FIG11 , the gate electrode of the electrostatic discharge transistor ET is electrically connected to the first plate EC11 of the first electrostatic discharge capacitor EC1 and the first plate EC21 of the second electrostatic discharge capacitor EC2, respectively. The first electrode of the electrostatic discharge transistor ET is electrically connected to the second plate EC12 of the first electrostatic discharge capacitor EC1 and the electrostatic discharge line ESDL, respectively. The second electrode of the electrostatic discharge transistor ET is electrically connected to the second plate EC22 of the second electrostatic discharge capacitor EC2. The second electrode of the electrostatic discharge transistor ET is also electrically connected to the first signal connection line DL1, the second signal connection line DL2, or the data signal line Data. When the electrostatic discharge circuit is the first electrostatic discharge circuit, the second electrode of the electrostatic discharge transistor ET is electrically connected to the first signal connection line DL1. When the electrostatic discharge circuit is the second electrostatic discharge circuit, the second electrode of the electrostatic discharge transistor ET is electrically connected to the second signal connection line DL2. When the electrostatic discharge circuit is an electrostatic discharge circuit other than the first and second electrostatic discharge circuits, the second electrode of the electrostatic discharge transistor ET is electrically connected to the data signal line Data.

[0164] Figure 12 is an enlarged view of area C2 in the display panel shown in Figures 4 to 9. Figure 12 illustrates two electrostatic discharge circuits, using the example of an example where the second electrodes of the electrostatic discharge transistors ET in both circuits are electrically connected to the data signal line Data. As shown in Figure 12 , the orthographic projection of the electrostatic discharge line ESDL on the substrate is electrically connected to the second power line VSS, and is electrically connected to the second power line VSS through a via.

[0165] In an exemplary embodiment, FIG13 is an enlarged view of region C3 in the display panel provided in FIG4 through FIG9 . As shown in FIG4 through FIG9 and FIG13 , when the display panel includes the first discharge structure E1, the first scan signal line G1 is provided with a first protrusion 10 extending along the second direction D2. The first protrusion 10 is located on a side of the first scan signal line G1 that is close to the pixel circuit electrically connected thereto. The first protrusion 10 includes a first tip 11. The second scan signal line G2 is provided with a second protrusion 20 extending along the second direction D2. The second protrusion 20 is located on a side of the second scan signal line G2 that is close to the pixel circuit electrically connected thereto. The second protrusion 20 includes a second tip 21.

[0166] In an exemplary embodiment, as shown in Figures 4 to 9 and 13, the first tip 11 of the first scan signal line G1 electrically connected to the first discharge structure E1 is arranged opposite to the second tip 21 of the second scan signal line G2 electrically connected to the first discharge structure E1, and the orthographic projection of the first discharge structure E1 on the substrate at least partially overlaps with the orthographic projection of the first tip 11 of the first scan signal line G1 electrically connected to the first discharge structure E1 and the orthographic projection of the second tip 21 of the second scan signal line G2 electrically connected to the second discharge structure E1 on the substrate.

[0167] In an exemplary embodiment, FIG14 is an enlarged view of region C4 in the display panel provided in FIG4 . As shown in FIG14 , when the display panel includes the second discharge structure E2, the first scan signal line G1 is provided with a third protrusion 30 extending at least partially along the second direction D2. The third protrusion 30 is located on a side of the first scan signal line G1 close to the gate driver circuit and includes a third tip 32. The second scan signal line G2 is further provided with a fourth protrusion 40 extending at least partially along the second direction D2. The fourth protrusion 40 is located on a side of the second scan signal line G2 close to the gate driver circuit and includes a fourth tip 41.

[0168] In an exemplary embodiment, as shown in FIG4 and FIG14 , the third tip 31 of the first scan signal line G1 electrically connected to the second discharge structure E2 is arranged opposite to the fourth tip 41 of the second scan signal line G2 electrically connected to the second discharge structure E2, and the orthographic projection of the second discharge structure E2 on the substrate at least partially overlaps with the orthographic projection of the third tip 31 of the first scan signal line G1 electrically connected to the second discharge structure E2 and the orthographic projection of the fourth tip 41 of the second scan signal line G2 electrically connected to the second discharge structure E2 on the substrate.

[0169] In an exemplary embodiment, FIG15 is an enlarged view of area C4 in the display panel provided in FIG5 . As shown in FIG5 and FIG15 , when the display panel includes a second discharge structure E2, the second discharge structure E2 is electrically connected to the first scan signal line G1 via a first signal line, and is electrically connected to the second scan signal line G2 via a second scan output line OUTL2. The first signal line includes either a first scan output line OUTL1 or a second signal connection line DL2. When the pixel circuit electrically connected to the first scan signal line G1 is a first pixel circuit, the first signal line is the first scan output line OUTL1. When the pixel circuit electrically connected to the first scan signal line G1 is a second pixel circuit, the first signal line is the second signal connection line DL2. FIG15 illustrates the first signal line as the first scan output line OUTL1.

[0170] In an exemplary embodiment, as shown in Figures 5 and 15, the first signal line electrically connected to the second discharge structure E2 is provided with a fifth protrusion 50 extending at least partially along the second direction D2. The fifth protrusion 50 is located on a side of the first signal line close to the gate driving circuit. The fifth protrusion 50 includes: a fifth tip 51; the second scan output line OUTL2 electrically connected to the second scan signal line G2 is provided with a sixth protrusion 60 extending at least partially along the second direction D2. The sixth protrusion 60 is located on a side of the second scan output line OUTL2 close to the gate driving circuit. The sixth protrusion 60 includes: a sixth tip 61.

[0171] In an exemplary embodiment, as shown in FIG5 and FIG15, the fifth tip 51 of the first signal line electrically connected to the second discharge structure E2 is arranged opposite to the sixth tip 61 of the second scan output line OUTL2 electrically connected to the second discharge structure E2, and the orthographic projection of the second discharge structure E2 on the substrate at least partially overlaps with the orthographic projection of the fifth tip 51 of the first signal line electrically connected to the second discharge structure E2 and the orthographic projection of the sixth tip 61 of the second scan output line OUTL2 electrically connected to the second discharge structure E2 on the substrate.

[0172] In an exemplary embodiment, as shown in Figures 6 to 9, the second discharge structure E2 is also electrically connected to the second low-level power line VGL2 or the second low-level connection portion VGL2_CL. Figures 6 and 8 are described by taking the second discharge structure E2 also being electrically connected to the second low-level power line VGL2 as an example. Figures 7 and 9 are described by taking the second discharge structure E2 also being electrically connected to the second low-level connection portion VGL2_CL as an example.

[0173] In an exemplary embodiment, FIG16 is an enlarged view of region C4 in the display panel provided in FIG6 and FIG8. As shown in FIG6, FIG8 and FIG16, when the second discharge structure E2 is electrically connected to the second low-level power line VGL2, the second low-level power line VGL2 is provided with a seventh protrusion 70 extending along the first direction D1. The seventh protrusion 70 includes a seventh pointed end 71.

[0174] In an exemplary embodiment, as shown in Figures 6, 8, and 16, a virtual straight line passing through the seventh tip 71 and extending along the first direction D1 is located between two other tips that at least partially overlap with the second discharge structure E2 on the substrate. Figures 6, 8, and 16 illustrate the example of the third tip 31 and the fourth tip 41 being the two other tips that at least partially overlap with the second discharge structure E2 on the substrate. In an exemplary embodiment, the fifth tip 51 and the sixth tip 61 may also be the two other tips that at least partially overlap with the second discharge structure E2 on the substrate.

[0175] In an exemplary embodiment, as shown in FIG. 6 , FIG. 8 and FIG. 16 , the orthographic projection of the second discharge structure E2 on the substrate also partially overlaps with the orthographic projection of the seventh tip 71 of the electrically connected second low-level power line VGL2 on the substrate.

[0176] In an exemplary embodiment, FIG17 is an enlarged view of region C4 in the display panel provided in FIG7 and FIG9. As shown in FIG7, FIG9 and FIG17, when the second discharge structure is electrically connected to the second low-level connection portion VGL2_CL, the second low-level connection portion VGL2_CL is provided with an eighth protrusion 80 extending along the first direction D1. The eighth protrusion 80 includes an eighth pointed tip 81.

[0177] In an exemplary embodiment, as shown in Figures 7, 9, and 17, a virtual straight line passing through the eighth tip 81 and extending along the first direction D1 is located between two other tips that at least partially overlap with the second discharge structure E2 on the substrate. Figures 7, 9, and 17 illustrate this by taking the fifth tip 51 and the sixth tip 61 as examples of the two other tips that at least partially overlap with the second discharge structure E2 on the substrate. In an exemplary embodiment, the other two tips that at least partially overlap with the second discharge structure E2 on the substrate may also be the third tip 31 and the fourth tip 41.

[0178] In an exemplary embodiment, as shown in FIG. 7 , FIG. 9 and FIG. 17 , the orthographic projection of the second discharge structure E2 on the substrate also partially overlaps with the orthographic projection of the eighth tip 81 of the electrically connected second low-level connection portion VGL2_CL on the substrate.

[0179] In exemplary embodiments, as shown in Figures 4 to 9, the driving circuit layer may further include at least one of a third discharge structure E3, a fourth discharge structure E4, a fifth discharge structure E5, and a sixth discharge structure E6. The third discharge structure E3 is electrically connected to a scan signal line near the non-display area and an electrostatic discharge line ESDL near the gate driving circuit, respectively. The fourth discharge structure E4 is electrically connected to the second low-level power line VGL2 and the electrostatic discharge line ESDL near the gate driving circuit, respectively. The fifth discharge structure E5 is electrically connected to the first low-level power line VGL1 and the second low-level power line VGL2, respectively. The sixth discharge structure E6 is electrically connected to the first power supply line VDDL and the second power supply line VSSL, respectively. The scan signal line is the first scan signal line G1 or the second scan signal line G2. Figures 4 and 5 illustrate the third discharge structure as an example, Figures 6 and 7 illustrate the third and fourth discharge structures as an example, and Figures 8 and 9 illustrate the third, fourth, fifth, and sixth discharge structures as an example.

[0180] In an exemplary embodiment, the first discharge structure E1 , the second discharge structure E2 , the third discharge structure E3 , the fourth discharge structure E4 , the fifth discharge structure E5 , and the sixth discharge structure E6 may be disposed in the same layer, which is not limited in the present disclosure.

[0181] In an exemplary embodiment, as shown in Figures 6 to 9, when the driving circuit layer includes: the third discharge structure E3 or the fourth discharge structure E4, the electrostatic release line ESDL close to the gate driving circuit includes: a first connecting line ESDL1 extending along the first direction D1 and a second connecting line ESDL2 extending along the second direction D2, and the first connecting line ESDL1 is electrically connected to the second connecting line ESDL2.

[0182] In an exemplary embodiment, FIG18 is an enlarged view of area C5 in the display panel shown in FIG4 . As shown in FIG4 and FIG18 , the scan signal line electrically connected to the third discharge structure E3 is provided with a ninth protrusion 90 extending along the second direction D2. The ninth protrusion 90 is located on a side of the scan signal line close to the electrostatic discharge circuit and includes a ninth tip 91. The first connection line ESDL1 of the electrostatic discharge line ESDL electrically connected to the third discharge structure E3 is provided with a tenth protrusion 100. The tenth protrusion 100 is located on a side of the first connection line ESDL1 close to the electrostatic discharge circuit ESD and includes a tenth tip 101. FIG4 illustrates the second scan signal line electrically connected to the third discharge structure E3 as an example.

[0183] In an exemplary embodiment, as shown in FIG. 4 and FIG. 18 , the ninth tip 91 of the scan signal line to which the third discharge structure E3 is electrically connected and the tenth tip 101 of the electrostatic discharge line ESDL to which the third discharge structure E3 is electrically connected are disposed opposite each other.

[0184] In an exemplary embodiment, as shown in FIG4 and FIG18, the orthographic projection of the third discharge structure E3 on the substrate at least partially overlaps with the orthographic projections of the ninth tip 91 of the scan signal line electrically connected thereto and the tenth tip 101 of the electrostatic discharge line ESDL electrically connected thereto.

[0185] In an exemplary embodiment, as shown in FIG. 5 , the third discharge structure E3 may be electrically connected to the scan signal line through the first signal link line DL1 .

[0186] In an exemplary embodiment, FIG19 is an enlarged view of area C5 in the display panel shown in FIG5 . As shown in FIG5 and FIG19 , the first signal connection line DL1 electrically connected to the third discharge structure E3 is provided with an eleventh protrusion 110 extending along the second direction D2. The eleventh protrusion 110 is located on the side of the first signal connection line DL1 closest to the electrostatic discharge circuit and includes an eleventh tip 111. The first connection line of the electrostatic discharge line ESDL electrically connected to the third discharge structure E3 is provided with a tenth protrusion 100. The tenth protrusion 100 is located on the side of the first connection line ESDL closest to the electrostatic discharge circuit and includes a tenth tip 101.

[0187] In an exemplary embodiment, as shown in FIG5 and FIG19, the eleventh tip of the first signal connection line DL1 electrically connected to the third discharge structure E3 and the tenth tip of the electrostatic discharge line ESDL electrically connected to the third discharge structure E3 are arranged opposite to each other.

[0188] 5 and 19 , the orthographic projection of the third discharge structure E3 on the substrate at least partially overlaps with the orthographic projections of the eleventh tip 111 of the electrically connected first signal connection line DL1 and the tenth tip 101 of the electrically connected electrostatic discharge line ESDL on the substrate.

[0189] In an exemplary embodiment, FIG20 is an enlarged view of region C5 in the display panel provided in FIG6 and FIG8 , and FIG21 is an enlarged view of region C5 in the display panel provided in FIG7 and FIG9 . As shown in FIG20 and FIG21 , the electrostatic discharge line ESDL electrically connected to the fourth discharge structure E4 may include a twelfth protrusion 120 located on a side of the first connection line ESDL of the electrostatic discharge line ESDL close to the gate driving circuit. The twelfth protrusion 120 includes a twelfth tip 121 . The second low-level power line VGL2 further includes a thirteenth protrusion 130 extending along the first direction D1. The thirteenth protrusion 130 is located on a side of the second low-level power line VGL2 close to the display area. The thirteenth protrusion 130 includes a thirteenth tip 131 . FIG20 illustrates an example in which the orthographic projection of the fourth discharge structure on the substrate partially overlaps with the orthographic projections of the ninth tip 91 and the tenth tip 101 on the substrate. FIG21 illustrates an example in which the orthographic projection of the fourth discharge structure on the substrate partially overlaps with the orthographic projections of the eleventh tip 111 and the tenth tip 101 on the substrate.

[0190] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the twelfth tip 121 of the electrostatic discharge line ESDL to which the fourth discharge structure E4 is electrically connected is disposed opposite to the thirteenth tip 131 of the second low-level power line VGL2 .

[0191] In an exemplary embodiment, as shown in FIG20 and FIG21, the orthographic projection of the fourth discharge structure E4 on the substrate at least partially overlaps with the orthographic projection of the twelfth tip 121 of the electrically connected electrostatic discharge line ESDL on the substrate and the orthographic projection of the thirteenth tip 131 of the second low-level power line VGL2 on the substrate.

[0192] In an exemplary embodiment, FIG22 is an enlarged view of area C6 in the display panel provided in FIG8 and FIG9. As shown in FIG8, FIG9 and FIG22, the first low-level power line VGL1 is provided with a fourteenth protrusion 140. The fourteenth protrusion 140 is located on a side of the first low-level power line VGL1 close to the second power supply line VSSL. The fourteenth protrusion 140 includes a fourteenth tip 141. The second low-level power line VGL2 is provided with a fifteenth protrusion 150. The fifteenth protrusion 150 is located on a side of the second low-level power line VGL2 close to the second power supply line VSSL. The fifteenth protrusion 150 includes a fifteenth tip 151.

[0193] In an exemplary embodiment, as shown in FIG. 8 , FIG. 9 , and FIG. 22 , the fourteenth tip 141 of the first low-level power line VGL1 is disposed opposite to the fifteenth tip 151 of the second low-level power line VGL2 .

[0194] In an exemplary embodiment, as shown in FIG8 , FIG9 and FIG22 , the orthographic projection of the fifth discharge structure E5 on the substrate at least partially overlaps with the orthographic projection of the fourteenth tip 141 of the first low-level power line VGL1 and the orthographic projection of the fifteenth tip 151 of the second low-level power line VGL2 on the substrate.

[0195] In an exemplary embodiment, FIG23 is an enlarged view of area C7 in the display panel provided in FIG8 and FIG9. As shown in FIG8, FIG9, and FIG23, the first power supply line VDDL is provided with a sixteenth protrusion 160 extending along the second direction D2. The sixteenth protrusion 160 is located on a side of the first power supply line VDDL close to the second power supply line VSSL. The sixteenth protrusion 160 includes a sixteenth tip 161. The second power supply line VSSL is provided with a seventeenth protrusion 170 extending along the second direction D2. The seventeenth protrusion 170 is located on a side of the second power supply line VSSL close to the first power supply line VDDL. The seventeenth protrusion 170 includes a seventeenth tip 171.

[0196] In an exemplary embodiment, as shown in FIG. 8 , FIG. 9 , and FIG. 23 , the sixteenth tip 161 of the first power supply line VDDL is disposed opposite to the seventeenth tip 171 of the second power supply line VSSL.

[0197] In an exemplary embodiment, as shown in FIG8 , FIG9 and FIG23 , an orthographic projection of the sixth discharge structure E6 on the substrate at least partially overlaps with an orthographic projection of the sixteenth tip 161 of the first power supply line VDDL and an orthographic projection of the seventeenth tip 171 of the second power supply line VSSL on the substrate.

[0198] In an exemplary embodiment, the driving circuit layer further includes: a plurality of first scan connection portions, a plurality of second scan connection portions, a plurality of data connection portions, a plurality of power connection portions, a plurality of sensing signal lines Sense, a plurality of sensing connection portions, and a power connection line VSS_CL. The first scan connection portions are electrically connected to the first scan signal line G1, the second scan connection portions are electrically connected to the second scan signal line G2, the data connection portions are electrically connected to the data signal line Data, the power connection portion is electrically connected to the first power line VDD, the sensing signal lines are electrically connected to the pixel circuits and the sensing connection portions, and the power connection line VSS_CL is electrically connected to the second power line VSS and the second power supply line VSSL, respectively.

[0199] In an exemplary embodiment, as shown in Figures 4 to 9 , the driving circuit layer may include: a shielding layer SHD, a semiconductor layer ACT, a first conductive layer Gate, and a second conductive layer SD. Figure 24 is a schematic diagram of a pixel circuit in the shielding layer, Figure 25 is a schematic diagram of a pixel circuit after forming a semiconductor layer, Figure 26 is a schematic diagram of a pixel circuit after forming a first conductive layer, and Figure 27 is a schematic diagram of a pixel circuit after forming a second conductive layer. Figure 28 is a schematic diagram of an electrostatic discharge circuit in the semiconductor layer, Figure 29 is a schematic diagram of an electrostatic discharge circuit after forming a first conductive layer, and Figure 30 is a schematic diagram of an electrostatic discharge circuit after forming a second conductive layer. Figures 24 to 27 are described using four pixel circuits P1 to P4 as an example, while Figures 28 to 30 are described using two electrostatic discharge circuits as an example.

[0200] In an exemplary embodiment, the driving circuit layer may further include: a first insulating layer located between the blocking layer and the semiconductor layer, a second insulating layer located between the semiconductor layer and the first conductive layer, a third insulating layer located between the first conductive layer and the second conductive layer, and a planar layer located on a side of the second conductive layer away from the substrate.

[0201] As shown in FIG. 4 to FIG. 9 and FIG. 24 to FIG. 30 , the shielding layer SHD at least includes: a second power line VSS, a first plate C1 of the capacitor, and first to fourth connection electrodes VL1 to VL4 .

[0202] In an exemplary embodiment, the first connection electrode VL1 is configured to be electrically connected to the first power line electrically connected to the first pixel circuit and the second pixel circuit, the second connection electrode VL2 is configured to be electrically connected to the first power line electrically connected to the third pixel circuit and the fourth pixel circuit, and the third connection electrode VL3 and the fourth connection electrode VL4 are configured to be electrically connected to the sensing signal line electrically connected to the first pixel circuit to the fourth pixel circuit.

[0203] As shown in Figures 4 to 9 and Figures 24 to 30, the semiconductor layer ACT includes at least: one or more of the first to sixth discharge structures E6, the active layers T11 to T31 of the first to third transistors, and the active layer ET1 of the electrostatic discharge transistor.

[0204] In an exemplary embodiment, the active layer of the first transistor may be reused as the second plate C2 of the capacitor.

[0205] As shown in Figures 4 to 9 and Figures 24 to 30, the first conductive layer Gate may at least include: a first power supply line VDDL, a second power supply line VSSL, a first low-level power line VGL1, a second low-level power line VGL2, a first scan signal line G1, a second scan signal line G2, a data connection part Data_CL, a power connection part VDD_CL, a sensing connection part Sense_CL, a control electrode T22 of the second transistor, and a control electrode ET2 of the electrostatic release transistor.

[0206] In an exemplary embodiment, the data connection portion Data_CL, the power connection portion VDD_CL, and the sense connection portion Sense_CL extend along the second direction.

[0207] In an exemplary embodiment, the control electrode ET2 of the electrostatic discharge transistor extends along the second direction.

[0208] In an exemplary embodiment, the control electrode ET2 of the electrostatic discharge transistor is multiplexed as the first plate EC11 of the first electrostatic discharge capacitor and the first plate EC21 of the second electrostatic discharge capacitor.

[0209] In an exemplary embodiment, the region where the first scan signal line G1 overlaps with the active layer of the first transistor is multiplexed as the control electrode T12 of the first transistor, and the region where the second scan signal line G2 overlaps with the active layer of the third transistor is multiplexed as the control electrode T32 of the third transistor.

[0210] In an exemplary embodiment, the control electrode T22 of the second transistor extends along the first direction.

[0211] As shown in Figures 4 to 9 and Figures 24 to 30, the second conductive layer SD may at least include: a data signal line Data, a first power line VDD, a first signal connection line DL1, a second signal connection line DL2, an electrostatic release line ESDL, a first scan output line OUTL1, a second scan output line OUTL2, a first scan connection part G1_CL, a second scan connection part G2_CL, a power connection line VSS_CL, a first low-level connection part VGL1_CL, a second low-level connection part VGL2_CL, the second electrode T14 of the first transistor, the second electrode T24 of the second transistor, the first electrode T33 of the third transistor, and the second electrode T34 of the third transistor, the first electrode ET3 of the electrostatic release transistor, and the second electrode ET4 of the electrostatic release transistor, the second plate EC12 of the first electrostatic release capacitor, and the second plate EC22 of the second electrostatic release capacitor.

[0212] In an exemplary embodiment, an orthographic projection of the data signal line Data on the substrate at least partially overlaps with an orthographic projection of the data connection portion Data_CL on the substrate and is electrically connected to the data connection portion Data_CL.

[0213] In an exemplary embodiment, the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projection of the power connection portion VDD_CL on the substrate and is electrically connected to the power connection portion VDD_CL. In an exemplary embodiment, the orthographic projection of the first power line VDD on the substrate located on a side of the first pixel circuit away from the second pixel circuit partially overlaps with the orthographic projection of the first connection electrode on the substrate and is electrically connected to the first connection electrode. The orthographic projection of the first power line VDD on the substrate located on a side of the fourth pixel circuit away from the third pixel circuit partially overlaps with the orthographic projection of the second connection electrode on the substrate and is electrically connected to the second connection electrode.

[0214] In an exemplary embodiment, an orthographic projection of the sensing signal line Sense on the substrate at least partially overlaps with orthographic projections of the sensing connection portion Sense_CL, the third connection electrode, and the fourth connection electrode on the substrate, and is electrically connected to the sensing connection portion Sense_CL, the third connection electrode, and the fourth connection electrode, respectively.

[0215] In an exemplary embodiment, for the first to fourth pixel circuits, the data signal line VDD is multiplexed as the first electrode T23 of the second transistor.

[0216] In an exemplary embodiment, a first power line VDD located on a side of a first pixel circuit away from a second pixel circuit is multiplexed as a first electrode T13 of a first transistor in the first pixel circuit, and the first electrode T13 of the first transistor in the second pixel circuit is electrically connected to the first power line VDD located on a side of the first pixel circuit away from the second pixel circuit via a first connection electrode. A first power line VDD located on a side of a fourth pixel circuit away from a third pixel circuit is multiplexed as a first electrode T13 of a first transistor in the fourth pixel circuit, and the first electrode T13 of the first transistor in the third pixel circuit is electrically connected to the first power line VDD located on a side of the fourth pixel circuit away from the third pixel circuit via a second connection electrode.

[0217] In an exemplary embodiment, the electrostatic discharge line is reset to the second electrode ET4 of the electrostatic discharge transistor and the second plate EC22 of the second electrostatic discharge capacitor.

[0218] In an exemplary embodiment, the data signal line, the first signal connection line, or the second signal connection line is multiplexed into the first electrode ET3 of the electrostatic discharge transistor and the second electrode EC12 of the first electrostatic discharge capacitor.

[0219] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer may be referred to as a (GI) layer, and the third insulating layer may be referred to as an interlayer dielectric (ILD) layer.

[0220] In an exemplary embodiment, the shielding layer, the first conductive layer, and the second conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can have a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarizing layers can be made of organic materials, such as resin.

[0221] In an exemplary embodiment, the semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0222] In an exemplary embodiment, the display panel provided in FIG4 can discharge static electricity to the first scan signal line and the second scan signal line by forming a discharge structure with a first discharge structure provided in the semiconductor layer and a first protrusion and a second protrusion provided in the first conductive layer. Furthermore, the display panel can discharge static electricity to the first scan signal line and the second scan signal line by forming a discharge structure with a second discharge structure provided in the semiconductor layer and a third protrusion and a fourth protrusion provided in the first conductive layer. Furthermore, the display panel provided in FIG4 can discharge static electricity to the static electricity discharge line and the second scan signal line by forming a discharge structure with a third discharge structure provided in the semiconductor layer and a ninth protrusion provided in the first conductive layer and a tenth protrusion provided in the second conductive layer. The display panel provided in FIG4 can discharge static electricity to all first scan signal lines, all second scan signal lines, the second signal connection line, and the static electricity discharge line.

[0223] In an exemplary embodiment, the display panel provided in FIG5 can discharge static electricity to the first scan signal line and the second scan signal line by forming a discharge structure with a first discharge structure provided in the semiconductor layer and a first protrusion and a second protrusion provided in the first conductive layer. The display panel provided in FIG5 can also discharge static electricity to the first scan signal line and the second scan signal line by forming a discharge structure with a second discharge structure provided in the semiconductor layer and a fifth protrusion and a sixth protrusion provided in the second conductive layer. The display panel provided in FIG5 can discharge static electricity to all first scan signal lines, all second scan signal lines, the static electricity discharge line, the first signal connection line, and the second signal connection line.

[0224] In an exemplary embodiment, the display panel shown in FIG6 can discharge static electricity to the first scan signal line and the second scan signal line by forming a discharge structure with a first discharge structure provided in the semiconductor layer and a first protrusion and a second protrusion provided in the first conductive layer. Furthermore, a second discharge structure provided in the semiconductor layer can discharge static electricity to the first scan signal line, the second scan signal line, and the second low-level power supply line by forming a discharge structure with a third protrusion provided in the semiconductor layer, a fourth protrusion provided in the first conductive layer, and a seventh protrusion provided in the first conductive layer. Furthermore, a third discharge structure provided in the semiconductor layer can discharge static electricity to the second scan signal line and the static electricity discharge line by forming a discharge structure with a ninth protrusion provided in the first conductive layer and a tenth protrusion provided in the second conductive layer. Furthermore, a fourth discharge structure provided in the semiconductor layer can discharge static electricity to the static electricity discharge line and the second low-level power supply line by forming a discharge structure with a twelfth protrusion provided in the second conductive layer and a thirteenth protrusion provided in the first conductive layer. The display panel shown in FIG6 can discharge static electricity to all first scan signal lines, all second scan signal lines, the static electricity discharge line, the first signal connection line, the second signal connection line, and the second low-level power supply line.

[0225] In an exemplary embodiment, the display panel provided in FIG7 can discharge static electricity to the first scan signal line and the second scan signal line by forming a discharge structure with a first discharge structure provided in the semiconductor layer and a first protrusion and a second protrusion provided in the first conductive layer. It can also discharge static electricity to the first scan output line, the second scan output line, and the second low-level connection portion by forming a discharge structure with a second discharge structure provided in the semiconductor layer and a third protrusion, a sixth protrusion, and an eighth protrusion provided in the second conductive layer. It can also discharge static electricity to the second scan signal line and the static electricity release line by forming a discharge structure with a third discharge structure provided in the semiconductor layer and an eleventh protrusion provided in the second conductive layer. It can also discharge static electricity to the static electricity release line and the second low-level power line by forming a discharge structure with a fourth discharge structure provided in the semiconductor layer and a twelfth protrusion provided in the second conductive layer and a thirteenth protrusion provided in the first conductive layer. The display panel provided in FIG7 can discharge static electricity to all first scan output lines, all first scan signal lines, all second scan output lines, all second scan signal lines, the static electricity release line, the first signal connection line, the second signal connection line, the second low-level connection portion, and the second low-level power line.

[0226] In an exemplary embodiment, the display panel provided in FIG8 can form a discharge structure by providing a first discharge structure provided in the semiconductor layer and a first protrusion and a second protrusion provided in the first conductive layer to discharge static electricity to the first scan signal line and the second scan signal line. It can also form a discharge structure by providing a second discharge structure provided in the semiconductor layer and a third protrusion, a fourth protrusion, and a seventh protrusion provided in the first conductive layer to discharge static electricity to the first scan signal line, the second scan signal line, and the second low-level power line. A discharge structure can also be formed by a third discharge structure provided in the semiconductor layer, a ninth protrusion provided in the first conductive layer, and a tenth protrusion provided in the second conductive layer to release static electricity to the second scan signal line and the static electricity release line. A fourth discharge structure provided in the semiconductor layer, a twelfth protrusion provided in the second conductive layer, and a thirteenth protrusion provided in the first conductive layer to form a discharge structure to release static electricity to the static electricity release line and the second low-level power line. A fifth discharge structure provided in the semiconductor layer, a fourteenth protrusion provided in the first conductive layer, and a fifteenth protrusion provided in the first conductive layer to form a discharge structure to release static electricity to the first low-level power line and the second low-level power line. A sixth discharge structure provided in the semiconductor layer, a sixteenth protrusion provided in the first conductive layer, and a seventeenth protrusion provided in the first conductive layer to form a discharge structure to release static electricity to the first power supply line and the second power supply line. The display panel provided in FIG8 can release static electricity to all first scan signal lines, all second scan signal lines, the static electricity release line, the first signal connection line, the second signal connection line, the first low-level power line, the second low-level power line, the first power supply line, and the second power supply line.

[0227] In an exemplary embodiment, the display panel provided in FIG9 can form a discharge structure by forming a first discharge structure provided in the semiconductor layer and a first protrusion and a second protrusion provided in the first conductive layer to discharge static electricity to the first scan signal line and the second scan signal line, and can also form a discharge structure by forming a second discharge structure provided in the semiconductor layer and a third protrusion, a sixth protrusion, and an eighth protrusion provided in the second conductive layer to discharge static electricity to the first scan output line, the second scan output line, and the second low-level connection portion, and can also form a discharge structure by forming a third discharge structure provided in the semiconductor layer and an eleventh protrusion and a tenth protrusion provided in the second conductive layer to discharge static electricity to the second scan signal line. The display panel provided in FIG9 can discharge static electricity to all first scan signal lines, all second scan signal lines, the static electricity release line, the first signal connection line, the second signal connection line, the first low-level power line, the second low-level power line, the first power supply line, and the second power supply line.

[0228] In exemplary embodiments, Figures 5, 7, and 9 illustrate a discharge architecture formed by a second discharge structure provided on the semiconductor layer and a protrusion provided on the second conductive layer. Because the insulating layer between the second conductive layer and the semiconductor layer is thick, the discharge architecture is less susceptible to breakdown, improving the reliability of the display panel.

[0229] In an exemplary embodiment, the gate driving circuit may include a plurality of cascaded shift registers, and at least one shift register may be electrically connected to at least one first scan output line and at least one second scan output line.

[0230] FIG31 is an equivalent circuit diagram of a shift register. As shown in FIG31 , the shift register may include: a first transistor M1 to a fifty-seventh transistor M57, and a first capacitor GC1 to a fifth capacitor GC5. The gate electrode of the first transistor M1 is electrically connected to the random signal terminal OE, the first electrode of the first transistor M1 is electrically connected to the signal input terminal, the second electrode of the first transistor M1 is electrically connected to the first electrode of the second transistor M2 and the first electrode of the third transistor M3, respectively, the control electrode of the second transistor M2 is electrically connected to the random signal terminal OE, the second electrode of the second transistor is electrically connected to the first node N1, the control electrode of the third transistor M3 is electrically connected to the first node N1, the second electrode of the third transistor M3 is electrically connected to the first high-level power supply terminal vgh1, the control electrode of the fourth transistor M4 is electrically connected to the first node N1, the first electrode of the fourth transistor M4 is electrically connected to the first clock signal terminal CLK1, and the fourth transistor M5 is electrically connected to the first high-level power supply terminal vgh1. The second electrode of the transistor M4 is electrically connected to the second node N2, the control electrode of the fifth transistor M5 is electrically connected to the first clock signal terminal CLK1, the first electrode of the fifth transistor M5 is electrically connected to the second node N2, the second electrode of the fifth transistor M5 is electrically connected to the third node N3, the control electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CLK1, the first electrode of the sixth transistor M6 is electrically connected to the third node N3, the second electrode of the sixth transistor M6 is electrically connected to the fourth node N4, the control electrode and the first electrode of the first seventh transistor M7_1 are electrically connected to the signal input terminal INPUT, the second electrode of the first seventh transistor M7_1 is electrically connected to the third node N3, and the second seventh transistor M7_1 is electrically connected to the fourth node N4. The control electrode of M7_2 is electrically connected to the signal input terminal INPUT, the first electrode of the second seventh transistor M7_2 is electrically connected to the third node N3, the second electrode of the second seventh transistor M7_2 is electrically connected to the fourth node N4, the control electrode of the eighth transistor M8 is electrically connected to the first reset signal terminal TRST, the first electrode of the eighth transistor M8 is electrically connected to the fourth node N4, the second electrode of the eighth transistor M8 is electrically connected to the third node N3, the control electrode of the ninth transistor M9 is electrically connected to the first reset signal terminal TRST, the first electrode of the ninth transistor M9 is electrically connected to the third node N3, the second electrode of the ninth transistor M9 is electrically connected to the first low-level power supply terminal vgl1, and the tenth transistor M A control electrode of the twelfth transistor M12 is electrically connected to the second reset signal terminal Reset, a first electrode of the twelfth transistor M12 is electrically connected to the third node N3, and a second electrode of the twelfth transistor M12 is electrically connected to the first low-level power supply terminal vgl1.The control electrode of the thirteenth transistor M13 is electrically connected to the fifth node N5, the first electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, the second electrode of the thirteenth transistor M13 is electrically connected to the third node N3, the control electrode of the fourteenth transistor M14 is electrically connected to the fifth node N5, the first electrode of the fourteenth transistor M14 is electrically connected to the third node N3, the second electrode of the fourteenth transistor M14 is electrically connected to the first low-level power supply terminal vgl1, the control electrode of the fifteenth transistor M15 is electrically connected to the sixth node N6, the first electrode of the fifteenth transistor M15 is electrically connected to the fourth node N4, the second electrode of the fifteenth transistor M15 is electrically connected to the third node N3, the control electrode of the sixteenth transistor M16 is electrically connected to the sixth node N6, and the A first electrode of the sixteenth transistor M16 is electrically connected to the third node N3, a second electrode of the sixteenth transistor M16 is electrically connected to the first low-level power supply terminal vgl1, a control electrode and a first electrode of the seventeenth transistor M17 are electrically connected to the second high-level power supply terminal vgh2, a second electrode of the seventeenth transistor M17 is electrically connected to the control electrode of the eighteenth transistor M18, a first electrode of the eighteenth transistor M18 is electrically connected to the second high-level power supply terminal vgh2, a second electrode of the eighteenth transistor M18 is electrically connected to the fifth node N5, a control electrode of the nineteenth transistor M19 is electrically connected to the fourth node N4, a first electrode of the nineteenth transistor M19 is electrically connected to the control electrode of the eighteenth transistor M18, and a second electrode of the nineteenth transistor M19 is electrically connected to the third low-level power supply terminal. The control electrode of the twentieth transistor M20 is electrically connected to the fourth node N4, the first electrode of the twentieth transistor M20 is electrically connected to the fifth node N5, the second electrode of the twentieth transistor M20 is electrically connected to the first low-level power supply terminal vgl, the control electrode of the twenty-first transistor M21 is electrically connected to the first clock signal terminal CLK1, the first electrode of the twenty-first transistor M21 is electrically connected to the fifth node N5, the second electrode of the twenty-first transistor M21 is electrically connected to the first electrode of the twenty-second transistor M22, the control electrode of the twenty-second transistor M22 is electrically connected to the first node N1, the second electrode of the twenty-second transistor M22 is electrically connected to the first low-level power supply terminal vgl1, and the control electrode of the twenty-third transistor M23 is electrically connected to the signal input terminal CLK1. The input terminal INPUT is electrically connected, a first electrode of the twenty-third transistor M23 is electrically connected to the fifth node N5, a second electrode of the twenty-third transistor M23 is electrically connected to the first low-level power supply terminal vgl, a control electrode of the twenty-fourth transistor M24 is electrically connected to the fourth node N4, a first electrode of the twenty-fourth transistor M24 is electrically connected to the second clock signal terminal CLK2, a second electrode of the twenty-fourth transistor M24 is electrically connected to the cascade signal terminal CR, a control electrode of the twenty-fifth transistor M25 is electrically connected to the fifth node N5, a first electrode of the twenty-fifth transistor M25 is electrically connected to the cascade signal terminal CR, a second electrode of the twenty-fifth transistor M25 is electrically connected to the seventh node N7, and a control electrode of the twenty-sixth transistor M26 is electrically connected to the sixth node N6.A first electrode of the twenty-sixth transistor M26 is electrically connected to the cascade signal terminal CR, a second electrode of the twenty-sixth transistor M26 is electrically connected to the seventh node N7, a control electrode of the twenty-seventh transistor M27 is electrically connected to the fourth node N4, a first electrode of the twenty-seventh transistor M27 is electrically connected to the third clock signal terminal CLK3, a second electrode of the twenty-seventh transistor M27 is electrically connected to the first output terminal OUT1, a control electrode of the twenty-eighth transistor M28 is electrically connected to the fifth node N5, a first electrode of the twenty-eighth transistor M28 is electrically connected to the first output terminal OUT1, a second electrode of the twenty-eighth transistor M28 is electrically connected to the second low-level power supply terminal vgl2, a control electrode of the twenty-ninth transistor M29 is electrically connected to the sixth node N6, a first electrode of the twenty-ninth transistor M29 is electrically connected to the first output terminal OUT1, a second electrode of the twenty-ninth transistor M29 is electrically connected to the second low-level power supply terminal vgl2, a control electrode of the thirtieth transistor M30 is electrically connected to the fourth node N4, and a first electrode of the thirtieth transistor M30 is electrically connected to the fourth node N5. The clock signal terminal CLK4 is electrically connected, a second electrode of the 30th transistor M30 is electrically connected to the second output terminal OUT2, a control electrode of the 31st transistor M31 is electrically connected to the fifth node N5, a first electrode of the 31st transistor M31 is electrically connected to the second output terminal OUT2, a second electrode of the 31st transistor M31 is electrically connected to the second low-level power supply terminal vgl2, a control electrode of the 32nd transistor M32 is electrically connected to the sixth node N6, a first electrode of the 32nd transistor M32 is electrically connected to the second output terminal OUT2, a second electrode of the 32nd transistor M32 is electrically connected to the second low-level power supply terminal vgl2, a control electrode of the 33rd transistor M33 is electrically connected to the first clock signal terminal CLK1, a first electrode of the 33rd transistor M33 is electrically connected to the second node N2, a second electrode of the 33rd transistor M33 is electrically connected to the eighth node N8, a control electrode of the 34th transistor M34 is electrically connected to the first clock signal terminal CLK1, and a first electrode of the 34th transistor M34 is electrically connected to the eighth node N8. A second electrode of the thirty-fourth transistor M34 is electrically connected to the ninth node N9, a control electrode and a first electrode of the first thirty-fifth transistor M35 are electrically connected to the signal input terminal INPUT, a second electrode of the first thirty-fifth transistor M35 is electrically connected to the eighth node N8, a control electrode of the second thirty-fifth transistor M35 is electrically connected to the signal input terminal INPUT, a first electrode of the second thirty-fifth transistor M35 is electrically connected to the eighth node N8, and a second electrode of the second thirty-fifth transistor M35 is electrically connected to the ninth node N9. A control electrode of the thirty-sixth transistor M36 is electrically connected to the first reset signal terminal TRST, a first electrode of the thirty-sixth transistor M36 is electrically connected to the tenth node N10, and a second electrode of the thirty-sixth transistor M36 is electrically connected to the eighth node N8. A control electrode of the thirty-seventh transistor M37 is electrically connected to the first reset signal terminal TRST, and a first electrode of the thirty-seventh transistor M37 is electrically connected to the eighth node N8.A second electrode of the thirty-seventh transistor M37 is electrically connected to the first low-level power supply terminal vgl1, a control electrode of the thirty-eighth transistor M38 is electrically connected to the tenth node N10, a first electrode of the thirty-eighth transistor M38 is electrically connected to the first high-level power supply terminal vgh1, a second electrode of the thirty-eighth transistor M38 is electrically connected to the eighth node N8, a control electrode of the thirty-ninth transistor M39 is electrically connected to the second reset signal terminal Reset, a first electrode of the thirty-ninth transistor M39 is electrically connected to the ninth node N9, a second electrode of the thirty-ninth transistor M39 is electrically connected to the eighth node N8, a control electrode of the fortieth transistor M40 is electrically connected to the second reset signal terminal Reset, and a first electrode of the fortieth transistor M40 is electrically connected to the eighth node N8. A second electrode of the 40th transistor M40 is electrically connected to the first low-level power supply terminal vgl1, a control electrode of the 41st transistor M41 is electrically connected to the fifth node N5, a first electrode of the 41st transistor M41 is electrically connected to the ninth node N9, a second electrode of the 41st transistor M41 is electrically connected to the eighth node N8, a control electrode of the 42nd transistor M42 is electrically connected to the fifth node N5, a first electrode of the 42nd transistor M42 is electrically connected to the eighth node N8, a second electrode of the 42nd transistor M42 is electrically connected to the first low-level power supply terminal vgl1, a control electrode of the 43rd transistor M43 is electrically connected to the sixth node N6, a first electrode of the 43rd transistor M43 is electrically connected to the ninth node N9, and a second electrode of the 43rd transistor M43 is electrically connected to the eighth node N8. The control electrode of the forty-fourth transistor M44 is electrically connected to the eighth node N8, the control electrode of the forty-fourth transistor M44 is electrically connected to the sixth node N6, the first electrode of the forty-fourth transistor M44 is electrically connected to the eighth node N8, the second electrode of the forty-fourth transistor M44 is electrically connected to the first low-level power supply terminal vgl1, the control electrode and the first electrode of the forty-fifth transistor M45 are electrically connected to the third high-level power supply terminal vgh3, the second electrode of the forty-fifth transistor M45 is electrically connected to the control electrode of the forty-sixth transistor M46, the first electrode of the forty-sixth transistor M46 is electrically connected to the third high-level power supply terminal vgh3, the second electrode of the forty-sixth transistor M46 is electrically connected to the sixth node N6, the control electrode of the forty-seventh transistor M47 is electrically connected to the ninth node N9, and the forty-seventh transistor M47 is electrically connected to the ninth node N9. A first electrode of the transistor M47 is electrically connected to the control electrode of the forty-sixth transistor M46, a second electrode of the forty-seventh transistor M47 is electrically connected to the third low-level power supply terminal vgl3, a control electrode of the forty-eighth transistor M48 is electrically connected to the ninth node N9, a first electrode of the forty-eighth transistor M48 is electrically connected to the sixth node N6, a second electrode of the forty-eighth transistor M48 is electrically connected to the first low-level power supply terminal vgl, a control electrode of the forty-ninth transistor M49 is electrically connected to the first clock signal terminal CLK1, a first electrode of the forty-ninth transistor M49 is electrically connected to the sixth node N6, a second electrode of the forty-ninth transistor M49 is electrically connected to the first electrode of the fiftieth transistor M50, and a control electrode of the fiftieth transistor M50 is electrically connected to the first node N1.A second electrode of the 50th transistor M50 is electrically connected to the first low-level power supply terminal vgl, a control electrode of the 51st transistor M51 is electrically connected to the signal input terminal INPUT, a first electrode of the 51st transistor M51 is electrically connected to the sixth node N6, a second electrode of the 51st transistor M51 is electrically connected to the first low-level power supply terminal vgl, a control electrode of the 52nd transistor M52 is electrically connected to the ninth node N9, a first electrode of the 52nd transistor M52 is electrically connected to the fourth clock signal terminal CLK4, a second electrode of the 52nd transistor M52 is electrically connected to the third output terminal OUT3, and a control electrode of the 53rd transistor M53 is electrically connected to the ninth node N9. The first electrode of the fifty-third transistor M53 is electrically connected to the third output terminal OUT3, the second electrode of the fifty-third transistor M53 is electrically connected to the second low-level power supply terminal vgl2, the control electrode of the fifty-fourth transistor M54 is electrically connected to the fifth node N5, the first electrode of the fifty-fourth transistor M54 is electrically connected to the third output terminal OUT3, the second electrode of the fifty-fourth transistor M54 is electrically connected to the second low-level power supply terminal vgl2, the control electrode of the fifty-fifth transistor M55 is electrically connected to the ninth node N9, the first electrode of the fifty-fifth transistor M55 is electrically connected to the fifth clock signal terminal CLK5, and the fifth A second electrode of the fifteenth transistor M55 is electrically connected to the fourth output terminal OUT4, a control electrode of the fifty-sixth transistor M56 is electrically connected to the sixth node N6, a first electrode of the fifty-sixth transistor M56 is electrically connected to the fourth output terminal OUT4, a second electrode of the fifty-sixth transistor M56 is electrically connected to the second low-level power supply terminal vgl2, a control electrode of the fifty-seventh transistor M57 is electrically connected to the fifth node N5, a first electrode of the fifty-seventh transistor M57 is electrically connected to the fourth output terminal OUT4, a second electrode of the fifty-seventh transistor M57 is electrically connected to the second low-level power supply terminal vgl2, and one end of the first capacitor GC1 is electrically connected to the first node N1. One end of the first capacitor GC1 is electrically connected to the first low-level power supply terminal, one end of the second capacitor GC2 is electrically connected to the fourth node N4, the other end of the second capacitor GC2 is electrically connected to the first output terminal OUT1, one end of the third capacitor GC3 is electrically connected to the fourth node N4, the other end of the third capacitor GC3 is electrically connected to the second output terminal OUT2, one end of the fourth capacitor GC4 is electrically connected to the ninth node N9, the other end of the fourth capacitor GC4 is electrically connected to the third output terminal OUT3, one end of the fifth capacitor GC5 is electrically connected to the ninth node N9, and the other end of the fifth capacitor GC5 is electrically connected to the fourth output terminal OUT4.

[0231] In an exemplary embodiment, the signal input terminal INPUT of the N-th shift register is electrically connected to the cascade signal terminal of the N-4-th shift register, the second reset signal terminal Reset of the N-th shift register is electrically connected to the cascade signal terminal of the N+8-th shift register, the first output terminal and the third output terminal of the N-th shift register are electrically connected to the two first scan output terminals, the second output terminal and the fourth output terminal of the N-th shift register are electrically connected to the two second scan output terminals, the first low-level power supply terminal of each stage of the shift register is electrically connected to the first low-level power supply line through the first low-level connecting portion, and the second low-level power supply terminal of each stage of the shift register is electrically connected to the second low-level power supply line through the second low-level connecting portion.

[0232] An embodiment of the present disclosure further provides a display device, including: the above-mentioned display panel.

[0233] The display panel is the display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0234] In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be any product or component with a display function, such as an LCD panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0235] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0236] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0237] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display panel, comprising: A substrate and a driving circuit layer disposed on the substrate, the substrate comprising: a display area and a non-display area, the driving circuit layer comprising: a pixel circuit arranged in an array in the display area, and a plurality of first scanning signal lines and a plurality of second scanning signal lines at least partially located in the display area, at least one pixel circuit being electrically connected to the first scanning signal line and the second scanning signal line, respectively, the first scanning signal line and the second scanning signal line electrically connected to the pixel circuit being located on either side of the pixel circuit and extending at least partially along a first direction; The driving circuit layer includes: multiple first discharge structures and / or multiple second discharge structures, at least one first discharge structure is electrically connected to a first scanning signal line and a second scanning signal line, respectively, the first scanning signal line and the second scanning signal line electrically connected to the first discharge structure are connected to the same row of pixel circuits, at least one second discharge structure is electrically connected to the first scanning signal line and the second scanning signal line, respectively, the first scanning signal line and the second scanning signal line electrically connected to the second discharge structure are connected to adjacent rows of pixel circuits, and are located between adjacent rows of pixel circuits.

2. The display panel according to claim 1, wherein The driving circuit layer further includes: a gate driving circuit located in a non-display area, a first low-level power line and a second low-level power line extending along a second direction, and a plurality of first scan output lines and a plurality of second scan output lines extending at least partially along the first direction, wherein the first direction and the second direction intersect, the first low-level power line and the second low-level power line are arranged in the same layer, the first scan output line and the second scan output line are arranged in the same layer, and the first low-level power line is located on a side of the first scan output line close to the substrate; The first scan output line is electrically connected to the first scan signal line, the second scan output line is electrically connected to the second scan signal line, and the gate drive circuit is electrically connected to the first low-level power line, the second low-level power line, the plurality of first scan output lines, and the plurality of second scan output lines, respectively; The first low level power line and the second low level power line are located on a side of the gate driving circuit close to the display area, and the first low level power line is located on a side of the second low level power line away from the display area.

3. The display panel according to claim 2, wherein: The driving circuit layer further includes: a plurality of data signal lines at least partially located in the display area, and a plurality of electrostatic discharge circuits and a plurality of electrostatic release lines located in the non-display area, wherein the data signal lines and the electrostatic release lines at least partially extend along the second direction, and the data signal lines and the electrostatic release lines are arranged in the same layer; The pixel circuit is electrically connected to the data signal line, and at least one electrostatic release circuit is electrically connected to the data signal line and the electrostatic release line respectively.

4. The display panel according to claim 3, wherein: The driving circuit layer further includes: a first power supply line at least partially located in the display area, and a first power supply line, a second power supply line, and a second power supply line located in the non-display area, the first power supply line providing a high level signal, and the second power supply line providing a low level signal; The first power supply line and the second power supply line are arranged in the same layer, the first power supply line is located on a side of the first power supply line away from the substrate, the second power supply line is located on a side of the second power supply line close to the substrate, the first power supply line is located on a side of the second power supply line away from the display area, and the second power supply line partially surrounds the first power supply line, and the second power supply line is arranged on a side of the first power supply line away from the display area and surrounds at least one side of the display area; The pixel circuit is electrically connected to the first power line, the orthographic projection of the first power supply line on the substrate partially overlaps with the orthographic projections of the first power line and the second power line on the substrate, and is electrically connected to the first power line, the orthographic projection of the second power line on the substrate partially overlaps with the multiple electrostatic release lines and the orthographic projection of the first power line on the substrate, and is electrically connected to the multiple electrostatic release lines and the second power supply line respectively.

5. The display panel according to claim 4, wherein: The driving circuit layer further includes: a first signal connection line and a second signal connection line, wherein the first signal connection line and the second signal connection line at least partially extend along a first direction, and the first signal connection line and the second signal connection line are electrically connected to different electrostatic discharge circuits respectively; The pixel circuit includes: a first pixel circuit and a second pixel circuit, wherein the second pixel circuit is located on a side of the first pixel circuit close to the second power supply line; An orthographic projection of a first scan signal line electrically connected to the first pixel circuit on the substrate partially overlaps with an orthographic projection of the first scan output line on the substrate, and the first pixel circuit is electrically connected to the first scan output line; an orthographic projection of a second scan signal line electrically connected to the first pixel circuit on the substrate partially overlaps with an orthographic projection of the second scan output line on the substrate, and the first pixel circuit is electrically connected to the second scan output line; The orthographic projection of the second scanning signal line electrically connected to the second pixel circuit on the substrate partially overlaps with the orthographic projection of the first signal connection line on the substrate, and is electrically connected to the first signal connection line. The orthographic projection of the first scanning signal line electrically connected to the second pixel circuit on the substrate partially overlaps with the orthographic projection of the second signal connection line on the substrate, and is electrically connected to the second signal connection line. The display panel according to claim 5 , wherein: The driving circuit layer further includes: a plurality of first low-level connecting portions arranged at intervals and a plurality of second low-level connecting portions arranged at intervals, the first low-level connecting portions and the second low-level connecting portions are arranged in the same layer, and the first low-level connecting portions are located on a side of the first low-level power line away from the substrate.

7. The display panel according to claim 6, wherein: When the display panel includes the first discharge structure, the first scanning signal line is provided with a first protrusion extending along the second direction, the first protrusion is located on a side of the first scanning signal line close to the electrically connected pixel circuit, and the first protrusion includes: a first tip; The second scanning signal line is provided with a second protrusion extending along the second direction, the second protrusion is located on a side of the second scanning signal line close to the electrically connected pixel circuit, and the second protrusion includes: a second tip; A first tip of a first scanning signal line electrically connected to the first discharge structure and a second tip of a second scanning signal line electrically connected to the first discharge structure are arranged opposite to each other, and an orthographic projection of the first discharge structure on the substrate at least partially overlaps with an orthographic projection of the first tip of the first scanning signal line electrically connected to the first discharge structure and an orthographic projection of the second tip of the second scanning signal line electrically connected to the first discharge structure on the substrate.

8. The display panel according to claim 6 or 7, wherein: When the display panel includes: the second discharge structure, the first scan signal line is provided with a third protrusion extending at least partially along the second direction, the third protrusion is located on a side of the first scan signal line close to the gate driving circuit, and the third protrusion includes: a third tip; The second scanning signal line is further provided with a fourth protrusion extending at least partially along the second direction, the fourth protrusion being located on a side of the second scanning signal line close to the gate driving circuit, the fourth protrusion comprising: a fourth tip; The third tip of the first scan signal line electrically connected to the second discharge structure is arranged opposite to the fourth tip of the second scan signal line electrically connected to the second discharge structure, and an orthographic projection of the second discharge structure on the substrate at least partially overlaps with an orthographic projection of the third tip of the first scan signal line electrically connected to the second discharge structure and an orthographic projection of the fourth tip of the second scan signal line electrically connected to the second discharge structure on the substrate.

9. The display panel according to claim 6 or 7, wherein: When the display panel includes: a second discharge structure, the second discharge structure is electrically connected to the first scan signal line through the first signal line, and is electrically connected to the second scan signal line through the second scan output line; The first signal line includes: a first scan output line or a second signal connection line. When the pixel circuit electrically connected to the first scan signal line is a first pixel circuit, the first signal line is a first scan output line. When the pixel circuit electrically connected to the first scan signal line is a second pixel circuit, the first signal line is a second signal connection line.

10. The display panel according to claim 9, wherein: The first signal line electrically connected to the second discharge structure is provided with a fifth protrusion extending at least partially along the second direction, the fifth protrusion is located on a side of the first signal line close to the gate driving circuit, and the fifth protrusion includes: a fifth tip; The second scan output line electrically connected to the second scan signal line is provided with a sixth protrusion extending at least partially along the second direction, the sixth protrusion being located on a side of the second scan output line close to the gate driving circuit, the sixth protrusion comprising: a sixth tip; The fifth tip of the first signal line electrically connected to the second discharge structure and the sixth tip of the second scan output line electrically connected to the second discharge structure are arranged opposite to each other, and an orthographic projection of the second discharge structure on the substrate at least partially overlaps with an orthographic projection of the fifth tip of the first signal line electrically connected to the second discharge structure and an orthographic projection of the sixth tip of the second scan output line electrically connected to the second discharge structure on the substrate.

11. The display panel according to claim 8 or 10, wherein: The second discharge structure is further electrically connected to a second low-level power line or a second low-level connection portion.

12. The display panel according to claim 11, wherein: When the second discharge structure is electrically connected to the second low-level power line, the second low-level power line is provided with a seventh protrusion extending along the first direction, the seventh protrusion comprising: a seventh tip; A virtual straight line passing through the seventh tip and extending along the first direction is located between the other two tips at least partially overlapping with the second discharge structure on the substrate; The orthographic projection of the second discharge structure on the substrate also partially overlaps with the orthographic projection of the seventh tip of the electrically connected second low-level power line on the substrate.

13. The display panel according to claim 11, wherein: When the second discharge structure is electrically connected to the second low-level connection portion, the second low-level connection portion is provided with an eighth protrusion extending along the first direction, the eighth protrusion comprising: an eighth tip; A virtual straight line passing through the eighth tip and extending along the first direction is located between the other two tips at least partially overlapping with the second discharge structure on the substrate; The orthographic projection of the second discharge structure on the substrate also partially overlaps with the orthographic projection of the eighth tip of the electrically connected second low-level connection portion on the substrate.

14. The display panel according to claim 6, wherein: The driving circuit layer further includes: at least one discharge structure among a third discharge structure, a fourth discharge structure, a fifth discharge structure and a sixth discharge structure; The third discharge structure is electrically connected to a scan signal line close to a non-display area and an electrostatic release line close to a gate drive circuit, respectively. The fourth discharge structure is electrically connected to a second low-level power line and an electrostatic release line close to a gate drive circuit, respectively. The fifth discharge structure is electrically connected to a first low-level power line and a second low-level power line, respectively. The sixth discharge structure is electrically connected to a first power supply line and a second power supply line, respectively. The scan signal line is a first scan signal line or a second scan signal line.

15. The display panel according to claim 14, wherein: The first discharge structure, the second discharge structure, the third discharge structure, the fourth discharge structure, the fifth discharge structure and the sixth discharge structure are arranged on the same layer.

16. The display panel according to claim 14 or 15, wherein: When the driving circuit layer includes the third discharge structure or the fourth discharge structure, the electrostatic release line close to the gate driving circuit includes a first connecting line extending along the first direction and a second connecting line extending along the second direction, and the first connecting line is electrically connected to the second connecting line.

17. The display panel according to claim 16, wherein: The scanning signal line electrically connected to the third discharge structure is provided with a ninth protrusion extending along the second direction, the ninth protrusion being located on a side of the scanning signal line close to the electrostatic discharge circuit, the ninth protrusion comprising: a ninth tip; The first connection line of the electrostatic discharge line electrically connected to the third discharge structure is provided with a tenth protrusion, the tenth protrusion is located on a side of the first connection line close to the electrostatic discharge circuit, and the tenth protrusion includes: a tenth tip; The ninth tip of the scanning signal line electrically connected to the third discharge structure and the tenth tip of the electrostatic release line electrically connected to the third discharge structure are arranged opposite to each other. The orthographic projection of the third discharge structure on the substrate at least partially overlaps with the orthographic projections of the ninth tip of the scan signal line electrically connected thereto and the tenth tip of the electrostatic discharge line electrically connected thereto.

18. The display panel according to claim 16, wherein: The third discharge structure is electrically connected to the scan signal line through the first signal connection line.

19. The display panel according to claim 18, wherein: The first signal connection line electrically connected to the third discharge structure is provided with an eleventh protrusion extending along the second direction, the eleventh protrusion is located on a side of the first signal connection line close to the electrostatic discharge circuit, and the eleventh protrusion includes: an eleventh tip; The first connection line of the electrostatic release line electrically connected to the third discharge structure is provided with a tenth protrusion, the tenth protrusion is located on a side of the first connection line of the electrostatic release line close to the electrostatic release circuit, the tenth protrusion includes: a tenth tip; The eleventh tip of the first signal connection line electrically connected to the third discharge structure and the tenth tip of the electrostatic release line electrically connected to the third discharge structure are arranged opposite to each other. The orthographic projection of the third discharge structure on the substrate at least partially overlaps with the orthographic projections of the eleventh tip of the electrically connected first signal connection line and the tenth tip of the electrically connected electrostatic discharge line on the substrate.

20. The display panel according to claim 14 or 15, wherein: The electrostatic release line electrically connected to the fourth discharge structure includes: a twelfth protrusion, the twelfth protrusion is located on a side of the first connection line of the electrostatic release line close to the gate drive circuit, and the twelfth protrusion includes: a twelfth tip; The second low-level power line is further provided with a thirteenth protrusion extending along the first direction, the thirteenth protrusion is located on a side of the second low-level power line close to the display area, and the thirteenth protrusion includes a thirteenth tip; The twelfth tip of the electrostatic discharge line electrically connected to the fourth discharge structure is arranged opposite to the thirteenth tip of the second low-level power line; The orthographic projection of the fourth discharge structure on the substrate at least partially overlaps with the orthographic projection of the twelfth tip of the electrically connected electrostatic discharge line on the substrate and the orthographic projection of the thirteenth tip of the second low-level power line on the substrate.

21. The display panel according to claim 14 or 15, wherein: The first low-level power supply line is provided with a fourteenth protrusion, the fourteenth protrusion is located on a side of the first low-level power supply line close to the second power supply line, the fourteenth protrusion includes: a fourteenth tip; The second low-level power line is provided with a fifteenth protrusion, the fifteenth protrusion is located on a side of the second low-level power line close to the second power supply line, and the fifteenth protrusion includes: a fifteenth tip; The fourteenth tip of the first low-level power line is arranged opposite to the fifteenth tip of the second low-level power line; The orthographic projection of the fifth discharge structure on the substrate at least partially overlaps with the orthographic projection of the fourteenth tip of the first low-level power line on the substrate and the orthographic projection of the fifteenth tip of the second low-level power line on the substrate.

22. The display panel according to claim 14 or 15, wherein: The first power supply line is provided with a sixteenth protrusion extending along the second direction, the sixteenth protrusion is located on a side of the first power supply line close to the second power supply line, and the sixteenth protrusion includes a sixteenth tip; The second power supply line is provided with a seventeenth protrusion extending along the second direction, the seventeenth protrusion is located on a side of the second power supply line close to the first power supply line, and the seventeenth protrusion includes a seventeenth tip; The sixteenth tip of the first power supply line is arranged opposite to the seventeenth tip of the second power supply line; An orthographic projection of the sixth discharge structure on the substrate at least partially overlaps with an orthographic projection of the sixteenth tip of the first power supply line on the substrate and an orthographic projection of the seventeenth tip of the second power supply line on the substrate.

23. The display panel according to claim 6, wherein: The driving circuit layer further includes: a plurality of first scanning connection parts, a plurality of second scanning connection parts, a plurality of data connection parts, a plurality of power connection parts, a plurality of sensing signal lines, a plurality of sensing connection parts and a power connection line; The first scan connection portion is electrically connected to the first scan signal line, the second scan connection portion is electrically connected to the second scan signal line, the data connection portion is electrically connected to the data signal line, the power connection portion is electrically connected to the first power line, the sensing signal line is electrically connected to the pixel circuit and the sensing connection portion, and the power connection line is electrically connected to the second power line and the second power supply line respectively.

24. The display panel according to claim 23, wherein: The driving circuit layer includes: a shielding layer, a semiconductor layer, a first conductive layer and a second conductive layer; The shielding layer at least includes: a second power line; The semiconductor layer at least includes: one or more of the first discharge structure to the sixth discharge structure; The first conductive layer at least includes: a first power supply line, a second power supply line, a first low-level power line, a second low-level power line, a first scan signal line, a second scan signal line, a data connection part, a power connection part and a sensing connection part. The second conductive layer includes at least: a data signal line, a first power line, a first signal connection line, a second signal connection line, an electrostatic release line, a first scan output line, a second scan output line, a first scan connection part, a second scan connection part, a power connection line, a first low-level connection part and a second low-level connection part.

25. A display device comprising: The display panel according to any one of claims 1 to 24.