Array substrate and display devic

Abstract

An array substrate and a display device. The array substrate comprises a base substrate, a gate line, a gate driving structure, an adapter structure, and an insulating layer. The base substrate comprises a first region and a second region, the gate line is located in the first region, and the gate driving structure is located in the second region; the adapter structure is located on the side of the gate line away from the base substrate, and the gate line is electrically connected to the gate driving structure by means of the adapter structure; the insulating layer is located between the gate line and the adapter structure and comprises a first via hole and a second via hole. The gate line comprises a first connecting portion and a second connecting portion, the second connecting portion is located between the gate driving structure and the first connecting portion, the first connecting portion is electrically connected to the adapter structure by means of the first via hole, and a straight line extending in a direction perpendicular to the base substrate sequentially passes through the second connecting portion, the second via hole and the adapter structure. In the present invention, the gate line is electrically connected to the adapter structure by means of the first connecting portion and the second connecting portion, thereby facilitating improving an electrical connection effect of the gate line and the gate driving structure.

Description

Array substrate and display device Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate and a display device. Background Art

[0002] Currently, large-size organic light-emitting diode display devices are becoming increasingly popular due to their high contrast, self-luminescence and other characteristics. For example, large-size organic light-emitting diode display devices may include 55-inch products, 95-inch products and the like.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide an array substrate and a display device.

[0005] An embodiment of the present disclosure provides an array substrate, comprising: a substrate substrate including a first region and a second region, the second region being located on at least one side of the first region in a first direction; a plurality of gate lines located in the first region of the substrate substrate, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; a gate drive structure located in the second region of the substrate substrate, the gate drive structure being configured to be electrically connected to the plurality of gate lines; a transfer structure located on a side of the plurality of gate lines away from the substrate substrate, the plurality of gate lines being electrically connected to the gate drive structure via the transfer structure; and an insulating layer located between the plurality of gate lines and the transfer structure. A portion of at least one gate line of the plurality of gate lines close to the gate drive structure comprises a first connecting portion and a second connecting portion, the second connecting portion being located between the gate drive structure and the first connecting portion; the insulating layer comprising at least one first via and at least one second via, the first connecting portion being electrically connected to the transfer structure via the first via to be electrically connected to the gate drive structure, and a straight line extending in a direction perpendicular to the substrate substrate sequentially passes through the second connecting portion, the second via, and the transfer structure.

[0006] For example, according to an embodiment of the present disclosure, at least a portion of the second connection portion is electrically connected to the transfer structure through the second via so as to be electrically connected to the gate drive structure; the transfer structure includes a plurality of sub-transfer structures, and the two sub-transfer structures that are respectively electrically connected to the first connection portion and the second connection portion of the same gate line are electrically connected to each other.

[0007] For example, according to an embodiment of the present disclosure, each gate line includes a gate line main body extending along a direction intersecting with the second direction, and in at least one gate line, the first connection portion and the second connection portion both protrude on the same side of the gate line main body in the second direction.

[0008] For example, according to an embodiment of the present disclosure, the transfer structure also includes a connecting line, and the two sub-transfer structures that are respectively electrically connected to the first connecting part and the second connecting part of the same gate line are electrically connected through the connecting line, and the two sub-transfer structures, the gate line main body and the connecting line form a hollow area.

[0009] For example, according to an embodiment of the present disclosure, the second connecting portion includes a tip portion.

[0010] For example, according to an embodiment of the present disclosure, the second connecting portion is located at an end of the gate line close to the gate driving structure.

[0011] For example, according to an embodiment of the present disclosure, the second connecting portion also includes a main body portion connected to the tip portion, the main body portion is closer to the gate line main body portion than the tip portion, and the ratio of the area of ​​the main body portion's orthographic projection on the base substrate to the area of ​​the first connecting portion's orthographic projection on the base substrate is 0.9 to 1.1.

[0012] For example, according to an embodiment of the present disclosure, in the main body portion and the tip portion connected to each other, the area of ​​the orthographic projection of the tip portion on the base substrate is smaller than the area of ​​the orthographic projection of the main body portion on the base substrate.

[0013] For example, according to an embodiment of the present disclosure, the gate drive structure also includes a first power line, which is the structure closest to the multiple gate lines among the structures in the gate drive structure that are arranged on the same layer as the multiple gate lines; the transfer structure also includes a connecting line electrically connected to the sub-transfer structure, and the extension direction of the first power line intersects with the extension direction of at least part of the connecting line. The gate drive structure includes an output end electrically connected to the multiple gate lines, and the output end is located on the side of the first power line away from the multiple gate lines, and the connecting line crosses the first power line and is electrically connected to the output end.

[0014] For example, according to an embodiment of the present disclosure, the distance between the gate line main body and the connecting line corresponding to the gate line main body in the second direction is smaller than the size of the first connecting portion in the second direction.

[0015] For example, according to an embodiment of the present disclosure, the at least one gate line is provided with at least one protrusion, and the at least one protrusion is located between the first connecting portion and the second connecting portion.

[0016] For example, according to an embodiment of the present disclosure, the at least one protrusion includes a plurality of protrusions, and among the plurality of protrusions, the area of ​​the orthographic projection of a protrusion closest to the second connecting portion on the substrate is larger than the area of ​​the orthographic projection of a protrusion farthest from the second connecting portion on the substrate.

[0017] For example, according to an embodiment of the present disclosure, the at least one first via includes multiple first vias, the at least one second via includes multiple second vias, and the ratio of the number of the multiple first vias to the number of the multiple second vias is 0.9 to 1.1.

[0018] For example, according to an embodiment of the present disclosure, the array substrate further includes: a plurality of sub-pixels, located in the first area on the base substrate and located on a side of the first connection portion away from the gate drive structure. The plurality of gate lines include a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines and the plurality of second gate lines are alternately arranged along the second direction, at least some of the sub-pixels include light-emitting elements and a drive circuit for driving the light-emitting elements to emit light, the drive circuit includes at least two transistors, and gates of two of the at least two transistors are electrically connected to the first gate line and the second gate line, respectively.

[0019] For example, according to an embodiment of the present disclosure, in the first gate line and the second gate line electrically connected to the same driving circuit, the first connection portion and the second connection portion of the first gate line are both located on a side of the first gate line close to the second gate line, and the first connection portion and the second connection portion of the second gate line are both located on a side of the second gate line close to the first gate line.

[0020] For example, according to an embodiment of the present disclosure, the array substrate further includes: a plurality of data lines located in the first region on the base substrate and arranged along the first direction; a plurality of second power lines located in the first region on the base substrate and arranged along the first direction, with at least a portion of the plurality of second power lines being disposed on the same layer as the plurality of data lines. The plurality of data lines are disposed on the same layer as at least a portion of the switching structure, and the driving circuit of each sub-pixel is electrically connected to one data line.

[0021] For example, according to an embodiment of the present disclosure, the driving circuit of at least part of the sub-pixels includes an active layer, the multiple sub-pixels include multiple first color sub-pixels and multiple second color sub-pixels, and the area of ​​the active layer of a first color sub-pixel is larger than the area of ​​the active layer of a second color sub-pixel.

[0022] For example, according to an embodiment of the present disclosure, the multiple sub-pixels are arranged in an array along the first direction and the second direction to form a plurality of pixel rows and a plurality of pixel columns, one of the first direction and the second direction is a row direction, and the other of the first direction and the second direction is a column direction, the multiple sub-pixels also include a plurality of third color sub-pixels and a plurality of fourth color sub-pixels, and at least one pixel row includes the first color sub-pixels, the second color sub-pixels, the third color sub-pixels and the fourth color sub-pixels arranged in a circular pattern along the row direction.

[0023] For example, according to an embodiment of the present disclosure, the first gate line and the second gate line electrically connected to the same driving circuit are respectively located on both sides of the pixel row where the driving circuit is located.

[0024] For example, according to an embodiment of the present disclosure, the at least one gate line is provided with at least one opening.

[0025] For example, according to an embodiment of the present disclosure, each gate line of at least part of the multiple gate lines includes multiple sub-gate lines arranged at intervals along its extension direction, and two adjacent sub-gate lines are electrically connected through a connecting unit, and the connecting unit and the gate line are located in different layers.

[0026] For example, according to an embodiment of the present disclosure, the connection unit is located between two adjacent sub-gate lines, and the connection unit includes a first connection unit and a second connection unit that are arranged between the two adjacent sub-gate lines and stacked, the first connection unit is located between the gate line and the base substrate, the second connection unit is located on the side of the gate line away from the base substrate, the first connection unit is electrically connected to the second connection unit, and the gate line is electrically connected to the second connection unit.

[0027] For example, according to an embodiment of the present disclosure, the array substrate further comprises: a plurality of data lines arranged along the first direction, the plurality of data lines being disposed on the same layer as at least part of the transition structure, and at least part of the plurality of data lines being disposed on the same layer as the second connection unit.

[0028] An embodiment of the present disclosure provides another array substrate, comprising: a substrate substrate, comprising a first region and a second region, wherein the second region is located on at least one side of the first region in a first direction; a plurality of gate lines, located in the first region of the substrate substrate, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; a gate drive structure, located in the second region of the substrate substrate, and the gate drive structure being configured to be electrically connected to the plurality of gate lines; a transfer structure, located on a side of the plurality of gate lines away from the substrate substrate, and the plurality of gate lines being electrically connected to the gate drive structure through the transfer structure; an insulating layer, located between the plurality of gate lines and the transfer structure. A portion of at least one of the plurality of gate lines close to the gate drive structure comprises a connecting portion and an electrostatic release pad, the electrostatic release pad being located between the gate drive structure and the connecting portion, and the electrostatic release pad comprising a tip portion; the insulating layer comprising at least one first via hole, the connecting portion being electrically connected to the transfer structure through the first via hole to be electrically connected to the gate drive structure.

[0029] For example, according to an embodiment of the present disclosure, the insulating layer further includes at least one second via hole, and a straight line extending in a direction perpendicular to the base substrate passes through the electrostatic release pad, the second via hole, and the transfer structure in sequence.

[0030] For example, according to an embodiment of the present disclosure, the electrostatic release pad is located at an end of the gate line close to the gate driving structure.

[0031] For example, according to an embodiment of the present disclosure, the electrostatic release pad further includes a main body connected to the tip portion, and a ratio of an area of ​​the main body on the base substrate to an area of ​​an orthographic projection of the connecting portion on the base substrate is 0.9 to 1.1.

[0032] For example, according to an embodiment of the present disclosure, the at least one gate line is provided with at least one protrusion, and the at least one protrusion is located between the connecting portion and the electrostatic release pad.

[0033] For example, according to an embodiment of the present disclosure, the array substrate further comprises: a plurality of sub-pixels, located in the first region on the base substrate and located on a side of the connection portion away from the gate drive structure; the plurality of gate lines comprise a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines and the plurality of second gate lines being alternately arranged along the second direction; at least some of the sub-pixels comprise light-emitting elements and a drive circuit for driving the light-emitting elements to emit light; the drive circuit comprises at least two transistors, and gates of two of the at least two transistors are electrically connected to the first gate line and the second gate line, respectively.

[0034] For example, according to an embodiment of the present disclosure, in the first gate line and the second gate line electrically connected to the same driving circuit, the connecting portion and the electrostatic release pad of the first gate line are both located on a side of the first gate line close to the second gate line, and the connecting portion and the electrostatic release pad of the second gate line are both located on a side of the second gate line close to the first gate line.

[0035] For example, according to an embodiment of the present disclosure, the multiple sub-pixels are arranged in an array along the first direction and the second direction to form multiple pixel rows and multiple pixel columns, and the first gate line and the second gate line electrically connected to the same driving circuit are respectively located on both sides of the pixel row where the driving circuit is located.

[0036] An embodiment of the present disclosure provides another array substrate, comprising: a base substrate, comprising a first region and a second region, wherein the second region is located on at least one side of the first region in a first direction; a plurality of gate lines, located in the first region of the base substrate, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; a gate drive structure, located in the second region of the base substrate, and the gate drive structure being configured to be electrically connected to the plurality of gate lines. Each gate line of at least some of the plurality of gate lines comprises a plurality of sub-gate lines arranged at intervals along its extension direction, two adjacent sub-gate lines being electrically connected via a connecting unit, and the connecting unit being located on a different layer from the gate line.

[0037] For example, according to an embodiment of the present disclosure, the connection unit is located between two adjacent sub-gate lines, and the connection unit includes a first connection unit and a second connection unit that are arranged between the two adjacent sub-gate lines and stacked, the first connection unit is located between the gate line and the base substrate, the second connection unit is located on the side of the gate line away from the base substrate, the first connection unit is electrically connected to the second connection unit, and the gate line is electrically connected to the second connection unit.

[0038] An embodiment of the present disclosure provides a display device, comprising the array substrate provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0040] FIG1 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.

[0041] FIG2 is an enlarged view of area A shown in FIG1 .

[0042] FIG3 is a schematic diagram of a partial cross-section structure taken along line BB′ shown in FIG2 .

[0043] FIG4 is a schematic diagram of a partial planar structure of an array substrate.

[0044] FIG5 is a schematic diagram of a partial structure of a gate line close to a gate driving structure according to an example of an embodiment of the present disclosure.

[0045] FIG6 is a schematic diagram of a portion of the structure of a gate line close to a gate driving structure according to an example of an embodiment of the present disclosure.

[0046] FIG7 is a schematic diagram of a portion of the structure of a gate line close to a gate driving structure according to an example of an embodiment of the present disclosure.

[0047] FIG. 8 is a schematic diagram of a 3T1C driving circuit for the array substrate.

[0048] FIG9A is a schematic plan view of an active layer in an array substrate provided in at least one embodiment of the present disclosure.

[0049] 9B is a plan view schematically showing a stack of an active layer and a first conductive layer where gate lines are located in an array substrate provided by at least one embodiment of the present disclosure.

[0050] FIG9C is a plan view of a second conductive layer where a transfer structure is located in an array substrate provided by at least one embodiment of the present disclosure.

[0051] 9D is a plan view schematically showing the stacking of the active layer, the first conductive layer, and the second conductive layer in the array substrate provided by at least one embodiment of the present disclosure.

[0052] FIG9E is a schematic plan view of a first electrode of a light-emitting element in an array substrate provided in at least one embodiment of the present disclosure.

[0053] 9F is a plan view schematically showing a stack of an active layer, a first conductive layer, a second conductive layer, and a first electrode of a light-emitting element in an array substrate provided by at least one embodiment of the present disclosure.

[0054] 10 and 11 are schematic plan views of a partial layer structure provided according to another example of an embodiment of the present disclosure.

[0055] FIG12 is a schematic diagram of a partial cross-sectional structure taken along line CC′ shown in FIG11 . DETAILED DESCRIPTION

[0056] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0057] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0058] The features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the features such as "parallel", "perpendicular" and "same" in the strict sense, as well as the cases where "approximately parallel", "approximately perpendicular" and "approximately the same" include certain errors. Taking into account the errors associated with the measurement and the measurement of specific quantities (for example, the limitations of the measurement system), it means that it is within the acceptable deviation range for a specific value determined by ordinary technicians in this field. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value. When the number of a component is not specifically specified in the following embodiments of the present disclosure, it means that the component can be one or more, or it can be understood as at least one. "At least one" means one or more, and "more than one" means at least two. The "same-layer arrangement" referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and their materials can be the same or different. The "integrated arrangement structure" in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process and connected to each other, and their materials can be the same or different.

[0059] The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate, gate lines located on the base substrate, a gate drive structure, a transfer structure, and an insulating layer. The base substrate includes a first region and a second region, the second region being located on at least one side of the first region in a first direction; a plurality of gate lines are located in the first region, the plurality of gate lines are arranged along a second direction, and the first direction intersects the second direction; the gate drive structure is located in the second region, and the gate drive structure is configured to be electrically connected to the plurality of gate lines; the transfer structure is located on a side of the plurality of gate lines away from the base substrate, and the plurality of gate lines are electrically connected to the gate drive structure through the transfer structure; the insulating layer is located between the plurality of gate lines and the transfer structure. A portion of at least one of the plurality of gate lines close to the gate drive structure includes a first connecting portion and a second connecting portion, the second connecting portion being located between the gate drive structure and the first connecting portion; the insulating layer includes at least one first via and at least one second via, the first connecting portion being electrically connected to the transfer structure through the first via to be electrically connected to the gate drive structure, and a straight line extending in a direction perpendicular to the base substrate sequentially passes through the second connecting portion, the second via, and the transfer structure. The gate lines in the array substrate provided by the embodiment of the present disclosure are electrically connected to the transfer structure through the first connecting portion and the second connecting portion, which is beneficial to improving the electrical connection effect between the gate lines and the gate driving structure.

[0060] The array substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0061] Figure 1 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure, Figure 2 is an enlarged view of area A shown in Figure 1, and Figure 3 is a schematic diagram of a partial cross-sectional structure taken along line BB' shown in Figure 2. As shown in Figures 1 to 3, the array substrate includes a base substrate 100, a plurality of gate lines 200 located on the base substrate 100, a gate drive structure 300, a transfer structure 400, and an insulating layer 500. The base substrate 100 includes a first area 101 and a second area 102, and the second area 102 is located on at least one side of the first area 101 in a first direction. For example, the first area 101 includes a display area for displaying an image, and the second area 102 includes a non-display area surrounding the display area. Figure 1 schematically shows the position where the first area 101 and the second area 102 meet, such as the dividing line between the first area 101 and the second area 102 can be located in the gap between the gate line 200 and the gate drive structure 300. For example, the second region 102 may be located on only one side of the first region 101 , or may be located on both sides of the first region 101 in the first direction, and this is not limited in the embodiment of the present disclosure.

[0062] As shown in Figures 1 to 3, a plurality of gate lines 200 are located in the first area 101 of the substrate 100, and the plurality of gate lines 200 are arranged along the second direction, and the first direction intersects the second direction. For example, Figure 1 schematically shows that the first direction is the X direction and the second direction is the Y direction, and the first direction and the second direction can be perpendicular. However, it is not limited to this, and the first direction and the second direction can be interchangeable, such as one of the first direction and the second direction can be the row direction and the other can be the column direction. For example, the angle between the first direction and the second direction can be 30 to 150 degrees, such as 60 to 120 degrees, such as 80 to 100 degrees, such as 85 to 95 degrees, etc.

[0063] As shown in Figures 1 to 3, the gate drive structure 300 is located in the second area 102 of the base substrate 100, and the gate drive structure 300 is configured to be electrically connected to the plurality of gate lines 200. For example, the gate drive structure 300 may include a plurality of gate drive units (gate drive integration on the array substrate, GOA), each gate drive unit being electrically connected to a row of sub-pixels to output a row scan signal that drives the sub-pixels in this row. For example, the gate drive unit may include a voltage-related CLK and CLKB signal pair, an input signal (Input), a gate shutoff signal (Vss), a reset signal (Reset), and an output signal (Output) of the current row. For example, the gate drive unit may include a 4T1C (including 4 TFTs and 1 capacitor C) unit structure, an 8T1C (including 8 TFTs and 1 capacitor C) unit structure, and the like.

[0064] As shown in Figures 1 to 3, the transfer structure 400 is located on a side of the plurality of gate lines 200 away from the base substrate 100, and the plurality of gate lines 200 are electrically connected to the gate driving structure 300 through the transfer structure 400. The insulating layer 500 is located between the plurality of gate lines 200 and the transfer structure 400. For example, the insulating layer 500 may be an interlayer insulating layer.

[0065] As shown in Figures 1 to 3, a portion of at least one gate line 200 of the plurality of gate lines 200 near the gate driving structure 300 includes a first connecting portion 210 and a second connecting portion 220, and the second connecting portion 220 is located between the gate driving structure 300 and the first connecting portion 210. For example, at least some of the gate lines 200 of the plurality of gate lines 200 include a first connecting portion 210 and a second connecting portion 220. For example, each gate line 200 of the plurality of gate lines 200 includes a first connecting portion 210 and a second connecting portion 220.

[0066] As shown in Figures 1 to 3, the insulating layer 500 includes at least one first via 501 and at least one second via 502. The first connection portion 210 is electrically connected to the adapter structure 400 through the first via 501 to electrically connect to the gate drive structure 300. A straight line extending in a direction perpendicular to the base substrate 100 sequentially passes through the second connection portion 220, the second via 502, and the adapter structure 400. The gate lines in the array substrate provided in the embodiments of the present disclosure are electrically connected to the adapter structure through the first and second connection portions, which helps to improve the electrical connection between the gate lines and the gate drive structure.

[0067] In some examples, as shown in FIG. 1 to FIG. 3 , at least a portion of the second connection portion 220 is electrically connected to the transfer structure 400 through the second via 502 to be electrically connected to the gate driving structure 300 .

[0068] In some examples, as shown in Figures 1 to 3, the at least one first via 501 includes a plurality of first vias 501, and the at least one second via 502 includes a plurality of second vias 502, and the ratio of the number of the plurality of first vias 501 to the number of the plurality of second vias 502 is 0.9 to 1.1. For example, the number of the plurality of first vias 501 is the same as the number of the plurality of second vias 502. By setting the number of the first vias to be the same as the number of the second vias, the disclosed embodiments can help improve the uniformity of the electrical connection between the first connecting portion and the second connecting portion and the transfer structure while reducing process manufacturing costs.

[0069] For example, the number of the first via holes 501 may be 2 to 20, such as 3 to 18, such as 4 to 16, etc. Providing multiple first via holes and multiple second via holes is beneficial to improving the electrical connection effect between the gate line and the transfer structure.

[0070] For example, the first connection portion 210 is connected to the adapter structure 400 through all of the first vias 501 that overlap with it. For example, the second connection portion 220 is connected to the adapter structure 400 through at least some of the second vias 502 that overlap with it. For example, the second connection portion 220 is connected to the adapter structure 400 through all of the second vias 502 that overlap with it. The disclosed embodiments improve the electrical connection between the gate line and the gate drive structure by electrically connecting at least a portion of the second connection portion to the adapter structure while simultaneously electrically connecting the first connection portion to the adapter structure.

[0071] For example, as shown in FIG. 3 , the array substrate further includes a buffer layer 101 and a gate insulating layer 102 located between the first connecting portion 220 and the base substrate 100 .

[0072] For example, the first connection portion 210 and the second connection portion 220 can be connection portions with the same shape and area, or at least one of the shape and area of ​​the first connection portion 210 and the second connection portion 220 is different, but the area of ​​the portion of the first connection portion 210 used for electrical connection to the adapter structure 400 and the area of ​​the portion of the second connection portion 220 used for electrical connection to the adapter structure 400 are the same.

[0073] In some examples, as shown in Figures 1 to 3, the transfer structure 400 includes multiple sub-transfer structures 410, and two sub-transfer structures 410 electrically connected to the first connection portion 210 and the second connection portion 220 of the same gate line 200 are electrically connected to each other. For example, along a direction perpendicular to the base substrate 100 (i.e., the Z direction shown in Figure 3), the first connection portion 210 and the sub-transfer structure 410 electrically connected thereto overlap, and the second connection portion 220 and the sub-transfer structure 410 electrically connected thereto overlap.

[0074] For example, as shown in Figures 1 and 2, the ratio of the area of ​​the orthographic projection of the first connection portion 210 on the base substrate 100 to the area of ​​the orthographic projection of the sub-interchange structure 410 on the base substrate 100 that overlaps with the first connection portion 210 is 0.5-1.5, or 0.6-1.4, or 0.7-1.3, or 0.8-1.2. For example, the orthographic projection of the first connection portion 210 on the base substrate 100 is completely within the orthographic projection of the sub-interchange structure 410 on the base substrate 100, and the orthographic projection of the second connection portion 220 on the base substrate 100 is completely within the orthographic projection of the sub-interchange structure 410 on the base substrate 100.

[0075] For example, as shown in Figures 1 to 3, the first connecting portion 210 and the second connecting portion 220 on the same gate line 200 are spaced apart. For example, two sub-adapter structures 410 electrically connected to the first connecting portion 210 and the second connecting portion 220 of the same gate line 200 are spaced apart. For example, the distance between the first connecting portion 210 and the second connecting portion 220 on the same gate line 200 is not less than the distance between the corresponding two sub-adapter structures 410. For example, the distance between the first connecting portion 210 and the second connecting portion 220 on the same gate line 200 is greater than the distance between the corresponding two sub-adapter structures 410.

[0076] The aforementioned "distance between the first connecting portion 210 and the second connecting portion 220" may refer to, but is not limited to, the distance between their adjacent edges. It may also refer to the distance between their centers in the X direction. The aforementioned "distance between the two sub-adapter structures 410" may refer to, but is not limited to, the distance between their adjacent edges. It may also refer to the distance between their centers in the X direction.

[0077] In some examples, as shown in Figures 1 to 3, the switching structure 400 also includes a connecting line 420, and the two sub-switching structures 410 electrically connected to the first connecting portion 210 and the second connecting portion 220 of the same gate line 200 are electrically connected via the connecting line 420. For example, the two sub-switching structures 410 and the connecting line 420 can be a structure arranged in an integrated manner. For example, the orthographic projection of the connecting line 420 on the base substrate 100 does not overlap with the orthographic projection of the gate line 200 on the base substrate 100. For example, the orthographic projection of the connecting line 420 on the straight line extending along the X direction overlaps with the orthographic projection of the gate line 200 on the straight line.

[0078] In some examples, as shown in Figures 1 to 3, each gate line 200 includes a gate line main body 230 extending in a direction intersecting with the second direction. For example, the gate line main body 230 extends along the first direction. For example, the maximum dimension of the gate line main body 230 in the second direction is not greater than the maximum dimension of any one of the first connecting portion 210 and the second connecting portion 220 in the second direction. For example, the maximum dimension of the gate line main body 230 in the second direction is less than the maximum dimension of any one of the first connecting portion 210 and the second connecting portion 220 in the second direction. For example, the gate line main body 230, the first connecting portion 210 and the second connecting portion 220 are an integrated structure. For example, a part of the gate line main body 230 is provided between the first connecting portion 210 and the second connecting portion 220.

[0079] In some examples, as shown in Figures 1 to 3, in at least one gate line 200, the first connection portion 210 and the second connection portion 220 both protrude from the same side of the gate line main portion 230 in the second direction. For example, the dimension of the portion of at least one of the first connection portion 210 and the second connection portion 220 that protrudes from the gate line main portion 230 in the second direction is not less than the maximum dimension of the gate line main portion 230 in the second direction.

[0080] For example, each of the plurality of gate lines 200 includes a first connection portion 210, and the plurality of first connection portions 210 included in the plurality of gate lines 200 are arranged along the second direction. For example, the plurality of first connection portions 210 are arranged at unequal intervals, where the interval between two adjacent first connection portions 210 with a larger interval is greater than the size of the first connection portion 210 in the second direction, and the interval between two adjacent first connection portions 210 with a smaller interval is less than the size of the first connection portion 210 in the second direction.

[0081] 1 to 3 , the two sub-transfer structures 410, the gate line main body 230, and the connecting line 420 form a hollow area 401. For example, the hollow area 401 may be in the shape of a polygon, such as a quadrilateral.

[0082] The array substrate provided by the embodiment of the present disclosure can be applied to a transparent display device. By providing a hollow area between the transfer structure and the gate line, the light transmittance of the array substrate can be improved.

[0083] For example, as shown in Figures 1 to 3, the area of ​​the hollow region 401 is larger than the area of ​​the orthographic projection of at least one of the first connecting portion 210 and the second connecting portion 220 on the base substrate 100. For example, the ratio of the area of ​​the hollow region 401 to the area of ​​the orthographic projection of at least one of the first connecting portion 210 and the second connecting portion 220 on the base substrate 100 can be 1.01 to 5, or 1.2 to 1.8, or 1.1 to 1.6, or 1.3 to 1.5, or 1.4 to 4.5, or 2 to 4, or 2.5 to 4.5, or 3 to 3.5, etc.

[0084] In some examples, as shown in Figures 1 and 2, the distance in the second direction between the gate line main portion 230 and the connecting line 420 corresponding to the gate line main portion 230 is less than the size of the first connecting portion 210 in the second direction. The connecting line corresponding to the gate line main portion is a connecting line included in the transition structure that is electrically connected to the first connecting portion included in the gate line where the gate line main portion is located.

[0085] For example, as shown in FIG. 1 and FIG. 2 , the gate line main body 230 and the connection line 420 corresponding to the gate line main body 230 are arranged in parallel.

[0086] In some examples, as shown in Figures 1 to 3, the gate drive structure 300 further includes a first power line 310. The first power line 310 is a structure in the gate drive structure 300 that is disposed in the same layer as the plurality of gate lines 200 and is closest to the plurality of gate lines 200. For example, the first power line 310 can be a power line VGL in the gate drive structure 300 for transmitting a low potential. For example, the low potential can be a constant voltage low potential. For example, the first power line 310 extends along the second direction.

[0087] 1 to 3 , the extension direction of the first power line 310 intersects with the extension direction of at least a portion of the connection line 420. For example, the extension direction of at least a portion of the connection line 420 is parallel to the first direction.

[0088] 2 , the shortest distance between the second connection portion 220 and the adjacent edges of the first power line 310 is smaller than the shortest distance between the adjacent edges of the second connection portion 220 and the first connection portion 210. In one example of the embodiment of the present disclosure, the probability of static electricity accumulation on the first connection portion can be reduced by maximizing the distance between the first connection portion and the second connection portion.

[0089] For example, the distance between the first connection portion 210 and other structures located on the side away from the second connection portion 220 and arranged on the same layer is smaller than the distance between the first connection portion 210 and the second connection portion 220 .

[0090] In some examples, as shown in Figures 1 to 3, the gate drive structure 300 includes an output terminal 320 electrically connected to the plurality of gate lines 200, the output terminal 320 is located on a side of the first power line 310 away from the plurality of gate lines 200, and the connecting line 420 is electrically connected to the output terminal 320 across the first power line 310. For example, the output terminal 320 can refer to the output terminal of a transistor in the gate drive unit. For example, the gate drive structure 300 can include two first power lines 310, and the connecting line 420 can be connected to the output terminal of the transistor across the two first power lines 310.

[0091] For example, as shown in Figure 1, the connecting line 420 is located on the side of the first power line 310 away from the base substrate 100, and the first power line 310 is provided with a plurality of openings 311. The above-mentioned openings 311 are provided at the position where the connecting line 420 overlaps with the first power line 310, which is beneficial to reduce the probability of crosstalk between the first power line and the connecting line.

[0092] For example, as shown in FIG1 , the film layer where the adapter structure 400 is located further includes a connection block 402. The connection block 402 overlaps with the first power line 300 and is electrically connected to the first power line 300 via a via in the insulating layer between the connection block 402 and the first power line 300, thereby facilitating reduced resistance of the first power line 300. For example, there are multiple connection blocks 402, which are arranged along the second direction, and a connection line 420 and an opening 311 are provided between two adjacent connection blocks 402.

[0093] For example, as shown in FIG1 , the area of ​​each connection block 402 is larger than the area of ​​the first connection portion 210. For example, the area of ​​each connection block 402 is larger than the area of ​​the hollow region 401. For example, the orthographic projection of the connection block 402 on a straight line extending along the Y direction overlaps with the orthographic projection of the first connection portion 210 on a straight line extending along the Y direction.

[0094] 1 to 3 , the second connection portion 220 is located at an end of the gate line 200 close to the gate driving structure 300 . For example, the second connection portion 220 is the end of the gate line 200 closest to the first power line 310 .

[0095] Figure 4 is a schematic diagram of a partial planar structure of an array substrate. As shown in Figure 4, the array substrate includes gate lines 20 and a gate drive structure 30 configured to be electrically connected to the gate lines 20. A connection portion 21 is provided at the end of the gate line 20 near the gate drive structure 30. The connection portion 21 is electrically connected to the gate drive structure 30 via a transfer structure located on another layer.

[0096] During the study, the inventors of the present application found that in the display field, static electricity has always been a major problem plaguing the industry. Organic light-emitting diode display products have more metal layers and are more sensitive to static electricity. In large-size display devices (such as 55-inch or 95-inch display devices), the length of the gate line is relatively long, such as up to 2 meters or more, and the length of the power line (VGL) in the gate drive structure that is arranged on the same layer as the gate line and closest to the gate line is also relatively long, such as up to 1 meter or more. Static electricity is easily generated at the end of the power line close to the gate drive unit, causing abnormal overlap between the gate drive unit and the gate line, and resulting in defective array substrates.

[0097] For example, as shown in Figure 4, the connecting portion 21 is located at the end of the power line of the gate line 20 close to the gate drive structure. Static electricity is easily generated between the connecting portion 21 of the gate line 20 and the power line. For example, static electricity is easily generated in the process of patterning the layer where the gate line 20 is located to produce structures such as the gate line and the power line. The static electricity is easily concentrated at the position of the connecting portion 21, causing the patterned vias of the interlayer insulating layer subsequently formed on the connecting portion 21 to be affected by static electricity and become black and fail, thereby affecting the electrical connection between the connecting portion 21 and the transfer structure subsequently formed on the interlayer insulating layer, resulting in affecting the electrical connection relationship between the gate line and the gate drive unit.

[0098] Compared with the array substrate shown in Figure 4, the array substrate provided by the embodiment of the present disclosure has an additional first connecting portion 210. Even if static electricity is generated at the position of the second connecting portion 220, causing part or all of the second connecting portion 220 to be unable to be electrically connected to the adapter structure, the first connecting portion 210 can have a good electrical connection relationship with the adapter structure, thereby improving the stability of the electrical connection relationship between the gate line and the gate drive structure.

[0099] FIG5 is a schematic diagram of a portion of the structure of a gate line close to a gate drive structure according to an example of an embodiment of the present disclosure. For example, as shown in FIG5 , each gate line 200 is provided with a first connecting portion 210 and a second connecting portion 220, and the first connecting portion 210 and the second connecting portion 220 have the same shape and area. Of course, the embodiment of the present disclosure is not limited thereto, and each of the plurality of gate lines may also be provided with a first connecting portion and a second connecting portion, the first connecting portion and the second connecting portion in some gate lines having the same shape and area, and the first connecting portion and the second connecting portion in some gate lines having different shapes.

[0100] Figure 6 is a schematic diagram of a partial structure of a gate line close to a gate driving structure provided according to an example of an embodiment of the present disclosure. The difference between the array substrate shown in Figure 6 and the array substrate shown in Figure 5 is that the shape of the second connecting portion 220 is different. For example, as shown in Figure 6, the second connecting portion 220 of at least one gate line 200 includes a tip portion 221. For example, each second connecting portion 220 includes a tip portion 221. Of course, the embodiment of the present disclosure is not limited to this. When the array substrate includes a plurality of second connecting portions, some of the second connecting portions may include a tip portion, and some of the second connecting portions may not include a tip portion. The array substrate shown in Figure 1 schematically shows that the second connecting portion includes a tip portion, but the array substrate shown in Figure 1 is not limited to the second connecting portion including a tip portion, and the second connecting portion may also not include a tip portion.

[0101] The embodiment of the present disclosure provides a pointed end portion at the second connection portion, which helps to concentrate the static electricity generated by the gate line at the second connection portion, reduce the probability of static electricity generation at the first connection portion, and improve the electrical connection effect between the first connection portion and the transition structure.

[0102] In some examples, as shown in FIG6 , the second connecting portion 220 further includes a main body portion 222 connected to the tip portion 221, and the main body portion 222 is closer to the gate line main body portion 230 than the tip portion 221. For example, the tip portion 221 and the main body portion 222 are integrally arranged. For example, the shape of the tip portion 221 can be a polygon, such as a quadrilateral, but is not limited thereto, and can also be a triangle, a pentagon, or the like.

[0103] For example, the second connection portion 221 may include at least one tip portion 221. For example, the second connection portion 221 may include a plurality of tip portions 221, and the plurality of tip portions 221 may include a tip portion located between the main body portion 222 and the first power line, a tip portion 221 located on a side of the main body portion 222 away from the gate line main body portion 230, a tip portion 221 located between the main body portion 222 and the first connection portion 210, and the like.

[0104] In some examples, as shown in FIG6 , the ratio of the area of ​​the orthographic projection of the main portion 222 on the base substrate 100 to the area of ​​the orthographic projection of the first connection portion 210 on the base substrate 100 is 0.9 to 1.1. For example, the area of ​​the orthographic projection of the main portion 222 on the base substrate 100 can be equal to the area of ​​the orthographic projection of the first connection portion 210 on the base substrate 100. For example, the main portion 222 can have the same shape and the same area as the first connection portion 210.

[0105] 6 , at least a portion of the orthographic projection of the tip portion 221 on a straight line extending in the Y direction does not overlap with the orthographic projection of the first connecting portion 210 on the straight line. For example, the orthographic projection of the tip portion 221 on the straight line does not overlap with the orthographic projection of the first connecting portion 210 on the straight line.

[0106] 6 , at least a portion of the orthographic projection of the tip portion 221 on the straight line extending in the X direction overlaps with the orthographic projection of the main body portion 222 on the straight line. For example, the orthographic projection of the tip portion 221 on the straight line extending in the X direction completely falls within the orthographic projection of the main body portion 222 on the straight line.

[0107] In some examples, as shown in FIG. 6 , in the body portion 222 and the tip portion 221 connected to each other, the orthographic projection area of ​​the tip portion 221 on the base substrate 100 is smaller than the orthographic projection area of ​​the body portion 222 on the base substrate 100 .

[0108] FIG7 is a schematic diagram of a portion of the structure of a gate line close to a gate driving structure according to an example of an embodiment of the present disclosure.

[0109] In some examples, as shown in FIG7 , at least one gate line 200 is provided with at least one protrusion 240, and the at least one protrusion 240 is located between the first connecting portion 210 and the second connecting portion 220. Providing at least one protrusion between the first connecting portion and the second connecting portion helps prevent static electricity from concentrating on the first connecting portion and affecting the electrical connection between the gate line and the transfer structure.

[0110] In some examples, as shown in FIG7 , the at least one protrusion 240 includes a plurality of protrusions 240. Among the plurality of protrusions 240, the orthographic projection area of ​​a protrusion 240 closest to the second connection portion 220 on the substrate is larger than the orthographic projection area of ​​a protrusion 240 farthest from the second connection portion 220 on the substrate. Since the static electricity concentrates less on protrusions farther from the second connection portion, the area of ​​the protrusion farthest from the second connection portion can be designed to be smaller.

[0111] 7 , the areas of the plurality of protrusions 240 gradually decrease from closer to the second connection portion 220 to farther away from the second connection portion 220. Providing a plurality of protrusions can further prevent static electricity from concentrating on the first connection portion.

[0112] For example, as shown in FIG. 7 , the shape of the protrusion 240 may be a polygon, such as a triangle, a quadrilateral, a pentagon, or the like.

[0113] For example, Figure 8 is a schematic diagram of a 3T1C drive circuit for the array substrate. The drive circuit for the array substrate provided in the embodiments of the present disclosure is not limited to a 3T1C drive circuit. This embodiment uses a 3T1C drive circuit as an example to illustrate the structure of the array substrate. As needed, the drive circuit may further include a compensation circuit, a reset circuit, and the like, which are not limited in the embodiments of the present disclosure.

[0114] In some examples, as shown in Figures 1 and 8, the array substrate further includes a plurality of sub-pixels 600, which are located in the first area 101 on the base substrate 100 and on the side of the first connecting portion 210 away from the gate driving structure 300. For example, the area where at least some of the plurality of sub-pixels 600 are located is a display area for displaying an image. As shown in Figures 1 and 8, the plurality of gate lines 200 include a plurality of first gate lines 250 and a plurality of second gate lines 260, and the plurality of first gate lines 250 and the plurality of second gate lines 260 are alternately arranged along the second direction. At least some of the sub-pixels 600 include a light-emitting element 610 and a driving circuit 620 that drives the light-emitting element 610 to emit light. The driving circuit 620 includes at least two transistors, and the gates of two of the at least two transistors are electrically connected to the first gate line 250 and the second gate line 260, respectively.

[0115] For example, as shown in FIG. 8 , the driving circuit 620 includes a first transistor T1 and a second transistor T2 . The gate of the first transistor T1 is electrically connected to the second gate line 260 , and the gate of the second transistor T2 is electrically connected to the first gate line 250 .

[0116] Figure 9A is a plan schematic diagram of the active layer in the array substrate provided in at least one embodiment of the present disclosure; Figure 9B is a plan schematic diagram of the active layer and the first conductive layer where the gate line is located in the array substrate provided in at least one embodiment of the present disclosure; Figure 9C is a plan schematic diagram of the second conductive layer where the transition structure is located in the array substrate provided in at least one embodiment of the present disclosure; Figure 9D is a plan schematic diagram of the active layer, the first conductive layer and the second conductive layer stacked in the array substrate provided in at least one embodiment of the present disclosure; Figure 9E is a plan schematic diagram of the first electrode of the light-emitting element in the array substrate provided in at least one embodiment of the present disclosure; Figure 9F is a plan schematic diagram of the active layer, the first conductive layer, the second conductive layer and the first electrode of the light-emitting element stacked in the array substrate provided in at least one embodiment of the present disclosure.

[0117] For example, as shown in Fig. 1 , the thickness of the base substrate 100 may be 50 to 1000 micrometers. For example, the base substrate 100 may be made of glass, such as quartz glass.

[0118] In some examples, as shown in FIG1 and FIG8 to FIG9F , the array substrate further includes a plurality of data lines 710 and a plurality of second power lines 720 located in the first region 101 of the base substrate 100. The plurality of data lines 710 are arranged along the first direction, and the plurality of second power lines 720 are arranged along the first direction. The plurality of second power lines 720 and the plurality of data lines 710 are disposed in the same layer. The driving circuit 610 of each sub-pixel 600 is electrically connected to one data line 710.

[0119] For example, as shown in Figures 1 and 8 to 9F, the driving circuit 620 further includes a driving transistor T3, the gate of which is connected to the second electrode of the first transistor T1, the first electrode of which is electrically connected to the second power line 720, and the second electrode of which is electrically connected to the first electrode of the light-emitting element 610 and the second electrode of the second transistor T2. The first electrode of the first transistor T1 is electrically connected to the data line 710 to receive a data signal. The first transistor T1 may also be referred to as a data write transistor.

[0120] For example, as shown in Figures 8 to 9F, the driving circuit 620 also includes a storage capacitor C, a first capacitor electrode of the storage capacitor C is electrically connected to the gate of the driving transistor T3 and the second electrode of the first transistor T1, and a second capacitor electrode of the storage capacitor C is electrically connected to the second electrode of the driving transistor T3, the first electrode 611 (for example, the anode) of the light-emitting element 610, and the second electrode of the second transistor T2.

[0121] For example, when a scan signal is applied through the second gate line 260 to turn on the first transistor T1, the data signal Vdata input to the driving circuit by the data line 710 can charge the storage capacitor C through the first transistor T1, thereby storing the data signal Vdata in the storage capacitor C, and the stored data signal Vdata can control the conduction degree of the driving transistor T3. The first electrode of the driving transistor T3 is configured to receive a power supply voltage (such as a high power supply voltage VDD), and the driving transistor T3 is configured to emit a current I when it is in the turned-on state. OLED is supplied to the light emitting element 610. A second electrode (eg, cathode) of the light emitting element 610 is configured to receive a second voltage VSS (low voltage, eg, ground voltage).

[0122] For example, as shown in Figures 1 and 8 to 9F, the array substrate further includes a plurality of sensing lines 730 located in the first region 101 of the base substrate 100. The plurality of sensing lines 730 are arranged along a first direction. For example, the first electrode of the second transistor T2 is electrically connected to the sensing line 730.

[0123] For example, large-size display products can compensate the drive circuit by combining electrical compensation with optical compensation. This approach combines the advantages of electrical and optical compensation to improve the uniformity of the display product. For example, electrical compensation can use the voltage or current of the drive circuit obtained by the sensing line to determine the compensation data to compensate for the characteristics of the driving thin-film transistor (such as threshold voltage and mobility). Optical compensation can compensate for the uniformity of the display panel as a whole.

[0124] For example, the driving circuit shown in FIG8 is a driving circuit that can detect the threshold voltage of a driving transistor. The second transistor T2 in the driving circuit is a sensing transistor, and the first electrode of the sensing transistor T2 is connected to a detection circuit (not shown) via a sensing line 730 to implement a compensation function. As shown in FIG8 , after the driving transistor T3 is turned on, the detection circuit can be charged via the second thin-film transistor T2, causing the potential of the second electrode of the driving transistor T3 to change. When the voltage Vs at the second electrode of the driving transistor T3 is equal to the difference between the gate voltage Vg of the driving transistor T3 and the threshold voltage Vth of the driving transistor, the driving transistor T3 is turned off. In this case, after the driving transistor T3 is turned off, the sensing voltage (i.e., the voltage Vb at the source electrode after the driving transistor T3 is turned off) can be obtained from the second electrode of the driving transistor T3 via the turned-on second transistor T2. After obtaining the voltage Vb at the source electrode after the driving transistor T3 is turned off, the threshold voltage Vth of the driving transistor T3 can be obtained as Vdata-Vb. In this way, compensation data can be established for each driving circuit based on the threshold voltage of the driving transistor in each driving circuit, thereby implementing a threshold voltage compensation function for each sub-pixel on the array substrate.

[0125] For example, the second electrode of the second transistor T2 can also input the current of the first electrode of the sensed light-emitting element 610 into the detection circuit via the sensing line to obtain the current used by the light-emitting element 610 to emit light, and then establish compensation data for each light-emitting element based on the current, thereby realizing optical compensation of each sub-pixel light-emitting element to achieve overall compensation for the uniformity of the display panel.

[0126] The transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are all described by taking thin film transistors as an example. The source and drain of the transistors used here may be symmetrical in structure, so their source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole as the second pole. In addition, transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). It should be noted that in the following description, the transistor in FIG. 8 is taken as an N-type transistor as an example, but this is not intended to limit the present disclosure.

[0127] In some examples, as shown in FIG. 9A to FIG. 9F , the plurality of data lines 400 and at least a portion of the transfer structure 400 are disposed on the same layer.

[0128] For example, as shown in Figures 1, 3, and 9A to 9F, the active layer 621 is located between the first conductive layer 622 and the base substrate 100, such as the active layer 621 is located between the buffer layer 101 and the gate insulating layer 102. For example, a light shielding layer is further provided between the active layer 621 and the base substrate, and the light shielding layer is located between the buffer layer 101 and the base substrate 100. For example, the orthographic projection of the active layer 621 on the base substrate overlaps with the orthographic projection of the light shielding layer on the base substrate. For example, a conductive layer may be further provided between the light shielding layer and the active layer 621 to serve as one plate of a storage capacitor. For example, a portion of the structure of the active layer 621 may serve as the other plate of the storage capacitor.

[0129] For example, the material of the active layer 621 may include oxide, such as amorphous oxide such as indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium tin zinc oxide (ITZO), or the like.

[0130] In some examples, as shown in Figures 1, 3, and 9A to 9F, the driving circuit 620 of at least some of the sub-pixels 600 includes an active layer 621, and the plurality of sub-pixels 600 include a first color sub-pixel 601 and a second color sub-pixel 602. The area of ​​the active layer 621 of the first color sub-pixel 601 is larger than the area of ​​the active layer 621 of the second color sub-pixel 602. For example, the first color sub-pixel 601 may be a red sub-pixel, and the second color sub-pixel 602 may be a green sub-pixel. Of course, the embodiments of the present disclosure are not limited thereto. The first color sub-pixel may be a blue sub-pixel, and the second color sub-pixel may be a red sub-pixel, or the first color sub-pixel may be a blue sub-pixel, and the second color sub-pixel may be a green sub-pixel. The width-to-length ratio (W / L) of the driving transistors of different color sub-pixels is different, and therefore different capacitances are required and the active layer areas are different.

[0131] In some examples, as shown in Figures 1, 3, and 9A to 9F, the plurality of sub-pixels 600 further includes a plurality of third-color sub-pixels 603 and a plurality of fourth-color sub-pixels 604. For example, the first-color sub-pixel 601, the second-color sub-pixel 602, the third-color sub-pixel 603, and the fourth-color sub-pixel 604 are red, green, blue, and white sub-pixels, respectively.

[0132] In some examples, as shown in FIG1 and FIG9A to FIG9F , a plurality of sub-pixels 600 are arrayed along a first direction and a second direction to form a plurality of pixel rows 6001 and a plurality of pixel columns 6002. One of the first direction and the second direction is a row direction, and the other of the first direction and the second direction is a column direction. For example, the first direction is a row direction, and the second direction is a column direction. However, this is not limiting, and the row direction and the column direction can be interchangeable.

[0133] In some examples, as shown in Figures 1 and 9A to 9F, at least one pixel row 6001 includes a first color sub-pixel 601, a second color sub-pixel 602, a third color sub-pixel 603, and a fourth color sub-pixel 604 that are sequentially arranged in a cyclic manner along the row direction. For example, two columns of dummy sub-pixels are provided between the first color sub-pixel 601 closest to the first connection portion 210 and the first connection portion 210, and these two columns of dummy sub-pixels are not used for display.

[0134] For example, as shown in FIG1 and FIG9A to FIG9F , the multiple sub-pixels 600 located in the same pixel column 6002 may be sub-pixels of the same color. However, the multiple sub-pixels located in the same pixel column may also be sub-pixels of the first color, the second color, the third color, and the fourth color, arranged cyclically in the column direction.

[0135] For example, as shown in Figures 3 and 9A to 9F, the second conductive layer 623 is located on a side of the first conductive layer 622 away from the substrate. For example, an insulating layer 500 is disposed between the first conductive layer 622 and the second conductive layer 623. For example, the second conductive layer 623 includes a data line 710, a second power line 720, and a sensing line 730.

[0136] For example, as shown in Figures 9A to 9F , the first conductive layer 622 is further provided with a plurality of first connecting bars 6221. For example, a portion of the first connecting bars 6221 overlaps with the data line 710 and is electrically connected to the data line 710 through a via hole in the insulating layer 500 to reduce the resistance of the data line 710; a portion of the first connecting bars 6221 overlaps with the second power line 720 and is electrically connected to the second power line 720 through a via hole in the insulating layer 500 to reduce the resistance of the second power line 720; and a portion of the first connecting bars 6221 overlaps with the sensing line 730 and is electrically connected to the sensing line 730 through a via hole in the insulating layer 500 to reduce the resistance of the sensing line 730.

[0137] In some examples, as shown in Figures 2 and 9B, at least one gate line 200 is provided with at least one opening 270. For example, each gate line 200 is provided with a plurality of openings 270. For example, as shown in Figures 9B to 9F, at least some of the openings 270 provided on the gate line 200 overlap with at least one of the data line 710, the second power line 720, and the sensing line 730.

[0138] By configuring the portion where the gate line intersects the signal line disposed in the second conductive layer as an open-hole structure, also known as a ring structure or a dual-channel structure, the device yield can be effectively improved. For example, the intersection of the signal lines is prone to electrostatic breakdown due to parasitic capacitance, resulting in a short circuit. During the inspection process, if a short circuit is detected in one channel of the ring structure, that channel can be removed (for example, by laser cutting), and the circuit structure can still operate normally through the other channel.

[0139] For example, as shown in Figures 9A to 9F, the second conductive layer 623 includes a plurality of second connecting bars 6231 arranged in an array. The second connecting bars 6231 overlap with the gate lines 200, and the second connecting bars 6231 are electrically connected to the gate lines 200 through vias in the insulating layer therebetween to reduce the resistance of the gate lines 200.

[0140] 9E and 9F , a third conductive layer 624 containing the first electrode 611 of the light-emitting element 610 is provided on a side of the second conductive layer 623 away from the first conductive layer 621. For example, the first electrode 611 of the light-emitting element 610 is electrically connected to the second electrode of the driving transistor through the second conductive layer 623.

[0141] In some examples, as shown in Figures 8 to 9F, in the first gate line 250 and the second gate line 260 electrically connected to the same driving circuit 620, the first connection portion 210 and the second connection portion 220 of the first gate line 250 are both located on the side of the first gate line 250 close to the second gate line 260, and the first connection portion 210 and the second connection portion 220 of the second gate line 260 are both located on the side of the second gate line 260 close to the first gate line 250.

[0142] 8 to 9F , the first gate line 250 and the second gate line 260 electrically connected to the same driving circuit 620 are located on both sides of the pixel row where the driving circuit 620 is located. For example, the first gate line 250 and the second gate line 260 are located between two adjacent pixel rows 6001.

[0143] For example, as shown in FIG9F , the first connection portion 210 and the second connection portion 220 of the gate line 200 both protrude toward a side where a pixel row 6001 adjacent to the gate line 200 is located.

[0144] 10 and 11 are schematic plan views of a partial layer structure provided according to another example of an embodiment of the present disclosure, and FIG. 12 is a schematic view of a partial cross-sectional structure taken along line CC′ shown in FIG. 11 .

[0145] The difference between the array substrate shown in Figures 10 and 11 and the array substrate in the example shown in Figures 1 to 9F lies primarily in the arrangement of the gate lines 200. For example, each gate line 200 shown in Figures 1 to 9F is a continuous gate line 200, while the gate line 200 shown in Figures 10 to 11 includes multiple sub-gate lines 201 spaced apart along its extension direction. Of course, the arrangement of multiple sub-gate lines 201 spaced apart as shown in Figures 10 to 11 can be applied to any of the examples shown in Figures 1 to 9F.

[0146] For example, a gate insulating layer, or GI layer for short, can be deposited using chemical vapor deposition (CVD). A gate metal layer is then deposited on the gate insulating layer using a sputtering device. The gate metal layer has a thickness of 200-1000 nanometers and can be made of materials such as aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), or titanium (Ti). The gate, gate lines, and other patterns are defined through processes such as photolithography and wet etching. While the photoresist is retained, the photoresist on the gate metal layer is used as a mask to dry-etch the GI pattern. During the GI dry etching process, the accumulation of charge in the long gate lines can easily lead to electrostatic discharge, which can break down the thin-film transistor and cause defects.

[0147] In some examples, as shown in Figures 10 and 11, each gate line 200 of at least some of the gate lines 200 of the plurality of gate lines 200 includes a plurality of sub-gate lines 201 arranged at intervals along the extension direction thereof, and two adjacent sub-gate lines 201 are electrically connected via a connecting unit 800, and the connecting unit 800 and the gate line 200 are located in different layers. In at least one example of the embodiments of the present disclosure, a gate line with a longer length is divided into a plurality of sub-gate lines with shorter lengths, and two adjacent sub-gate lines are electrically connected via connecting units located in different layers, which can reduce the probability of a large amount of static electricity being concentrated at the end of the gate line. For example, the gate line made in the display area is divided into a plurality of sub-gate lines during the process, and the specific number of segments is designed as needed. Subsequently, the entire gate line is connected by the connecting unit. In this way, during the dry etching process of the gate insulating layer, electrostatic discharge caused by charge accumulation on the gate line that is too long may be avoided, thereby ensuring the yield of the display product and improving the quality of the display product.

[0148] For example, as shown in FIG10 , a gate line 200 includes a plurality of sub-gate lines 201 arranged along the X direction.

[0149] In some examples, as shown in Figures 10 to 12, the connection unit 800 is located between two adjacent sub-gate lines 201, and the connection unit 800 includes a first connection unit 801 and a second connection unit 802 arranged therebetween and stacked. The first connection unit 801 is located between the gate line 200 and the base substrate 100, and the second connection unit 802 is located on the side of the gate line 200 away from the base substrate 100. The first connection unit 801 is electrically connected to the second connection unit 802, and the gate line 200 is electrically connected to the second connection unit 802, thereby realizing electrical connection between the two adjacent sub-gates.

[0150] 10 to 12 , the array substrate further includes a light shielding layer 104 located between the active layer and the base substrate 100 . For example, the light shielding layer 104 includes a first connection unit 801 .

[0151] For example, a sputtering device may be used to deposit a metal layer on the base substrate 100 , and the metal layer may be patterned through processes such as photolithography and wet etching to form patterns of the transparent capacitor layer 105 and the light shielding layer 105 .

[0152] 3 and 12 , the thickness of the buffer layer 101 may be 150 to 500 nanometers. For example, the material of the buffer layer 101 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0153] In some examples, as shown in Figures 10 to 12 , the plurality of data lines 710 are disposed on the same layer as the second connection unit 802. For example, the transfer structure is disposed on the same layer as the second connection unit 802.

[0154] 10 to 12 , the second connection unit 802 is electrically connected to the sub-gate line 201 through a via 503 in the insulating layer 500. For example, the first connection unit 801 is electrically connected to the first connection unit 801 through a via 504 in the insulating layer between the first connection unit 801 and the second connection unit 802.

[0155] For example, the insulating layer 500 may be a single layer or a multi-layer film layer including silicon nitride or silicon oxide.

[0156] For example, as shown in Figures 10 to 12, two second connection units 802 electrically connected to the two adjacent sub-grid lines 201 are provided between two adjacent sub-grid lines 201, and a first connection unit 801 is provided between the two adjacent sub-grid lines 201. The two second connection units 802 are electrically connected to the first connection unit 801 to achieve electrical connection between the two adjacent sub-grid lines 201. Of course, the embodiments of the present disclosure are not limited thereto, and the two adjacent sub-grid lines can also be electrically connected directly through the first connection portion located therebetween.

[0157] For example, the material of the film layer where the data line is located may include aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), etc., and the thickness of the film layer may be 200-1000 nanometers.

[0158] For example, a passivation layer and a planarization layer may be further provided on the side of the data line away from the base substrate, and the first electrode of the light emitting element is electrically connected to the driving circuit through via holes in the passivation layer and the planarization layer.

[0159] For example, the material of the first electrode of the light emitting element may include aluminum, molybdenum, copper, indium tin oxide, etc. For example, the thickness of the first electrode of the light emitting element may be 100 to 600 nanometers.

[0160] For example, a pixel-defining pattern is provided on a side of the first electrode of the light-emitting element away from the substrate. For example, the pixel-defining pattern includes an opening for defining the light-emitting area of ​​the light-emitting element and a defining portion surrounding the opening. For example, the defining portion may have a thickness of 1.8 to 2 microns.

[0161] The gate line in the array substrate shown in FIG. 10 to FIG. 12 may be provided with only one of the first connection portion and the second connection portion to achieve electrical connection with the gate driving structure.

[0162] Another embodiment of the present disclosure provides an array substrate, comprising: a base substrate, a plurality of gate lines located on the base substrate, a gate drive structure, a transfer structure, and an insulating layer. The base substrate comprises a first region and a second region, the second region being located on at least one side of the first region in a first direction; a plurality of gate lines being located in the first region, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; the gate drive structure being located in the second region, and the gate drive structure being configured to be electrically connected to the plurality of gate lines; the transfer structure being located on a side of the plurality of gate lines away from the base substrate, and the plurality of gate lines being electrically connected to the gate drive structure through the transfer structure; and the insulating layer being located between the plurality of gate lines and the transfer structure. A portion of at least one of the plurality of gate lines close to the gate drive structure comprises a connecting portion and an electrostatic release pad, the electrostatic release pad being located between the gate drive structure and the first connecting portion, the electrostatic release pad comprising a tip portion; and the insulating layer comprising at least one first via, the connecting portion being electrically connected to the transfer structure through the first via to be electrically connected to the gate drive structure. The embodiment of the present disclosure provides an electrostatic release pad on the gate line, which helps to concentrate the static electricity generated by the gate line on the electrostatic release pad, reduce the probability of static electricity generation in the first connection part, and ensure the electrical connection between the first connection part and the adapter structure.

[0163] As shown in Figures 1 to 3 and Figure 6, the array substrate includes: a base substrate 100, a plurality of gate lines 200 located on the base substrate 100, a gate driving structure 300, a transfer structure 400, and an insulating layer 500. The base substrate 100 includes a first region 101 and a second region 102, wherein the second region 102 is located on at least one side of the first region 101 in a first direction; the plurality of gate lines 200 are located in the first region 101, and the plurality of gate lines 200 are arranged along a second direction, wherein the first direction intersects the second direction; the gate driving structure 300 is located in the second region 102, and is configured to be electrically connected to the plurality of gate lines 200; the transfer structure 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100, and the plurality of gate lines 200 are electrically connected to the gate driving structure 300 via the transfer structure 300; and the insulating layer 500 is located between the plurality of gate lines 200 and the transfer structure 300. The portion of at least one gate line 200 of the multiple gate lines 200 close to the gate driving structure 300 includes a connecting portion 210 and an electrostatic release pad 220, the electrostatic release pad 220 is located between the gate driving structure 300 and the connecting portion 210, and the electrostatic release pad 220 includes a tip portion 221; the insulating layer 500 includes at least one first via 501, and the connecting portion 210 is electrically connected to the transfer structure 400 through the first via 501 to be electrically connected to the gate driving structure 300.

[0164] Compared with the array substrate shown in Figure 4, the gate lines of the array substrate provided by the embodiment of the present disclosure are provided with connecting parts and electrostatic release pads at the same time, which can concentrate the static electricity generated at the ends of the gate lines to the electrostatic release pads as much as possible, so that the connecting parts can have a good electrical connection relationship with the transfer structure, thereby improving the stability of the electrical connection relationship between the gate lines and the gate drive structure.

[0165] In some examples, as shown in FIG. 3 , the insulating layer 500 further includes at least one second via 502 , and a straight line extending perpendicular to the base substrate 100 passes through the electrostatic release pad 220 , the second via 502 , and the transfer structure 400 in sequence.

[0166] In some examples, as shown in FIG. 1 to FIG. 3 and FIG. 6 , the electrostatic discharge pad 220 is located at an end of the gate line 200 close to the gate driving structure 300 .

[0167] In some examples, as shown in Figures 1 to 3 and Figure 6, the electrostatic release pad 220 further includes a main body portion 222 connected to the tip portion 221, and the ratio of the area of ​​the main body portion 222 on the base substrate 100 to the area of ​​the orthographic projection of the connecting portion 210 on the base substrate 100 is 0.9 to 1.1.

[0168] The features of the tip portion and the main body of the electrostatic release pad in this embodiment may be the same as the features of the tip portion and the main body of the second connecting portion in the above embodiment, and are not described again here.

[0169] 7 , at least one gate line 200 is provided with at least one protrusion 240, and at least one protrusion 240 is located between the connection portion 210 and the electrostatic discharge pad 220. The protrusion in this embodiment may have the same features as the protrusion in the above embodiment, and will not be described again here.

[0170] In some examples, as shown in Figures 1 and 8, the array substrate further includes a plurality of sub-pixels 600, which are located in the first region 101 on the base substrate 100 and on a side of the connection portion 210 away from the gate driving structure 300. The plurality of gate lines 200 include a plurality of first gate lines 250 and a plurality of second gate lines 260, which are alternately arranged along the second direction. At least some of the sub-pixels 600 include a light-emitting element 610 and a driving circuit 620 that drives the light-emitting element 610 to emit light. The driving circuit 620 includes at least two transistors, and the gates of two of the at least two transistors are electrically connected to the first gate line 250 and the second gate line 260, respectively. The features of this embodiment, such as the sub-pixels and their connection relationship with the gate lines, are the same as the corresponding features in the above-mentioned embodiments and are not further described here.

[0171] In some examples, as shown in FIG1 , in a first gate line 250 and a second gate line 260 electrically connected to the same driving circuit, the connecting portion 210 and the electrostatic release pad 220 of the first gate line 250 are both located on a side of the first gate line 250 close to the second gate line 260, and the connecting portion 210 and the electrostatic release pad 220 of the second gate line 260 are located on a side of the second gate line 260 close to the first gate line 250. The positional relationship between the first and second gate lines and the connecting portions and the electrostatic release pad provided thereon in this embodiment is the same as the positional relationship between the first and second gate lines and the first and second connecting portions provided thereon in the above-described embodiment, and is not further described herein.

[0172] In some examples, as shown in FIG9F , a plurality of sub-pixels 600 are arranged in an array along a first direction and a second direction to form a plurality of pixel rows 6001 and a plurality of pixel columns 6002. A first gate line 250 and a second gate line 260 electrically connected to the same driving circuit are located on either side of the pixel row 6001 where the driving circuit is located. The positional relationship between the first gate line and the second gate line and the pixel row in this embodiment is the same as the corresponding positional relationship in the above embodiment and will not be further described here.

[0173] Another embodiment of the present disclosure provides an array substrate, the array substrate comprising: a base substrate, a plurality of gate lines located on the base substrate, and a gate drive structure. The base substrate comprises a first region and a second region, the second region being located on at least one side of the first region in a first direction; a plurality of gate lines being located in the first region, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; the gate drive structure being located in the second region, and the gate drive structure being configured to be electrically connected to the plurality of gate lines. Each gate line in at least some of the plurality of gate lines comprises a plurality of sub-gate lines arranged at intervals along its extension direction, two adjacent sub-gate lines being electrically connected via a connecting unit, and the connecting unit and the gate line being located in different layers. In the array substrate provided by the embodiment of the present disclosure, a gate line with a longer length is divided into a plurality of sub-gate lines with a shorter length, and two adjacent sub-gate lines are electrically connected via connecting units located in different layers, which can reduce the probability of a large amount of static electricity being concentrated at the ends of the gate lines, thereby ensuring the yield of the display product and improving the quality of the display product.

[0174] As shown in Figures 1 and 10 to 12, the array substrate includes a base substrate 100, a plurality of gate lines 200 located on the base substrate 100, and a gate drive structure 300. The base substrate 100 includes a first region 101 and a second region 102, wherein the second region 102 is located on at least one side of the first region 101 in a first direction; the plurality of gate lines 200 are located in the first region 101, and the plurality of gate lines 200 are arranged along a second direction, wherein the first direction intersects the second direction; the gate drive structure 300 is located in the second region 102, and the gate drive structure 300 is configured to be electrically connected to the plurality of gate lines 200. Each gate line 200 of at least a portion of the plurality of gate lines 200 includes a plurality of sub-gate lines 201 arranged at intervals along its extension direction, and two adjacent sub-gate lines 201 are electrically connected via a connecting unit 800, and the connecting unit 800 and the gate line 200 are located on different layers.

[0175] In the disclosed embodiment, a longer gate line is divided into multiple shorter sub-gate lines, and two adjacent sub-gate lines are electrically connected through connecting units located in different layers, which can reduce the probability of generating a large amount of static electricity concentrated at the end of the gate line. For example, the gate line produced in the display area is divided into multiple sub-gate lines during the process, and the specific number of segments is designed according to needs. The entire gate line is subsequently connected through the connecting unit. This can avoid electrostatic discharge and breakdown of the thin film transistor due to charge accumulation in the gate line being too long during the dry etching process of the gate insulating layer, thereby ensuring the yield of the display product and improving the quality of the display product.

[0176] In some examples, as shown in Figures 10 to 12, the connection unit 800 is located between two adjacent sub-gate lines 201, and the connection unit 800 includes a first connection unit 801 and a second connection unit 802 arranged therebetween and stacked. The first connection unit 801 is located between the gate line 200 and the base substrate 100, and the second connection unit 802 is located on the side of the gate line 200 away from the base substrate 100. The first connection unit 801 is electrically connected to the second connection unit 802, and the gate line 200 is electrically connected to the second connection unit 802.

[0177] The sub-grid lines and the connection units in this embodiment may have the same features as the sub-grid lines and the connection units in the examples shown in FIG. 10 to FIG. 12 , and are not described in detail here.

[0178] For example, the gate line provided in this embodiment, which includes multiple sub-gate lines, can be applied to the array substrate shown in Figure 4 to reduce the probability of static electricity concentration in the connecting portion 21, and can also be applied to the embodiments shown in Figure 5 or 6 to further reduce the probability of static electricity concentration in the first connecting portion, which is beneficial to improving the electrical connection effect between the gate line and the gate driving unit.

[0179] Another embodiment of the present disclosure provides a display device, comprising the array substrate described in any of the above embodiments.

[0180] The display device provided by the embodiment of the present disclosure adds a first connecting portion. Even if static electricity is generated at the location of the second connecting portion, causing part or all of the second connecting portion to be unable to be electrically connected to the adapter structure, the first connecting portion can still have a good electrical connection relationship with the adapter structure, thereby improving the stability of the electrical connection relationship between the gate line and the gate drive structure.

[0181] The gate lines of the display device provided by the embodiment of the present disclosure are provided with connecting portions and electrostatic release pads at the same time, which can concentrate the static electricity generated at the ends of the gate lines to the electrostatic release pads as much as possible, so that the connecting portions can have a good electrical connection relationship with the transfer structure, thereby improving the stability of the electrical connection relationship between the gate lines and the gate drive structure.

[0182] In the display device provided by the embodiment of the present disclosure, a longer gate line is divided into multiple shorter sub-gate lines, and two adjacent sub-gate lines are electrically connected through connection units located in different layers. This can reduce the probability of a large amount of static electricity being concentrated at the end of the gate line, thereby ensuring the yield of the display product and improving the quality of the display product.

[0183] For example, the display device provided in the embodiment of the present disclosure may be an organic light emitting diode display device.

[0184] For example, the display device may further include a cover plate located on the display side of the array substrate.

[0185] For example, the display device may be any product or component with a display function, such as a mobile phone, tablet computer, laptop computer, navigator, etc., with an under-screen camera, but this embodiment is not limited thereto.

[0186] For example, the display device may be a large-sized transparent display device.

[0187] There are a few points to note:

[0188] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0189] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0190] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising: A base substrate, comprising a first region and a second region, wherein the second region is located on at least one side of the first region in a first direction; a plurality of gate lines located in the first region of the base substrate, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; a gate driving structure, located in the second region of the base substrate, and configured to be electrically connected to the plurality of gate lines; A transfer structure is located on a side of the plurality of gate lines away from the base substrate, and the plurality of gate lines are electrically connected to the gate driving structure through the transfer structure; an insulating layer, located between the plurality of gate lines and the transfer structure, Wherein, a portion of at least one of the plurality of gate lines close to the gate driving structure includes a first connecting portion and a second connecting portion, and the second connecting portion is located between the gate driving structure and the first connecting portion. The insulating layer includes at least one first via and at least one second via, the first connecting portion is electrically connected to the transfer structure through the first via to be electrically connected to the gate drive structure, and a straight line extending in a direction perpendicular to the substrate passes through the second connecting portion, the second via and the transfer structure in sequence.

2. The array substrate according to claim 1, wherein: At least a portion of the second connecting portion is electrically connected to the transfer structure through the second via hole to be electrically connected to the gate driving structure; The transfer structure includes a plurality of sub-transfer structures, and two sub-transfer structures electrically connected to the first connection portion and the second connection portion of the same gate line are electrically connected to each other.

3. The array substrate according to claim 2, wherein: Each gate line includes a gate line main portion extending in a direction intersecting the second direction. In the at least one gate line, the first connection portion and the second connection portion both protrude from the same side of the gate line main portion in the second direction.

4. The array substrate according to claim 3, wherein: The transfer structure further includes a connecting line, and the two sub-transfer structures electrically connected to the first connecting portion and the second connecting portion of the same gate line are electrically connected via the connecting line. The two sub-transfer structures, the gate line main body and the connecting line form a hollow area.

5. The array substrate according to claim 3 or 4, wherein: The second connecting portion includes a tip portion.

6. The array substrate according to claim 5, wherein: The second connecting portion is located at an end of the gate line close to the gate driving structure.

7. The array substrate according to claim 5, wherein: The second connecting portion also includes a main body connected to the tip portion, the main body is closer to the gate line main body than the tip portion, and the ratio of the area of ​​the main body's orthographic projection on the base substrate to the area of ​​the first connecting portion's orthographic projection on the base substrate is 0.9 to 1.

1.

8. The array substrate according to claim 7, wherein: In the main body portion and the tip portion that are connected to each other, an area of ​​an orthographic projection of the tip portion on the base substrate is smaller than an area of ​​an orthographic projection of the main body portion on the base substrate.

9. The array substrate according to any one of claims 2 to 3, wherein: The gate driving structure further includes a first power line, which is a structure closest to the plurality of gate lines among the structures in the gate driving structure that are arranged in the same layer as the plurality of gate lines; The transfer structure also includes a connecting line electrically connected to the sub-transfer structure, the extension direction of the first power line intersects with the extension direction of at least part of the connecting line, and the gate drive structure includes an output end electrically connected to the multiple gate lines, the output end is located on a side of the first power line away from the multiple gate lines, and the connecting line crosses the first power line and is electrically connected to the output end.

10. The array substrate according to claim 4, wherein: A distance between the gate line main body and the connecting line corresponding to the gate line main body in the second direction is smaller than a size of the first connecting portion in the second direction.

11. The array substrate according to any one of claims 5 to 8, wherein: The at least one gate line is provided with at least one protrusion, and the at least one protrusion is located between the first connecting portion and the second connecting portion.

12. The array substrate according to claim 11, wherein: The at least one protrusion includes a plurality of protrusions, and an orthographic projection area of ​​a protrusion closest to the second connection portion on the base substrate is larger than an orthographic projection area of ​​a protrusion farthest from the second connection portion on the base substrate.

13. The array substrate according to any one of claims 1 to 12, wherein: The at least one first via hole includes a plurality of first via holes, the at least one second via hole includes a plurality of second via holes, and a ratio of the number of the plurality of first via holes to the number of the plurality of second via holes is 0.9 to 1.

1.

14. The array substrate according to any one of claims 1 to 13, further comprising: a plurality of sub-pixels located in the first region on the base substrate and located on a side of the first connecting portion away from the gate driving structure; The plurality of gate lines include a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines and the plurality of second gate lines are alternately arranged along the second direction, at least some sub-pixels include light-emitting elements and a driving circuit for driving the light-emitting elements to emit light, the driving circuit includes at least two transistors, and the gates of two of the at least two transistors are electrically connected to the first gate line and the second gate line, respectively.

15. The array substrate according to claim 14, wherein: In the first gate line and the second gate line electrically connected to the same driving circuit, the first connection portion and the second connection portion of the first gate line are both located on a side of the first gate line close to the second gate line, and the first connection portion and the second connection portion of the second gate line are both located on a side of the second gate line close to the first gate line.

16. The array substrate according to claim 14 or 15, further comprising: a plurality of data lines, located in the first area on the base substrate and arranged along the first direction; A plurality of second power lines are located in the first area on the base substrate and arranged along the first direction, and at least part of the plurality of second power lines are arranged in the same layer as the plurality of data lines. The plurality of data lines are arranged in the same layer as at least a portion of the switching structure, and the driving circuit of each sub-pixel is electrically connected to one data line.

17. The array substrate according to any one of claims 14 to 16, wherein: The driving circuit of at least some of the sub-pixels includes an active layer, the multiple sub-pixels include multiple first color sub-pixels and multiple second color sub-pixels, and the area of ​​the active layer of a first color sub-pixel is larger than the area of ​​the active layer of a second color sub-pixel.

18. The array substrate according to claim 17, wherein: The plurality of sub-pixels are arrayed along the first direction and the second direction to form a plurality of pixel rows and a plurality of pixel columns, one of the first direction and the second direction is a row direction, and the other of the first direction and the second direction is a column direction. The multiple sub-pixels also include multiple third color sub-pixels and multiple fourth color sub-pixels, and at least one pixel row includes the first color sub-pixels, the second color sub-pixels, the third color sub-pixels and the fourth color sub-pixels arranged in a circular pattern along the row direction.

19. The array substrate according to claim 18, wherein: The first gate line and the second gate line electrically connected to the same driving circuit are respectively located on both sides of the pixel row where the driving circuit is located.

20. The array substrate according to any one of claims 1 to 19, wherein: The at least one gate line is provided with at least one opening.

21. The array substrate according to any one of claims 1 to 15, wherein: Each gate line in at least part of the plurality of gate lines includes a plurality of sub-gate lines arranged at intervals along its extension direction, and two adjacent sub-gate lines are electrically connected via a connecting unit, and the connecting unit and the gate line are located in a different layer.

22. The array substrate according to claim 21, wherein: The connection unit is located between two adjacent sub-gate lines, and the connection unit includes a first connection unit and a second connection unit that are arranged between the two adjacent sub-gate lines and stacked. The first connection unit is located between the gate line and the base substrate, and the second connection unit is located on the side of the gate line away from the base substrate. The first connection unit is electrically connected to the second connection unit, and the gate line is electrically connected to the second connection unit.

23. The array substrate according to claim 22, further comprising: A plurality of data lines are arranged along the first direction, The plurality of data lines are arranged on the same layer as at least a portion of the switching structure, and at least a portion of the plurality of data lines is arranged on the same layer as the second connecting unit.

24. An array substrate, comprising: A base substrate, comprising a first region and a second region, wherein the second region is located on at least one side of the first region in a first direction; a plurality of gate lines located in the first region of the base substrate, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; a gate driving structure, located in the second region of the base substrate, and configured to be electrically connected to the plurality of gate lines; A transfer structure is located on a side of the plurality of gate lines away from the base substrate, and the plurality of gate lines are electrically connected to the gate driving structure through the transfer structure; an insulating layer, located between the plurality of gate lines and the transfer structure, Wherein, a portion of at least one of the plurality of gate lines close to the gate driving structure includes a connecting portion and an electrostatic release pad, the electrostatic release pad is located between the gate driving structure and the connecting portion, and the electrostatic release pad includes a tip portion; The insulating layer includes at least one first via hole, and the connecting portion is electrically connected to the transfer structure through the first via hole to be electrically connected to the gate driving structure.

25. The array substrate according to claim 24, wherein: The insulating layer further includes at least one second via hole, and a straight line extending in a direction perpendicular to the base substrate passes through the electrostatic release pad, the second via hole, and the transfer structure in sequence.

26. The array substrate according to claim 24 or 25, wherein: The electrostatic release pad is located at an end of the gate line close to the gate driving structure.

27. The array substrate according to any one of claims 24 to 26, wherein: The electrostatic discharge pad further includes a main body portion connected to the tip portion, and a ratio of an area of ​​the main body portion on the base substrate to an area of ​​an orthographic projection of the connecting portion on the base substrate is 0.9 to 1.

1.

28. The array substrate according to any one of claims 24 to 27, wherein: The at least one gate line is provided with at least one protrusion, and the at least one protrusion is located between the connecting portion and the electrostatic release pad.

29. The array substrate according to any one of claims 24 to 28, further comprising: a plurality of sub-pixels, located in the first area on the base substrate and located on a side of the connecting portion away from the gate driving structure; The plurality of gate lines include a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines and the plurality of second gate lines are alternately arranged along the second direction, at least some sub-pixels include light-emitting elements and a driving circuit for driving the light-emitting elements to emit light, the driving circuit includes at least two transistors, and the gates of two of the at least two transistors are electrically connected to the first gate line and the second gate line, respectively.

30. The array substrate according to claim 29, wherein: In the first gate line and the second gate line electrically connected to the same driving circuit, the connecting portion and the electrostatic release pad of the first gate line are both located on a side of the first gate line close to the second gate line, and the connecting portion and the electrostatic release pad of the second gate line are both located on a side of the second gate line close to the first gate line.

31. The array substrate according to claim 29 or 30, wherein: The plurality of sub-pixels are arranged in an array along the first direction and the second direction to form a plurality of pixel rows and a plurality of pixel columns. The first gate line and the second gate line electrically connected to the same driving circuit are respectively located on both sides of the pixel row where the driving circuit is located.

32. An array substrate, comprising: A base substrate, comprising a first region and a second region, wherein the second region is located on at least one side of the first region in a first direction; a plurality of gate lines located in the first region of the base substrate, the plurality of gate lines being arranged along a second direction, the first direction intersecting the second direction; a gate driving structure, located in the second region of the base substrate, and configured to be electrically connected to the plurality of gate lines; Each gate line of at least part of the plurality of gate lines includes a plurality of sub-gate lines spaced apart along its extension direction, and two adjacent sub-gate lines are electrically connected via a connecting unit, and the connecting unit and the gate line are located in different layers.

33. The array substrate according to claim 32, wherein: The connection unit is located between two adjacent sub-gate lines, and the connection unit includes a first connection unit and a second connection unit that are arranged between the two adjacent sub-gate lines and stacked. The first connection unit is located between the gate line and the base substrate, and the second connection unit is located on the side of the gate line away from the base substrate. The first connection unit is electrically connected to the second connection unit, and the gate line is electrically connected to the second connection unit.

34. A display device comprising the array substrate according to any one of claims 1 to 33.