Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a pixel driving circuit, the pixel driving circuit comprising a transistor. The display panel further comprises: a base substrate (90), a first active layer, and a shielding layer; the first active layer is located on one side of the base substrate (90), and at least part of the structure of the first active layer is used for forming a transistor channel region; the shielding layer is located between the base substrate (90) and the first active layer, the shielding layer is a conductive layer, the shielding layer comprises a plurality of independently provided shielding portions, and at least some of different shielding portions are used for receiving different signals. The display panel has a relatively high integration level.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In related technologies, a display panel needs to integrate circuit structures such as a pixel driving circuit, a gate driving circuit, and a detection circuit, which results in the display panel requiring a larger layout space to set up the above circuit structures.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit, the pixel driving circuit includes a transistor, and the display panel further includes: a base substrate, a first active layer, and a blocking layer, the first active layer is located on one side of the base substrate, at least a portion of the structure of the first active layer is used to form a channel region of the transistor; the blocking layer is located between the base substrate and the first active layer, the blocking layer is a conductive layer, and the blocking layer includes a plurality of independently arranged blocking portions, at least some of the different blocking portions are used to receive different signals.

[0006] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor; the plurality of shielding portions include the first initial signal line.

[0007] In an exemplary embodiment of the present disclosure, the first active layer includes a first active portion and a third sub-active portion, the first active portion is used to form a channel region of the first transistor, the first active portion includes a first sub-active portion and a second sub-active portion, and the third sub-active portion is connected between the first sub-active portion and the second sub-active portion; the first initial signal line includes a first extension portion, and the orthographic projection of the first extension portion on the base substrate at least partially overlaps with the orthographic projection of the third sub-active portion on the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the display panel further includes: a first conductive layer, the first conductive layer is located on a side of the first active layer facing away from the base substrate, the first conductive layer includes a first reset signal line, the orthographic projection of the first reset signal line on the base substrate extends along a first direction and covers the orthographic projection of the first active portion on the base substrate, and a partial structure of the first reset signal line is used to form a gate of the first transistor; the first initial signal line includes a second extension portion, the orthographic projection of the second extension portion on the base substrate at least partially overlaps with the orthographic projection of the first reset signal line on the base substrate.

[0009] In an exemplary embodiment of the present disclosure, the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on the side of the first active layer away from the base substrate, and the fourth conductive layer includes a first initial connection line; wherein, the orthographic projection of the first initial signal line on the base substrate extends along a first direction, the orthographic projection of the first initial connection line on the base substrate extends along a second direction, the first direction and the second direction intersect, and the first initial connection line is connected to the first initial signal line intersecting with its orthographic projection on the base substrate through a via.

[0010] In an exemplary embodiment of the present disclosure, the display panel also includes a light-emitting unit, the pixel driving circuit includes a seventh transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the plurality of shielding portions include the second initial signal line.

[0011] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode is connected to the first electrode of the light-emitting unit; the first active layer includes a sixth active portion and a seventh active portion, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor; the display panel further includes: a first conductive layer, the first conductive layer being located on a side of the first active layer facing away from the base substrate, the first conductive layer including: an enable signal line and a second reset signal line, the orthographic projection of the enable signal line on the base substrate extending along a first direction and covering the orthographic projection of the sixth active portion on the base substrate, and a portion of the structure of the enable signal line forming a gate of the sixth transistor; the orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering the orthographic projection of the seventh active portion on the base substrate, and a portion of the structure of the second reset signal line forming a gate of the seventh transistor; wherein the orthographic projection of the second initial signal line on the base substrate is located between the orthographic projection of the enable signal line and the orthographic projection of the second reset signal line on the base substrate.

[0012] In an exemplary embodiment of the present disclosure, the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on the side of the first active layer away from the base substrate, and the fourth conductive layer includes a second initial connection line; wherein, the orthographic projection of the second initial connection line on the base substrate extends along a first direction, the orthographic projection of the second initial connection line on the base substrate extends along a second direction, the first direction and the second direction intersect, and the second initial connection line is connected to the second initial signal line intersecting with its orthographic projection on the base substrate through a via.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, the first active layer includes a third active portion, and the third active portion is used to form a channel region of the driving transistor; the multiple blocking portions include a first blocking portion, the first blocking portion is connected to a stable voltage source, and the orthographic projection of the first blocking portion on the substrate covers the orthographic projection of the third active portion on the substrate.

[0014] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to the power line; the display panel also includes: a first conductive layer, the first conductive layer is located on the side of the first active layer away from the base substrate, the first conductive layer includes a first conductive portion, the orthographic projection of the first conductive portion on the base substrate covers the orthographic projection of the third active portion on the base substrate, the first conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor; the power line forms the stable voltage source, and the first blocking portion is used to form the second electrode of the capacitor.

[0015] In an exemplary embodiment of the present disclosure, the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on the side of the first conductive layer away from the base substrate, the fourth conductive layer includes the power line, and the positive projection of the power line on the base substrate extends along the second direction; the display panel includes a plurality of pixel driving circuits distributed in an array in the first direction and the second direction, the first direction and the second direction intersect, the plurality of first blocking portions distributed in the first direction are connected, and the power line is connected to the first blocking portion through a via.

[0016] In an exemplary embodiment of the present disclosure, the power line includes a third extension portion, a fourth extension portion, and a fifth extension portion connected between the third extension portion and the fourth extension portion, the size of the orthographic projection of the fifth extension portion on the substrate in the first direction is larger than the size of the orthographic projection of the third extension portion on the substrate in the first direction, the size of the orthographic projection of the fifth extension portion on the substrate in the first direction is larger than the size of the orthographic projection of the fourth extension portion on the substrate in the first direction, the first direction and the second direction intersect; the orthographic projection of the fifth extension portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate, and at least a partial structure of the fifth extension portion is used to form the second electrode of the capacitor.

[0017] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, wherein a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; the first active layer further includes a second active portion and a sixth sub-active portion, the second active portion is used to form a channel region of the second transistor, the second active portion includes a fourth sub-active portion and a fifth sub-active portion, and the sixth sub-active portion is connected between the fourth sub-active portion and the fifth sub-active portion; the blocking layer further includes a second blocking portion, the second blocking portion is connected to the first blocking portion, the first blocking portion includes a first edge, the second blocking portion includes a second edge, the first edge and the second edge are connected, and the angle between the orthographic projection of the first edge on the substrate and the orthographic projection of the second edge on the substrate is less than 180°, and the orthographic projection of the second blocking portion on the substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion on the substrate.

[0018] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor; a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode is connected to the second electrode of the driving transistor; the first active layer further includes a first active portion, a second active portion, and an eighth active portion, the first active portion is used to form a channel region of the first transistor, the second active portion is used to form a channel region of the second transistor, and the eighth active portion is connected between the first active portion and the second active portion; the blocking layer further includes a third blocking portion, the third blocking portion is connected to the first blocking portion, the first blocking portion includes a first edge, the third blocking portion includes a third edge, the first edge and the third edge are connected, and an angle between an orthographic projection of the first edge on the substrate and an orthographic projection of the third edge on the substrate is less than 180°, and the orthographic projection of the third blocking portion on the substrate at least partially overlaps with the orthographic projection of the eighth active portion on the substrate.

[0019] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a second transistor, wherein the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the first active layer further includes a first active portion, a second active portion, a sixth sub-active portion, and an eighth active portion, the first active portion is used to form a channel region of the first transistor, the second active portion is used to form a channel region of the second transistor, the second active portion includes a fourth sub-active portion and a fifth sub-active portion, the sixth sub-active portion is connected between the fourth sub-active portion and the fifth sub-active portion, and the eighth active portion is connected between the first active portion and the second active portion; the display panel further includes a first conductive layer, the first conductive layer is located on a side of the first active layer away from the base substrate, the first conductive layer includes a first conductive portion and a first gate line, the first conductive portion The orthographic projection on the substrate covers the orthographic projection of the third active portion on the substrate, and the orthographic projection of the first gate line on the substrate extends along the first direction and covers the orthographic projection of the second active portion on the substrate; the blocking layer also includes a second blocking portion, a third blocking portion, and a first connecting portion, the second blocking portion is connected to the first blocking portion, and the orthographic projection of the second blocking portion on the substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion on the substrate; the third blocking portion is connected to the first blocking portion, and the orthographic projection of the third blocking portion on the substrate at least partially overlaps with the orthographic projection of the eighth active portion on the substrate; the first connecting portion is connected between the second blocking portion and the third blocking portion in the adjacent pixel driving circuits in the first direction, and the orthographic projection of the first connecting portion on the substrate is located on the side of the orthographic projection of the first gate line on the substrate away from the orthographic projection of the first conductive portion on the substrate.

[0020] In an exemplary embodiment of the present disclosure, the display panel further includes a display area and a frame area located around the display area, part of the blocking portion is located in the display area, and part of the blocking portion is located in the frame area.

[0021] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a plurality of transistors, and the plurality of shielding parts include a constant voltage shielding part corresponding to the transistor, the orthographic projection of the constant voltage shielding part on the substrate and the orthographic projection of the channel region of the corresponding transistor on the substrate at least partially overlap; at least partially different constant voltage shielding parts are used to receive different power supply voltages.

[0022] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes an N-type transistor and a P-type transistor; the multiple constant voltage shielding parts include a positive voltage shielding part and a negative voltage shielding part, the positive voltage shielding part is used to receive a positive power supply voltage, and the negative voltage shielding part is used to receive a negative power supply voltage; the positive voltage shielding part's positive projection on the substrate at least partially overlaps with the positive projection of the P-type transistor channel region on the substrate, and the negative voltage shielding part's positive projection on the substrate at least partially overlaps with the positive projection of the N-type transistor channel region on the substrate.

[0023] In an exemplary embodiment of the present disclosure, the display panel also includes a light-emitting unit, and the pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, and the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the multiple constant voltage shielding parts include multiple positive voltage shielding parts, and the multiple positive voltage shielding parts It includes: a first positive pressure shielding part, a second positive pressure shielding part, and a third positive pressure shielding part, the orthographic projection of the first positive pressure shielding part on the substrate covers the orthographic projection of the driving transistor channel region on the substrate; the orthographic projection of the second positive pressure shielding part on the substrate covers the orthographic projection of the fifth transistor channel region on the substrate and the orthographic projection of the sixth transistor channel region on the substrate; the orthographic projection of the third positive pressure shielding part on the substrate covers the orthographic projection of the fourth transistor channel region on the substrate and the orthographic projection of the seventh transistor channel region on the substrate; wherein, the positive voltage received by the first positive pressure shielding part is greater than the positive voltage received by the second positive pressure shielding part, and the positive voltage received by the third positive pressure shielding part is greater than the positive voltage received by the first positive pressure shielding part.

[0024] In an exemplary embodiment of the present disclosure, the display panel includes a high-density integration area and a low-density integration area, the density of transistors in the high-density integration area is greater than the density of transistors in the low-density integration area; the high-density integration area includes a first high-density integration area and a second high-density integration area, the second high-density integration area is located on a side of the first high-density integration area away from the low-density integration area; in the constant-voltage blocking part corresponding to the same transistor in the pixel driving circuit, the absolute value of the voltage received by the constant-voltage blocking part located in the first high-density integration area is greater than the absolute value of the voltage received by the constant-voltage blocking part located in the second high-density integration area.

[0025] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0028] FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;

[0029] FIG2 is a timing diagram of signals at each node in a driving method of the pixel driving circuit shown in FIG1 ;

[0030] FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0031] FIG4 is a structural diagram of the shielding layer in FIG3 ;

[0032] FIG5 is a structural diagram of the first active layer in FIG3;

[0033] FIG6 is a structural diagram of the first conductive layer in FIG3 ;

[0034] FIG7 is a structural diagram of the fourth conductive layer in FIG3;

[0035] FIG8 is a structural diagram of the fifth conductive layer in FIG3 ;

[0036] FIG9 is a structural diagram of the shielding layer and the first active layer in FIG3 ;

[0037] FIG10 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG3 ;

[0038] FIG11 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in FIG3 ;

[0039] FIG12 is a partial cross-sectional view of the display panel shown in FIG3 taken along dotted line AA;

[0040] FIG13 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0041] FIG14 is a structural diagram of the shielding layer in FIG13 ;

[0042] FIG15 is a structural layout diagram of the barrier layer and the first active layer in FIG13;

[0043] FIG16 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0044] FIG17 is a structural layout diagram of the fourth conductive layer in FIG16;

[0045] FIG18 is a structural layout diagram of the fifth conductive layer in FIG16 ;

[0046] FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in FIG16 ;

[0047] FIG20 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0048] FIG21 is a structural diagram of the shielding layer in FIG20 ;

[0049] FIG22 is a structural layout diagram of the fourth conductive layer in FIG20 ;

[0050] FIG23 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in FIG20;

[0051] FIG24 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0052] FIG25 is a structural layout diagram of the fourth conductive layer in FIG24;

[0053] FIG26 is a structural layout diagram of the fifth conductive layer in FIG24;

[0054] FIG27 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in FIG24 ;

[0055] FIG28 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0056] FIG29 is a schematic diagram of the circuit structure of a pixel driving circuit in another exemplary embodiment of the display panel disclosed herein;

[0057] FIG30 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG29;

[0058] FIG31 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0059] FIG32 is a structural diagram of the shielding layer in FIG31;

[0060] FIG33 is a structural layout diagram of the first active layer in FIG31;

[0061] FIG34 is a structural layout diagram of the first conductive layer in FIG31;

[0062] FIG35 is a structural layout diagram of the second conductive layer in FIG31;

[0063] FIG36 is a structural layout diagram of the second active layer in FIG31;

[0064] FIG37 is a structural layout diagram of the third conductive layer in FIG31;

[0065] FIG38 is a structural layout diagram of the fourth conductive layer in FIG31;

[0066] FIG39 is a structural diagram of the fifth conductive layer in FIG27;

[0067] FIG40 is a structural layout diagram of the shielding layer and the first active layer in FIG31;

[0068] FIG41 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG31 ;

[0069] FIG42 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG31;

[0070] FIG43 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG31 ;

[0071] FIG44 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG31 ;

[0072] FIG45 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG31 ;

[0073] FIG46 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG31 ;

[0074] FIG47 is a partial cross-sectional view taken along dotted line BB in FIG31;

[0075] FIG48 is another exemplary structural diagram of the display panel disclosed herein. DETAILED DESCRIPTION

[0076] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0077] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0078] As shown in Figure 1, a circuit structure diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure is shown. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first transistor T1 has a first electrode connected to the first initial signal terminal Vinit1, a second electrode connected to the node N, and a gate connected to the first reset signal terminal Re1. The second transistor T2 has a first electrode connected to the node N, a second electrode connected to the second electrode of the driving transistor T3, and a gate connected to the first gate drive signal terminal G1. The gate of the driving transistor T3 is connected to the node N. The fourth transistor T4 has a first electrode connected to the data signal terminal Da, a second electrode connected to the first electrode of the driving transistor T3, and a gate connected to the first gate drive signal terminal G1. The fifth transistor T5 has a first electrode connected to the first power supply terminal VDD, a second electrode connected to the first electrode of the driving transistor T3, and a gate connected to the enable signal terminal EM. The sixth transistor T6 has a first electrode connected to the second electrode of the driving transistor T3, and a gate connected to the enable signal terminal EM. The seventh transistor T7 has a first electrode connected to the second initial signal terminal Vinit2, a second electrode connected to the second electrode of the sixth transistor T6, and a gate connected to the second reset signal terminal Re2. A capacitor C is connected between the gate of the driving transistor T3 and the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit OLED, and the pixel driving circuit is used to drive the light-emitting unit OLED to emit light. The light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors.

[0079] As shown in Figure 2, it is a timing diagram of the signals on each node in a driving method of the pixel driving circuit shown in Figure 1. Among them, G1 represents the timing diagram of the signal on the first gate driving signal terminal G1, Re1 represents the timing diagram of the signal on the first reset signal terminal Re1, Re2 represents the timing diagram of the signal on the second reset signal terminal Re2, EM represents the timing diagram of the signal on the enable signal terminal EM, and Da represents the timing diagram of the signal on the data signal terminal Da. The driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light-emitting phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N. During the compensation phase t2, the second reset signal terminal Re2 and the first gate drive signal terminal G1 output low-level signals, turning on the fourth transistor T4, the second transistor T2, and the seventh transistor T7. Simultaneously, the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driver transistor T3. The second initial signal terminal Vini2 inputs a second initial signal to the second electrode of the sixth transistor T6. During the light-emitting phase t3, the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. The driver transistor T3 drives the light-emitting unit to emit light under the voltage Vdata+Vth at node N. According to the driver transistor output current formula, I = (μWCox / 2L)(Vgs-Vth)², where μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driver transistor channel; L is the length of the driver transistor channel; Vgs is the gate-source voltage difference of the driver transistor; and Vth is the threshold voltage of the driver transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth)2. This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that in other exemplary embodiments, the pixel driving circuit can also have other driving methods. For example, the first transistor T1 and the seventh transistor T7 can both be turned on during the reset phase.

[0080] This exemplary embodiment also provides a display panel, which may include a base substrate, a blocking layer, a first active layer, a first conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence, wherein an insulating layer may be provided between the adjacent layers. As shown in Figures 3-11, Figure 3 is a structural layout diagram of an exemplary embodiment of a display panel disclosed herein, Figure 4 is a structural layout diagram of the blocking layer in Figure 3, Figure 5 is a structural layout diagram of the first active layer in Figure 3, Figure 6 is a structural layout diagram of the first conductive layer in Figure 3, Figure 7 is a structural layout diagram of the fourth conductive layer in Figure 3, Figure 8 is a structural layout diagram of the fifth conductive layer in Figure 3, Figure 9 is a structural layout diagram of the blocking layer and the first active layer in Figure 3, Figure 10 is a structural layout diagram of the blocking layer, the first active layer, and the first conductive layer in Figure 3, and Figure 11 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 3. The display panel may include multiple pixel driving circuits as shown in Figure 1.

[0081] As shown in Figures 3, 4, and 9, the shielding layer can be a conductive layer and can include a plurality of first initial signal lines Vinit1, second initial signal lines Vinit2, a first shielding portion 61, a second shielding portion 62, and a third shielding portion 63. The orthographic projection of the first initial signal line Vinit1 on the substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate can both extend along the first direction X. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 1, and the second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 1. The first shielding portion 61 is connected to the second shielding portion 62 and the third shielding portion 63, respectively. The first shielding portions 61 spaced apart in the first direction X can be connected sequentially. The first shielding portion 61 can include a first edge 611, the second shielding portion 62 can include a second edge 622, and the third shielding portion 63 can include a third edge 633. The first edge 611 is connected to the second edge 622. The angle between the orthographic projection of the first edge 611 on the substrate and the orthographic projection of the second edge 622 on the substrate can be less than 180°. For example, the angle between the orthographic projection of the first edge 611 on the substrate and the orthographic projection of the second edge 622 on the substrate can be 90°. The first edge 611 is connected to the third edge 633. The angle between the orthographic projection of the first edge 611 on the substrate and the orthographic projection of the third edge 633 on the substrate can be less than 180°. For example, the angle between the orthographic projection of the first edge 611 on the substrate and the orthographic projection of the third edge 633 on the substrate can be 90°.

[0082] As shown in Figures 3, 5, and 9, the first active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The first active portion 71 is used to form the channel region of the first transistor T1, the second active portion 72 is used to form the channel region of the second transistor T2, the third active portion 73 is used to form the channel region of the driving transistor T3, the fourth active portion 74 is used to form the channel region of the fourth transistor T4, the fifth active portion 75 is used to form the channel region of the fifth transistor T5, the sixth active portion 76 is used to form the channel region of the sixth transistor T6, and the seventh active portion 77 is used to form the channel region of the seventh transistor T7. The first active portion 71 may include a first sub-active portion 711 and a second sub-active portion 712. The first active layer further includes a third sub-active portion 713 connected between the first sub-active portion 711 and the second sub-active portion 712. The second active portion 72 may include a fourth sub-active portion 724 and a fifth sub-active portion 725. The first active layer further includes a sixth sub-active portion 726 connected between the fourth sub-active portion 724 and the fifth sub-active portion 725. The first active layer may further include an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, a fourteenth active portion 714, a fifteenth active portion 715, and a sixteenth active portion 716. The eighth active portion 78 is connected between the first active portion 71 and the second active portion 72, the ninth active portion 79 is connected to one end of the third active portion 73 of the fifth active portion 75, the tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the sixteenth active portion 716 is connected to one end of the fourth active portion 74 away from the third active portion 73, the fourteenth active portion 714 is connected to one end of the seventh active portion 77 away from the sixth active portion 76, and the fifteenth active portion 715 is connected to one end of the first active portion 71 away from the second active portion 72. The first active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.

[0083] As shown in Figures 3, 6, and 10, the first conductive layer may include a first reset signal line Re1, a first gate line G1, an enable signal line EM, a second reset signal line Re2, and a first conductive portion 11. Among them, the orthographic projection of the first reset signal line Re1 on the base substrate, the orthographic projection of the first gate line G1 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending straight or bent along the direction. The orthographic projection of the first reset signal line Re1 on the base substrate can cover the orthographic projection of the first active portion 71 on the base substrate. Part of the structure of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The first reset signal line Re1 can be used to provide a first reset signal terminal in the pixel driving circuit shown in Figure 1. The orthographic projection of the second reset signal line Re2 on the base substrate can overlap the orthographic projection of the seventh active portion 77 on the base substrate. A portion of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The second reset signal line Re2 can be used to provide a second reset signal terminal in the pixel driving circuit shown in FIG1 . The orthographic projection of the first gate line G1 on the base substrate can overlap the orthographic projections of the second active portion 72 and the fourth active portion 74 on the base substrate. A portion of the first gate line G1 can be used to form the gate of the second transistor T2. Another portion of the first gate line G1 can be used to form the gate of the fourth transistor T4. The first gate line G1 can be used to provide a first gate driving signal terminal in the pixel driving circuit shown in FIG1 . The orthographic projection of the enable signal line EM on the base substrate can cover the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the base substrate. Part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and another part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6. The enable signal line EM can be used to provide an enable signal terminal in the pixel driving circuit shown in Figure 1. The orthographic projection of the first conductive portion 11 on the base substrate can cover the orthographic projection of the third active portion 73 on the base substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. In addition, the display panel can use the first conductive layer as a mask to perform a conductor processing on the first active layer. That is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0084] In this exemplary embodiment, as shown in Figures 3, 4, 6, 9, and 10, the orthographic projection of the first shielding portion 61 on the substrate can overlap with the orthographic projection of the third active portion 73 on the substrate. For example, the orthographic projection of the first shielding portion 61 on the substrate can cover the orthographic projection of the third active portion 73 on the substrate. The first shielding portion 61 can be connected to a stable voltage source. For example, the first shielding portion 61 can be connected to the first power supply terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, etc. in Figure 1. The first shielding portion 61 can be used to shield the driving transistor T3 from noise from other signals. When the first shielding portion 61 is connected to the first power supply terminal VDD, the first shielding portion 61 can also be used to form the second electrode of the capacitor C. The orthographic projection of the second blocking portion 62 on the substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion 726 on the substrate. The second blocking portion 62 can stabilize the voltage of the sixth sub-active portion 726, thereby reducing leakage current from the sixth sub-active portion 726 to the source and drain of the second transistor caused by voltage fluctuations in the sixth sub-active portion 726. The orthographic projection of the third blocking portion 63 on the substrate at least partially overlaps with the orthographic projection of the eighth active portion 78 on the substrate. The third blocking portion 63 can stabilize the voltage of the eighth active portion 78, thereby reducing voltage fluctuations at the gate of the driving transistor T3. As shown in FIG4 , the first initial signal line Vinit1 includes a first extension portion Vinit11 and a second extension portion Vinit12. The orthographic projection of the first extension portion Vinit11 on the base substrate can at least partially overlap with the orthographic projection of the third sub-active portion 713 on the base substrate. The first extension portion Vinit11 can stabilize the voltage of the third sub-active portion 713, thereby reducing leakage current from the third sub-active portion 713 to the source and drain of the first transistor caused by voltage fluctuations in the third sub-active portion 713. The orthographic projection of the second extension portion Vinit12 on the base substrate can at least partially overlap with the orthographic projection of the first reset signal line Re1 on the base substrate, thereby improving the transmittance of the display panel.

[0085] As shown in Figures 3, 7, and 11, the fourth conductive layer may include a first initial connection line 4Vinit1, a power line VDD, a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, and a fourth bridge portion 44. The orthographic projection of the first initial connection line 4Vinit1 on the base substrate and the orthographic projection of the power line VDD on the base substrate may both extend along a second direction Y, and the second direction Y may intersect with the first direction X. For example, the second direction Y may be a column direction, and the first direction X may be a row direction. The first initial connection line 4Vinit1 may be connected to the first initial signal line Vinit1 and the fifteenth active portion 715 through vias H, respectively, to connect the first initial signal terminal and the first electrode of the first transistor. The black squares in the figures indicate the locations of the vias. In this exemplary embodiment, the first initial connection line 4Vinit1 and the first initial signal line Vinit1 may form a grid structure, which may reduce the voltage difference between the first initial signal terminals at different locations on the display panel. The power line VDD can provide a first power terminal. The power line VDD can be connected to the first shielding portion 61 and the ninth active portion 79 through vias, thereby connecting the second electrode of the capacitor, the first power terminal, and the first electrode of the fifth transistor. As shown in Figures 3, 7, and 11, the power line VDD can include a third extension portion VDD3, a fourth extension portion VDD4, and a fifth extension portion VDD5. The fifth extension portion VDD5 is connected between the third extension portion VDD3 and the fourth extension portion VDD4. The orthogonal projection of the fifth extension portion VDD5 on the substrate in the first direction X is larger than the orthogonal projection of the third extension portion VDD3 on the substrate in the first direction X. The orthogonal projection of the fifth extension portion VDD5 on the substrate in the first direction X is larger than the orthogonal projection of the fourth extension portion VDD4 on the substrate in the first direction X. The orthogonal projection of the fifth extension portion VDD5 on the substrate can also at least partially overlap with the orthogonal projection of the first conductive portion 11 on the substrate. The fifth extension portion VDD5 can also be used to form the second electrode of the capacitor C. The orthographic projection of the first conductive portion 11 on the substrate is denoted by an area S1. The overlapping area of ​​the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the fifth extension portion VDD5 on the substrate is denoted by an area S2. S2 / S1 may be greater than or equal to 60%. For example, S2 / S1 may be 60%, 70%, 80%, 90%, 100%, etc. The power line VDD and the first shielding portion 61 may also form a grid structure. This arrangement can reduce voltage differences between the first power terminals at different locations on the display panel.

[0086] As shown in Figures 3, 7, and 11, the first bridge portion 41 can be connected to the second initial signal line Vinit2 and the fourteenth active portion 714 through vias, respectively, to connect the first electrode and the second initial signal terminal of the seventh transistor. The second bridge portion 42 can be connected to the tenth active portion 710 through a via to connect the second electrode of the sixth transistor and the second electrode of the seventh transistor. The third bridge portion 43 can be connected to the sixteenth active portion 716 through a via to connect the first electrode of the fourth transistor. The fourth bridge portion 44 can be connected to the eighth active portion 78 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2, the second electrode of the first transistor T1, and the gate of the driving transistor T3.

[0087] As shown in Figures 3 and 8, the fifth conductive layer may include a fifth bridge portion 55 and a data line Da. The data line Da may be used to provide the data signal terminal shown in Figure 1. The fifth bridge portion 55 may be connected to the second bridge portion 42 via a via to connect to the second electrode of the sixth transistor. The fifth bridge portion 55 may also be connected to the first electrode of the light-emitting unit. The orthographic projection of the data line Da on the base substrate may extend along the second direction Y. The data line Da may be connected to the third bridge portion 43 via a via to connect to the first electrode of the fourth transistor and the data signal terminal.

[0088] It should be noted that, as shown in Figures 3 and 11, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. The black squares merely indicate the locations of the vias; different vias represented by black squares in different locations can penetrate different insulating layers.

[0089] FIG12 is a partial cross-sectional view of the display panel shown in FIG3 taken along dashed line AA. The display panel may further include a buffer layer 91, an insulating layer 92, a dielectric layer 93, a passivation layer 94, and a first planarization layer 95. The base substrate, the shielding layer, the buffer layer 91, the first active layer, the insulating layer 92, the first conductive layer, the dielectric layer 93, the fourth conductive layer, the passivation layer 94, the first planarization layer 95, and the fifth conductive layer are stacked in this order. The buffer layer 91 may include a silicon oxide layer and a silicon nitride layer. The insulating layer 92 can be a single-layer structure or a multi-layer structure. The material of the insulating layer 92 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The dielectric layer 93 can be a silicon nitride layer. The passivation layer 94 can be a silicon oxide layer. The material of the first planar layer 95 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The material of the first conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate. The materials of the fourth and fifth conductive layers can include metal materials, such as one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, or a titanium / aluminum / titanium laminate. The display panel may further include a second flat layer, an electrode layer, and a pixel definition layer, wherein the second flat layer is located on the side of the fifth conductive layer facing away from the base substrate, the electrode layer is located on the side of the second flat layer facing away from the base substrate, and the pixel definition layer is located on the side of the electrode layer facing away from the base substrate.

[0090] It should be noted that the scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are only schematic structural diagrams. In addition, qualifiers such as first and second are only used to define different structural names and do not imply a specific order.

[0091] As shown in Figures 13-15, Figure 13 is a structural layout diagram of another exemplary embodiment of the display panel disclosed in the present invention, Figure 14 is a structural layout diagram of the blocking layer in Figure 13, and Figure 15 is a structural layout diagram of the blocking layer and the first active layer in Figure 13.

[0092] As shown in Figures 14 and 15, the first active layer may further include a seventeenth active portion 717, the seventeenth active portion 717 being connected between the second active portion 72 and the sixth active portion 76, and the orthographic projection of the seventeenth active portion 717 on the base substrate extending along the second direction Y, wherein the seventeenth active portion 717 is the equipotential point of the second pole of the driving transistor. The difference between the display panel shown in Figure 13 and the display panel shown in Figure 3 is that in the display panel shown in Figure 13, there is a break D1 between adjacent first blocking portions 61 in the first direction X, that is, adjacent first blocking portions 61 in the first direction X are not directly connected. The orthographic projection of the break D1 on the base substrate intersects with the orthographic projection of the seventeenth active portion 717 on the base substrate. This setting can reduce the parasitic capacitance between the seventeenth active portion 717 and the blocking layer, thereby improving the problem of image sticking in the display panel. As shown in Figure 14, the shielding layer includes a first connecting portion 64, which is connected between the third shielding portion 63 and the second shielding portion 62 in adjacent pixel driving circuits located in the same row. The orthographic projection of the first connecting portion 64 on the base substrate can be located on a side of the orthographic projection of the first gate line G1 on the base substrate away from the orthographic projection of the first conductive portion 11 on the base substrate. That is, the orthographic projection of the first connecting portion 64 on the base substrate does not overlap with the orthographic projection of the seventeenth active portion 717 on the base substrate. This exemplary embodiment can connect two adjacent first shielding portions 61 in the first direction X through the first connecting portion 64. In addition, the other structures of the display panel shown in Figure 14 can be the same as the display panel shown in Figure 3.

[0093] As shown in Figures 16-19, Figure 16 is a structural layout of another exemplary embodiment of the display panel disclosed herein, Figure 17 is a structural layout of the fourth conductive layer in Figure 16, Figure 18 is a structural layout of the fifth conductive layer in Figure 16, and Figure 19 is a structural layout of the blocking layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 16.

[0094] The display panel shown in FIG16 differs from the display panel shown in FIG3 in that the fifth conductive layer in the display panel shown in FIG16 may further include a second initial connection line 5Vinit2. The orthographic projection of the second initial connection line 5Vinit2 on the base substrate may extend along the second direction Y. The second initial connection line 5Vinit2 may be connected to the first bridge portion 41 via a via to connect to the second initial signal line Vinit2. The second initial connection line 5Vinit2 and the second initial signal line Vinit2 may form a grid structure, which may reduce the voltage difference between the second initial signal terminals at different locations on the display panel. The other structures of the display panel shown in FIG16 may be the same as those of the display panel shown in FIG3.

[0095] As shown in Figures 20-23, Figure 20 is a structural layout of another exemplary embodiment of the display panel disclosed herein, Figure 21 is a structural layout of the blocking layer in Figure 20, Figure 22 is a structural layout of the fourth conductive layer in Figure 20, and Figure 23 is a structural layout of the blocking layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 20.

[0096] The display panel shown in FIG20 differs from the display panel shown in FIG3 in that the fourth conductive layer in the display panel shown in FIG20 further includes a second initial connection line 4Vinit2. Two adjacent columns of pixel drive circuits can each be provided with a first initial connection line 4Vinit1 and a second initial connection line 4Vinit2. The fourth conductive layer can also include a sixth bridge portion 46. The first initial connection line 4Vinit1 can be connected to the first initial signal line Vinit1 via the sixth bridge portion 46, and the second initial connection line 4Vinit2 can be connected to the second initial signal line Vinit2 via the first bridge portion 41. The other structures of the display panel shown in FIG20 can be the same as those of the display panel shown in FIG3.

[0097] As shown in Figures 24-27, Figure 24 is a structural layout of another exemplary embodiment of the display panel disclosed herein, Figure 25 is a structural layout of the fourth conductive layer in Figure 24, Figure 26 is a structural layout of the fifth conductive layer in Figure 25, and Figure 27 is a structural layout of the blocking layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 24.

[0098] The display panel shown in Figure 24 differs from the display panel shown in Figure 3 in that the fourth conductive layer of the display panel shown in Figure 24 lacks a power line VDD. Instead, the fourth conductive layer is provided with a seventh bridge 47, which is connected to the first shielding portion 61 via a via. The fifth conductive layer of the display panel shown in Figure 24 also includes a power line VDD and a second initial connection line 5Vinit2. The power line VDD is connected to the seventh bridge 47 via a via to connect to the second electrode of the capacitor. The orthographic projection of the power line VDD on the substrate also covers the orthographic projection of the fourth bridge 44 on the substrate. This shields the fourth bridge 44 from noise interference from other signals, thereby reducing voltage fluctuations at the gate of the driving transistor T3. The second initial connection line 5Vinit2 is connected to the first bridge 41 via a via, forming a grid structure with the second initial signal line Vinit2. This grid structure reduces voltage differences between the second initial signal terminals at different locations on the display panel. The other structures of the display panel shown in Figure 24 are the same as those of the display panel shown in Figure 3.

[0099] This exemplary embodiment utilizes a shielding layer to form part of the signal lines and device structures in the display panel, thereby improving the integration of the display panel. In addition, compared to the display panel in the related art, the display panel forms the second electrode of the capacitor through the first shielding portion 61 and the fifth extension portion VDD5, and the display panel does not need to be provided with a second gate layer. In the display panel, the second shielding portion 62 and the third shielding portion 63 are directly connected to the first shielding portion 61, and the second shielding portion 62 and the third shielding portion 63 do not need to be connected to the power line through a via, thereby reducing the number of vias. It should be understood that the shielding layer may also include other independently provided shielding portions, and the shielding portions may also be used to form other signal lines and device structures.

[0100] In the related art, the PI layer (polyimide) in the base substrate easily generates a negative electrostatic field, which can cause the threshold of the transistor to be positively biased. For example, this negative electrostatic field can easily cause the threshold of the driving transistor to shift positively, and the positive shift of the threshold of the driving transistor can cause undesirable phenomena such as the copper rod test of the display panel to turn green. The above-mentioned first shielding portion 61 can shield the impact of the above-mentioned negative electrostatic field on the threshold of the driving transistor T3. In addition, the shielding layer can be a light-shielding structure, which can prevent the influence of light on the characteristics of the transistor.

[0101] In related art, a positive bias in the threshold of the driving transistor T3 increases the drive current at the same grayscale, which can easily cause the display panel to appear greenish. In this exemplary embodiment, the first shielding portion 61 can receive a positive power supply voltage. The positive electric field generated by the first shielding portion 61 causes the threshold of the driving transistor to appear negative, thereby reducing the risk of the display panel appearing greenish.

[0102] It should be understood that in other exemplary embodiments, the threshold voltages of other transistors in the pixel driving circuit may also experience threshold drift, thereby leading to problems such as transistor leakage current. For example, in Figure 1, the leakage current of the first transistor T1 and the second transistor T2 may cause defects such as flickering of the display panel, and the leakage current of the sixth transistor T6 may cause defects such as a four-split screen of the display panel. In this exemplary embodiment, the blocking layer may also include other blocking parts, and the orthographic projections of the other blocking parts on the substrate may respectively cover at least part of the structure of the orthographic projections of the channel regions of other transistors on the substrate. The other blocking parts may be independently provided or at least partially connected. Wherein, the blocking part is independently provided, which may be understood as the blocking part being not connected to the other blocking parts.

[0103] Multiple independently arranged shielding portions can receive different power supply voltages, and the size of the power supply voltage received by the shielding portion can be affected by the type of transistor. For example, the shielding portion below the P-type transistor can receive a positive power supply voltage, and the positive electric field formed by the shielding portion can make the threshold of the P-type transistor negatively biased, thereby reducing the turn-off leakage current of the P-type transistor. The shielding portion below the N-type transistor can be connected to a negative power supply voltage, and the negative electric field formed by the shielding portion can make the threshold of the N-type transistor positively biased, thereby reducing the turn-off leakage current of the N-type transistor. For example, the first transistor and the second transistor in Figure 1 can be N-type transistors, and a shielding portion can be provided below the first transistor and the second transistor, and the shielding portion below the first transistor and the second transistor can receive a negative power supply voltage.

[0104] In addition, the magnitude of the power supply voltage received by the shielding portion can be determined by the operating state of the transistors. For example, in this exemplary embodiment, because the fourth transistor T4 and the seventh transistor T7 are in a forward-biased state for a long time, and the fifth transistor T5 and the sixth transistor T6 are in a negative-biased state for a long time, the positive voltage received by the shielding portion below the fourth transistor T4 and the seventh transistor T7 can be greater than the positive voltage received by the shielding portion below the fifth transistor T5 and the sixth transistor T6. For example, the voltage received by the shielding portion below the fourth transistor T4 and the seventh transistor T7 can be 6.6V, and the voltage received by the shielding portion below the fifth transistor T5 and the sixth transistor T6 can be 2.6V.

[0105] Furthermore, the magnitude of the power supply voltage received by the shielding portion may be affected by the size of the transistor. For example, if the aspect ratio of the channel region of the driver transistor is greater than the aspect ratio of the channel region of the fifth transistor T5, the voltage received by the shielding portion below the driver transistor may be greater than the voltage received by the shielding portion below the fifth transistor T5. For example, the voltage received by the shielding portion below the driver transistor may be 4.6V.

[0106] In addition, the magnitude of the power supply voltage received by the shielding portion may be affected by the position of the transistor. There are differences in the density of transistors in different areas of the display panel, and the threshold value of the transistor near the low-density transistor area is prone to shift. As shown in Figure 28, it is a structural schematic diagram of an exemplary embodiment of the display panel of the present disclosure. The display panel may include a high-density integration area H and a low-density integration area L, and the density of transistors in the high-density integration area H is greater than the density of transistors in the low-density integration area L. The high-density integration area includes a first high-density integration area H1 and a second high-density integration area H2, and the second high-density integration area H2 is located on the side of the first high-density integration area H1 away from the low-density integration area L. In the shielding portion corresponding to the same transistor in the pixel driving circuit, the absolute value of the voltage received by the shielding portion located in the first high-density integration area H1 is greater than the absolute value of the voltage received by the shielding portion located in the second high-density integration area H2. For example, in the shielding portion corresponding to the driving transistor in the pixel driving circuit, the shielding portion corresponding to the driving transistor in the first high-density integrated area H1 is used to receive a positive power supply voltage that is greater than the positive power supply voltage that is received by the shielding portion corresponding to the driving transistor in the second high-density integrated area H2. For another example, when the first transistor in FIG1 is an N-type transistor, in the shielding portion corresponding to the first transistor in the pixel driving circuit, the shielding portion corresponding to the first transistor in the first high-density integrated area H1 is used to receive a negative power supply voltage that is less than the positive power supply voltage that is received by the shielding portion corresponding to the first transistor in the second high-density integrated area H2.

[0107] In this exemplary embodiment, the low-density integration area L may be a border area of ​​the display panel, an under-screen camera integration area, a light-transmitting area in the display area, etc. The density of transistors in the low-density integration area L may be zero.

[0108] In this exemplary embodiment, the pixel driving circuit in the display panel may also have other structures. FIG. 29 is a schematic diagram of the circuit structure of a pixel driving circuit in another exemplary embodiment of the display panel disclosed herein. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The difference from the pixel driving circuit shown in FIG. 1 is that the first and second transistors in the pixel driving circuit shown in FIG. 29 are N-type transistors.

[0109] As shown in Figure 30, this is a timing diagram of each node in a driving method for the pixel driving circuit in Figure 29. G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a first reset phase t1, a compensation phase t2, a second reset phase t3, and a light-emitting phase t4. In the first reset phase t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. During the compensation phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da outputs a drive signal to write a voltage Vdata+Vth (i.e., the sum of the voltages Vdata and Vth) to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the drive transistor T3. During the second reset phase t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. During the light-emitting phase t4, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the drive transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth stored in the capacitor C.

[0110] The output current formula of the driving transistor is as follows:

[0111] I=(μWCox / 2L)(Vgs-Vth)2

[0112] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor.

[0113] According to the above formula for the output current of the driving transistor, substituting the gate voltage Vdata + Vth and the source voltage Vdd of the driving transistor in the pixel driving circuit of the present disclosure into the above formula yields: the output current of the driving transistor in the pixel driving circuit of the present disclosure, I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth)². This pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current.

[0114] This exemplary embodiment also provides another display panel, which may include a substrate, a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer stacked in sequence, wherein an insulating layer may be provided between the above layers. As shown in Figures 31-46, Figure 31 is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein, Figure 32 is a structural layout diagram of the blocking layer in Figure 31, Figure 33 is a structural layout diagram of the first active layer in Figure 31, Figure 34 is a structural layout diagram of the first conductive layer in Figure 31, Figure 35 is a structural layout diagram of the second conductive layer in Figure 31, Figure 36 is a structural layout diagram of the second active layer in Figure 31, Figure 37 is a structural layout diagram of the third conductive layer in Figure 31, and Figure 38 is a structural layout diagram of Figure 31. FIG39 is a structural layout of the fourth conductive layer in FIG37 , FIG40 is a structural layout of the blocking layer and the first active layer in FIG31 , FIG41 is a structural layout of the blocking layer, the first active layer, and the first conductive layer in FIG31 , FIG42 is a structural layout of the blocking layer, the first active layer, the first conductive layer, and the second conductive layer in FIG31 , and FIG43 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG31 , Figure 44 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, and third conductive layer in Figure 31 ; Figure 45 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, and fourth conductive layer in Figure 31 ; Figure 46 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, fourth conductive layer, and fifth conductive layer in Figure 31 . The display panel may include multiple pixel drive circuits as shown in Figure 29 . As shown in Figure 46 , the multiple pixel drive circuits may include a first pixel drive circuit P1 and a second pixel drive circuit P2 adjacently arranged in the row direction X. The first pixel drive circuit P1 and the second pixel drive circuit P2 may be arranged in mirror symmetry. The first pixel drive circuit P1 and the second pixel drive circuit P2 may form a repeating unit, and the display panel may include multiple repeating units arranged in an array in the row direction X and the column direction Y.

[0115] As shown in Figures 31, 32, and 40, the shielding layer may include a positive pressure shielding part BSM1 and a negative pressure shielding part BSM2. The positive pressure shielding part BSM1 is used to receive a positive power supply voltage, and the negative pressure shielding part BSM2 is used to receive a negative power supply voltage. The positive pressure shielding part BSM1 and the negative pressure shielding part BSM2 on the substrate may both extend along the column direction Y. The negative pressure shielding parts BSM2 adjacent to each other in the row direction X may be connected to each other or independently provided. The positive pressure shielding parts BSM1 adjacent to each other in the row direction X may be connected to each other or independently provided. The shielding layer may be a conductor structure, for example, the shielding layer may be a molybdenum layer.

[0116] As shown in Figures 31, 33, 40, and 41, the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, and an eleventh active portion 711. The third active portion 73 may be used to form a channel region of the driving transistor T3; the fourth active portion 74 may be used to form a channel region of the fourth transistor T4; the fifth active portion 75 may be used to form a channel region of the fifth transistor T5; the sixth active portion 76 may be used to form a channel region of the sixth transistor T6; and the seventh active portion 77 may be used to form a channel region of the seventh transistor T7. The eighth active portion 78 is connected to a side of the fifth active portion 75 away from the third active portion 73. The ninth active portion 79 is connected between the eighth active portion 78 in the first pixel driving circuit P1 and the eighth active portion 78 in the second pixel driving circuit P2. The tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, and the eleventh active portion 711 is connected between the sixth active portion 76 and the third active portion 73. The eighth active portion 78 can be used to form the first electrode of the fifth transistor. In this exemplary embodiment, the eighth active portions of two adjacent pixel driving circuits are connected via the ninth active portion 79, thereby reducing the voltage difference between the first power supply terminals in the adjacent pixel driving circuits. As shown in FIG40 , the orthographic projection of the positive pressure shielding portion BSM1 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73, the orthographic projection of the fourth active portion 74, the orthographic projection of the fifth active portion 75, and the orthographic projection of the seventh active portion 77. For example, the orthographic projection of the positive pressure shielding portion BSM1 on the substrate can cover the orthographic projection of the third active portion 73, the orthographic projection of the fourth active portion 74, the orthographic projection of the fifth active portion 75, and the orthographic projection of the seventh active portion 77. The first active layer can be formed of polycrystalline silicon material, and accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon thin film transistors.

[0117] As shown in Figures 31, 34, and 41, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal shown in Figure 29; the enable signal line EM can be used to provide the enable signal terminal shown in Figure 29; and the second reset signal line Re2 can be used to provide the second reset signal terminal shown in Figure 29. The orthographic projections of the second gate line G2, the enable signal line EM, and the second reset signal line Re2 on the substrate can all extend along the row direction X. The orthographic projection of the second gate line G2 on the substrate overlaps the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate, and a portion of the enable signal line EM is used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active portion 77 on the base substrate, and a portion of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the first conductive portion 11 on the base substrate covers the orthographic projection of the third active portion 73 on the base substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor. As shown in Figure 41, the second gate line G2 in the pixel driving circuit of this row can be reused as the second reset signal line Re2 in the pixel driving circuit of the previous row. This setting can improve the integration of the pixel driving circuit and reduce the layout area of ​​the pixel driving circuit. In addition, the display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0118] As shown in Figures 31, 35, and 42, the second conductive layer may include: a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G1, and a plurality of second conductive portions 22. The first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 29, the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 29, and the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 29. The orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the third reset signal line 2Re1 on the base substrate, and the orthographic projection of the third gate line 2G1 on the base substrate can all extend along the row direction X. As shown in Figure 35, the second conductive layer may further include a plurality of third connecting portions 23. In the same repeating unit, the third connecting portion 23 is connected between two second conductive portions 22 adjacent in the row direction. In addition, in other exemplary embodiments, in adjacent repeating units in the row direction, adjacent second conductive portions 22 may also be connected.

[0119] As shown in Figures 31, 36, and 43, the second active layer may include an active portion 81, which may include a first active portion 811, a second active portion 812, and a twelfth active portion 813 connected to each other. The first active portion 811 may be used to form the channel region of the first transistor; the second active portion 812 may be used to form the channel region of the second transistor T2; and the twelfth active portion 813 is connected to an end of the second active portion 812 away from the first active portion 811. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 on the substrate may overlap the orthographic projection of the second active portion 812 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor. The orthographic projection of the third reset signal line 2Re1 on the substrate can overlap the orthographic projection of the first active portion 811 on the substrate. Part of the structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1. The orthographic projection of the negative voltage blocking portion BSM2 on the substrate can overlap the orthographic projection of the first active portion 811 and the orthographic projection of the second active portion 812 on the substrate. For example, the orthographic projection of the negative voltage blocking portion BSM2 on the substrate can overlap the orthographic projection of the first active portion 811 and the orthographic projection of the second active portion 812 on the substrate.

[0120] As shown in Figures 31, 37, and 44, the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1. The orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the first gate line 3G1 on the base substrate may both extend along the row direction X. The first reset signal line 3Re1 may be used to provide the first reset signal terminal shown in Figure 29. The orthographic projection of the first reset signal line 3Re1 on the base substrate may cover the orthographic projection of the first active portion 811 on the base substrate. Part of the structure of the first reset signal line 3Re1 may be used to form the top gate of the first transistor T1. At the same time, the first reset signal line 3Re1 may be connected to the third reset signal line 2Re1 through a via located in the edge routing area of ​​the display panel. The first gate line 3G1 can be used to provide the first gate drive signal terminal shown in Figure 29. The orthographic projection of the first gate line 3G1 on the substrate can cover the orthographic projection of the second active portion 812 on the substrate. Part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the edge routing area of ​​the display panel. As shown in Figures 31 and 44, in the same pixel drive circuit, the orthographic projection of the first conductive portion 11 on the substrate can be located between the orthographic projection of the first gate line 3G1 on the substrate and the orthographic projection of the enable signal line EM on the substrate; the orthographic projection of the first reset signal line 3Re1 on the substrate can be located on the side of the orthographic projection of the first gate line 3G1 on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The orthographic projection of the second gate line G2 on the substrate can be located between the orthographic projection of the first gate line 3G1 on the substrate and the orthographic projection of the first reset signal line 3Re1 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate can be located on a side of the orthographic projection of the enable signal line EM on the substrate that is away from the orthographic projection of the first conductive portion 11 on the substrate. Furthermore, the display panel can use the third conductive layer as a mask to perform a conductorization process on the second active layer, i.e., the region of the second active layer covered by the third conductive layer can form a channel region of the transistor, and the region of the second active layer not covered by the third conductive layer forms a conductor structure.

[0121] As shown in Figures 31, 38, and 45, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, and a second initial signal line Vinit2. Among them, the first bridge portion 41 can be connected to the third connection portion 23 through two vias H, and connected to the ninth active portion 79 through a via to connect the first pole of the fifth transistor and the second electrode of the capacitor C. It should be noted that the black squares in this exemplary embodiment represent the positions of the vias, and this exemplary embodiment only marks some of the vias. The first bridge portion 41 can be mirror-symmetrical with the mirror symmetry plane of the first pixel driving circuit P1 and the second pixel driving circuit P2. The second bridge portion 42 can be connected to the tenth active portion 710 through a via to connect the second pole of the sixth transistor T6 and the first pole of the seventh transistor T7. The third bridge portion 43 can be connected to the eleventh active portion 711 and the twelfth active portion 813 through vias, respectively, to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the second electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the second active layer and the first conductive portion 11 between the first active portion 811 and the second active portion 812 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor. As shown in Figure 35, an opening 221 is formed on the second conductive portion 22. The orthographic projection of the via connecting between the first conductive portion 11 and the fourth bridge portion 44 on the substrate is located within the orthographic projection of the opening 221 on the substrate, so that the conductive structure in the via is insulated from the second conductive portion 22. The fifth bridge portion 45 can be connected to the second active layer on the side of the first active portion 811 away from the second active portion 812 and the first initial signal line Vinit1 through vias, respectively, to connect the second electrode of the first transistor and the first initial signal terminal. In two adjacent repeating units in the row direction, two adjacent pixel driving circuits can share the same fifth bridge portion 45. The sixth bridge portion 46 can be connected to the first active layer of the fourth active portion 74 on the side away from the third active portion 73 through a via hole to connect to the first electrode of the fourth transistor. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 29. The second initial signal line Vinit2 can be connected to the first active layer of the seventh active portion 77 on the side away from the sixth active portion 76 through a via hole to connect to the second electrode and the second initial signal terminal of the seventh transistor.

[0122] As shown in Figures 31, 39, and 46, the fifth conductive layer may include multiple power lines VDD, multiple data lines Da, and a seventh bridge portion 57. The orthographic projections of the power line VDD and the data line Da on the substrate may both extend along the column direction Y. The power line VDD may be used to provide the first power supply terminal shown in Figure 29, and the data line Da may be used to provide the data signal terminal shown in Figure 29. As shown in Figure 31, a power line may be provided for each column of pixel driving circuits. The power line VDD in the first pixel driving circuit P1 may be connected to the first bridge portion 41 via a via, and the power line VDD in the second pixel driving circuit P2 may be connected to the same first bridge portion 41 via a via, thereby connecting the first electrode of the fifth transistor to the first power supply terminal. The data line Da may be connected to the sixth bridge portion 46 via a via to connect the first electrode of the fourth transistor to the data signal terminal. The seventh bridge portion 57 may be connected to the second bridge portion 42 via a via to connect the first electrode of the seventh transistor. As shown in FIG39 , the power line VDD may include a first extension portion VDD1, a second extension portion VDD2, and a third extension portion VDD3. The second extension portion VDD2 is connected between the first extension portion VDD1 and the third extension portion VDD3. The orthogonal projection of the second extension portion VDD2 on the substrate in the row direction X may be larger than the orthogonal projection of the first extension portion VDD1 on the substrate in the row direction X, and the orthogonal projection of the second extension portion VDD2 on the substrate in the row direction X may be larger than the orthogonal projection of the third extension portion VDD3 on the substrate in the row direction X. The orthogonal projection of the second extension portion VDD2 on the substrate may cover the orthogonal projections of the first active portion 811 and the second active portion 812 on the substrate. The second extension portion VDD2 can reduce the impact of light on the characteristics of the first transistor T1 and the second transistor T2. In two adjacent repeating units in the row direction, the second extension portions VDD2 in two adjacent pixel driving circuits can be connected to each other, so that the power line VDD and the second conductive portion 22 can form a grid structure. The power line of the grid structure can reduce the voltage drop of the power signal thereon.

[0123] As shown in FIG31 , the electrode layer may include a plurality of electrode portions, and the plurality of electrode portions include: a plurality of R electrode portions R, a plurality of G electrode portions G, and a plurality of B electrode portions B.

[0124] As shown in FIG47 , which is a partial cross-sectional view along dotted line BB in FIG31 , the display panel may include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a first planar layer 97, and a second planar layer 98. Specifically, the base substrate 90, the light shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the first planar layer 97, the fifth conductive layer, the second planar layer 98, and the electrode layer are stacked in sequence. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be a single-layer structure or a multi-layer structure. The material of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 96 can be a silicon nitride layer. The materials of the first planarizing layer 97 and the second planarizing layer 98 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer. The fourth conductive layer and the fifth conductive layer may include metal materials, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a stack, or a titanium / aluminum / titanium stack.

[0125] As shown in Figure 48, it is another exemplary structural diagram of the display panel of the present disclosure. The display panel may include a display area AA and a frame area B located around the display area. The above-mentioned shielding portion may also be provided in the frame area B. For example, the frame area B may include a first frame area B1 for integrating a gate drive circuit and a fan-out area B2 for fanning out a data line. The shielding portion located in the first frame area B1 can form a signal line or device structure in the gate drive circuit, and the shielding portion located in the fan-out area B2 can be used to form a fan-out line of the data line. In addition, the shielding portion located in the frame area B can be used to form a signal line or device structure in the detection circuit. This setting can evenly distribute the shielding layer on the substrate, so that problems such as uneven etching and poor control of process parameters will not be caused during the process.

[0126] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0127] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0128] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a transistor, and the display panel further includes: substrate; a first active layer, located on one side of the substrate, wherein at least a portion of the first active layer is used to form a channel region of the transistor; The shielding layer is located between the base substrate and the first active layer. The shielding layer is a conductive layer. The shielding layer includes a plurality of independently arranged shielding parts. At least some of the different shielding parts are used to receive different signals.

2. The display panel according to claim 1, wherein: The pixel driving circuit includes a driving transistor and a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor; The plurality of shielding portions include the first initial signal line.

3. The display panel according to claim 2, wherein: The first active layer includes a first active portion and a third sub-active portion, the first active portion is used to form a channel region of the first transistor, the first active portion includes a first sub-active portion and a second sub-active portion, and the third sub-active portion is connected between the first sub-active portion and the second sub-active portion; The first initial signal line includes a first extending portion, and an orthographic projection of the first extending portion on the base substrate at least partially overlaps with an orthographic projection of the third sub-active portion on the base substrate.

4. The display panel according to claim 2, wherein: The display panel further includes: a first conductive layer located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first reset signal line, an orthographic projection of the first reset signal line on the base substrate extending along a first direction and covering an orthographic projection of the first active portion on the base substrate, and a portion of the first reset signal line forming a gate of the first transistor; The first initial signal line includes a second extending portion, and an orthographic projection of the second extending portion on the base substrate at least partially overlaps with an orthographic projection of the first reset signal line on the base substrate.

5. The display panel according to claim 2, wherein: The display panel further includes: a fourth conductive layer, located on a side of the first active layer facing away from the base substrate, the fourth conductive layer comprising a first initial connection line; The orthographic projection of the first initial signal line on the base substrate extends along a first direction, the orthographic projection of the first initial connection line on the base substrate extends along a second direction, the first direction and the second direction intersect, and the first initial connection line is connected to the first initial signal line intersecting with its orthographic projection on the base substrate through a via. The display panel according to claim 1 , wherein: The display panel further includes a light-emitting unit, the pixel driving circuit includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light-emitting unit; The plurality of shielding portions include the second initial signal line.

7. The display panel according to claim 6, wherein: The pixel driving circuit further includes a driving transistor and a sixth transistor, wherein a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light emitting unit; The first active layer includes a sixth active portion and a seventh active portion, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor; The display panel further includes: a first conductive layer, the first conductive layer being located on a side of the first active layer facing away from the base substrate, the first conductive layer including: an enable signal line, an orthographic projection of the enable signal line on the base substrate extending along a first direction and covering an orthographic projection of the sixth active portion on the base substrate, wherein a portion of the structure of the enable signal line is used to form a gate of the sixth transistor; a second reset signal line, an orthographic projection of the second reset signal line on the base substrate extending along a first direction and covering an orthographic projection of the seventh active portion on the base substrate, and a portion of the second reset signal line forming a gate of the seventh transistor; The orthographic projection of the second initial signal line on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate.

8. The display panel according to claim 6, wherein: The display panel further includes: a fourth conductive layer, located on a side of the first active layer facing away from the base substrate, the fourth conductive layer comprising a second initial connection line; The orthographic projection of the second initial signal line on the base substrate extends along a first direction, the orthographic projection of the second initial connection line on the base substrate extends along a second direction, the first direction and the second direction intersect, and the second initial connection line is connected to the second initial signal line intersecting with its orthographic projection on the base substrate through a via.

9. The display panel according to claim 1, wherein: The pixel driving circuit includes a driving transistor, the first active layer includes a third active portion, and the third active portion is used to form a channel region of the driving transistor; The plurality of shielding parts include a first shielding part, the first shielding part is connected to a stable voltage source, and the orthographic projection of the first shielding part on the base substrate covers the orthographic projection of the third active part on the base substrate.

10. The display panel according to claim 9, wherein: The pixel driving circuit further comprises a capacitor, wherein a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to a power line; The display panel further includes: a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form a gate of the driving transistor and a first electrode of the capacitor; The power line forms the stable voltage source, and the first shielding portion is used to form the second electrode of the capacitor.

11. The display panel according to claim 10, wherein: The display panel further includes: a fourth conductive layer, located on a side of the first conductive layer away from the base substrate, the fourth conductive layer comprising the power line, an orthographic projection of the power line on the base substrate extending along the second direction; The display panel includes a plurality of pixel driving circuits arrayed in a first direction and a second direction, the first direction and the second direction intersect, a plurality of first shielding portions distributed in the first direction are connected, and the power line is connected to the first shielding portion through a via.

12. The display panel according to claim 11, wherein: The power line includes a third extension portion, a fourth extension portion, and a fifth extension portion connected between the third extension portion and the fourth extension portion, wherein a size of an orthographic projection of the fifth extension portion on the substrate in the first direction is larger than a size of an orthographic projection of the third extension portion on the substrate in the first direction, and a size of an orthographic projection of the fifth extension portion on the substrate in the first direction is larger than a size of an orthographic projection of the fourth extension portion on the substrate in the first direction, and the first direction and the second direction intersect; The orthographic projection of the fifth extension portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and at least a portion of the structure of the fifth extension portion is used to form a second electrode of the capacitor.

13. The display panel according to claim 9, wherein: The pixel driving circuit further includes a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; The first active layer further includes a second active portion and a sixth sub-active portion, the second active portion is used to form a channel region of the second transistor, the second active portion includes a fourth sub-active portion and a fifth sub-active portion, and the sixth sub-active portion is connected between the fourth sub-active portion and the fifth sub-active portion; The blocking layer also includes a second blocking portion, the second blocking portion is connected to the first blocking portion, the first blocking portion includes a first edge, the second blocking portion includes a second edge, the first edge and the second edge are connected, and the angle between the orthographic projection of the first edge on the base substrate and the orthographic projection of the second edge on the base substrate is less than 180°, and the orthographic projection of the second blocking portion on the base substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion on the base substrate.

14. The display panel according to claim 9, wherein: The pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to the first initial signal line, and a second electrode is connected to the gate of the driving transistor; a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode is connected to the second electrode of the driving transistor; The first active layer further includes a first active portion, a second active portion, and an eighth active portion, wherein the first active portion is used to form a channel region of the first transistor, the second active portion is used to form a channel region of the second transistor, and the eighth active portion is connected between the first active portion and the second active portion; The blocking layer also includes a third blocking portion, the third blocking portion is connected to the first blocking portion, the first blocking portion includes a first edge, the third blocking portion includes a third edge, the first edge and the third edge are connected, and the angle between the orthographic projection of the first edge on the base substrate and the orthographic projection of the third edge on the base substrate is less than 180°, and the orthographic projection of the third blocking portion on the base substrate at least partially overlaps with the orthographic projection of the eighth active portion on the base substrate.

15. The display panel according to claim 9, wherein: The pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to the first initial signal line, and a second electrode is connected to the gate of the driving transistor; a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode is connected to the second electrode of the driving transistor; The first active layer further includes a first active portion, a second active portion, a sixth sub-active portion, and an eighth active portion, wherein the first active portion is used to form a channel region of the first transistor, the second active portion is used to form a channel region of the second transistor, the second active portion includes a fourth sub-active portion and a fifth sub-active portion, the sixth sub-active portion is connected between the fourth sub-active portion and the fifth sub-active portion, and the eighth active portion is connected between the first active portion and the second active portion; The display panel further includes a first conductive layer, the first conductive layer being located on a side of the first active layer facing away from the base substrate, the first conductive layer including a first conductive portion and a first gate line, the orthographic projection of the first conductive portion on the base substrate covering the orthographic projection of the third active portion on the base substrate, and the orthographic projection of the first gate line on the base substrate extending along a first direction and covering the orthographic projection of the second active portion on the base substrate; The shielding layer further includes a second shielding portion, a third shielding portion, and a first connecting portion, wherein the second shielding portion is connected to the first shielding portion, and an orthographic projection of the second shielding portion on the base substrate at least partially overlaps with an orthographic projection of the sixth sub-active portion on the base substrate; The third blocking portion is connected to the first blocking portion, and an orthographic projection of the third blocking portion on the base substrate at least partially overlaps with an orthographic projection of the eighth active portion on the base substrate; The first connecting portion is connected between the second blocking portion and the third blocking portion in the adjacent pixel driving circuits in the first direction, and the orthographic projection of the first connecting portion on the base substrate is located on a side where the orthographic projection of the first gate line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate.

16. The display panel according to claim 1, wherein The display panel further includes a display area and a frame area located around the display area. Part of the shielding portion is located in the display area, and part of the shielding portion is located in the frame area.

17. The display panel according to claim 1, wherein: The pixel driving circuit includes a plurality of transistors, the plurality of shielding portions include a constant voltage shielding portion corresponding to the transistor, and an orthographic projection of the constant voltage shielding portion on the substrate at least partially overlaps with an orthographic projection of a channel region of the corresponding transistor on the substrate; At least some of the different constant voltage blocking parts are used to receive different power supply voltages.

18. The display panel according to claim 17, wherein: The pixel driving circuit includes an N-type transistor and a P-type transistor; The plurality of constant voltage shielding parts include a positive pressure shielding part and a negative pressure shielding part, the positive pressure shielding part is used to receive a positive power supply voltage, and the negative pressure shielding part is used to receive a negative power supply voltage; The positive pressure shielding portion has an orthographic projection on the substrate that at least partially overlaps with the orthographic projection of the P-type transistor channel region on the substrate, and the negative pressure shielding portion has an orthographic projection on the substrate that at least partially overlaps with the orthographic projection of the N-type transistor channel region on the substrate.

19. The display panel according to claim 17, wherein: The display panel further includes a light-emitting unit, and the pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors; A first electrode of the fourth transistor is connected to the data line, and a second electrode is connected to the first electrode of the driving transistor; The first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode is connected to the first electrode of the driving transistor; The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting unit; A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit; The plurality of constant pressure shielding parts include a plurality of positive pressure shielding parts, and the plurality of positive pressure shielding parts include: a first positive pressure shielding portion, wherein an orthographic projection of the first positive pressure shielding portion on the base substrate covers an orthographic projection of the driving transistor channel region on the base substrate; a second positive pressure shielding portion, wherein the orthographic projection of the second positive pressure shielding portion on the base substrate covers the orthographic projection of the fifth transistor channel region on the base substrate and the orthographic projection of the sixth transistor channel region on the base substrate; a third positive pressure shielding portion, wherein the orthographic projection of the third positive pressure shielding portion on the base substrate covers the orthographic projection of the fourth transistor channel region on the base substrate and the orthographic projection of the seventh transistor channel region on the base substrate; The positive voltage received by the first positive pressure shielding part is greater than the positive voltage received by the second positive pressure shielding part, and the positive voltage received by the third positive pressure shielding part is greater than the positive voltage received by the first positive pressure shielding part.

20. The display panel according to claim 17, wherein The display panel includes a high-density integration area and a low-density integration area, wherein the density of transistors in the high-density integration area is greater than the density of transistors in the low-density integration area; The high-density integrated region includes a first high-density integrated region and a second high-density integrated region, wherein the second high-density integrated region is located on a side of the first high-density integrated region away from the low-density integrated region; In the constant voltage blocking parts corresponding to the same transistor in the pixel driving circuit, the absolute value of the voltage received by the constant voltage blocking part located in the first high-density integrated area is greater than the absolute value of the voltage received by the constant voltage blocking part located in the second high-density integrated area.

21. A display device, wherein: The display panel comprises the display panel according to any one of claims 1 to 20.