Shift register unit,driving control circuit,display apparatus and driving method

Abstract

Provided in the embodiments of the present disclosure are a shift register unit, a driving control circuit, a display apparatus and a driving method. The shift register unit comprises: an input circuit, which is configured to provide an input signal to a first node in response to a first clock signal; a reset circuit, which is configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit, which is configured to provide the second clock signal to the second node in response to a first control signal; and an output circuit, which is configured to provide a third clock signal to a driving output end in response to a signal of the first node and to provide a second reference signal to the driving output end in response to a signal of the second node, wherein the duration of the active level of the first control signal is longer than the duration of the active level of a signal of the driving output end.

Description

Shift register unit, drive control circuit, display device and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a drive control circuit, a display device, and a driving method. Background Art

[0002] With the rapid development of display technology, display devices are increasingly moving towards high integration and low cost. Among them, GOA (Gate Driver on Array) technology integrates TFT (Thin Film Transistor) drive control circuitry on the array substrate of a display device to drive the display. This drive control circuit typically consists of multiple cascaded shift register units. However, the output of these shift register units is unstable, leading to display anomalies.

[0003] Summary of the Invention

[0004] The shift register unit provided by the embodiment of the present disclosure includes:

[0005] an input circuit configured to provide an input signal to the first node in response to a first clock signal;

[0006] a reset circuit configured to provide the first reference signal to the second node in response to the second clock signal;

[0007] a first control circuit configured to provide the second clock signal to the second node in response to a first control signal;

[0008] an output circuit configured to provide a third clock signal to a driver output terminal in response to a signal at the first node, and to provide a second reference signal to the driver output terminal in response to a signal at the second node;

[0009] The duration of the effective level of the first control signal is longer than the duration of the effective level of the signal at the driving output end.

[0010] In some examples, the duration of the effective level of the first control signal is approximately equal to twice the duration of the effective level of the signal at the driving output terminal.

[0011] In some examples, the first control circuit includes a first transistor;

[0012] A control electrode of the first transistor is configured to receive the first control signal, a first electrode of the first transistor is configured to receive the second clock signal, and a second electrode of the first transistor is coupled to the second node.

[0013] In some examples, the input circuit includes a second transistor;

[0014] A control electrode of the second transistor is configured to receive the first clock signal, a first electrode of the second transistor is configured to receive the input signal, and a second electrode of the second transistor is coupled to the first node.

[0015] In some examples, the input circuit further includes a third transistor; the second electrode of the second transistor is coupled to the first node through the third transistor;

[0016] A control electrode of the third transistor is configured to receive the first clock signal, a first electrode of the third transistor is coupled to the second electrode of the second transistor, and a second electrode of the third transistor is coupled to the first node.

[0017] In some examples, the shift register unit further includes: a first noise reduction circuit;

[0018] The first noise reduction circuit is configured to provide the third clock signal to the first electrode of the third transistor in response to the signal at the driving output terminal.

[0019] In some examples, the first noise reduction circuit includes: a fourth transistor;

[0020] The control electrode of the fourth transistor is coupled to the driving output terminal, the first electrode of the fourth transistor is configured to receive the third clock signal, and the second electrode of the fourth transistor is coupled to the first electrode of the third transistor.

[0021] In some examples, the first control circuit is coupled to a first electrode of the third transistor, and a signal at the first electrode of the third transistor is the first control signal.

[0022] In some examples, the first control circuit is coupled to the first node, and the signal of the first node is the first control signal.

[0023] In some examples, the output circuit includes: a fifth transistor, a sixth transistor, and a first capacitor;

[0024] A control electrode of the fifth transistor is coupled to the first node, a first electrode of the fifth transistor is configured to receive the third clock signal, and a second electrode of the fifth transistor is coupled to the driving output terminal;

[0025] A control electrode of the sixth transistor is coupled to the second node, a first electrode of the sixth transistor is configured to receive the second reference signal, and a second electrode of the sixth transistor is coupled to the driving output terminal;

[0026] A first electrode plate of the first capacitor is coupled to the first node, and a second electrode plate of the first capacitor is coupled to the driving output terminal.

[0027] In some examples, the output circuit further includes: a second capacitor;

[0028] A first electrode plate of the second capacitor is coupled to the second node, and a second electrode plate of the second capacitor is configured to receive the second reference signal.

[0029] In some examples, the shift register unit further includes: a second control circuit;

[0030] The second control circuit is configured to provide the second reference signal to the first node in response to a signal at a second node.

[0031] In some examples, the second control circuit includes: a seventh transistor;

[0032] A control electrode of the seventh transistor is coupled to the second node, a first electrode of the seventh transistor is configured to receive the second reference signal, and a second electrode of the seventh transistor is coupled to the first node.

[0033] In some examples, the second control circuit further includes: an eighth transistor; the second electrode of the seventh transistor is coupled to the first node through the eighth transistor;

[0034] The control electrode of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, and the second electrode of the eighth transistor is coupled to the first node.

[0035] In some examples, the shift register unit further includes: a second noise reduction circuit;

[0036] The second noise reduction circuit is configured to provide the first reference signal to the first electrode of the eighth transistor in response to a signal at the first node.

[0037] In some examples, the second noise reduction circuit includes: a ninth transistor;

[0038] A control electrode of the ninth transistor is coupled to the first node, a first electrode of the ninth transistor is configured to receive the first reference signal, and a second electrode of the ninth transistor is coupled to the first electrode of the eighth transistor.

[0039] In some examples, the reset circuit includes a tenth transistor;

[0040] A control electrode of the tenth transistor is configured to receive the second clock signal, a first electrode of the tenth transistor is configured to receive the first reference signal, and a second electrode of the tenth transistor is coupled to the second node.

[0041] The driving control circuit provided by the embodiment of the present disclosure includes a plurality of the above-mentioned shift register units connected in cascade;

[0042] The input signal of the first stage shift register unit is provided by the frame trigger signal terminal;

[0043] In two adjacent stages of shift register units, the input signal of the next stage of shift register unit is provided by the driving output end of the previous stage of shift register unit.

[0044] The display device provided by the embodiment of the present disclosure includes the above-mentioned drive control circuit.

[0045] The driving method for the above-mentioned shift register unit provided in an embodiment of the present disclosure includes:

[0046] In the input stage, the input circuit provides the input signal to the first node in response to the first clock signal; the first control circuit provides the second clock signal to the second node in response to the first control signal; and the output circuit provides the third clock signal to the driving output terminal in response to the signal of the first node;

[0047] In the output stage, the first control circuit provides the second clock signal to the second node in response to the first control signal; the output circuit provides the third clock signal to the driving output terminal in response to the signal of the first node;

[0048] In the reset phase, the reset circuit provides a first reference signal to the second node in response to the second clock signal; and the output circuit provides a second reference signal to the driving output terminal in response to the signal of the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of some structures of a shift register in the related art;

[0050] FIG2 is a timing diagram of some signals of a shift register in the related art;

[0051] FIG3 is a schematic diagram of some structures of a shift register provided by an embodiment of the present disclosure;

[0052] FIG4 is a schematic diagram of another structure of a shift register provided by an embodiment of the present disclosure;

[0053] FIG5 is a timing diagram of some signals of a shift register provided by an embodiment of the present disclosure;

[0054] FIG6 is a flowchart of some driving methods provided by an embodiment of the present disclosure;

[0055] FIG7 is a schematic diagram of some further structures of a shift register provided by an embodiment of the present disclosure;

[0056] FIG8 is a schematic diagram of some further structures of a shift register provided by an embodiment of the present disclosure;

[0057] FIG9 is a schematic diagram of some further structures of a shift register provided by an embodiment of the present disclosure;

[0058] FIG10 is a schematic diagram of some further structures of a shift register provided by an embodiment of the present disclosure;

[0059] FIG11 is a schematic diagram of some further structures of a shift register provided by an embodiment of the present disclosure;

[0060] FIG12a is a schematic diagram of some further structures of a shift register provided by an embodiment of the present disclosure;

[0061] FIG12 b is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0062] FIG13 is another signal timing diagram of the shift register provided by an embodiment of the present disclosure;

[0063] FIG14a is a schematic diagram of some further structures of a shift register provided by an embodiment of the present disclosure;

[0064] FIG14b is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0065] FIG15 is a further signal timing diagram of the shift register provided by an embodiment of the present disclosure;

[0066] FIG16 is a schematic diagram of some structures of the drive control circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0068] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0069] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0070] As shown in Figure 1, the shift register unit may include transistors M01-M010 and capacitors C01-C02. The corresponding signal timing diagram is shown in Figure 2. GCK1-GCK3 represent clock signals, GIP represents an input signal, n01 represents a signal at node N01, n02 represents a signal at node N02, and gso represents a signal driving output terminal GSO.

[0071] During input phase T01, clock signal GCK1 is at a low level, turning on transistors M01 and M02. The low-level input signal GIP is supplied to node N01, turning on transistors M05 and M09. The conductive M09 supplies the low-level signal VGL to node N03. The conductive transistor M05 supplies the high-level clock signal GCK2 to the driver output terminal GSO, causing the output signal GSO to be high and turning off transistor M03. Clock signal GCK3 is at a high level, turning off transistor M010. The input signal GIP is at a low level, turning on transistor M04 and supplying the high-level signal VGH to node N02, turning off transistor M06.

[0072] During output phase T02, clock signal GCK1 is high, and transistors M01 and M02 are turned off. Clock signal GCK3 is high, and transistor M010 is turned off. Input signal GIP is high, and transistor M04 is turned off. Therefore, nodes N01 and N02 are both in a floating state. Capacitor C01 maintains node N01 at a low level, controlling transistors M05 and M09 to conduct. The conducting transistor M05 supplies the low level of clock signal GCK2 to driver output terminal GSO, causing signal GSO outputted from driver output terminal GSO to be low. The bootstrap effect of capacitor C01 further lowers the voltage level at node N01, controlling transistor M05 to conduct as fully as possible, thereby supplying the low level of clock signal GCK2 to driver output terminal GSO, causing signal GSO outputted from driver output terminal GSO to be low and controlling transistor M03 to conduct. The conducting transistor M03 supplies the low level of signal GSO to node N04. The capacitor C02 can maintain the node N02 at a high level, thereby controlling the transistor M06 to be turned off.

[0073] However, in the above-mentioned shift register unit, since the signal received by the gate of transistor M04 is the input signal GIP, transistor M04 can only be turned on in the input phase t01, and cannot be turned on in the remaining phases. Especially in the output phase t02, node N02 does not input a high-level signal, but is maintained by capacitor C02, so that node N02 is high. However, since transistor M010 has leakage current, the high level maintained by node N02 by capacitor C02 will be pulled down (as shown in Figure 2, the portion shown by the solid line in signal n01 is the actual level of node N02 in the t02 phase, and the portion shown by the dotted line is the ideal level of node N02 in the t02 phase). This causes the signal gso output by the driver output terminal GSO to be unstable (as shown in Figure 2, the portion shown by the solid line in signal gso is the actual level of signal gso in the t02 phase, and the portion shown by the dotted line is the ideal level of signal gso in the t02 phase).

[0074] Although the capacitor C02 is provided in the above shift register unit, in actual application, the voltage can only be divided by the capacitor C02. 02 / (c 02 +c gd(M06)+cN02(others)) to maintain the stability of node N02. The greater the voltage division, the more stable node N02. In order to ensure that node N02 is not pulled down, capacitor C02 can be set to be relatively large. However, for example, when the width of the channel region of transistor M06 is 400um and the capacitance value of capacitor C02 is 500fF, node N02 still has a downward jump of about 1V. As shown in Figure 2, in the output stage T02, affected by the output jump, node N02 will jump from 7V to 4.9V. As the capacitance C02 increases, the downward adjustment amplitude of node N02 decreases, but the level of node N02 cannot reach 7V. Therefore, although capacitor C02 is set to be relatively large, it cannot completely keep node N02 from being pulled down, and it will also cause the shift register unit to occupy a relatively large space.

[0075] In order to solve the above problems, the embodiments of the present disclosure provide a shift register unit, which can improve the stability of the node.

[0076] In an embodiment of the present disclosure, as shown in FIG3 , a shift register unit may include an input circuit 10, a reset circuit 20, a first control circuit 30, and an output circuit 40. The input circuit 10 is configured to provide an input signal GIP to a first node N1 in response to a first clock signal CK1. The reset circuit 20 is configured to provide a first reference signal VREF1 to a second node N2 in response to a second clock signal CK2. The first control circuit 30 is configured to provide a second clock signal CK2 to a second node N2 in response to a first control signal CS1. The output circuit 40 is configured to provide a third clock signal CK3 to a driver output terminal GSO in response to a signal at the first node N1, and to provide a second reference signal VREF2 to a driver output terminal GSO in response to a signal at the second node N2. Furthermore, the duration of the active level of the first control signal CS1 is greater than the duration of the active level of the signal at the driver output terminal GSO.

[0077] The shift register unit provided in the embodiments of the present disclosure increases the on-time of the first control circuit by ensuring that the duration of the first control signal's active level is longer than the duration of the signal driving the output terminal's active level. This increases the duration of the second clock signal provided to the second node, thereby stabilizing the level of the second node through the input signal. This eliminates the need for additional large capacitors to achieve level stability at the second node, improving output stability while also reducing footprint.

[0078] In some embodiments of the present disclosure, as shown in FIG4 , the first control circuit 30 includes a first transistor M1 , wherein a control electrode of the first transistor M1 is configured to receive a first control signal CS1 , a first electrode of the first transistor M1 is configured to receive a second clock signal CK2 , and a second electrode of the first transistor M1 is coupled to a second node N2 .

[0079] Exemplarily, the first transistor M1 is turned on under the control of the active level of the first control signal CS1 and is turned off under the control of the inactive level of the first control signal CS1. For example, if the first transistor M1 is a P-type transistor, the active level of the first control signal CS1 is a low level, and the inactive level is a high level. Alternatively, if the first transistor M1 is an N-type transistor, the active level of the first control signal CS1 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the first transistor can be determined according to the actual application requirements and is not limited here.

[0080] In some embodiments of the present disclosure, as shown in FIG4 , the input circuit 10 may include a second transistor M2 , wherein a control electrode of the second transistor M2 is configured to receive a first clock signal CK1 , a first electrode of the second transistor M2 is configured to receive an input signal GIP , and a second electrode of the second transistor M2 is coupled to the first node N1 .

[0081] Exemplarily, the second transistor M2 is turned on when the first clock signal CK1 is at an active level and turned off when the first clock signal CK1 is at an inactive level. For example, if the second transistor M2 is a P-type transistor, the active level of the first clock signal CK1 is a low level, and the inactive level is a high level. Alternatively, if the second transistor M2 is an N-type transistor, the active level of the first clock signal CK1 is a high level, and the inactive level is a low level. In practical applications, the specific implementation of the second transistor can be determined based on actual application requirements and is not limited here.

[0082] In some embodiments of the present disclosure, as shown in FIG4 , the output circuit 40 includes: a fifth transistor M5, a sixth transistor M6, and a first capacitor C1. The control electrode of the fifth transistor M5 is coupled to the first node N1, the first electrode of the fifth transistor M5 is configured to receive the third clock signal CK3, and the second electrode of the fifth transistor M5 is coupled to the driver output terminal GSO. The control electrode of the sixth transistor M6 is coupled to the second node N2, the first electrode of the sixth transistor M6 is configured to receive the second reference signal VREF2, and the second electrode of the sixth transistor M6 is coupled to the driver output terminal GSO. The first electrode plate of the first capacitor C1 is coupled to the first node N1, and the second electrode plate of the first capacitor C1 is coupled to the driver output terminal GSO.

[0083] Exemplarily, the fifth transistor M5 is turned on under the control of the active level of the signal at the first node N1 and is turned off under the control of the inactive level of the signal at the first node N1. For example, if the fifth transistor M5 is a P-type transistor, the active level of the signal at the first node N1 is a low level, and the inactive level is a high level. Alternatively, if the fifth transistor M5 is an N-type transistor, the active level of the signal at the first node N1 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the fifth transistor can be determined according to the needs of the actual application and is not limited here.

[0084] Exemplarily, the sixth transistor M6 is turned on under the control of the active level of the signal at the second node N2, and is turned off under the control of the inactive level of the signal at the second node N2. For example, if the sixth transistor M6 is a P-type transistor, the active level of the signal at the second node N2 is a low level, and the inactive level is a high level. Alternatively, if the sixth transistor M6 is an N-type transistor, the active level of the signal at the second node N2 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the sixth transistor can be determined according to the needs of the actual application and is not limited here.

[0085] In some embodiments of the present disclosure, as shown in FIG4 , the shift register unit further includes a second control circuit 50. The second control circuit 50 is configured to provide a second reference signal VREF2 to the first node N1 in response to a signal at the second node N2. For example, the second control circuit 50 includes a seventh transistor M7. A control electrode of the seventh transistor M7 is coupled to the second node N2, a first electrode of the seventh transistor M7 is configured to receive the second reference signal VREF2, and a second electrode of the seventh transistor M7 is coupled to the first node N1.

[0086] Exemplarily, the seventh transistor M7 is turned on when the active level of the signal at the second node N2 is controlled, and is turned off when the inactive level of the signal at the second node N2 is controlled. For example, if the seventh transistor M7 is a P-type transistor, the active level of the signal at the second node N2 is a low level, and the inactive level is a high level. Alternatively, if the seventh transistor M7 is an N-type transistor, the active level of the signal at the second node N2 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the seventh transistor can be determined based on actual application requirements and is not limited here.

[0087] In some embodiments of the present disclosure, as shown in FIG4 , the reset circuit 20 includes a tenth transistor M10 , wherein a control electrode of the tenth transistor M10 is configured to receive the second clock signal CK2 , a first electrode of the tenth transistor M10 is configured to receive the first reference signal VREF1 , and a second electrode of the tenth transistor M10 is coupled to the second node N2 .

[0088] Exemplarily, the tenth transistor M10 is turned on under the control of the active level of the second clock signal CK2 and is turned off under the control of the inactive level of the second clock signal CK2. For example, if the tenth transistor M10 is a P-type transistor, the active level of the second clock signal CK2 is a low level, and the inactive level is a high level. Alternatively, if the tenth transistor M10 is an N-type transistor, the active level of the second clock signal CK2 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the tenth transistor can be determined according to the needs of the actual application and is not limited here.

[0089] In some embodiments of the present disclosure, the signal timing diagram corresponding to the shift register unit shown in FIG4 may be as shown in FIG5 . In this diagram, GIP represents the input signal, CK1 represents the first clock signal, CK2 represents the second clock signal, CK3 represents the third clock signal, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, gso represents the signal of the driver output terminal GSO, and CS1 represents the first control signal. When the active level is low, the duration ts2 of the low level of the first control signal CS1 is greater than the duration ts1 of the low level of the signal gso of the driver output terminal GSO. For example, the duration ts2 of the low level of the first control signal CS1 may be approximately equal to twice the duration ts1 of the low level of the signal gso of the driver output terminal GSO. Alternatively, when the active level is high, the duration ts2 of the high level of the first control signal CS1 is greater than the duration ts1 of the high level of the signal gso of the driver output terminal GSO. For example, the duration ts2 of the high level of the first control signal CS1 may be approximately equal to twice the duration ts1 of the high level of the signal gso driving the output terminal GSO.

[0090] It should be noted that in actual processes, due to limitations of process conditions or other factors, the above equality relationship may not be completely the same and may have some deviations. Therefore, as long as the above equality relationship roughly meets the above conditions, it falls within the scope of protection of this disclosure. For example, the above equality relationship can be an equality allowed within the allowable error range.

[0091] In a specific implementation, the control electrode of the transistor can be used as the upper electrode. Furthermore, depending on the direction of signal flow, the first electrode of the transistor can be used as its source electrode, and the second electrode can be used as its drain electrode; or the first electrode can be used as its drain electrode, and the second electrode can be used as its source electrode, without making a specific distinction here.

[0092] It should be noted that the transistors mentioned in the above embodiments of the present disclosure may be TFTs or metal oxide semiconductor field effect transistors (MOS), which are not limited here.

[0093] To simplify the manufacturing process, in the specific implementation, in the embodiment of the present disclosure, all transistors can be P-type transistors as shown in Figure 4. Of course, all transistors can also be N-type transistors, which is not limited here.

[0094] The above is merely an example to illustrate the specific structure of the shift register unit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuits is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0095] The embodiment of the present disclosure further provides a driving method for a shift register unit, as shown in FIG6 , which may include the following steps:

[0096] S10, input stage, the input circuit responds to the first clock signal and provides the input signal to the first node; the first control circuit responds to the first control signal and provides the second clock signal to the second node; the output circuit responds to the signal of the first node and provides the third clock signal to the driving output end.

[0097] S20, output stage, the first control circuit provides the second clock signal to the second node in response to the first control signal; the output circuit provides the third clock signal to the driving output terminal in response to the signal of the first node.

[0098] S30, reset stage, the reset circuit provides the first reference signal to the second node in response to the second clock signal; the output circuit provides the second reference signal to the driving output terminal in response to the signal of the second node.

[0099] The driving method provided by the disclosed embodiments increases the on-time of the first control circuit by ensuring that the duration of the first control signal's active level is longer than the duration of the signal at the driver output terminal's active level. This increases the duration of the second clock signal provided to the second node, thereby stabilizing the level of the second node through the input signal. This eliminates the need for additional large capacitors to achieve level stability at the second node. This not only improves output stability but also reduces footprint.

[0100] In some embodiments of the present disclosure, when the shift register unit further includes a second control circuit, during the reset phase, the second control circuit may provide a second reference signal to the first node in response to a signal at the second node.

[0101] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit shown in FIG. 4 as an example and combining it with the signal timing diagram shown in FIG. 5 .

[0102] Specifically, the input phase T1, output phase T2, and reset phase T3 in the signal timing diagram shown in FIG5 are selected. It should be noted that the signal timing diagram shown in FIG5 only represents the operation process of a certain shift register unit within one frame. The operation process of the shift register unit in other frames is basically the same as the operation process in this frame, and will not be described in detail here.

[0103] During input phase T1, the first clock signal CK1 is at a low level, the second transistor M2 is turned on, and the low-level input signal GIP is provided to the first node N1, which controls the fifth transistor M5 to be turned on. The turned-on fifth transistor M5 provides the high-level third clock signal CK3 to the driver output terminal GSO, causing the signal gso output from the driver output terminal GSO to be high. The second clock signal CK2 is at a high level, and the tenth transistor M10 is turned off. The first control signal CS1 is at a low level, turning on the first transistor M1 and providing the high-level second reference signal VREF2 to the second node N2, which controls the sixth transistor M6 and the seventh transistor M7 to be turned off.

[0104] During output phase T2, the first clock signal CK1 is high, and the second transistor M2 is turned off. The second clock signal CK2 is high, and the tenth transistor M10 is turned off. The first control signal CS1 is low, turning on the first transistor M1 and providing the high-level second reference signal VREF2 to the second node N2, turning off the sixth transistor M6 and the seventh transistor M7. Consequently, the first node N1 is in a floating state. The first capacitor C1 maintains the first node N1 at a low level, turning on the fifth transistor M5. The turned-on fifth transistor M5 provides the low-level voltage of the third clock signal CK3 to the driver output terminal GSO, causing the signal gso output from the driver output terminal GSO to be low. The bootstrap effect of the first capacitor C1 further lowers the voltage level of the first node N1, controlling the fifth transistor M5 to be as fully turned on as possible, thereby providing the low-level voltage of the third clock signal CK3 to the driver output terminal GSO, causing the signal gso output from the driver output terminal GSO to be low.

[0105] During the reset phase T3, the first clock signal CK1 is at a high level, and the second transistor M2 is turned off. The first control signal CS1 is at a high level, and the first transistor M1 is turned off. The second clock signal CK2 is at a low level, turning on the tenth transistor M10 and providing the low-level first reference signal VREF1 to the second node N2, thereby controlling the sixth and seventh transistors M6 and M7 to turn on. The turned-on seventh transistor M7 provides the high-level second reference signal VREF2 to the first node N1, controlling the fifth transistor M5 to turn off. The turned-on sixth transistor M6 provides the high-level second reference signal VREF2 to the driver output terminal GSO, causing the signal gso output from the driver output terminal GSO to be high.

[0106] It should be noted that by controlling the first transistor M1 to be conductive during both the input phase T1 and the output phase T2 via the first control signal CS1, a high-level second reference signal VREF2 can be provided to the second node N2 during both phases, preventing the second node N2 from floating during these phases. This allows the second node N2 to be stabilized (e.g., at 7V) during the output phase. Furthermore, since the high-level second reference signal VREF2 is provided to the second node N2 during both the input phase T1 and the output phase T2, a capacitor need not be provided at the control electrode of the sixth transistor M6, further reducing the space occupied by the shift register unit. For example, when no capacitor is provided at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be set to be greater than 50 μm or 100 μm, thereby achieving stable output of the shift register unit.

[0107] The present disclosure provides some other structural diagrams of the shift register unit, as shown in Figure 7, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0108] In some embodiments of the present disclosure, as shown in FIG7 , the output circuit 40 further includes a second capacitor C2. A first electrode plate of the second capacitor C2 is coupled to the second node N2, and a second electrode plate of the second capacitor C2 is configured to receive a second reference signal VREF2. This further stabilizes the voltage level of the second node N2 via the second capacitor C2.

[0109] It should be noted that the signal timing diagram corresponding to the shift register unit shown in Figure 7 can be shown in Figure 5. Moreover, the operation process of the shift register unit shown in Figure 7 combined with the signal timing shown in Figure 5 can refer to the operation process of the above-mentioned shift register unit and will not be repeated here.

[0110] It should be noted that the signal stability of the second node N2 can be further improved by providing the second capacitor C2. In practical applications, the width of the channel region of the sixth transistor M6 can be made less than 400 μm, and the capacitance of the terahertz capacitor can be only 50 fF to 200 fF to ensure stable output of the shift register unit.

[0111] The present disclosure provides further structural diagrams of shift register units, as shown in Figure 8, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0112] In some embodiments of the present disclosure, as shown in FIG8 , the input circuit 10 further includes a third transistor M3 ; the second electrode of the second transistor M2 is coupled to the first node N1 via the third transistor M3 . The control electrode of the third transistor M3 is configured to receive the first clock signal CK1 , the first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2 , and the second electrode of the third transistor M3 is coupled to the first node N1 .

[0113] Exemplarily, the third transistor M3 is turned on under the control of the active level of the first clock signal CK1 and is turned off under the control of the inactive level of the first clock signal CK1. For example, if the third transistor M3 is a P-type transistor, the active level of the first clock signal CK1 is a low level, and the inactive level is a high level. Alternatively, if the third transistor M3 is an N-type transistor, the active level of the first clock signal CK1 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the third transistor can be determined based on the actual application requirements and is not limited here.

[0114] It should be noted that the signal timing diagram corresponding to the shift register unit shown in FIG8 can be shown as FIG5 . Furthermore, the third transistor M3 is turned on by the first clock signal CK1 during the input phase T1, thereby providing the low-level input signal GIP to the first node N1 in conjunction with the turned-on second transistor M2. The third transistor M3 is turned off by the first clock signal CK1 during the output phase T2 and the reset phase T3. Furthermore, the process of performing other operations of the shift register unit shown in FIG8 in conjunction with the signal timing shown in FIG5 can refer to the operating process of the above-mentioned shift register unit and will not be described in detail here.

[0115] It should be noted that, by providing two transistors in the input circuit 10 , the influence of the leakage current of the first node N1 on the signal of the first node N1 can be reduced, thereby improving the signal stability of the first node N1 .

[0116] The present disclosure provides further structural diagrams of shift register units, as shown in Figure 9, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0117] In some embodiments of the present disclosure, as shown in FIG9 , the shift register unit further includes a first noise reduction circuit 60. The first noise reduction circuit 60 is configured to provide a third clock signal CK3 to a first electrode of the third transistor M3 in response to a signal at the drive output terminal GSO. Exemplarily, the first noise reduction circuit 60 includes a fourth transistor M4. A control electrode of the fourth transistor M4 is coupled to the drive output terminal GSO, a first electrode of the fourth transistor M4 is configured to receive the third clock signal CK3, and a second electrode of the fourth transistor M4 is coupled to a first electrode of the third transistor M3.

[0118] Exemplarily, the fourth transistor M4 is turned on under the control of the active level of the signal at the drive output terminal GSO, and is turned off under the control of the inactive level of the signal at the drive output terminal GSO. For example, if the fourth transistor M4 is a P-type transistor, the active level of the signal at the drive output terminal GSO is a low level, and the inactive level is a high level. Alternatively, if the fourth transistor M4 is an N-type transistor, the active level of the signal at the drive output terminal GSO is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the fourth transistor can be determined according to the needs of the actual application and is not limited here.

[0119] In some embodiments of the present disclosure, when the shift register unit further includes a first noise reduction circuit, in the output phase, the first noise reduction circuit may provide a third clock signal to the first electrode of the third transistor in response to a signal at the driving output terminal.

[0120] It should be noted that the signal timing diagram corresponding to the shift register unit shown in FIG9 can be shown as FIG5 . Furthermore, in the output phase T2, the fourth transistor M4 is turned on by the control of the signal gso at the drive output terminal GSO, providing the low level of the third clock signal CK3 to the first electrode of the third transistor M3. In the input phase T1 and the reset phase T3, the fourth transistor M4 is turned off by the control of the signal gso at the drive output terminal GSO. Furthermore, the process of performing other operations of the shift register unit shown in FIG9 in conjunction with the signal timing diagram shown in FIG5 can refer to the operating process of the shift register unit described above and will not be described in detail here.

[0121] It should be noted that, by providing the first noise reduction circuit 60, the low level of the third clock signal CK3 can be provided to the first electrode of the third transistor M3 in the output stage, which can further reduce the influence of the leakage current of the first node N1 on the signal of the first node N1 and further improve the signal stability of the first node N1.

[0122] The present disclosure provides further structural diagrams of shift register units, as shown in Figure 10, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0123] In some embodiments of the present disclosure, as shown in FIG10 , the second control circuit 50 may further include: an eighth transistor M8; a second electrode of the seventh transistor M7 coupled to the first node N1 via the eighth transistor M8; a control electrode of the eighth transistor M8 coupled to the second node N2; a first electrode of the eighth transistor M8 coupled to the second electrode of the seventh transistor M7; and a second electrode of the eighth transistor M8 coupled to the first node N1.

[0124] Exemplarily, the eighth transistor M8 is turned on under the control of the active level of the signal at the second node N2, and is turned off under the control of the inactive level of the signal at the second node N2. For example, if the eighth transistor M8 is a P-type transistor, the active level of the signal at the second node N2 is a low level, and the inactive level is a high level. Alternatively, if the eighth transistor M8 is an N-type transistor, the active level of the signal at the second node N2 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the eighth transistor can be determined according to the needs of the actual application and is not limited here.

[0125] It should be noted that the signal timing diagram corresponding to the shift register unit shown in FIG10 can be shown as FIG5 . Furthermore, the eighth transistor M8 is turned on in the reset phase T3 by the voltage level of the second node N2, and in conjunction with the turned-on seventh transistor M7, provides the high-level second reference signal VREF2 to the first node N1. The eighth transistor M8 is turned off in the input phase T1 and the output phase T2 by the voltage level of the second node N2. Furthermore, the other operations performed by the shift register unit shown in FIG10 in conjunction with the signal timing diagram shown in FIG5 can refer to the aforementioned operation process 6 of the shift register unit and are not further described here.

[0126] It should be noted that, by providing the eighth transistor M8 , the influence of the leakage current of the first node N1 on the signal of the first node N1 can be reduced, thereby further improving the signal stability of the first node N1 .

[0127] The present disclosure provides further structural diagrams of shift register units, as shown in Figure 11, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0128] In some embodiments of the present disclosure, as shown in FIG11 , the shift register unit further includes: a second noise reduction circuit 70; wherein the second noise reduction circuit 70 is configured to provide a first reference signal VREF1 to a first electrode of the eighth transistor M8 in response to a signal at the first node N1. Exemplarily, the second noise reduction circuit 70 includes: a ninth transistor M9; wherein a control electrode of the ninth transistor M9 is coupled to the first node N1, a first electrode of the ninth transistor M9 is configured to receive the first reference signal VREF1, and a second electrode of the ninth transistor M9 is coupled to a first electrode of the eighth transistor M8.

[0129] Exemplarily, the ninth transistor M9 is turned on under the control of the active level of the signal at the first node N1, and is turned off under the control of the inactive level of the signal at the first node N1. For example, if the ninth transistor M9 is a P-type transistor, the active level of the signal at the first node N1 is a low level, and the inactive level is a high level. Alternatively, if the ninth transistor M9 is an N-type transistor, the active level of the signal at the first node N1 is a high level, and the inactive level is a low level. In actual applications, the specific implementation of the ninth transistor can be determined according to the needs of the actual application and is not limited here.

[0130] In some embodiments of the present disclosure, when the shift register unit further includes a second noise reduction circuit, during the input phase, the second noise reduction circuit may provide a first reference signal to the first electrode of the eighth transistor in response to the signal at the first node. Furthermore, during the output phase, the second noise reduction circuit may provide the first reference signal to the first electrode of the eighth transistor in response to the signal at the first node.

[0131] It should be noted that the signal timing diagram corresponding to the shift register unit shown in FIG11 can be shown as FIG5 . Furthermore, the ninth transistor M9 is turned on during the input phase T1 and the output phase T2 by the level control of the first node N1, providing the low-level first reference signal VREF1 to the first electrode of the eighth transistor M8. The ninth transistor M9 is turned off during the reset phase T3 by the level control of the first node N1. Furthermore, the process of performing other operations of the shift register unit shown in FIG11 in conjunction with the signal timing diagram shown in FIG5 can refer to the operating process of the shift register unit described above and will not be described in detail here.

[0132] It should be noted that, by providing the ninth transistor M9 , the influence of the leakage current of the first node N1 on the signal of the first node N1 can be further reduced, and the signal stability of the first node N1 can be further improved.

[0133] The present disclosure provides some further structural diagrams of shift register units, as shown in Figure 12a, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0134] In some embodiments of the present disclosure, as shown in FIG12a , the first control circuit 30 is coupled to the first electrode of the third transistor M3 , and the signal at the first electrode of the third transistor M3 is the first control signal CS1 . Specifically, the control electrode of the first transistor M1 is coupled to the first electrode of the third transistor M3 .

[0135] For example, the signal timing diagram corresponding to the shift register unit shown in FIG12a is shown in FIG13. m1 represents the signal at the control electrode of the first transistor M1. Furthermore, the process of performing other operations of the shift register unit shown in FIG12a in conjunction with the signal timing diagram shown in FIG13 can refer to the operating process of the shift register unit described above and will not be described in detail here.

[0136] It should be noted that, through the signal control of the first electrode of the third transistor M3, the first transistor M1 is turned on in both the input stage T1 and the output stage T2, so that the high-level second reference signal VREF2 can be provided to the second node N2 in both stages, avoiding the second node N2 from floating in these two stages, so that the second node N2 can be stabilized in the output stage (for example, it can be stabilized at 7V).

[0137] In some exemplary embodiments, since a high-level second reference signal VREF2 is provided to the second node N2 during both the input phase T1 and the output phase T2, the second capacitor C2 may not be provided, as shown in FIG12b . This can further reduce the space occupied by the shift register unit. For example, when the second capacitor C2 is not provided at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be greater than 50 μm or 100 μm, thereby achieving stable output of the shift register unit.

[0138] The present disclosure provides some further structural diagrams of shift register units, as shown in Figure 14a, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0139] In some embodiments of the present disclosure, as shown in FIG14 a , the first control circuit 30 is coupled to the first node N1 , and the signal of the first node N1 is the first control signal CS1 . Specifically, the control electrode of the first transistor M1 is coupled to the first node N1 .

[0140] For example, the signal timing diagram corresponding to the shift register unit shown in FIG14a is shown in FIG15 . m1 represents the signal at the control electrode of the first transistor M1. Furthermore, the process of performing other operations of the shift register unit shown in FIG14a in conjunction with the signal timing diagram shown in FIG15 can refer to the operating process of the shift register unit described above and will not be described in detail here.

[0141] It should be noted that, by controlling the first transistor M1 to be turned on in both the input stage T1 and the output stage T2 through the signal of the first node N1, a high-level second reference signal VREF2 can be provided to the second node N2 in both stages, thereby preventing the second node N2 from floating in these two stages, thereby making the second node N2 stable in the output stage (for example, stable at 7V).

[0142] In some exemplary embodiments, since a high-level second reference signal VREF2 is provided to the second node N2 during both the input phase T1 and the output phase T2, the second capacitor C2 may not be provided, as shown in FIG14b . This can further reduce the space occupied by the shift register unit. For example, when the second capacitor C2 is not provided at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be greater than 50 μm or 100 μm, thereby achieving stable output of the shift register unit.

[0143] The embodiments of the present disclosure also provide some drive control circuits. As shown in FIG16 , the drive control circuit includes a plurality of cascaded shift register units SR(1), SR(2), SR(3)…SR(N-1), SR(N) (a total of N shift register units). The input signal GIP of the first-stage shift register unit SR(1) is provided by the frame trigger signal terminal STV. Furthermore, in two adjacent stages of shift register units, the input signal GIP of the next-stage shift register unit is provided by the drive output terminal GSO of the previous-stage shift register unit.

[0144] Specifically, the specific structure of each shift register unit in the above-mentioned drive control circuit is the same as the above-mentioned shift register unit in the present disclosure in terms of function and structure, and the repeated parts are not repeated here. The drive control circuit can be configured in a liquid crystal display panel or an electroluminescent display panel, without limitation here.

[0145] Specifically, in the above-mentioned drive control circuit provided by the embodiment of the present disclosure, the first reference signal VREF1 of each shift register unit is provided by the same first DC signal terminal, and the second reference signal VREF2 of each shift register unit is provided by the same second DC signal terminal.

[0146] Specifically, in the above-mentioned drive control circuit provided in the embodiment of the present disclosure, as shown in Figure 16, the first clock signal CK1 of the 3k-2 stage shift register unit, the second clock signal CK2 of the 3k-1 stage shift register unit, and the third clock signal CK3 of the 3k stage shift register unit are all provided by the same clock terminal, namely the first clock terminal ck1. The second clock signal CK2 of the 3k-2 stage shift register unit, the third clock signal CK3 of the 3k-1 stage shift register unit, and the first clock signal CK1 of the 3k stage shift register unit are all provided by the same clock terminal, namely the second clock terminal ck2. The third clock signal CK3 of the 3k-2 stage shift register unit, the first clock signal CK1 of the 3k-1 stage shift register unit, and the second clock signal CK2 of the 3k stage shift register unit are all provided by the same clock terminal, namely the third clock terminal ck3. Wherein, k is a positive integer.

[0147] The present disclosure also provides a display device including the aforementioned drive control circuit. The display device solves problems similar to those solved by the aforementioned drive control circuit. Therefore, the implementation of the display device can refer to the implementation of the aforementioned drive control circuit, and any repetitions will not be repeated here.

[0148] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0149] In a specific implementation, the display device may include multiple pixel units, multiple gate lines, and data lines. Each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. The display device provided in the embodiments of the present disclosure may be an organic light-emitting display device or a liquid crystal display device, without limitation.

[0150] In the embodiment of the present disclosure, a plurality of gate lines are also provided with corresponding drive control circuits; one gate line is coupled to the drive output terminal of a first-stage shift register unit in the drive control circuit. For example, when the display device provided in the embodiment of the present disclosure is a liquid crystal display device, the TFT in the sub-pixel can be coupled to the gate line, and the drive control circuit can be used as a gate drive circuit, and the gate drive circuit is coupled to the gate line and is used to provide a gate scan signal to the TFT in the sub-pixel. It should be noted that the TFT in the sub-pixel can be an N-type transistor or a P-type transistor, which is not limited here.

[0151] In some embodiments of the present disclosure, when the display device provided in the embodiments of the present disclosure is an organic light-emitting display device, the display device further includes a plurality of light-emitting control signal lines; a drive control circuit is provided for each of the plurality of light-emitting control signal lines; and one light-emitting control signal line is coupled to the drive output terminal of a first-stage shift register unit in the drive control circuit. Furthermore, a plurality of gate lines are also provided with a drive control circuit; and one gate line is coupled to the drive output terminal of a first-stage shift register unit in the drive control circuit. For example, in an organic light-emitting display device, a plurality of organic light-emitting diodes and a pixel circuit connected to each organic light-emitting diode are generally provided. A light-emitting control transistor for controlling the light emission of the organic light-emitting diode and a scan control transistor for controlling the input of a data signal are generally provided in the pixel circuit.

[0152] In a specific implementation, the light-emitting control transistor can be coupled to a light-emitting control signal line, and the scan control transistor can be coupled to a gate line. The organic light-emitting display device can include the aforementioned drive control circuit provided by an embodiment of the present disclosure. The drive control circuit can function as a light-emitting drive circuit, coupled to the light-emitting control transistor, and used to provide a light-emitting control signal to the light-emitting control transistor. Alternatively, the drive control circuit can function as a gate drive circuit, coupled to a gate line, and used to provide a gate scan signal to the scan control transistor.

[0153] Of course, the organic light-emitting display device may also include two of the above-mentioned driving control circuits provided in the embodiments of the present disclosure, wherein one of the driving control circuits may serve as a light-emitting driving circuit, coupled to a light-emitting control transistor, and used to provide a light-emitting control signal to the light-emitting control transistor; and the other driving control circuit may serve as a gate driving circuit, coupled to a gate line, and used to provide a gate scanning signal to the scanning control transistor, which is not limited here.

[0154] The shift register unit, drive control circuit, display device, and drive method provided by the embodiments of the present disclosure increase the on-time of the first control circuit by ensuring that the duration of the active level of the first control signal is longer than the duration of the active level of the signal at the drive output terminal. This increases the duration of the second clock signal provided to the second node, thereby stabilizing the level of the second node through the input signal. This eliminates the need for additional large capacitors to achieve level stability at the second node, improving output stability while also reducing footprint.

[0155] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0156] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A shift register unit, comprising: An input circuit configured to provide an input signal to a first node in response to a first clock signal; A reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; A first control circuit configured to provide the second clock signal to the second node in response to a first control signal; An output circuit configured to provide a third clock signal to a drive output in response to a signal of the first node, and provide a second reference signal to the drive output in response to a signal of the second node; Wherein, a duration of an active level of the first control signal is greater than a duration of an active level of a signal of the drive output.

2. The shift register unit according to claim 1, wherein The duration of the active level of the first control signal is approximately equal to 2 times the duration of the active level of the signal of the drive output.

3. The shift register unit according to claim 1 or 2, wherein The first control circuit includes a first transistor; A control electrode of the first transistor is configured to receive the first control signal, a first pole of the first transistor is configured to receive the second clock signal, and a second pole of the first transistor is coupled to the second node.

4. The shift register unit according to any one of claims 1-3, wherein, The input circuit includes a second transistor; A control electrode of the second transistor is configured to receive the first clock signal, a first pole of the second transistor is configured to receive the input signal, and a second pole of the second transistor is coupled to the first node.

5. The shift register unit according to claim 4, wherein The input circuit further includes a third transistor; the second pole of the second transistor is coupled to the first node through the third transistor; A control electrode of the third transistor is configured to receive the first clock signal, a first pole of the third transistor is coupled to the second pole of the second transistor, and a second pole of the third transistor is coupled to the first node.

6. The shift register unit as described in claim 5, wherein, The shift register unit further includes: a first noise reduction circuit; The first noise reduction circuit is configured to provide the third clock signal to the first pole of the third transistor in response to a signal of the drive output.

7. The shift register unit according to claim 6, wherein, The first noise reduction circuit includes: a fourth transistor; A control electrode of the fourth transistor is coupled to the drive output, a first pole of the fourth transistor is configured to receive the third clock signal, and a second pole of the fourth transistor is coupled to the first pole of the third transistor.

8. The shift register unit according to claim 6 or 7, wherein The first control circuit is coupled to the first pole of the third transistor, and the signal of the first pole of the third transistor is the first control signal.

9. The shift register unit according to any one of claims 1-7, wherein, The first control circuit is coupled to the first node, and the signal of the first node is the first control signal.

10. The shift register unit according to any one of claims 1-9, wherein, The output circuit includes: a fifth transistor, a sixth transistor, and a first capacitor; A control electrode of the fifth transistor is coupled to the first node, a first pole of the fifth transistor is configured to receive the third clock signal, and a second pole of the fifth transistor is coupled to the drive output; A control electrode of the sixth transistor is coupled to the second node, a first pole of the sixth transistor is configured to receive the second reference signal, and a second pole of the sixth transistor is coupled to the drive output; The first electrode plate of the first capacitor is coupled to the first node, and the second electrode plate of the first capacitor is coupled to the drive output terminal.

11. The shift register unit according to claim 10, wherein, The output circuit further includes: a second capacitor; The first electrode plate of the second capacitor is coupled to the second node, and the second electrode plate of the second capacitor is configured to receive the second reference signal.

12. The shift register unit according to any one of claims 1-11, wherein, The shift register unit further includes: a second control circuit; The second control circuit is configured to provide the second reference signal to the first node in response to a signal at the second node.

13. The shift register unit according to claim 12, wherein, The second control circuit includes: a seventh transistor; The control electrode of the seventh transistor is coupled to the second node, the first pole of the seventh transistor is configured to receive the second reference signal, and the second pole of the seventh transistor is coupled to the first node.

14. The shift register unit according to claim 13, wherein, The second control circuit further includes: an eighth transistor; the second pole of the seventh transistor is coupled to the first node through the eighth transistor; The control electrode of the eighth transistor is coupled to the second node, the first pole of the eighth transistor is coupled to the second pole of the seventh transistor, and the second pole of the eighth transistor is coupled to the first node.

15. The shift register unit according to claim 14, wherein, The shift register unit further includes: a second noise reduction circuit; The second noise reduction circuit is configured to provide the first reference signal to the first pole of the eighth transistor in response to a signal at the first node.

16. The shift register unit according to claim 15, wherein, The second noise reduction circuit includes: a ninth transistor; The control electrode of the ninth transistor is coupled to the first node, the first pole of the ninth transistor is configured to receive the first reference signal, and the second pole of the ninth transistor is coupled to the first pole of the eighth transistor.

17. The shift register unit according to any one of claims 1-16, wherein, The reset circuit includes a tenth transistor; The control electrode of the tenth transistor is configured to receive the second clock signal, the first pole of the tenth transistor is configured to receive the first reference signal, and the second pole of the tenth transistor is coupled to the second node.

18. A drive control circuit includes a plurality of shift register units cascaded as described in any one of claims 1-17; The input signal of the first-stage shift register unit is provided by a frame trigger signal terminal; In two adjacent stages of shift register units, the input signal of the next-stage shift register unit is provided by the drive output terminal of the previous-stage shift register unit.

19. A display device includes the drive control circuit as described in claim 18.

20. A driving method for a shift register unit as described in any one of claims 1-17, includes: Input stage, the input circuit provides an input signal to the first node in response to a first clock signal; The first control circuit provides a second clock signal to the second node in response to a first control signal; The output circuit provides a third clock signal to the drive output terminal in response to a signal at the first node; Output stage, the first control circuit provides the second clock signal to the second node in response to a first control signal; The output circuit provides a third clock signal to the drive output terminal in response to a signal at the first node; During the reset phase, the reset circuit provides a first reference signal to the second node in response to the second clock signal; The output circuit provides a second reference signal to the drive output in response to the signal of the second node.