Method and circuit for voltage droop response

Abstract

The present techniques relate to a method(s) and circuit(s) for implementing a voltage droop response and discloses a method of responding to a voltage droop in an electronic circuit; the method compr

Description

[0001] The present techniques relate to a method and circuit for implementing a voltage droop response. In particular, the present techniques relate to responding to voltage droop events and voltage recovery events in an information processing system.

[0002] Some computer circuits (e.g. a central processor unit (CPU) or graphics processor unit (GPU)) may experience performance issues. For example, a CPU can generate voltage droops due to large changes in current required from a power delivery network (PDN).

[0003] There is a need for mitigation action to address such performance issues.

[0004] The present techniques relate to addressing or mitigating such performance issues, or improving known mitigation techniques.

[0005] According to a first approach of present techniques, there is provided a method of responding to a voltage droop in an electronic circuit; the method comprising: switching activity, in response to a voltage droop event, from a nominal clock source to a fallback clock source after a predetermined delay in time according to a programmable delay value.

[0006] The method may comprise detecting a voltage droop event.

[0007] Switching activity from the nominal clock source to the fallback clock source may comprise switching a state machine from a nominal state to a fallback state.

[0008] The predetermined delay in time according to the programmable delay value may correspond to a duration between starting a delay counter and the delay counter reaching the programmable delay value. For example, the delay counter may start at zero and count upwards until it reaches the programmable delay value. Alternatively, the predetermined delay in time according to the programmable delay value may correspond to a duration between starting the delay counter at the programmable delay value and the delay counter reaching zero. Accordingly, a predetermined threshold is determined according to the programmable delay value.

[0009] The switching may comprise: switching activity, in response to a voltage droop event, from the nominal clock source to a zero source; starting, in response to switching activity to the zero source, a delay counter; and switching activity, in response to the delay counter reaching a predetermined threshold according to the programmable delay value, from the zero source to the fallback clock source.

[0010] The method may comprise: switching activity, in response to a sign-off violation event, to the zero source.

[0011] Switching to a zero source may comprise pausing activity such that activity does not proceed according to any clock. Switching to a zero source may comprise stopping activity so that no further clock edges propagate once activity is switched to that source. Activity may be switched to a zero source in response to events other than a sign off-violation. For example, in response to a voltage droop event, activity may be switched from the nominal clock source to the zero source before being switched from the zero source to the fallback clock source.

[0012] A sign-off violation event may be a severe voltage droop event, an event for which switching to the fallback clock frequency is not sufficient to ensure correct execution of the circuit function. A sign-off violation may be the result of a rare, deep droop event such as a brown-out from the power-source. Alternatively, when a circuit is operating at a lower bound of an acceptable voltage margin, any droop may trigger a sign-off violation, as any drop in voltage risks causing hold-timing failures as opposed to set-up timing failures which may be addressed by frequency reduction. In response to a sign-off violation event, activity may be stopped, paused or held. Execution of the circuit function may rely on static data retention within the circuit until the sign-off violation event has passed.

[0013] In some embodiments, switching activity to a zero source is triggered by receipt of an asynchronous signal; and is configured to pause activity within one cycle of the nominal clock source.

[0014] The method may comprise: switching activity, in response to a voltage recovery event, from the fallback clock source to the nominal clock source after a predetermined delay in time according to the programmable delay value and a predetermined duration according to a programmable minimum fallback value.

[0015] The method may comprise detecting a voltage recovery event.

[0016] The predetermined duration according to the programmable minimum fallback value may correspond to a duration between starting the minimum fallback duration counter and the minimum fallback duration counter reaching the programmable minimum fallback value. For example, the minimum fallback duration counter may start at zero and count upwards until it reaches the programmable minimum fallback value. Alternatively, the predetermined duration according to the programmable minimum fallback value may correspond to a duration between starting the minimum fallback duration counter at the programmable delay value and the minimum fallback duration counter reaching zero.

[0017] Switching activity, in response to a voltage recovery event, may comprise: starting, in response to a voltage recovery event, a minimum fallback duration counter; switching activity, in response to the minimum fallback duration counter reaching a predetermined threshold according to the programmable minimum fallback value, from the fallback clock source to the zero source; starting, in response to switching activity to the zero source, the delay counter; and switching activity, in response to the delay counter reaching a predetermined threshold according to the programmable delay value, from the zero source to the nominal clock source.

[0018] The method may comprise resetting the minimum fallback duration counter in response to a voltage droop event occurring after the minimum fallback duration counter is started and before the minimum fallback duration counter reaches the predetermined threshold according to the programmable minimum fallback value. For example, the method may comprise resetting the minimum fallback duration counter in response to a voltage droop event occurring after the minimum fallback duration counter is started and before the minimum fallback duration counter reaches programmable minimum fallback value. Alternatively, the method may comprise resetting the minimum fallback duration counter in response to a voltage droop event occurring after the minimum fallback duration counter is started and before the minimum fallback duration counter reaches zero.

[0019] The predetermined duration defined by the programmable minimum fallback value may have a substantially identical duration to the predetermined delay defined by the programmable delay value.

[0020] The predetermined duration defined by the programmable minimum fallback value may have a substantially different duration to the predetermined delay defined by the programmable delay value.

[0021] The predetermined delay defined by the programmable delay value may be zero. . In other words, the predetermined delay may have a duration of zero seconds; no duration, i.e. there may be no delay.

[0022] In a further approach, there is provided an electronic circuit configured to respond to a voltage droop in another electronic circuit; the electronic circuit providing: a nominal clock source; a fallback clock source; and a programmable delay value; wherein, in response to a voltage droop event, the electronic circuit is switched from the nominal clock source to the fallback clock source after a predetermined delay in time according to the programmable delay value. In some embodiments, the electronic circuit configured to respond to a voltage droop is a clock multiplexer circuit. In some embodiments, the electronic circuit experiencing voltage droop is a voltage droop detector circuit. In some embodiments, the electronic circuit comprises a subject circuit upon which an impact of voltage droop is mitigated.

[0023] In a further approach, there is provided an electronic circuit comprising a programmable state machine according to an approach of present techniques, wherein the programmable state machine is configured to be switched, in response to a voltage droop event, from a nominal state to a fallback state.

[0024] In response to a voltage droop event, the state machine may be switched from the nominal state to a zero state; in response to switching the state machine to the zero state, a delay counter may be started; and in response to the delay counter reaching a predetermined threshold according to the programmable delay value, the state machine may be switched from the zero state to the fallback state.

[0025] In response to a sign-off violation event, the state machine may be switched to the zero state.

[0026] In some embodiments, the state machine is switched to the zero state on receipt of an asynchronous signal and within one cycle of the nominal clock source.

[0027] In response to a voltage recovery event, the state machine may be switched from the fallback state to the nominal state after a predetermined delay in time according to the programmable delay value and a predetermined duration according to a programmable minimum fallback value.

[0028] In response to a voltage recovery event, a minimum fallback duration counter may be started; in response to the minimum fallback duration counter reaching a predetermined threshold according to the programmable minimum fallback value, the state machine may be switched from the fallback state to the zero state; in response to switching the state machine to the zero state, the delay counter may be started; and in response to the delay counter reaching a predetermined threshold according to the programmable delay value, the state machine may be switched from the zero state to the nominal state.

[0029] In response to a voltage droop event occurring after the minimum fallback duration counter is started and before the minimum fallback duration counter reaches the predetermined threshold according to the programmable minimum fallback value, the minimum fallback duration counter may be reset.

[0030] The predetermined duration defined by the programmable minimum fallback value may have a substantially identical duration to the predetermined delay defined by the programmable delay value.

[0031] The predetermined duration defined by the programmable minimum fallback value may have a substantially different duration to the predetermined delay defined by the programmable delay value.

[0032] The predetermined delay defined by the programmable delay counter may be zero. In other words, the predetermined delay may have a duration of zero seconds; no duration, i.e. there may be no delay.

[0033] In a further approach, there is provided a method of responding to a voltage droop in an integrated circuit, the method comprising: storing a set of clock parameters in a clock selection state machine, the clock parameters comprising a nominal clock operating at a nominal frequency, a fallback clock operating at a fallback frequency different to the nominal frequency, and a configurable output clock; wherein, when the state machine is in a nominal state, the output clock is configured to output the nominal frequency and, when the state machine is in a fallback state, the output clock is configured to output the fallback frequency; switching, in response to a voltage droop event, the state machine to the fallback state; and switching, in response to a voltage recovery event, the state machine to the nominal state; wherein, when the state machine is switched to the fallback state, the output clock is switched to output zero for a predetermined delay according to a programmable delay value before being switched to the fallback frequency; and wherein, when the state machine is switched to the nominal state, after a predetermined duration according to a programmable minimum fallback value, the output clock is switched to output zero for a predetermined delay according to the programmable delay value before being switched to the nominal frequency.

[0034] In a further approach, there is provided a programmable state machine comprising circuitry configured to respond to a voltage droop in an integrated circuit; the programmable state machine circuitry comprising: a nominal clock operating at a nominal frequency; a fallback clock operating at a fallback frequency different to the nominal frequency; and an output clock; wherein, when the state machine is in a nominal state, the output clock is configured to output the nominal frequency and, when the state machine is in a fallback state, the output clock is configured to output the fallback frequency; wherein, in response to a voltage droop event, the state machine is switched from the nominal state to the fallback state and, in response to a voltage recovery event, the state machine is switched from the fallback state to the nominal state; wherein, when the state machine is switched to the fallback state, the output clock is switched to output zero for a predetermined delay according to a programmable delay value before being switched to the fallback frequency; and wherein, when the state machine is switched to the nominal state, after a predetermined duration according to a programmable minimum fallback value, the output clock is switched to output zero for a predetermined delay according to the programmable delay value before being switched to the nominal frequency.

[0035] In a further approach, there is provided method of programming the programmable state machine according an approach of present techniques, the method comprising: carrying out at least one of testing, measuring, simulating, provisioning or bootstrapping a response of the integrated circuit to a voltage droop event; setting the programmable delay value; carrying out at least one of testing, measuring, simulating, provisioning or bootstrapping a response of the integrated circuit to a voltage recovery event; and setting the programmable minimum fallback value.

[0036] Testing a response of the integrated circuit to a voltage droop event may comprise exposing the programmable state machine to a voltage droop event to determine an appropriate value for the predetermined delay of the programmable delay counter. Testing a response of the integrated circuit to a voltage recovery event may comprise exposing the programmable state machine to a voltage recovery event to determine an appropriate value for the predetermined duration of the programmable minimum fallback duration counter.

[0037] Measuring a response of the integrated circuit to a voltage droop event may comprise exposing the programmable state machine to a voltage droop event and measuring a parameter of the programmable state machine to determine an appropriate value for the predetermined delay of the programmable delay counter. Measuring a response of the integrated circuit to a voltage recovery event may comprise exposing the programmable state machine to a voltage recovery event and measuring a parameter of the programmable state machine to determine an appropriate value for the predetermined duration of the programmable minimum fallback duration counter.

[0038] Simulating a response of the integrated circuit to a voltage droop event may comprise simulating the programmable state machine to determine an appropriate value for the predetermined delay of the programmable delay counter. Simulating a response of the integrated circuit to a voltage recovery event may comprise simulating the programmable state machine to determine an appropriate value for the predetermined duration of the programmable minimum fallback duration counter.

[0039] Provisioning a response of the integrated circuit to a voltage droop event may comprise setting a value for the predetermined delay of the programmable delay counter determined from empirical data without testing the programmable state machine. Provisioning a response of the integrated circuit to a voltage recovery event may comprise setting a value for the predetermined delay of the programmable minimum fallback duration counter determined from empirical data without testing the programmable state machine.

[0040] Bootstrapping a response of the integrated circuit to a voltage droop event may comprise setting a value for the predetermined delay of the programmable delay counter from data received by the programmable state machine from a remote server on start-up or reset. Provisioning a response of the integrated circuit to a voltage recovery event may comprise setting a value for the predetermined delay of the programmable minimum fallback duration counter from data received by the programmable state machine from a remote server on startup or reset.

[0041] In a further approach, there is provided an electronic circuit comprising electronic logic components operable to perform the steps of the method according to an approach of the disclosure.

[0042] In a further approach, there is provided a non-transitory computer readable medium to store computer-readable code for fabrication of a programmable state machine according to an approach of the disclosure.

[0043] In a further approach, there is provided a system comprising: the electronic circuit of an approach of the disclosure implemented in at least one packaged chip; at least one system component; and a board; wherein the at least one packaged chip and the at least one system component are assembled on the board.

[0044] In a further approach, there is provided a chip-containing product comprising the system of an approach of the disclosure assembled on a further board with at least one other product component.

[0045] In a further approach, there is provided a non-transitory computer-readable medium to store computer-readable code for fabrication of the circuitry for detecting a voltage droop event of any one of the preceding approaches of the disclosure.

[0046] Implementations of the disclosed technology will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0047] Figure 1 shows a simple example of a multiplex arrangement operable to implement at least a part of the process of the present technology in hardware;

[0048] Figure 2 shows a waveform for switch to fallback frequency for an output clock with paused transition during a droop event;

[0049] Figure 3 shows a waveform for switch to fallback frequency for an output clock with minimal transition during a droop event;

[0050] Figure 4 shows a waveform for stop and no switch to fallback frequency for an output clock during a droop event;

[0051] Figure 5 shows a waveform for a subsequent droop event being detected during a period of transition;

[0052] Figure 6 shows a waveform for a signoff violation during a droop event;

[0053] Figure 7 shows a flow diagram for switch to fallback frequency for an output clock with paused transition during a droop event;

[0054] Figure 8 shows a flow diagram for switch to fallback frequency for an output clock with minimal transition during a droop event;

[0055] Figure 9 shows a flow diagram for stop and no switch to a fallback frequency for an output clock during a droop event;

[0056] Figure 10 shows a system and a chip-containing product; and

[0057] Figure 11 shows a schematic diagram of a clock multiplexer circuit according to an approach of present techniques.

[0058] Switching activity of synchronous digital circuits on a chip, such as circuits implementing processors, can vary significantly over a small number of clock cycles (typically <10). This may correspond to periods shorter than response times of power supplies and a power distribution network (PDN) to the chip, which may result in transient variations of a supply voltage. Voltage droops are of particular concern, as a reduction in voltage may cause the digital circuit to execute incorrectly (e.g., brown-out). Operating at excess voltage to mitigate such brown-out events during a rare voltage droop is undesirable as it increases a power consumption of the digital circuit.

[0059] The methods described herein refer to reactive droop mitigation schemes with low intervention latency. These techniques rely on dedicated circuitry to protect the operation of a digital circuit, a subject circuit. This includes the detection of one or more types of voltage droop conditions and application of a mitigation response to the synchronous clock that drives the activity of the subject circuit. Present techniques discuss implementing mitigation action in response to a voltage droop in an electronic circuit (e.g., a droop detector circuit), for example, to avoid circuit malfunction.

[0060] Clock management of Central Processing Units (CPU) and Graphics Processing Unit (GPU) shader cores have a direct impact on system performance especially in thermally constrained environments for battery operated devices.

[0061] Modern day CPUs and GPUs generate voltage droops due to large changes in current required from the Power Delivery Network (PDN). This calls for mitigation techniques to minimise voltage margining for lower power and heat generation, whilst minimising the effect on performance. Lowering the clock frequency during a droop event is one mitigation strategy.

[0062] Sustaining performance requires a robust mechanism to compensate for heat generated in this mode. Lowering voltage and clock frequency, is one of the techniques used to manage the thermal budget and extend battery life.

[0063] Power Delivery Network characteristics vary over silicon on chip systems. Accordingly, a standard droop response is not appropriate for every power delivery network implementation. Present techniques provide a way of controlling or programming a droop mitigation response to a droop event, depending on system characteristics. In one example, a user tests the power delivery system and programs an appropriate droop response depending on the Power Delivery Network characteristics.

[0064] Referring to Figure 1, a multiplexer structure operable to implement at least a part of the process of the present technology is shown in hardware. Figure 1 shows a multiplexer 100 such as one module of part of a Clock Control State Machine (CCSM) arrangement operable in an electronic circuit.

[0065] There are several clock domains in a state machine according to present techniques. The output clock goes into two stages of clock mux. The first stage has a pair of clock muxes, which are controlled by clksel_nom and clksel_fb. The output of the first mux is called clk_nominal. This clock has the higher frequency and is typically a high frequency fast clock that goes into any CPU / GPU sub-system. The output of the second mux is called clk_fallback. This clock has the lower frequency and acts as a fallback frequency in case of a droop event. This is the fallback clock that goes into the CPU / GPU sub-system in the case of a droop event. The second stage ofclock mux is between clk_nominal and clk_fallback. This is controlled by clksel. The control switches at the time of a droop event. The output of the mux is called clk_droop_mitigated. Clock domain clk_droop_mitigated is in normal circumstances clk_nominal, and switches to clk_fallback in case of a droop event.

[0066] CLOCK MUX 106 is operable to receive inputs NOM clock 102, representing the nominal source at the current normal voltage and frequency tuning, and FB clock 104, representing the currently available fallback source at the droop mitigation voltage and frequency. CLOCK MUX 106 is controlled by clksel 108 to select the source to be used to provide output clkout 111.

[0067] Droop mitigation state machine 110 outputs clksel 108 in response to a detection of a droop event by droop detector 112 which has input func_clk 114 connected to NOM clock 102. Droop mitigation state machine 110 has output TRIG_DROOP 116 connected to input 118 of droop mitigation state machine 110.

[0068] Figure 1 thus shows an implementation of a glitch-free multiplexer that can have the following droop mitigation strategies for clkout 111 when TRIG_DROOP 116 is output: • Select the NOM clock if clksel[1:0] - 0’b01. The droop event is ignored and the clksel is driven by clk_nominal. • Select the FB clock if clksel[1:0] = 0’b10. The droop event caused clksel to switch to fallback frequency. • Select no clock if clksel[1:0] = O’bOO. In other words, stop the clock propagation.

[0069] Figure 2 shows a waveform for switch to fallback frequency for an output clock with paused transition during a droop event.

[0070] With reference to Figure 2, a number of signals are synchronised with the nominal clock (NOM clock 102 in Figure 1) clk_nominal, and the output clock (clk_droop_mitigated or clkout 111 in Figure 1). The output clock is initially at the nominal frequency. At a high level, when a droop event is detected, the output clock pauses, and then switches to a (lower) fallback frequency for some time. Then, after the droop event, the output clock pauses again, and then switches back to the nominal frequency. The signal clksel controls the multiplexer 100 that controls which of the nominal or fallback clock is selected as the output clock.

[0071] Present techniques provide a first delay / counter A which extends the first pause between the output clock switching from the nominal clock to the fallback clock, for a defined amount of time. The present techniques also provide a second delay / counter B which defines a minimum time for which the output clock will run at the fallback frequency while TRIG_DROOP remains stable at 1 ’b0 before switching back to the nominal clock.

[0072] The output clock is initially at the nominal frequency (clksel = NOMINAL). At time 1), a droop event is detected (TRIG_DROOP high). Shortly after, the output clock is stopped (stopclk_nominal high and clksel = NOCLK). At time 2), the stop signal goes low, which triggers the first delay / counter A. After the delay A, the output clock will run at the fallback frequency whilst TRIG_DROOP is still high (clksel=FALLBACK). At time 3) once the droop event is over (TRIG_DROOP is low), the counter B is triggered. The output clock will continue running at the fallback frequency until the counter B finishes running, even though the droop event is not present. At time 4), the output clock is paused again for the delay A, after which the output clock will continue running at the nominal frequency once again to conclude the droop mitigation, time 5) (clksel=NOMINAL).

[0073] This means that the counter values or delay amounts A and B can be programmed appropriately depending on the PDN characteristics.

[0074] For some PDNs, the pause between switching the output clock from the nominal frequency to the fallback frequency should be minimised. In this case, as shown in Figure 3, the delay A can be set to a minimum (zero) to minimise the pause and provide a direct transition from the nominal clock to the fallback clock (and back to the nominal clock) that is as fast as possible. The clksel goes directly from NOMINAL to FALLBACK in this case.

[0075] As also shown in Figure 3, the counter B will only start counting down once TRIG_DROOP goes low (droop event finishes, voltage recovers). Therefore, in the event that TRIG_DROOP goes low as soon the fallback clock starts running, the fallback clock will still continue for a minimum time set by the counter B. Switching back to the nominal frequency from the fallback frequency may cause the voltage to dip, which may cause another droop event to be detected. The counter B is programmed in this way to ensure that the voltage sufficiently increases following the droop event, to avoid any triggering of another droop event.

[0076] In some scenarios, the output clock should be paused (remain off) for the duration of the droop event before returning to the nominal clock, i.e. the fallback clock is not used. This may be useful when the circuit is in the lowest dynamic voltage and frequency scaling (DVFS) mode, which means a fallback clock cannot be safely used when a droop event is occurring (see submission “Droop mitigation scheme with sign off”).

[0077] As shown in Figure 4, at time 1) when stopclk_nominal goes low, the output clock clk_droop_mitigated will remain off (clksel=NOCLK). At time 2) when TRIG_DROOP is low, the counter B begins counting down as usual. Meanwhile the output clock remains off (clksel=NOCLK). At time 3) after the counter B has finished, the output clock begins running again at the nominal frequency (clksel=NOMINAL). Note that the delay A is not of any significance in this case as the clksel is set to NOCLK.

[0078] Figure 5 shows a case where a TRIG_DROOP is triggered whilst the counter B is already running. As shown, at time 1), the counter B will reset following TRIG_DROOP going high again. Then at time 2), the counter B will begin counting down again once TRIG_DROOP is low.

[0079] Figure 6 shows a scenario where a signoff violation occurs during droop mitigation (i.e. where the voltage drops too low). At time 1) whilst the output clock is running at the fallback frequency to provide droop mitigation, a signoff event occurs (TRIG_SOFF high). In response, the output clock is paused (clksel = NOCLK). Then at time 2) when TRIG_DROOP and TRIG_SOFF are low, the counter B will begin counting down as usual.

[0080] Figure 7 shows a flow diagram for switch to fallback frequency for an output clock with paused transition during a droop event.

[0081] The flow depends on the value of TRANSITION_PAUSE. If the value of TRANSITION_PAUSE is not zero, this means that clk_droop_mitigated is paused for the period specified by TRANSITION_PAUSE in each clock domain transition. That is, transiting from clk_nominal to clk_fallback, and again back from clk_fallback to clk_nominal. This is referred to as “Paused Transition”.

[0082] Figure 8 shows a flow diagram for switch to fallback frequency for an output clock with minimal transition during a droop event. If the value of TRANSITION_PAUSE is set to O’xO, this means transition to clk_fallback with minimum latency of clock mux is configured. This is referred to as “Immediate Transition”. Note that the solid boxes are to be bypassed. They are shown to ease comparison across different mitigation flows.

[0083] Figure 9 shows a flow diagram for stop and no switch to a fallback frequency for an output clock during a droop event.

[0084] Figure 9 describes the clock mitigation flow when the CCSM pauses clk_droop_mitigated during the entire droop event. Note that the solid boxes are to be bypassed. They are shown to ease comparison across different mitigation flows. The clk_droop_mitigated must be stopped as soon as there is a trigger on TRIG_DROOP. This is achieved through an internally generated signal called stopclk_nominal. Since TRIG_DROOP is synchronized with clk_nominal, and the second phase of clock mux is driving clk_nominal, TRIG_DROOP does not need any resynchronization. “stopclk_nominal” is an internal signal that goes from 0’b0-0’b1 as soon as there is a O’bO-O’b1 transition on TRIG_DROOR This is used to stop the clk_droop_mitigated as quickly as possible. Both “stopclk_nominal” and TRIG_DROOP are synchronized with clk_nominal. The stopclk_nominal signal is reset to O’bO when the CCSM has registered the event. The state of the “cur_clksel<1:0>” is used to confirm the same.

[0085] The method and circuit according to the present technology may thus be used in mitigating droop conditions in systems having dynamic voltage and frequency scaling, and that method may be realised in the form of a non-transitory computer readable medium comprising a structure of data and imperatives operable to cause a device to construct a set of electronic logic components which, when embedded in an electronic device and activated thereon, cause the electronic device to perform the steps of the method of the present technology as described hereinabove.

[0086] As will be clear to one of skill in the art, a hybrid approach may also be taken, in which hardware logic, firmware and / or software may be used in any combination to implement the present technology.

[0087] As shown in Figure 10, one or more packaged chips 400, with the circuitry described above implemented on one chip or distributed over two or more of the chips, are manufactured by a semiconductor chip manufacturer. In some examples, the chip product 400 made by the semiconductor chip manufacturer may be provided as a semiconductor package which comprises a protective casing (e.g. made of metal, plastic, glass or ceramic) containing the semiconductor devices implementing the circuitry described above and connectors, such as lands, balls or pins, for connecting the semiconductor devices to an external environment. Where more than one chip 400 is provided, these could be provided as separate integrated circuits (provided as separate packages), or could be packaged by the semiconductor provider into a multi-chip semiconductor package (e.g. using an interposer, or by using three-dimensional integration to provide a multi-layer chip product comprising two or more vertically stacked integrated circuit layers).

[0088] In some examples, a collection of chiplets (i.e. small modular chips with particular functionality) may itself be referred to as a chip. A chiplet may be packaged individually in a semiconductor package and / or together with other chiplets into a multi-chiplet semiconductor package (e.g. using an interposer, or by using three-dimensional integration to provide a multilayer chiplet product comprising two or more vertically stacked integrated circuit layers).

[0089] The one or more packaged chips 400 are assembled on a board 402 together with at least one system component 404 to provide a system 406. For example, the board may comprise a printed circuit board. The board substrate may be made of any of a variety of materials, e.g. plastic, glass, ceramic, or a flexible substrate material such as paper, plastic or textile material. The at least one system component 404 comprise one or more external components which are not part of the one or more packaged chip(s) 400. For example, the at least one system component 404 could include, for example, any one or more of the following: another packaged chip (e.g. provided by a different manufacturer or produced on a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor and / or a sensor.

[0090] A chip-containing product 416 is manufactured comprising the system 406 (including the board 402, the one or more chips 400 and the at least one system component 404) and one or more product components 412. The product components 412 comprise one or more further components which are not part of the system 406. As a non-exhaustive list of examples, the one or more product components 412 could include a user input / output device such as a keypad, touch screen, microphone, loudspeaker, display screen, haptic device, etc.; a wireless communication transmitter / receiver; a sensor; an actuator for actuating mechanical motion; a thermal control device; a further packaged chip; an interface module; a resistor; a capacitor; an inductor; a transformer; a diode; and / or a transistor. The system 406 and one or more product components 412 may be assembled on to a further board 414.

[0091] The board 402 or the further board 414 may be provided on or within a device housing or other structural support (e.g. a frame or blade) to provide a product which can be handled by a user and / or is intended for operational use by a person or company.

[0092] The system 406 or the chip-containing product 416 may be at least one of: an enduser product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automation control system. For example, as a non-exhaustive list of examples, the chip-containing product could be any of the following: a telecommunications device, a mobile phone, a tablet, a laptop, a computer, a server (e.g. a rack server or blade server), an infrastructure device, networking equipment, a vehicle or other automotive product, industrial machinery, consumer device, smart card, credit card, smart glasses, avionics device, robotics device, camera, television, smart television, DVD players, set top box, wearable device, domestic appliance, smart meter, medical device, heating / lighting control device, sensor, and / or a control system for controlling public infrastructure equipment such as smart motorway or traffic lights.

[0093] Figure 11 shows a schematic diagram of a clock multiplexer circuit 1100 according to an approach of present techniques. The clock multiplexer circuit 1100 has five inputs and one output. The inputs to the clock multiplexer circuit 1100 include a nominal clock source 1102 (clk_nominal), a fallback clock source 1104 (clk_fallback), a clock selector input 1106 (clksel[1:0]), a reset input 1108 (reset), and a stop clock input 1110 (stpclk_nominal). The output of the clock multiplexer circuit 1100 is the selected clock, or mitigated clock, 1112 (selected_clk).

[0094] Inside the clock multiplexer circuit 1100, combinational and synchronisation logic blocks 1114 are disposed between the inputs and the outputs of the circuit 1100. The clock multiplexer circuit 1100 is configured to select one of the nominal clock source 1102, the fallback clock source 1104, or no clock source to propagate through the multiplexer to the output. In normal use, when a voltage droop event is not present, the clock selector input 1106 causes the nominal clock input 1102 to be selected so that the nominal clock is output at the selected clock output 1112. In the alternative, during a voltage droop event, the clock selector input 1106 may cause the fallback clock input 1104 to be selected so that the fallback clock is output at the selected clock output 1112.

[0095] For signals from the nominal clock source 1102 or the fallback clock source 1104 to reach the output, the logic blocks 1114 must be traversed. Accordingly, there is some latency, or delay, incurred as the signal is propagated through the multiplexer circuit 1100. In this way, when switching from a first source to a second source, clock edges of the first source may continue to propagate through the multiplexer after the second source has been selected using the clock selector input 1106. For example, when switching activity from the nominal clock source 1102 to the fallback clock source 1104, there may be a delay between the clock selector input changing to 2’b01 and the selected clock 1112 changing to the frequency of the fallback clock source 1104. This is undesirable, for example, when a voltage droop event is triggered, as nominal clock edges may continue to propagate through the multiplexer to the selected clock output 1112 which may cause a subject circuit that receives the selected clock output 1112 to malfunction during a voltage droop event.

[0096] Accordingly, it may be desirable to prevent legacy clock edges propagating through the multiplexer circuit 1100 after the clock selector input 1106 is changed. This may be achieved by temporarily stopping any signals passing to the selected clock output. This may be called stopping, pausing or gating the output clock. In the embodiment of Fig. 11, this is achieved using the stop clock input 1110. As shown in Fig. 11, signals received at the stop clock input 1110 bypass the logic blocks 1114 to arrive directly at an AND gate 1116 which feeds into a clock gate 1118, and final OR gate 1120. In this way, the stop clock input 1110 does not pass through the combinational or synchronisation logic 1114 and therefore is not delayed such logic.

[0097] The signal received at the stop clock input 1110 may act to stop any clock edges propagating to the selected clock output 1112 very rapidly, e.g., within one clock cycle, so that no further rising edges reach the output 1112 and the selected clock is stopped. The signal received at the stop clock input 1110 may be asynchronous. By bypassing the logic blocks 1114, signals from the stop clock input 1110 may switch activity at the selected clock output 1112 to a zero source substantially instantaneously, i.e., within one nominal clock cycle.

[0098] In this way, when a signal is received at the stop clock input 1110, activity is switched to the zero source (i.e., paused). The signal may be an asynchronous signal. Switching activity to the zero source (i.e., pausing the selected clock output 1112) may be triggered by receipt of a signal at the stop clock input 1110. Receipt of such a signal may be configured to pause activity (switch activity to a zero source) within one cycle of the nominal clock source.

[0099] Following receipt of a signal at the stop clock input 1110 and subsequent gating or pausing of the output clock 1112, edges of a selected clock source, e.g., the fallback clock source may propagate through the logic blocks 1114 towards the selected clock output 1112. After a predetermined delay has elapsed, the signal at the stop clock input 1110 may be changed to allow the output clock 1112 to restart. When it restarts, the output clock 1112 may output the fallback clock, as selected by the clock selector input 1106. The same process may be followed when switching from the fallback clock source 1104 to the nominal clock source 1102. In this way, no legacy clock edges are delivered to the subject circuit and circuit malfunction is mitigated. The predetermined delay is configurable according to a delay value. The delay value may be zero. In this case, the output clock may restart immediately after gating by an asynchronous signal at the stop clock input 1110.

[0100] As will be appreciated by one skilled in the art, the present technology may be embodied as a method, a circuit or a computer readable medium comprising data and imperatives to cause construction of a circuit. Accordingly, the present technique may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software, firmware and hardware. Where the word “component” is used, it will be understood by one of ordinary skill in the art to refer to any portion of any of the above embodiments.

[0101] Furthermore, the present technique may take the form of a computer program product tangibly embodied in a non-transitory computer readable medium having computer readable program code embodied thereon. A computer readable medium may be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.

[0102] Concepts described herein may be embodied in computer-readable code for fabrication of an apparatus that embodies the described concepts. For example, the computer-readable code can be used at one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising the apparatus embodying the concepts. The above computer-readable code may additionally or alternatively enable the definition, modelling, simulation, verification and / or testing of an apparatus embodying the concepts described herein.

[0103] For example, the computer-readable code for fabrication of an apparatus embodying the concepts described herein can be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register-transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define a HDL representation of the one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High-Speed Integrated Circuit Hardware Description Language) as well as intermediate representations such as FIRRTL. Computer-readable code may provide definitions embodying the concept using system-level modelling languages such as SystemC and SystemVerilog or other behavioural representations of the concepts that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0104] Additionally or alternatively, the computer-readable code may define a low-level description of integrated circuit components that embody concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. The one or more netlists or other computer-readable representation of integrated circuit components may be generated by applying one or more logic synthesis processes to an RTL representation to generate definitions for use in fabrication of an apparatus embodying the invention. Alternatively or additionally, the one or more logic synthesis processes can generate from the computer-readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purposes of verification and test of the concepts prior to fabrication in an integrated circuit or the FPGA may be deployed in a product directly.

[0105] The computer-readable code may comprise a mix of code representations for fabrication of an apparatus, for example including a mix of one or more of an RTL representation, a netlist representation, or another computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus embodying the invention. Alternatively or additionally, the concept may be defined in a combination of a computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus and computer-readable code defining instructions which are to be executed by the defined apparatus once fabricated.

[0106] Such computer-readable code can be disposed in any known transitory computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductor, magnetic disk, or optical disc. An integrated circuit fabricated using the computer-readable code may comprise components such as one or more of a central processing unit, graphics processing unit, neural processing unit, digital signal processor or other components that individually or collectively embody the concept.

[0107] The program code may execute entirely on the user's computer, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network. Code components may be embodied as procedures, methods or the like, and may comprise sub-components which may take the form of instructions or sequences of instructions at any of the levels of abstraction, from the direct machine instructions of a native instruction-set to high-level compiled or interpreted language constructs.

[0108] It will also be clear to one of skill in the art that all or part of a logical method according to embodiments of the present techniques may suitably be embodied in a logic apparatus comprising logic elements to perform the steps of the method, and that such logic elements may comprise components such as logic gates in, for example a programmable logic array or application-specific integrated circuit. Such a logic arrangement may further be embodied in enabling elements for temporarily or permanently establishing logic structures in such an array or circuit using, for example, a virtual hardware descriptor language, which may be stored using fixed carrier media.

[0109] In one alternative, an embodiment of the present techniques may be realized in the form of a computer implemented method of deploying a service comprising steps of deploying computer program code operable to, when deployed into a computer infrastructure or network and executed thereon, cause the computer system or network to perform all the steps of the method.

[0110] Ina further alternative, an embodiment of the present technique may be realized in the form of a data carrier having functional data thereon, the functional data comprising functional computer data structures to, when loaded into a computer system or network and operated upon thereby, enable the computer system to perform all the steps of the method.

[0111] In the present application, the words “configured to...” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a “configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation.

[0112] In the present application, lists of features preceded with the phrase “at least one of’ mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of: [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in combination (without C), Aand C in combination (without B), B and C in combination (without A), or A, B and C in combination.

[0113] Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that many improvements and modifications can be made to the foregoing exemplary embodiments without departing from the scope of the present disclosure.

Claims

1. A method of responding to a voltage droop in an electronic circuit; the method comprising:switching activity, in response to a voltage droop event, from a nominal clock source to a fallback clock source after a predetermined delay in time according to a programmable delay value.

2. A method according to claim 1, wherein switching activity from the nominal clock source to the fallback clock source comprises switching a state machine from a nominal state to a fallback state.

3. A method according to claim 1 or claim 2, wherein switching activity from the nominal clock source to the fallback clock source comprises:switching activity, in response to a voltage droop event, from the nominal clock source to a zero source;starting, in response to switching activity to the zero source, a delay counter; andswitching activity, in response to the delay counter reaching a predetermined threshold according to the programmable delay value, from the zero source to the fallback clock source.

4. A method according to any preceding claim, further comprising: switching activity, in response to a sign-off violation event, to the zero source.

5. A method according to claim 3 or claim 4, wherein switching activity to a zero source is triggered by receipt of an asynchronous signal; and is configured to pause activity within one cycle of the nominal clock source.

6. A method according to any preceding claim, further comprising:switching activity, in response to a voltage recovery event, from the fallback clock source to the nominal clock source after a predetermined delay in time according to the programmable delay value and a predetermined duration according to a programmable minimum fallback value.

7. A method according to claim 6, wherein switching activity, in response to a voltage recovery event, comprises:starting, in response to a voltage recovery event, a minimum fallback duration counter;switching activity, in response to the minimum fallback duration counter reaching a predetermined threshold according to the programmable minimum fallback value, from the fallback clock source to the zero source;starting, in response to switching activity to the zero source, the delay counter; andswitching activity, in response to the delay counter reaching a predetermined threshold according to the programmable delay value, from the zero source to the nominal clock source.

8. A method according to claim 7, further comprising resetting the minimum fallback duration counter in response to a voltage droop event occurring after the minimum fallback duration counter is started and before the minimum fallback duration counter reaches the predetermined threshold according to the programmable minimum fallback value.

9. A method according to any preceding claim, wherein the predetermined delay defined by the programmable delay value is zero.

10. An electronic circuit configured to respond to a voltage droop; the electronic circuit providing:a nominal clock source; a fallback clock source; and memory for storing a programmable delay value;wherein, in response to a voltage droop event, the electronic circuit is switched from the nominal clock source to the fallback clock source after a predetermined delay in time according to the programmable delay value stored in the memory.

11. The electronic circuit of claim 10, further comprising a state machine, wherein the state machine is configured to be switched, in response to a voltage droop event, from a nominal state to a fallback state.

12. A state machine according to claim 11, wherein:in response to a voltage droop event, the state machine is switched from the nominal state to a zero state;in response to switching the state machine to the zero state, a delay counter is started; andin response to the delay counter reaching a predetermined threshold according to the programmable delay value, the state machine is switched from the zero state to the fallback state.

13. A state machine according to claim 11 or 12, wherein, in response to a sign-off violation event, the state machine is switched to the zero state.

14. A state machine according to any one of claims 11 to 13, wherein the state machine is switched to the zero state on receipt of an asynchronous signal and within one cycle of the nominal clock source.

15. A state machine according to any one of claims 11 to 14, wherein, in response to a voltage recovery event, the state machine is switched from the fallback state to the nominal state after a predetermined delay in time according to the programmable delay value and a predetermined duration according to a programmable minimum fallback value.

16. A state machine according to claim 15, wherein:in response to a voltage recovery event, a minimum fallback duration counter is started;in response to the minimum fallback duration counter reaching a predetermined threshold according to the programmable minimum fallback value, the state machine is switched from the fallback state to the zero state;in response to switching the state machine to the zero state, the delay counter is started; andin response to the delay counter reaching a predetermined threshold according to the programmable delay value, the state machine is switched from the zero state to the nominal state.

17. A state machine according to claim 16, wherein, in response to a voltage droop event occurring after the minimum fallback duration counter is started and before the minimum fallback duration counter reaches the predetermined threshold according to the programmable minimum fallback value, the minimum fallback duration counter is reset.

18. A method of responding to a voltage droop in an integrated circuit, the method comprising:storing a set of clock parameters in a clock selection state machine, the clock parameters comprising a nominal clock operating at a nominal frequency, a fallback clock operating at a fallback frequency different to the nominal frequency, and a configurable output clock;wherein, when the state machine is in a nominal state, the output clock is configured to output the nominal frequency and, when the state machine is in a fallback state, the output clock is configured to output the fallback frequency;switching, in response to a voltage droop event, the state machine to the fallback state; andswitching, in response to a voltage recovery event, the state machine to the nominal state;wherein, when the state machine is switched to the fallback state, the output clock is switched to output zero for a predetermined delay according to a programmable delay value before being switched to the fallback frequency; andwherein, when the state machine is switched to the nominal state, after a predetermined duration according to a programmable minimum fallback value, the output clock is switched to output zero for a predetermined delay according to the programmable delay value before being switched to the nominal frequency.

19. A state machine comprising circuitry configured to respond to a voltage droop in an integrated circuit; the programmable state machine circuitry comprising:a nominal clock operating at a nominal frequency;a fallback clock operating at a fallback frequency different to the nominal frequency; andan output clock; wherein, when the state machine is in a nominal state, the output clock is configured to output the nominal frequency and, when the state machine is in a fallback state, the output clock is configured to output the fallback frequency;wherein, in response to a voltage droop event, the state machine is switched from the nominal state to the fallback state and, in response to a voltage recovery event, the state machine is switched from the fallback state to the nominal state;wherein, when the state machine is switched to the fallback state, the output clock is switched to output zero for a predetermined delay according to a programmable delay value before being switched to the fallback frequency; andwherein, when the state machine is switched to the nominal state, after a predetermined duration according to a programmable minimum fallback value, the output clock is switched to output zero for a predetermined delay according to the programmable delay value before being switched to the nominal frequency.

20. A method of calibrating the state machine according to claim 19, the method comprising:carrying out at least one of testing, measuring, simulating, provisioning or bootstrapping a response of the integrated circuit to a voltage droop event;setting the programmable delay value;carrying out at least one of testing, measuring, simulating, provisioning or bootstrapping a response of the integrated circuit to a voltage recovery event; andsetting the programmable minimum fallback value.

21. An electronic circuit comprising electronic logic components operable to perform the steps of the method according to any one of claims 1 to 9, 18 or 20.

22. A non-transitory computer-readable medium to store computer-readable code for fabrication of an electronic circuit according to any one of claims 9 to 17, 19 or 21.

23. A system comprising:the electronic circuit of any of claims 9 to 17, 19 or 21 implemented in at least one packaged chip;at least one system component; anda board;wherein the at least one packaged chip and the at least one system component are assembled on the board.

24. A chip-containing product comprising the system of claim 23 assembled on a further board with at least one other product component.

25. A non-transitory computer-readable medium to store computer-readable code for fabrication of the circuitry for detecting a voltage droop event of any preceding claim.

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