Implementing neural networks in hardware
By grouping neural network layers and using on-chip memory with pre-fetching techniques, the inefficiencies in memory access for neural networks are addressed, leading to reduced bandwidth and power consumption.
GB2637252BActive Publication Date: 2026-07-02IMAGINATION TECH LTD
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Patent Information
- Authority / Receiving Office
- GB · GB
- Patent Type
- Patents
- Current Assignee / Owner
- IMAGINATION TECH LTD
- Filing Date
- 2022-12-22
- Publication Date
- 2026-07-02
AI Technical Summary
Technical Problem
Neural networks require large memory bandwidth for reading and writing data and weights, exacerbated by repeated access to off-chip memory, which is inefficient and power-consuming.
Method used
Implementing neural networks in hardware by grouping layers into layer groups and tile groups, using on-chip memory for intermediate data storage, and employing pre-fetching techniques to reduce memory access, particularly for input data that is read multiple times.
Benefits of technology
Reduces memory bandwidth usage and power consumption by optimizing memory access patterns, allowing for more efficient processing of large input datasets and weights.
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Abstract
Implementing a neural network in hardware, particularly as an accelerator. The neural network comprises a plurality of layers and the layers are grouped into a plurality of layer groups, each layer gr
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