Asic package with photonics and vertical power delivery
Patent Information
- Authority / Receiving Office
- HK · HK
- Patent Type
- Patents
- Current Assignee / Owner
- GOOGLE LLC
- Filing Date
- 2023-08-13
- Publication Date
- 2026-07-10
AI Technical Summary
Existing I/O systems in ASIC packages cannot handle the data throughput required by ASIC dies, resulting in severe signal loss and limiting the performance of ASIC dies.
The photonic module is integrated into an ASIC package, and trace length is reduced by using a substrate with low dielectric constant and dielectric loss materials. At the same time, a voltage regulator is used to reduce copper loss during power delivery, and an LGA socket connection is used to reduce the risk of solder joint damage.
It effectively reduces signal loss and heat accumulation during power transmission, increases data transmission bandwidth, reduces production costs, and improves package maintainability.
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Abstract
Description
[0001] Case Analysis
[0002] This application is a divisional application of Chinese invention patent application 202010817738.2, filed on August 14, 2020. Technical Field
[0003] This application relates to an integrated circuit (IC) package and an application-specific integrated circuit (ASIC) package. Background Technology
[0004] Application-specific integrated circuit (ASIC) packages, which include one or more ASIC dies, are becoming increasingly capable of high-speed processing. As the processing speed of ASIC dies continues to increase, the input / output (I / O) system connecting the ASIC package to other components may become a bottleneck. In this regard, the I / O system may not have sufficient bandwidth to handle the data throughput required by the ASIC die, thus limiting the ASIC die from operating at its full potential. Summary of the Invention
[0005] One aspect of this disclosure provides an integrated circuit (IC) package comprising: a substrate; an IC die mounted to the substrate; one or more photonic modules attached to the substrate; and one or more serializer / parallelizer (SerDes) interfaces connecting the IC die to the one or more photonic modules. The one or more SerDes interfaces may include multiple copper traces, and the copper traces may be placed on the substrate. In some cases, the IC die may be an application-specific integrated circuit (ASIC) die. In some cases, the IC package may be configured to connect to a land surface grid array (LGA) socket. Power can be delivered to the IC package via the LGA socket.
[0006] In some cases, one or more photonic modules may include a controller. The controller can manage data transmission between the corresponding photonic module and the IC die. Each of the one or more photonic modules may also include a photonic integrated circuit (PIC) and a fiber optic array. Each of the one or more SerDes interfaces may include a first side connected to the corresponding photonic module and a corresponding second side connected to the IC die. In some examples, one or more photonic modules may be mounted to one or more additional substrates, and the one or more additional substrates may be attached to the substrate via one or more sockets.
[0007] Another aspect of this disclosure provides an application-specific integrated circuit (ASIC) package comprising: a substrate; an ASIC die mounted to the substrate; one or more photonic modules attached to the substrate; one or more serializer / parallelizer (SerDes) interfaces connecting the ASIC die to the one or more photonic modules; and a voltage regulator. In some cases, the voltage regulator may be mounted to the opposite side of the substrate to which the ASIC die is mounted. The one or more SerDes interfaces may include multiple copper traces, and the copper traces may be placed on the substrate. In some examples, the substrate may be configured to connect to a land surface grid array (LGA) socket, and power may be delivered to the voltage regulator via the LGA socket.
[0008] In some cases, each of one or more photonic modules in an ASIC package may include a controller that manages data transmission between the corresponding photonic module and the ASIC die. Each of the one or more photonic modules may also include a photonic integrated circuit (PIC) and a fiber optic array. One or more SerDes interfaces may include a first side and an opposing second side, wherein for each SerDes interface, the first side is connected to the corresponding photonic module, and the opposing second side is connected to the ASIC die. One or more photonic modules may be mounted to one or more additional substrates, wherein the one or more additional substrates may be attached to the substrate via one or more sockets. Attached Figure Description
[0009] Figure 1 This is a top view of an ASIC package with integrated I / O interfaces according to aspects of this disclosure.
[0010] Figure 2 This is a side sectional view of an ASIC package with integrated I / O interface and voltage regulator according to aspects of this disclosure.
[0011] Figure 3 This is a side sectional view of an ASIC package with integrated I / O interface according to aspects of this disclosure.
[0012] Figure 4 This is a side cross-sectional view of an ASIC package with an integrated I / O interface on a separate substrate, according to aspects of this disclosure.
[0013] Figure 5 This is a side sectional view of an ASIC package with an integrated I / O interface and an integrated voltage regulator on a separate substrate, according to aspects of this disclosure.
[0014] Figure 6This is a view of the serializer / parallelizer interface according to aspects of this disclosure.
[0015] Figure 7 This is a side cross-sectional view of an ASIC package connected to a substrate via a ball grid array. Detailed Implementation
[0016] This technology generally relates to application-specific integrated circuit (ASIC) packages with integrated photonic modules and vertically integrated power regulators. As described above, the I / O system connecting the ASIC package to other components may not have sufficient bandwidth to handle the data throughput required by the ASIC die. To address this issue, I / O systems with approximately 100 Gbps bandwidth can be used to reduce I / O system bottlenecks. However, these I / O systems are typically connected to the ASIC package via an interface through an external connection. As the interface bandwidth increases to handle the throughput of the I / O system, the traces of the interface carrying signals between the I / O system and the ASIC die can cause signal loss, such as through high-frequency roll-off. The trace length from the ASIC die to the interface of the externally located I / O system can exacerbate signal loss.
[0017] To reduce signal loss at the interface, the substrate through which the interface traces travel can be made of a material with low dielectric constant (Dk) and low dielectric loss (Df). Furthermore, the surface roughness of the traces can be reduced to further limit signal loss. However, even with low Dk and Df materials and smooth traces, only a small improvement in signal loss can be achieved.
[0018] To remove or further remedy signal loss issues, the I / O system, including the photonic module, can be integrated into the ASIC package. Integrating the photonic module reduces the length of the trace connecting it to the ASIC die, thus minimizing signal loss. In this regard, the length of the interface trace can be integrated into a low-Dk and low-Df PCB. The trace connecting the ASIC die to the external I / O system might be approximately 10 inches. During operation at 100Gbps, a 10-inch trace might experience approximately 20dB of signal loss.
[0019] By integrating the photonic modules into the ASIC package and attaching the photonic modules 220A and 220B to the same substrate as the ASIC die 221 (e.g. Figure 1As shown in the top cross-sectional view of the ASIC package 201, the lengths of traces 291A and 292B can be reduced. In this respect, traces 291A and 291B in the interface from the ASIC die 210 to the integrated photonic modules 220A and 220B can be reduced to approximately 40-50 mm. Therefore, at an operating speed of 100 Gbps, the signal loss can be reduced by approximately 10 dB relative to the signal loss at the interface connecting the ASIC die to the I / O system outside the ASIC package. This allows the PCB into which the interface traces are integrated to have higher Dk and Df values, which saves on material and manufacturing costs while still providing improved signal transmission. These advantages can continue to be realized at even higher operating speeds (such as 200 Gbps or higher).
[0020] Figures 2 to 5 An example of an ASIC package configuration with an integrated photonic module is shown. For example, and as... Figure 2 As shown, the ASIC package 201 includes an ASIC die 210 mounted to a substrate 202 via a socket 203. The socket can be a ball grid array (BGA), land surface grid array (LGA), pin grid array (PGA), or other such socket connections. The ASIC package 201 also includes photonic modules (as shown by dashed boxes 220A and 220B), which include fiber arrays 226A and 226B, photonic integrated circuits (PICs) 224A and 224B, and controllers 222A and 222B, which can be used as an I / O system for the ASIC package. Photonic modules 220A and 220B can be attached to the substrate, such as... Figure 2 The substrate 202 is further shown in the diagram. As described herein, the attachment of photonic modules 220A and 220B can be permanent or via a removable connection. Figure 2 The interfaces shown by the bidirectional arrow lines 290A and 290B, such as the serializer / parallelizer (SerDes) interface (described herein), connect photonic modules 220A and 220B to ASIC die 210.
[0021] The ASIC package 201 may also include a voltage regulator 230, which is mounted to the opposite side of the substrate 202 where the ASIC die 210 is mounted. Figure 2 As indicated by dashed arrow 232, power can be transmitted to the ASIC die 210 via voltage regulator 230. ASIC package 201 can be configured to connect to a socket (such as LGA socket 280) through which power from an external power source (indicated by bidirectional dashed arrow 231) can be supplied to voltage regulator 230. ASIC package 201 may include a housing (such as housing 207) in which the components of ASIC package 201 are located.
[0022] Photonic modules (such as photonic modules 220A and 220B) may include any number of components, including fiber arrays 226A and 226B, photonic integrated circuits (PICs) 224A and 224B, and / or controllers 222A and 222B. The components in the photonic module may be discrete elements and / or combinations of elements. For example, the fiber array may be integrated into the PIC and / or the PIC may be integrated into the controller.
[0023] Fiber optic arrays (such as fiber optic arrays 226A and 226B) can be a collection of one or more fiber optic cables capable of carrying optical signals into or out of an ASIC package (such as ASIC package 201). Fiber optic arrays can be one-dimensional (1D) or two-dimensional (2D) arrays of fiber optic cables. Fiber optic arrays can be coupled to the PIC via lateral or vertical coupling.
[0024] Fiber optic arrays can be mounted on a support structure. For example, and as... Figure 2 As shown, fiber array 226A is mounted on support 228A, and fiber array 226B is mounted on support 228B. The support allows the fiber arrays to be attached to a substrate, such as substrate 202. Depending on the shape and size of the support, the physical height and positioning of the fiber arrays can be adjusted. For example, by increasing the height of the support (such as support 228A), the fiber array 226A attached to the support can be positioned further away from substrate 202 and higher within the ASIC package 201. In some cases, supports 228A and 228B can be configured to position the fiber arrays 226A and 226B at a specific angle relative to the substrate.
[0025] Photonic integrated circuits (such as the PIC 224A and 224B) can be configured to convert electrical signals into optical signals and / or convert optical signals into electrical signals. For example, and referring to... Figure 2 The ASIC package 201 includes two photonic modules 220A and 220B, each photonic module including a PIC 224A and 224B. The first PIC 224A can be configured to receive optical signals from an attached fiber array 226A and convert the optical signals into electrical signals. The first PIC can then transmit the electrical signals to an attached controller 222A. The second PIC 224B can be configured to receive electrical signals from an attached controller 222B and convert the electrical signals into optical signals for transmission from the ASIC package through the attached fiber array 226B. In some cases, the PIC may include one or more waveguides for guiding the optical signals between the PIC and the fiber array.
[0026] A controller can be used to direct the flow of electrical signals between an ASIC die and a PIC. For example, and as... Figure 2As shown, ASIC package 201 includes two controllers 222A and 222B. Controllers 222A and 222B can be transimpedance amplifiers (TIAs) and / or integrated circuits (ICs) configured to modulate or demodulate signals. For example, controller 222A can receive modulated signals from PIC 224A, such as signals modulated using Pulse Amplitude Modulation 4 (PAM4) or some other type of modulation. Controller 222A can demodulate the signal and transmit it to ASIC die 210 via an interface (such as interface 290A). Controller 222B can receive unmodulated signals from ASIC die 210 via interface 290B. Controller 222B can modulate the signal using PAM4 or some other modulation and transmit the modulated signal to PIC 224A. In some cases, the controllers can amplify the signal or perform other digital signal processing on the signal.
[0027] Photonic modules can be connected to ASIC dies via an interface (such as a SerDes interface). For example, and as... Figure 2 As shown, the SerDes interface (indicated by bidirectional arrows 290A and 290B) connects the ASIC die 210 to two photonic modules 220A and 220B. Return to reference Figure 1 The SerDes interface may include a set of traces (such as copper traces 291A and 291B) that connect the ASIC die 210 to the photonic modules 220A and 220B. The copper traces 291A and 291B may be printed directly onto the substrate and / or implemented via wires.
[0028] At each end of the interface trace may be a serializer and / or a parallelizer, which can be connected to the die and / or photonic module. In this respect, each end of the trace may include a serializer and a parallelizer to allow bidirectional communication on the trace. For example, and as... Figure 6 An exploded view of interface 290A shows a serializer 293A on the first end of some trace 291A connected to a parallelizer 294B on the opposite side of trace 291A. Similarly, serializer 293B is located on the opposite side of the trace to parallelizer 294A. Although only nine traces are shown in each SerDes interface 290A and 290B, any number of traces can be present in the interface. In some cases, serializers and parallelizers can be integrated into a controller and / or ASIC. In some examples, serializers and parallelizers can be integrated into a combined serializer / parallelizer.
[0029] During operation, serializers 293A and 293B can convert parallel signals into serial signals for transmission on trace 291A. Parallelizers 294A and 294B at the other end of trace 291A can then convert the serial signals back into parallel signals.
[0030] Components of the photonic module can be mounted on the same substrate as the ASIC die and / or on different substrates. For example, and as... Figure 2 and Figure 3 As shown, the components of photonic modules 220A and 220B are mounted on the same substrate (substrate 202) as the ASIC die 210. By mounting photonic modules 220A and 220B on the same substrate as the ASIC die, vertical transitions between the SerDes interfaces 290A and 290B between the substrates can be avoided, thereby reducing impedance that may cause signal loss.
[0031] exist Figure 4 and Figure 5 In this embodiment, the components of two photonic modules 420A and 420B, compared to photonic modules 220A and 220B, are mounted on different substrates 403A and 403B, respectively. Both substrates 403A and 403B are different from substrate 402, which is on which the ASIC die 410 is mounted.
[0032] like Figure 4 and Figure 5 As further shown, substrates 403A and 403B, on which photonic modules are mounted, can be connected to substrate 402, on which ASIC die 410 is mounted. This connection can be formed via high-speed sockets and / or soldering, such as connecting substrate 403A to socket 415A of substrate 402 and substrate 403B to socket 415B of substrate 402. Although Figure 4 and Figure 5 The diagram shows photonic modules 420A and 420B mounted on different substrates 403A and 403B, respectively. Photonic modules 420A and 420B can also be mounted on the same substrate. The substrate can be a printed circuit board (PCB) or other suitable material.
[0033] An ASIC package having a photonic module on a substrate different from the ASIC die may include an interface that connects the photonic module to the ASIC die via the substrate. For example, and respectively as... Figure 4 and Figure 5As shown in ASIC packages 401 and 501, the SerDes interfaces, indicated by double arrow lines 490A and 490B, connect photonic modules 420A and 420B to ASIC die 410. In this respect, SerDes interface 490A can pass through socket 415A to connect photonic module 420A on substrate 403A to ASIC die 410 on substrate 402. Similarly, SerDes interface 490B can pass through socket 415B to connect photonic module 420B on substrate 403B to ASIC die 410 on substrate 402.
[0034] By mounting photonic modules 420A and 420B on different substrates (such as on...) Figure 4 and Figure 5 As shown in ASIC packages 401 and 501, the length of the trace in the SerDes interface can be longer than when the photonic module is mounted on the same substrate as the ASIC die (such as in...). Figure 2 and Figure 3 The SerDes interface is longer (as shown in ASIC packages 201 and 301). When photonic modules are on different substrates, the increased length of the SerDes interface can increase signal loss as the signal travels along the SerDes trace, and may also increase the signal travel time between components. However, compared to ASIC packages 201 and 301, the production yield of ASIC packages 401 and 501 can be improved because damaged components (e.g., damaged photonic modules, damaged ASIC dies, etc.) can be replaced without replacing the entire ASIC package.
[0035] The increased processing speed of ASIC dies (such as ASIC dies 210 and 410) can also increase the power required to operate the ASIC die. In this respect, and as... Figure 7 As shown, the ASIC package 701 can be connected to a power source (not shown) via a ball grid array (BGA) 716. The BGA 716 may include a plurality of solder balls, such as solder balls 714, formed on the base of the ASIC package 701. The solder balls may be aligned with corresponding pads (such as copper pads 715) formed on a substrate 780 on which the ASIC package 701 is to be mounted. The solder balls are soldered to their corresponding pads to permanently mount the ASIC package 701 to the substrate 780. For example, solder balls 714 are soldered to corresponding pads 715 to form solder joints. Power can be delivered to the ASIC die 710 via the solder joints of the BGA 716 and wires and / or other such connections (not shown) within the substrate 702, and in some cases to photonic modules 720A and 720B, as indicated by dashed arrow 731.
[0036] Increased power draw from the ASIC die 710 may lead to increased heat within the ASIC package due to copper losses generated by wires and / or other such connections that carry power to the ASIC die 710 via the ASIC package 710 and substrate 702. Copper losses, also known as "I losses," are a significant thermal phenomenon. 2 R-loss (where "I" is the current flowing through the copper in the wiring and "R" is the resistance of the wiring) is the heat dissipated as current flows through the wiring. The temperature rise caused by the increased power consumption of the ASIC die 710 may lead to BGA solder electromigration and potential failure of one or more solder joints. The temperature rise may also affect the thermal performance of the ASIC die 710, which may lead to failure of the ASIC die 710 or other components of the ASIC package 701.
[0037] To reduce copper losses caused by wires, planes (e.g., copper planes), and / or other such connections that deliver power to the ASIC die via the ASIC package, voltage regulators can be integrated into the ASIC package. For example, such as Figure 2 As shown in the ASIC package 201, the voltage regulator 230 is mounted to the opposite side of the substrate 202 where the ASIC die 210 is mounted. And as... Figure 5 As shown in the ASIC package 501, the voltage regulator 530 is mounted to the opposite side of the substrate 402 where the ASIC die 410 is mounted. Power can be supplied to the voltage regulators 230 and 530 from an external power source. In this respect, the external power source can supply power to the voltage regulators 230 and 530 respectively through the socket of the ASIC package to be mounted, such as... Figure 2 and Figure 5 The dashed double arrows 231 and 531 are shown respectively. Then, the voltage regulators 230, 530 can supply power to the ASIC dies 210, 410 via one or more wires, planes (e.g., copper planes) and / or other such connections on or within the substrate.
[0038] The voltage regulator can maintain consistent power consumption from an external power source, thereby preventing or reducing the increase in power carried by wires, traces, and / or other such connections on or within the substrate. Furthermore, the length of the wires, traces, and / or other such connections between the voltage regulator and the ASIC dies (such as ASIC dies 210 and 410) can be reduced relative to when ASIC dies 210 and 410 receive power directly from an external power source, respectively, as shown below. Figure 3 and Figure 4As indicated by dashed arrows 331 and 431 in the diagram. Because socket contacts on ASIC packages (such as contact 215 of ASIC package 201) typically have high contact resistance, the heat loss generated by the power flowing through contact 215 can be significant. By moving the voltage regulators into the ASIC package, the amount of power flowing through contact 215 can be reduced. Therefore, the heat generated within ASIC packages 201 and 501 by copper losses can be reduced. Although voltage regulators 230 and 530 are shown as being directly below ASIC dies 210 and 410, the voltage regulators can be offset from the ASIC dies.
[0039] Heat can be further reduced by using radiators and heat sinks. For example, and as... Figure 2 and Figure 3 As shown, heat sink 240 can be positioned around ASIC die 210 to remove heat generated by ASIC die 210 from ASIC die 210. Similarly, heat sink 440 can be positioned around ASIC die 410 to remove heat generated by ASIC die 410 from ASIC die 410.
[0040] Heat sinks can be positioned inside the ASIC package to remove heat (such as heat generated by the photonic module and ASIC die) from the package's interior and direct it to the ASIC package housing. For example, and as... Figure 2 and Figure 3 As shown, heat sink 250 can be positioned above ASIC die 210 and heat sink 240. Heat sink 250 can dissipate heat from ASIC die 210 and heat sink 240. Similarly, heat sink 450 can dissipate heat from ASIC die 410 and heat sink 240.
[0041] As described above, a typical ASIC package can be connected to power via pins soldered onto a ball grid array (BGA). However, given the larger size of ASIC packages with integrated photonic modules and / or voltage regulators, LGA sockets, such as... Figures 2 to 5 The LGA sockets are 280 and 480. (See reference.) Figure 2The LGA socket 280 may include pins 214 aligned with contacts 215 formed on the substrate 202. When the ASIC package 201 is arranged such that the contacts 215 are aligned with the pins 214, the ASIC package 201 can be secured to the LGA socket 280. In some cases, the pins 214 may be soldered to the contacts 215. However, the pins 214 can provide sufficient contact with the contacts 215 of the ASIC package to reduce the need for solder joints, thereby reducing the risk of solder electromigration. Instead of soldering or other methods, latches or other such locking mechanisms may also hold the ASIC package 201 in place within the LGA socket 280. The ASIC package 201 can be removed from the LGA socket 280 if it is not soldered to it.
[0042] although Figures 2 to 5 The example ASIC packages 201, 301, 401, and 501 shown include only a single ASIC die 210 or 410, but each ASIC package may include any number of ASIC dies. Furthermore, each ASIC package may include any number of photonic modules, components within photonic modules, voltage regulators, or other components. Additionally, although the packages described herein are described as ASIC packages with ASIC dies, any type of die, such as an integrated circuit die, can be used.
[0043] The features described herein allow for the integration of photonic modules into an ASIC package. This reduces or eliminates I / O system bottlenecks. Furthermore, signal loss at the interface between the photonic module and the ASIC die can be reduced. Additionally, by integrating the voltage regulator into the ASIC package, copper losses from wires, traces, and / or other such connections that deliver power to the ASIC die through the ASIC package can be reduced. Configuring the ASIC package for mounting in an LGA socket reduces the risk of solder joint damage and solder electromigration and provides the ability to remove the ASIC package as needed.
[0044] Although the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. Therefore, it should be understood that various modifications can be made to the illustrative embodiments and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims.
Claims
1. An integrated circuit (IC) package, comprising: First substrate; One or more additional substrates; IC die, wherein the IC die is mounted to the first surface of the first substrate; One or more photonic modules, wherein each of the one or more photonic modules is mounted to at least one of the one or more additional substrates; and A voltage regulator is mounted on a second surface of the first substrate, directly below the IC die, wherein the second surface of the first substrate is opposite to the first surface of the first substrate, and power is transmitted to the IC die through the voltage regulator.
2. The IC package according to claim 1, further comprising: One or more serializer / parallelizer (SerDes) interfaces, which directly connect the IC die to the one or more photonic modules.
3. The IC package according to claim 2, wherein, The one or more SerDes interfaces include multiple copper traces; and The plurality of copper traces are placed on the first substrate.
4. The IC package according to claim 3, wherein, Each of the one or more SerDes interfaces includes a first side and a second side opposite to the first side. In each of the one or more SerDes interfaces, the first side is connected to a corresponding photonic module in the one or more photonic modules, and the second side is connected to the IC die.
5. The IC package according to claim 1, wherein, Each of the one or more photonic modules includes a controller, wherein each controller manages data transmission between its respective photonic module and the IC die.
6. The IC package according to claim 5, wherein, Each of the one or more photonic modules further includes a photonic integrated circuit (PIC) and a fiber optic array.
7. The IC package according to claim 1, wherein, The IC package is configured to connect to a shore grid array (LGA) socket.
8. The IC package according to claim 7, wherein, Power is transmitted to the IC package via the LGA socket.
9. The IC package according to claim 1, wherein, Each of the one or more additional substrates is attached to the first substrate via one or more sockets.
10. The IC package according to claim 1, wherein, Each of the one or more additional substrates is mounted in a removable manner.
11. An application-specific integrated circuit (ASIC) package, comprising: First substrate; One or more additional substrates; An ASIC die, wherein the ASIC die is mounted to a first surface of the first substrate; One or more photonic modules, wherein each of the one or more photonic modules is mounted to at least one of the one or more additional substrates; and A voltage regulator is mounted on a second surface of the first substrate, directly below the ASIC die, wherein the second surface of the first substrate is opposite to the first surface of the first substrate, and power is transmitted to the ASIC die through the voltage regulator.
12. The ASIC package of claim 11, further comprising: One or more serializer / parallelizer (SerDes) interfaces, which directly connect the ASIC die to the one or more photonic modules.
13. The ASIC package according to claim 12, wherein, The one or more SerDes interfaces include multiple copper traces; and The plurality of copper traces are placed on the first substrate.
14. The ASIC package according to claim 13, wherein, Each of the one or more SerDes interfaces includes a first side and a second side opposite to the first side. In each of the one or more SerDes interfaces, the first side is connected to a corresponding photonic module in the one or more photonic modules, and the second side is connected to the ASIC die.
15. The ASIC package according to claim 11, wherein, Each of the one or more photonic modules includes a controller, wherein each controller manages data transmission between its respective photonic module and the ASIC die.
16. The ASIC package according to claim 15, wherein, Each of the one or more photonic modules further includes a photonic integrated circuit (PIC) and a fiber optic array.
17. The ASIC package according to claim 11, wherein, The ASIC package is configured to connect to a shore grid array (LGA) socket.
18. The ASIC package according to claim 17, wherein, Power is transmitted to the voltage regulator via the LGA socket.
19. The ASIC package according to claim 11, wherein, Each of the one or more additional substrates is attached to the first substrate via one or more sockets.
20. The ASIC package according to claim 11, wherein, Each of the one or more additional substrates is mounted in a removable manner.