Matrix array detector with multiple groups of driver modules and implementing method thereof

Abstract

To provide a matrix array detector capable of reading out consecutive pixel rows or reading out a group of a plurality of pixel rows, and a usage method thereof.SOLUTION: A pixel array is matrixed along the rows and columns to generate a signal. Row conductors L(i), L(i+1), L(i+2), and L(i+3) each drive one row of pixels. Each driver module (SR_A) of a first group (A) sends a selection signal (Out_A) to one of the row conductors of the first group. Each driver module (SR_B) of a second group (B) sends a selection signal (Out_B) to one of the row conductors of the second group. The row conductors of the first and second groups are interlaced.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a matrix array detector and a method for implementing the detector. The present invention is useful in generating visible images, but is not limited to this technical field. For example, it is possible to generate a pressure or temperature map or a two-dimensional representation of a chemical or electrical potential. These maps or representations form an image of a physical quantity. The present invention is particularly applicable to an active matrix array detector used for detection purposes in an imaging device such as a TFT plate that employs, for example, ionizing radiation (e.g., X-rays) (where TFT represents "thin film transistor").

Background Art

[0002] In a matrix array detector, a pixel represents the basic sensing element of the detector. Each pixel converts the physical influence received by each pixel into an electrical signal. Electrical signals from various pixels are collected in the matrix array readout stage and then digitized so that they can be processed and stored to form an image. A pixel is formed by a region sensitive to a physical influence and, for example, sends out an electric current of charges. The physical influence can be electromagnetic radiation that sends out a flow of photons, and ultimately, the present invention will be described using this type of radiation, and the charge current depends on the flow of photons received by the sensing region. Generalizing to any matrix array detector is straightforward.

[0003] A matrix array image detector includes row conductors that connect pixels in the same row to each other and column conductors that connect pixels in the same column to each other. The column conductors are connected to a converter circuit that is generally arranged at the end of the matrix array (sometimes called the "column leg").

[0004] Each pixel typically contains a photosensitive element (or photodetector), which may be, for example, a photodiode, photoresistor, or phototransistor. Large-sized photosensitive matrix arrays exist, potentially having millions of pixels arranged in rows and columns. Each pixel further consists of an electronic circuit, such as a switch, capacitor, and resistor, with an actuator downstream. The assembly of the photosensitive element and electronic circuit allows for the generation and collection of electric charge. The electronic circuit typically allows the charge collected within each pixel to be reset after charge transfer. The role of the actuator is to transfer or replicate the charge collected by the circuit into the column conductors. This transfer occurs when the actuator receives a command from the row conductor to do so. The output of the actuator corresponds to the output of the pixel. The terms “row conductor” and “column conductor” are entirely arbitrary; it is, of course, possible to switch between them.

[0005] In this type of detector, pixels operate in two stages: an image acquisition stage in which the pixel's electronic circuitry accumulates the charge generated by the photosensitive element, and a readout stage in which the collected charge is transferred or replicated within the column conductor by an actuator.

[0006] During the readout phase, a readout command is transmitted via row conductors to all actuators in the same row of the matrix array. Each pixel in this row is readout by transferring its electrical information (e.g., charge, voltage, current, frequency, etc.) to its associated column conductor.

[0007] For an image frame, rows of pixels can be sequentially selected one after another in the direction of scanning the columns of a matrix array over a row selection time corresponding to a portion of the frame duration, allowing an appropriate signal (e.g., voltage) to be applied to the pixels of that row. Thus, row selection corresponds to applying a high-level signal that controls the ON state of the switching device of the corresponding row of pixels during the corresponding row selection time. Outside of the row selection time, the switching device is kept OFF by applying a suitable low-level signal. For example, if the switching device is a transistor and the applied signal is a voltage, it is customary to use VGon to represent the voltage corresponding to a high level (and therefore the ON state of the switching transistor) and VGoff to represent the voltage corresponding to a low level (and therefore the OFF state of the switching transistor).

[0008] Rows may be controlled by a control circuit including one or more shift registers in series, each shift register including multiple cascaded stages, each stage being suitable for switching between high and low levels of signals applied to actuators of pixels in the corresponding row of the matrix array according to a series of row selection operations (e.g., vertical scanning). The control circuits may be implemented within an integrated circuit, and the same integrated circuit may have multiple control circuits for multiple rows in the matrix array, for example. The integrated circuit may be located outside the matrix array, for example, and may be connected to the matrix array by wire connection means (e.g., by a flexible ribbon cable). The control circuits may also be mounted on a plate having pixels, as described in the brochure International Publication No. 2012 / 152836A1 filed in the name of the present applicant.

[0009] This allows for a reduction in the number of signals applied to the plate, and therefore the size and number of flexible connectors used to connect the plate to surrounding electronic equipment. This integrated control circuit architecture results in a significant simplification of the detector architecture by reducing the number of components and simplifying the manufacturing process.

[0010] However, this architecture determines the order in which the matrix rows are driven. This order is determined by the connections of the control circuits and the matrix rows. In some cases, it may be desirable to change the order in which the matrix rows are controlled. More specifically, it may be desirable to group multiple pixels together in order to read them out all at once. This grouping, known as "binning" in the above literature, allows for an improved signal-to-noise ratio for each element being read out. Another advantage of grouping pixels is improved detector sensitivity. However, this grouping negatively impacts spatial resolution.

[0011] If the information from each pixel is charge, this grouping of pixels can be achieved by redistributing the charge from the pixels being grouped onto a common capacitor (e.g., located in the converter circuit at the base of the column). This can be achieved in a detector such as the one described in International Publication No. 2012 / 152836A1 by sequentially reading out each row of pixels. However, in such a detector, grouping pixels in consecutive rows does not allow for an improvement in detector readout speed and therefore an increase in the frequency of the image produced by the detector. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] International Publication No. 2012 / 152836A1 Pamphlet [Overview of the project] [Problems that the invention aims to solve]

[0013] The present invention aims to overcome all or some of the above problems by providing a detector. The control circuit of this detector enables either conventional sequential readout or grouping of pixels belonging to consecutive rows, thereby increasing the readout speed. The present invention is particularly advantageous in a detector in which the control circuit and pixels are generated on the same substrate. [Means for solving the problem]

[0014] To achieve this objective, one subject of the present invention is: - An array of pixels that is sensitive to physical influences and arranged in a matrix along the rows and columns of pixels, wherein each pixel generates a signal according to the physical influence, and the rows of pixels are physically ordered; - Each row conductor allows a row of pixels to be driven; and -A matrix array detector comprising driver modules, each associated with one row conductor (L) and sending a selection signal to one of the row conductors, the driver modules being distributed into multiple groups interlaced according to the order of the rows of pixels, The driver modules in each group are chained together in the physical order of the rows associated with that group of driver modules, and the chaining of each group of driver modules is independent of the chaining of one or more other groups of driver modules.

[0015] Advantageously, the matrix array detector further includes a module for generating a plurality of tokens, each of which is sent to the input of the first driver module among the driver modules in each group of driver modules, and within each group of driver modules, the output of each module is connected to the input of a higher-ranked module, and the driver modules are ordered within each group of those groups in the order of the rows of pixels to the conductor from which the driver module sends a selected signal.

[0016] Advantageously, the pixels and the driver modules are produced on the same substrate based only on n-type thin-film transistors or only on p-type thin-film transistors.

[0017] Another subject of the invention is a method of using a matrix array detector according to the invention. Here, driver modules belonging to separate groups and connected to successive row conductors can receive simultaneous control signals so as to drive successive rows simultaneously, or the control signals can be alternated so as to drive successive rows separately.

[0018] The invention is better understood and further advantages become apparent by reading the detailed description of one embodiment given by way of example and illustrated by the accompanying drawings.

Brief Description of the Drawings

[0019] [Figure 1] An exemplary matrix array of pixels that can be implemented in a detector according to the invention is shown. [Figure 2] An exemplary detector according to the invention is shown. [Figure 3] An exemplary embodiment of one of the plurality of driver modules that can be implemented in the detector of FIG. 2 is shown. [Figure 4] Another exemplary embodiment of the plurality of driver modules that can be implemented in the detector of FIG. 2 is shown. [Figure 5] A detailed example of the driver module of FIG. 4 is shown. [Figure 6] An example of the operation of a detector implementing driver modules chained within only one group as shown in FIG. 5 is shown in the form of a timing diagram. [Figure 7] An example of the operation of a detector implementing driver modules chained within two groups for individual readout of the pixels of the detector as shown in FIG. 5 is shown in the form of a timing diagram. [Figure 8] An example of the operation of a detector implementing driver modules chained within two groups for common readout of the pixels of two successive rows as shown in FIG. 5 is shown in the form of a timing diagram.

Best Mode for Carrying Out the Invention

[0020] For clarity, the same elements will have the same reference numerals in the various drawings.

[0021] The following description is provided with reference to a matrix array detector (referred to as pixels) including a plurality of basic electronic circuits each including an element sensitive to a physical quantity. The basic electronic circuits are pixels sensitive to light radiation in the example being described. It will be apparent that the present invention can be implemented for other detectors sensitive to any form of physical quantity that enables, for example, a pressure or temperature map to be generated.

[0022] FIG. 1 schematically shows a detection area 10 of a matrix array detector. This area includes a 2-row × 2-column matrix for ease of understanding. Four pixels P are formed at the intersection of each row and column. Of course, an actual matrix array is usually much larger and features a large number of rows and columns. The matrix array of pixels belongs to a matrix array detector 12 that enables a digitized image to be generated.

[0023] Each pixel P includes a photosensitive area represented herein by a photodiode D and an electronic processing circuit formed in the example of FIG. 1 by a single transistor T. The reference numerals of components D and T are each followed by two coordinates i and i + 1 defining the rank of the row and two coordinates j and j + 1 defining the rank of the column. The rows and columns are ordered in the physical order they occupy within the matrix array of pixels. The pixels shown are also known as 1T pixels since each holds one transistor whose function is further described below.

[0024] It is common practice to fabricate a matrix array of pixels containing thin-film field-effect transistors (TFTs), commonly known as "thin-film transistors." TFTs can be based on metal oxides, such as transistors based on amorphous or crystalline indium, gallium, and zinc oxide (known by the abbreviation IGZO). Other families of TFTs may be employed, such as organic TFTs, amorphous silicon TFTs, or polycrystalline silicon TFTs. Some of these last types of TFTs have been synthesized at low temperatures. These are known by the acronym LTPS, meaning "low-temperature polycrystalline silicon."

[0025] Pixels P in the same column are connected to the column conductor Col. This conductor allows information to be collected from the connected pixels. Pixels P in the same row are connected to the row conductor L, which carries a signal VG that allows the corresponding row of the pixel to be controlled.

[0026] During the image acquisition phase that occurs after the reset operation, the irradiation received by the photodiode D reduces the potential of its cathode. This image acquisition phase is followed by a readout phase in which the potential of the photodiode D is read out. To do this, transistor T is turned on and thus acts as a switch controlled by a control signal VG applied to its gate.

[0027] The column conductor Col, once selected by the signal VG, is used to collect information from the pixels in the corresponding column.

[0028] In detectors where the pixels are simpler, the present invention can be implemented by replacing the transistor T with a simple diode that is turned on by a signal VG. The present invention can also be implemented in detectors where the pixels include multiple transistors. In particular, it is a known practice to implement 3T pixels that include a photodiode reset transistor and a follower transistor in addition to the readout transistor described above. In this type of 3T pixel, a second row conductor carries a reset signal that enables the reset transistor to be controlled.

[0029] Figure 2 schematically shows the entire detector 12. The detector 12 includes a plate 14 that forms the substrate on which the components of the detection area 10 are fabricated. A driver module 16 that sends control signals to all of the row conductors L is located on this same plate 14. Alternatively, the driver module 16 may be fabricated on a substrate different from the plate 14. However, fabricating the driver module 16 on the same substrate as the pixels P makes it possible to limit the number of connections that connect the plate 14 to its periphery.

[0030] The detector 12 includes a readout circuit 18 connected to the column conductor Col. The readout circuit 18 is typically fabricated on a substrate different from the plate 14. The readout circuit 18 is connected to the plate 14 by a ribbon cable.

[0031] The detector 12 includes a circuit 20 that enables the driver module 16 to be driven and enables the signal from the readout circuit 18 to be retrieved, in particular for multiplexing.

[0032] Figure 3 shows a first exemplary embodiment of four driver modules 16, each configured to drive a row of pixels. It is clearly understood that the present invention can be implemented for pixels of a very large number of rows. More specifically, the output Out_A(n) of the first driver module, denoted by SR_A(N), is connected to the row conductor L(i) carrying the read signal VG for row i. The output Out_B(n) of the second driver module, denoted by SR_B(N), is connected to the row conductor L(i+1) carrying the read signal VG for row i+1. The output Out_A(n+1) of the third driver module, denoted by SR_A(N+1), is connected to the row conductor L(i+2) carrying the read signal VG for row i+2. The output Out_B(n+1) of the fourth driver module, denoted by SR_B(N+1), is connected to the row conductor L(i+3) carrying the read signal VG for row i+3. The rows and driver modules are ordered in the order shown in Figure 3. More specifically, in the case of individual readouts of each row of pixels, row i is read, then row i+1, then row i+2, and finally row i+3. As will be further seen below, the driver module is also configured to enable readouts by grouping rows into consecutive pairs.

[0033] In the example shown, the driver modules are distributed into two groups: SR_A(N) and SR_A(N+1) in a first group A, and SR_B(N) and SR_B(N+1) in a second group B. The present invention can be implemented with many groups of driver modules. Rows are also grouped into two groups: LA for rows L(i) and L(i+2) on the one hand, and LB for rows L(i+1) and L(i+3) on the other hand. Driver module group A is associated with rows of group LA, and driver module group B is associated with rows of group LB. Groups LA and LB of rows and therefore groups A and B of driver modules are interlaced. More specifically, within each group, the driver modules are ordered according to the physical order of the rows of the matrix array. For the two groups of driver modules A and B, in the physical order of the rows of the matrix array, the first driver module of the first group A: SR_A(1) drives the first row L(1) of the matrix array. The first driver module of the second group B, SR_B(1), drives the second row L(2). The second driver module of the first group A, SR_A(2), drives the third row L(4). The second driver module of the second group B, SR_B(2), drives the fourth row L(1), and so on, up to the last row of the matrix array. More generally, by the K groups of driver modules, using the following notation: i: The rank of the current row in the physical order of the rows in the matrix array. j: Rank of the module within that group k: The rank of the group between 1 and K. Row i is driven by a module of rank j in a group of rank k: i = (j-1)K + k.

[0034] Distributing rows and driver modules into various groups that are associated with each other makes it possible to drive groups of rows in different ways, and in particular by adapting the synchronization of various groups of driver modules, and therefore by adapting the synchronization of driving groups of rows.

[0035] Figure 3 shows one embodiment that allows for a particularly simple connection of driver modules. It is clearly understood that other connections are possible. Each driver module includes inputs In_A(n), In_B(n), In_A(n+1), and In_B(n+1), respectively, which enable it to receive instructions for the module, and outputs Out_A(n), Out_B(n), Out_A(n+1), and Out_B(n+1), respectively, which enable it to drive the rows associated with the sequence. In each group, the driver modules are chained together in the order of the rows associated with the group. The chaining of one group is independent of the chaining of one or more other groups of driver modules. More specifically, in the example shown, output Out_A(n) is connected to input In_A(n+1), and output Out_B(n) is connected to input In_B(n+1).

[0036] Detector 12 includes a generator module 30 that enables the generation of a first token IN_A, which is sent to the input of the first driver module SR_A(N) of group A. The generator module 30 also enables the generation of a second token IN_B, which is sent to the input of the first driver module SR_B(N) of group B. The chain of driver modules enables tokens to propagate from one driver module to the next within the same group. More generally, the generator module 30 enables the generation of a number of tokens equal to the number of groups of driver modules.

[0037] In addition, the driver module receives one or more control signals N controls A from group A and one or more control signals N controls B from group B. These control signals are, for example, clocks at a speed at which tokens propagate from one module to other modules within the same group. The control signals can be generated by a generation module 30 (e.g., within circuit 20) which may be located on plate 14 or on a substrate away from plate 14. Connections of the control signals between various driver modules and connections from output to input between consecutive modules can be made on plate 14 and therefore do not require external connections.

[0038] Detector 12 can operate in various ways by generating the signal VG for each row either sequentially in the order of the rows in the matrix array (allowing individual readout of pixels of detector 12), or simultaneously within two driver modules of the same rank within two groups. In other words, the signal VG is transmitted simultaneously by driver modules SR_A(N), SR_B(N), and then by driver modules SR_A(N+1), SR_B(N+1), allowing for the grouping of information originating from pixels of various rows. The choice between the two types of detector readout (either individually or per pixel group) is made by changing the transmission time of tokens IN_A, IN_B and, possibly, the transmission time of the driver module control signals. Simultaneous transmission of the two tokens allows for group-by-group readout. Alternating transmission of the two tokens allows for individual readout.

[0039] By distributing the driver modules into two groups, it is possible to group the readout of two rows of pixels. More generally, K groups make it possible to group the readout of K rows. It is also possible to group rows in a way that is a divisor of the number of groups. For example, four groups of driver modules make it possible to read the matrix array individually, rather than in groups of two rows or four rows, according to offsets in the transmission of tokens and corresponding control signals for various groups.

[0040] Figure 4 shows another exemplary embodiment of four driver modules 16, each configured to drive a row of pixels. In this example, each driver module includes an input stage E and an output stage S. The input stage E sends an activation signal Outa or Outb to the corresponding output stage S. In the case of activation by the input stage, the corresponding output stage transmits the output signal of the driver module (represented herein by Gateline). This example having two stages corresponds to the scheme described in the aforementioned International Publication No. 2012 / 152836A1 brochure. Token transmission between two consecutive driver modules of the same group is achieved using an activation signal sent to the input stage of the higher-rank module. The input stages of the various modules and their connections that enable token transmission form a shift register. Each output stage forms an amplifier that allows the activation signal to be adapted to the characteristics of the signal VG.

[0041] Figure 5 shows a more detailed diagram of one of the driver modules from Figure 4. The integrated structure forming the row addressing device according to the present invention can essentially include single-type (i.e., p-type or n-type; n-type is preferred for its better performance) transistor TFTs. Therefore, all transistors described below can be single-type (n-type or p-type) thin-film transistors (TFTs).

[0042] The structure shown in Figure 5 corresponds to one advantageous embodiment in which each stage n of the row addressing device includes an input stage 50 and an output stage 51. With respect to the stage n of the row addressing device, each of the input stage 50 and the output stage 51 includes most of the elements contained within the row addressing stage n described above with reference to, for example, Figure 3. It should be noted that in the exemplary embodiment described, the rows n of the matrix array are associated with each stage n of the addressing device. However, in alternative examples not shown in the drawings, it is possible to conceive of row addressing device structures in which a given stage controls multiple rows, or otherwise some rows are not controlled by a stage.

[0043] Therefore, the input stage 50 of stage n of the row addressing device may be formed by a shift register including an output row that renders an activation signal Out(n) as an output. The input stage 50 may include an output transistor T30 of the input stage that transmits a pulse of the clock signal at the activation output Out(n). The gate of the output transistor T30 of the input stage may be connected to an internal node of the input stage of the row addressing device, its source may be connected to the activation output Out(n), and its drain may receive a signal from the first clock CLK1. A boost capacitor C20 of the input stage may be connected between the gate and source of the output transistor T30 of the input stage. A first control transistor T10 of the input stage can precharge the gate of the output transistor T30 of the input stage. Therefore, the source of the first control transistor T10 of the input stage is connected to the gate of the output transistor T30 of the input stage. The gate and drain of the first control transistor T10 of the input stage are controlled by the activation output Out(n-1) of stage n-1 of the addressing device of the previous row n-1.

[0044] The second control transistor T20 of the input stage can discharge the gate of the output transistor T30 of the input stage. Thus, the drain of the second control transistor T20 of the input stage is connected to the gate of the output transistor T30 of the input stage. The compensation capacitor C10 of the input stage may, advantageously, be placed between the signal from the first clock CLK1 and the signal from the second clock CLK2 which is out of phase.

[0045] Advantageously, the discharge transistor T40 of the input stage can be connected to the activation output Out(n) of the input stage 50 of stage n of the row addressing device. The gate of the discharge transistor T40 of the input stage is connected to the gate of the second control transistor T20 of the input stage; and also to the activation output signal Out(n+1) of the next stage n+1.

[0046] Similarly, the output stage 51 of stage n of the row addressing device may be formed by a shift register containing an output row that renders a signal Sn as an output. The output stage 51 may include an output transistor T31 of the output stage that transmits a pulse of the clock signal at output Sn. The gate of the output transistor T31 may be connected to an internal node of the stage of the row addressing device, its source may be connected to output Sn, and its drain may receive a signal from a third clock CLK3. A boost capacitor C21 of the output stage may be connected between the gate and source of the output transistor T31 of the output stage. A first control transistor T11 of the output stage can precharge the gate of the output transistor T31 of the output stage. Thus, the source of the first control transistor T11 of the output stage is connected to the gate of the output transistor T31 of the output stage. The gate and drain of the first control transistor T11 of the output stage are controlled by the activation output Out(n) of the input stage 50 of stage n of the addressing device.

[0047] The second control transistor T21 of the output stage can discharge the gate of the output transistor T31 of the output stage. Therefore, the drain of the second control transistor T21 of the output stage is connected to the gate of the output transistor T31 of the output stage. The compensation capacitor C11 of the output stage can advantageously be placed between the signal from the third clock CLK3 and the out-of-phase signal from the fourth clock CLK4. The specialness of the third and fourth clocks CLK3 and CLK4 is that their duty cycles may be different, and the sum of their respective periods at high levels corresponds to the periods of the first and second clocks CLK1 and CLK2.

[0048] Advantageously, the output stage discharge transistor T41 can be connected to the output Sn of the output stage 51 of the row addressing device, which sends the activation signal for row n. The gate of the output stage discharge transistor T41 is connected to the gate of the second control transistor T21 of the output stage; and also to the activation output Out(n+1) of the next stage n+1.

[0049] According to another specific feature of the present invention, the input stage 50 also includes an input stage reset transistor TR whose gate is controlled by a pulse of a reset signal. The source of the input stage reset transistor TR may be connected to the source of a second control transistor T20 of the input stage. The drain of the input stage reset transistor TR may be connected to the drain of the second control transistor T20 of the input stage.

[0050] In the same manner, the output stage 51 also includes an output stage reset transistor TR, whose gate, as well as the gate of the input stage reset transistor, is controlled by a pulse of the reset signal. The source of the output stage reset transistor TR may be connected to the sources of the output stage second control transistor T21 and the output stage discharge transistor T41, respectively, and to the sources of the input stage second control transistor T20 and the input stage discharge transistor T40, respectively. The drain of the output stage reset transistor TR may be connected to the drain of the input stage second control transistor T21.

[0051] Therefore, the reset pulse makes it possible to impose an off state on various transistors in the input stage 50 and the output stage 51.

[0052] Additionally, the output stage 51 may include a row reset transistor TL. The row reset transistor TL is controlled via its gate by a specific signal. The drain of the row reset transistor TL is connected to the source of the output transistor T31 of the output stage. The source of the row reset transistor TL may be connected to the sources of transistors T20, T40, T21, and T41. The row reset transistor TL of stage n makes it possible to force the voltage on row n to a low state. The row reset transistor TL makes it possible to control the voltage on the row (i.e., with respect to the output of the output stage of the stage) and, in particular, to apply a low impedance voltage to the row during the "dead time". Specifically, in a typical manner, the driving of an X-ray detector includes, for example, a reset stage, followed by an X-ray application stage (or "X window"), and then a readout stage. During the X window period, the X-rays are converted into electrons in the photodiode; the X window period is relatively long (usually up to 3.2 seconds), so the row reset transistor TL makes it possible to avoid any drift in the matrix array.

[0053] Again, advantageously, each output stage 51 may include a matrix array reset switch, formed by, for example, a matrix array reset transistor TLON, which enables a complete reset of the matrix array. The matrix array reset transistor TLON may be controlled by a matrix array reset signal applied to its gate and drain. The source of the matrix array reset transistor TLON may be connected to the source of the output transistor T31 of the output stage. The matrix array reset signal controlling the matrix array reset transistor TLON may be a voltage VGoff or an activation voltage VGon. When the matrix array reset transistor TLON is in the activated state, i.e., when the activation voltage VGon is applied, the activation voltage is applied to the entire matrix array.

[0054] In fact, a complete reset of the matrix array can be performed according to a sequence defined by the activation of the matrix array reset transistor TLON for a sufficient period of time, followed by the activation of the row reset transistor TL, which allows the rows to return to the voltage VGoff.

[0055] Figure 6 shows the operation of the driver module of Figure 5, arranged in a single group as described in International Publication No. 2012 / 152836A1, in the form of a timing diagram. A single token IN is sent to the gate and drain of the control transistor T10 of the input stage E of the first driver module. Clocks CLK1 and CLK2 are in opposite phase and have equal proportions of high and low levels. Clocks CLK3 and CLK4 are also in opposite phase and have cycle times that are half the cycle times of clocks CLK1 and CLK2. The high-level period of clock CLK4 is longer than that of clock CLK3.

[0056] Figure 6 also shows the signals Out(n) in four consecutive rows. Each signal Out(n) is offset by half a cycle of clock CLK1 relative to the previous clock. The signals Gateline(n) are also shown for the same four rows. A dead time TM is observed between the two high levels of the two consecutive signals Gateline. This dead time corresponds to the high-level period of clock CLK3. The minimum high-level period of clock CLK3 is required to ensure the gate of transistor T31 is charged. It is impossible to eliminate this dead time by directly chaining the driver modules within a single group.

[0057] Conversely, by distributing the driver modules across multiple groups, it is possible to mask the dead time between two consecutive modules in the same group for individual pixel readouts using a high level of the signal gateline from another group.

[0058] Figure 7 shows an example of the operation of detector 12 in the form of a timing diagram, which implements driver modules linked in two groups for individual readout of the detector pixels, as shown in Figure 5. For the first group A, there are token INA and four clocks CLK1A, CLK2A, CLK3A, and CLK4A. Clocks CLK1A and CLK2A are in opposite phase. Clocks CLK3A and CLK4A are also in opposite phase, having a cycle time that is half the cycle time of clocks CLK1 and CLK2. Unlike the clocks described using Figure 6, the four clocks CLK1A, CLK2A, CLK3A, and CLK4A have equally large high and low levels.

[0059] Figure 7 also shows the token INB and the four clocks CLK1B, CLK2B, CLK3B, and CLK4B for group B. Compared to group A, the signals of group B are offset by one-quarter of the cycles of clock CLK1A.

[0060] For group A, the two signals OutA(1) and OutA(2) and the two signals Gateline(1) and Gateline(3) correspond to the two consecutive driver modules of group A. Signals Gateline(1) and Gateline(3) enable driving rank 1 and 3 rows of the matrix array. Similarly, for group B, the two signals OutB(1) and OutB(2) and the two signals Gateline(2) and Gateline(4) correspond to the two consecutive driver modules of group B. Signals Gateline(2) and Gateline(4) enable driving rank 2 and 4 rows of the matrix array. In other words, the driver modules of group A generate signal Gatelines for odd-numbered rows of the matrix array, and the driver modules of group B generate signal Gatelines for even-numbered rows.

[0061] Interlacing the two groups allows for an extension of the high-level period of the clock CLK3A. Therefore, it is possible to ensure the charging of the gate of transistor T31 without any dead time between the two consecutive lines. Specifically, the gate of transistor T31 in the driver module of group A is charged while the signal gateline of group B is at a high level.

[0062] Figure 8 shows another example in timing diagram form of the operation of detector 12 implementing the driver module shown in Figure 5 for common readout of pixels in consecutive rows, still chained within two groups. In other words, consecutive even and odd rows are readout simultaneously. In the operation described with the help of Figure 8, token INA is transmitted simultaneously with token INB. Similarly, clocks CLK1A, CLK2A, CLK3A, and CLK4A are transmitted simultaneously with their corresponding clocks CLK1B, CLK2B, CLK3B, and CLK4B. Thus, signals OutA(1) and OutA(2), OutA(3) and OutA(4), Gateline(1) and Gateline(2), Gateline(3) and Gateline(4) are simultaneous.

[0063] The operation in Figure 8 is similar to the operation in Figure 6, which has a dead time TM between signals Gateline(2) and Gateline(3). To limit the duration of this dead time, the periods of high levels of clocks CLK3A and CLK3B are shorter than the periods of low levels of the same clocks.

[0064] The detector 12, equipped with multiple groups of driver modules linked together, allows for the selection of various operating modes as needed, particularly for individual pixel readouts of the matrix array, while also offering the possibility of eliminating any dead time between two readouts of two consecutive rows of the matrix array. The detector 12 also allows for the grouping of signals originating from multiple pixels for batch readout.

[0065] Two examples of operations for reading out a matrix array of pixels P are given. In the diagram in Figure 1, row conductor L is used to open-drive transistor T(i,j). This transistor is used for both reading out and resetting each pixel P(i,j). For reading out and resetting (e.g., individual readout and batch reset), the pixels can be driven in the same way or in different ways. [Explanation of symbols]

[0066] 10 Detection Areas 12 Matrix Array Detectors 14 plates 16 Driver Modules 18 Readout Circuit 20 circuits 30 Generation Modules 50, E input stage 51. S Output Stage A, B Driver Module Group CLK1 First Clock CLK2 Second Clock CLK3 The third clock CLK4 The fourth clock CLK1A Group A clock CLK1B Group B clock C10 Input stage compensation capacitor C11 Output stage compensation capacitor C20 Input stage boost capacitor C21 Boost capacitor for the output stage Col row conductor D Photodiode INA, INB token IN_A First token IN_B Second Token In_A, In_B, In_A(n+1), In_B(n+1) input L-shaped conductor LA, LB Group Out_A(n) Output of the first driver module Out_A(n+1) Output of the third driver module Out_B(n) Output of the second driver module Out_B(n+1) Output of the 4th driver module Out(n) Activation Output Outa, Outb activation signal OutA(1), OutA(2), Gateline(1), Gateline(3) Signals of Group A OutB(1), OutB(2), Gateway(2), Gateway(4) Signals of Group B P pixels SR_A(N) First driver module of Group A SR_B(N) First driver module of Group B Sn output T Transistor TL row reset transistor TLON Matrix Array Reset Transistor TM Dead Time TR Reset Transistor T10 First control transistor of the input stage T11 First control transistor of the output stage T20 Second control transistor of the input stage T21 Second control transistor of the output stage T30 Input stage output transistor T31 Output transistor of the output stage T40 Input stage discharge transistor T41 Output stage discharge transistor VG control signal VGoff voltage VGon activation voltage

Claims

1. an array (10) of pixels sensitive to a physical influence and arranged in a matrix along rows and columns of pixels (P), each pixel (P) generating a signal according to a physical influence, said rows of pixels being physically ordered; row conductors (L), each allowing one row of said pixels (P) to be driven; and A matrix array detector including driver modules (SR_A, SR_B), each associated with one row conductor (L) and sending a selection signal (Out_A, Out_B; Gateline) to one of said row conductors (L), said driver modules being distributed into a plurality of groups interlaced according to the order of the rows of pixels, said driver modules (SR_A, SR_B) of each group (A, B) being chained together in the physical order of the rows associated with that group of driver modules, said chaining of each group of driver modules being independent of the chaining of said one or more other groups of driver modules.

2. a module (30) for generating a plurality of tokens (INA, INB) each of which is sent to an input (In_A(N), In_B(N)) of a first one of the driver modules (SR_A(N)) of each group (A, B); 10. The matrix array detector of claim 1 further comprising: A matrix array detector in which, within each group of driver modules, the output (Out_A(n), Out_B(n)) of each module is connected to the input (In_A(n+1), In_B(n+1)) of the module of higher rank, and the driver modules are ordered within each of their groups (A, B) in the order of the rows of the pixels to the conductors to which the driver modules send the selection signals.

3. 3. The matrix array detector according to claim 1, wherein the pixels (P) and the driver modules (SR_A, SR_B) are produced on the same substrate (14) based on only n-type thin film transistors or only p-type thin film transistors.

4. 4. A method of using a matrix array detector according to any one of claims 1 to 3, wherein driver modules (16) belonging to separate groups (A, B) and connected to successive row conductors (L) can receive simultaneous control signals to drive the successive rows simultaneously, or can alternate control signals to drive the successive rows separately.

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