Light-emitting device

Abstract

To provide a display with high definition; to provide a display with low power consumption; to provide a display with high luminance; to provide a display with a high opening ratio.SOLUTION: A display has first wiring, second wiring, third wiring, and a pixel electrode. The first wiring extends in a first direction and is applied with a source signal. The second wiring extends in a second direction intersecting with the first direction and is applied with a gate signal. The third wiring is applied with a constant potential. The first wiring and the pixel electrode are provided in an overlapping manner with the third wiring therebetween.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a display device. One aspect of the present invention relates to an electronic device including a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] In recent years, the high definition of display panels has been advanced. As devices that require high-definition display panels, for example, devices for virtual reality (VR: Virtual Reality) or augmented reality (AR: Augmented Reality) have been actively developed in recent years.

[0004] In addition, typical display devices applicable to display panels include a liquid crystal display device, a light-emitting device including a light-emitting element such as an organic EL (Electro Luminescence) element or a light-emitting diode (LED: Light Emitting Diode), and electronic paper that performs display by an electrophoretic method or the like.

[0005] The basic configuration of an organic EL element is such that a layer containing a light-emitting organic compound is sandwiched between a pair of electrodes. By applying a voltage to this element, light emission can be obtained from the light-emitting organic compound. A display device to which such an organic EL element is applied can realize a thin, lightweight, high-contrast, and low-power consumption display device because a backlight required in a liquid crystal display device or the like is not necessary. For example, an example of a display device using an organic EL element is described in Patent Document 1.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2002-324673 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The wearable devices for VR or AR mentioned above require a lens for focusing between the eyes and the display panel. Because this lens magnifies a portion of the screen, if the display panel has low resolution, it can lead to problems such as a diminished sense of reality and immersion.

[0008] Furthermore, in the case of battery-powered devices, reducing the power consumption of the display panel is required to extend the continuous usage time. In particular, transparent devices for AR require high brightness to display images superimposed on ambient light.

[0009] One aspect of the present invention aims to provide a display device with high resolution. One aspect of the present invention aims to provide a display device with low power consumption. One aspect of the present invention aims to provide a display device with high brightness. One aspect of the present invention aims to provide a display device with a high aperture ratio. One aspect of the present invention aims to provide a highly reliable display device.

[0010] One aspect of the present invention aims to provide a novel display device, display module, or electronic device. Alternatively, it aims to provide a method for manufacturing the above-mentioned display device with high yield. Another aspect of the present invention aims to mitigate at least one of the problems of the prior art.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a display device having a first wiring, a second wiring, a third wiring, and a pixel electrode. The first wiring extends in a first direction and is supplied with a source signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a gate signal. The third wiring is supplied with a constant potential. Furthermore, the first wiring and the pixel electrode are arranged in overlapping manner via the third wiring.

[0013] Another aspect of the present invention is a display device comprising a first wiring, a second wiring, a third wiring, a pixel electrode, a first transistor, and a second transistor. The first wiring extends in a first direction and is supplied with a source signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a gate signal. The third wiring is supplied with a first potential. The first wiring and the pixel electrode are superimposed via the third wiring. The first transistor has one source and drain electrically connected to the first wiring, and its gate electrically connected to the second wiring. The second transistor has one source and drain electrically connected to the pixel electrode, and its other source and drain electrically connected to the third wiring. The first transistor and the second transistor each have a semiconductor layer through which current flows in a first direction.

[0014] Another aspect of the present invention is a display device comprising a first wiring, a second wiring, a third wiring, a pixel electrode, a first transistor, and a second transistor. The first wiring extends in a first direction and is supplied with a source signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a gate signal. The third wiring is supplied with a first potential. The first wiring and the pixel electrode are arranged in overlapping configuration via the third wiring. The first transistor has one source and drain electrically connected to the first wiring, and its gate electrically connected to the second wiring. The second transistor has one source and drain electrically connected to the pixel electrode, and its other source and drain electrically connected to the third wiring. The first and second transistors each have a semiconductor layer through which current flows in a second direction.

[0015] Furthermore, it is preferable to have multiple dummy layers. In this case, it is preferable that the dummy layers contain the same semiconductor material as the semiconductor layer, and that the dummy layers have portions whose upper surface shape is substantially the same as that of the semiconductor layer. Moreover, it is preferable that the multiple dummy layers and semiconductor layers are arranged at equal intervals in the second or first direction.

[0016] Furthermore, it is preferable that any of the above configurations include a fourth wiring, a third transistor, and a fourth transistor. The third transistor has one source and drain electrically connected to the fourth wiring, and the other source and drain electrically connected to the gate of the second transistor. The fourth transistor has one source and drain electrically connected to the fourth wiring, and the other source and drain electrically connected to the pixel electrode. The fourth wiring is also provided with a second potential lower than the first potential.

[0017] Also, in any of the above, it is preferable to have a fifth transistor. The fifth transistor is a transistor in which a channel is formed in silicon. Further, the semiconductor layer contains one or both of indium and zinc. Furthermore, it is preferable that the first transistor and the second transistor are provided above the fifth transistor.

[0018] Also, in any of the above, the third wiring preferably has a grid-like top surface shape. At this time, it preferably has a first portion extending in a first direction and a second portion extending in a second direction. Further, it is preferable that the pixel electrode and the first wiring are provided so as to overlap via the first portion.

[0019] Also, in any of the above, it is preferable to have a plurality of pixel electrodes. A light-emitting region is provided on the pixel electrode. It is preferable that the plurality of light-emitting regions are arranged such that in a plan view, one light-emitting region is surrounded by six light-emitting regions.

[0020] Also, in the above, the light-emitting region preferably has a substantially hexagonal top surface shape. Further, the light-emitting region preferably has a top surface shape in which the inner angles at two opposite corners out of six corners are larger than 120 degrees, and the inner angles at the remaining four corners are less than 120 degrees.

[0021] Or, in the above, the light-emitting region preferably has a substantially hexagonal top surface shape. Further, the pixel electrode preferably has a top surface shape in which all the inner angles of the six corners are 120 degrees, the lengths of two opposite sides out of the six sides are the same, and the lengths of the other four sides are the same.

[0022] Also, in any of the above, it is preferable that three adjacent light-emitting regions are arranged so as to be located at the vertices of an isosceles triangle.

[0023] Also, one aspect of the present invention is a display module having any of the above display devices and a connector or an integrated circuit.

[0024] Moreover, one aspect of the present invention is an electronic device having the display module and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

Effects of the Invention

[0025] According to one aspect of the present invention, a display device with high definition can be provided. Or, a display device with low power consumption can be provided. Or, a display device with high brightness can be provided. Or, a display device with a high aperture ratio can be provided. Or, a display device with high reliability can be provided.

[0026] Moreover, according to one aspect of the present invention, a novel display device, display module, or electronic device, etc. can be provided. Or, a method for manufacturing the above-described display device with high yield can be provided. Or, at least one of the problems of the prior art can be at least alleviated.

[0027] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0028] [Figure 1] FIGS. 1(A) to 1(C) are diagrams showing a configuration example of a display device. [Figure 2] FIG. 2 is a diagram showing a configuration example of a display device. [Figure 3] FIGS. 3(A) to 3(E) are diagrams showing a configuration example of a display device. [Figure 4] FIGS. 4(A) to 4(E) are diagrams showing a configuration example of a display device. [Figure 5] FIGS. 5(A) to 5(E) are diagrams showing a configuration example of a display device. [Figure 6] FIGS. 6(A) to 6(D) are diagrams showing a configuration example of a display device. [Figure 7] Figure 7 shows an example of a display device configuration. [Figure 8] Figures 8(A) to 8(F) show examples of the configuration of a display device. [Figure 9] Figures 9(A) to 9(F) show examples of the configuration of a display device. [Figure 10] Figures 10(A) to 10(D) are circuit diagrams showing examples of the configuration of a display device. [Figure 11] Figures 11(A) to 11(D) are circuit diagrams showing examples of the configuration of a display device. [Figure 12] Figure 12 is a timing chart showing an example of a driving method for a display device. [Figure 13] Figure 13 shows an example of a display device configuration. [Figure 14] Figure 14 shows an example of a display device configuration. [Figure 15] Figures 15(A) to 15(D) are circuit diagrams showing examples of protection circuit configurations. [Figure 16] Figure 16 is a block diagram showing an example of a display device configuration. [Figure 17] Figure 17 is a block diagram showing an example of a display device configuration. [Figure 18] Figure 18 is a block diagram showing an example of a display device configuration. [Figure 19] Figures 19(A) and 19(B) are circuit diagrams showing example configurations of display devices. [Figure 20] Figures 20(A) to 20(C) are circuit diagrams and schematic diagrams showing examples of the configuration of a display device. [Figure 21] Figure 21 is a block diagram showing an example of a display device configuration. [Figure 22] Figures 22(A) to 22(C) show examples of the configuration of a light-emitting device. [Figure 23] Figures 23(A) to 23(C) show examples of the configuration of a display device. [Figure 24] Figures 24(A) and 24(B) show examples of the configuration of electronic equipment. [Figure 25] Figures 25(A) and 25(B) show examples of the configuration of electronic equipment. [Figure 26] Figure 26 shows an example of the transistor configuration according to the embodiment. [Figure 27] Figures 27(A) and 27(B) show the electrical characteristics of the transistor according to the embodiment. [Figure 28] Figure 28 is an optical microscope image of the fabrication stage of the display panel according to the embodiment. [Figure 29] Figure 29 is a photograph of the display state of the display panel according to the embodiment. [Modes for carrying out the invention]

[0029] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0030] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatch patterns are the same, and reference numerals may not be assigned.

[0031] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0032] Furthermore, ordinal numbers such as "the first," "the second," etc., used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0033] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0034] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, that direction may be described as "down," and the opposite direction as "up."

[0035] In this specification, the term "EL layer" refers to a layer (also called a light-emitting layer) provided between a pair of electrodes of a light-emitting element and containing at least a light-emitting substance, or a laminate including a light-emitting layer.

[0036] In this specification, a display panel, which is one form of a display device, has the function of displaying (outputting) images or the like on its display surface. Therefore, a display panel is one form of an output device.

[0037] Furthermore, in this specification, a display panel on which a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) is attached, or on which an IC is mounted on the board using a COG (Chip On Glass) method, may be referred to as a display panel module, display module, or simply a display panel.

[0038] (Embodiment 1) This embodiment describes an example of the configuration of a display device according to one aspect of the present invention.

[0039] One aspect of the present invention is a display device having a plurality of pixels arranged in a matrix. The display device has a plurality of source lines (first wiring) to which source signals (also called video signals, data signals, etc.) are supplied, and a plurality of gate lines (second wiring) to which gate signals (also called scan signals, scanning signals, etc.) are supplied. The source lines are provided to extend in a first direction, and the gate lines are provided to extend in a second direction intersecting the first direction.

[0040] A pixel is provided corresponding to the intersection of one source line and one gate line. A pixel has one or more display elements and one or more transistors. A pixel has pixel electrodes that function as electrodes for the display elements.

[0041] Here, if electrical noise originating from signals supplied to source lines, gate lines, or other wiring propagates to the pixel electrodes, the potential of the pixel electrodes changes, potentially causing the pixel's gradation to deviate from the intended value. As a result, the display quality of the image displayed by the display device may be impaired. Source lines, in particular, have a higher frequency input signal than gate lines, and therefore have a greater impact on the potential of the pixel electrodes.

[0042] One possible measure to reduce electrical crosstalk between the source line and the pixel electrode is to physically separate the pixel electrode and the source line. In particular, preventing the source line and the pixel electrode from overlapping is effective in reducing this crosstalk. However, this method necessitates reducing the size of the pixel electrode, leading to a decrease in the aperture ratio (effective light emission area ratio) of the display device.

[0043] Therefore, in one aspect of the present invention, the source line and the pixel electrode are superimposed via a wiring (third wiring) to which a constant potential is supplied. As a result, electrical noise from the source line is shielded by the third wiring and its propagation to the pixel electrode can be suppressed. Therefore, the area of ​​the pixel electrode can be increased, and the aperture ratio of the display device can be increased.

[0044] The third wiring is preferably a wiring that supplies a constant potential to the pixels. For example, when an organic EL element is used as the display element, the third wiring can also serve as wiring for supplying the anode potential or cathode potential to the organic EL element. The third wiring can also serve as wiring for supplying the power supply potential (such as high power supply potential (VDD) or low power supply potential (VSS)) to the pixels.

[0045] The third wiring can have a striped top surface shape extending along the first direction, which is the direction in which the source wire extends. The third wiring may also have a portion that aligns with the second direction, or it may have a grid-like top surface shape with portions that align with both the first and second directions.

[0046] This configuration suppresses the effects of electrical crosstalk between source lines and other wiring and pixel electrodes, and allows for the free superpositioning of pixel electrodes and wiring, thereby enabling the realization of extremely high-resolution display devices. For example, it is possible to realize display devices with resolutions of 1000 ppi or higher, 2000 ppi or higher, 3000 ppi or higher, 4000 ppi or higher, or 5000 ppi or higher, and 30000 ppi or lower, 20000 ppi or lower, or 15000 ppi or lower.

[0047] Below, we will explain more specific examples with reference to the diagrams.

[0048] [Configuration Example 1] Figure 1(A) shows a schematic perspective view illustrating the stacked structure of one sub-pixel of the display device 10. The sub-pixel includes a pixel circuit 11, a light-emitting element 12, wiring 21, wiring 22, and wiring 23. The light-emitting element 12 has a pixel electrode 24.

[0049] Wiring 21 functions as a source wire and extends in the Y direction. Wiring 22 functions as a gate wire and extends in the X direction. Wiring 23 is supplied with a constant potential and has a portion that extends in the Y direction.

[0050] The light-emitting element 12 is provided inside the pixel electrode 24. As the light-emitting element 12, for example, an electroluminescent element can be suitably used, in which a layer containing a light-emitting substance (also called an EL layer) is sandwiched between a pair of electrodes, and light is emitted by an electric current flowing between the pair of electrodes. In particular, it is preferable to use an organic EL element in which a light-emitting organic compound is used for the EL layer.

[0051] The pixel circuit 11 is a circuit for controlling the current flowing to the light-emitting element 12. Preferably, the pixel circuit 11 has one or more transistors.

[0052] The pixel electrode 24 and the wiring 21 have overlapping regions in a plan view. Furthermore, the pixel electrode 24 and the wiring 21 are superimposed via the wiring 23. In this way, by placing the wiring 23, which is supplied with a constant potential, between the pixel electrode 24 and the wiring 21, even if the pixel electrode 24 is placed superimposed on the wiring 21, electrical noise from the wiring 21 is shielded by the wiring 23 and prevented from propagating to the pixel electrode 24. As a result, the area of ​​the pixel electrode 24 can be increased, which in turn increases the light-emitting area of ​​the light-emitting element 12 and increases the aperture ratio (effective light-emitting area ratio) of the display device 10.

[0053] In this specification, "plan view" refers to the view from the display surface side of the display device 10.

[0054] Figure 1(B) shows an example of the display device 10X without wiring 23. In this case, electrical noise from wiring 21 may propagate to the pixel electrode 24 located above it, causing a change in the potential of the pixel electrode 24, which may result in a shift in the luminescence brightness of the light-emitting element 12.

[0055] Furthermore, Figure 1(C) shows an example of the display device 10Y when the width of the pixel electrode 24 in the X direction is reduced and it is arranged so that it does not overlap with the wiring 21. In this case, while the occurrence of crosstalk due to electrical noise from the wiring 21 can be suppressed, the light-emitting area of ​​the light-emitting element 12 becomes smaller, so the aperture ratio of the display device 10 is reduced.

[0056] Thus, the display device 10 according to one aspect of the present invention can achieve high resolution and a high aperture ratio. Furthermore, because the aperture ratio can be increased, brightness can be increased and power consumption can be reduced. In addition, because the current required for the desired brightness can be reduced, a display device with low power consumption can be realized.

[0057] [Configuration Example 2] The following section will describe more specific examples of pixel configurations.

[0058] [Configuration Example 2-1] Figure 2 shows a schematic top view of a pixel 20 of the display device 10A. The pixel 20 has sub-pixels 20R, 20G, and 20B. The display device 10A has multiple pixels 20, and the pixels 20 are arranged periodically in the X and Y directions.

[0059] Sub-pixel 20R has an element-emitting element 12R that emits red light. Sub-pixel 20G has an element-emitting element 12G that emits green light. Sub-pixel 20B has an element-emitting element 12B that emits blue light.

[0060] The light-emitting elements 12R, 12G, and 12B may each contain different light-emitting materials, or they may each be configured as a combination of a white-emitting light-emitting element and a color filter, or they may each be configured as a combination of a blue or purple light-emitting element and a color conversion material (such as a quantum dot).

[0061] Figures 3(A) to 3(E) show schematic top views of a single sub-pixel 20X extracted from the pixel 20 shown in Figure 2. Sub-pixel 20X can be applied to sub-pixels 20R, 20G, and 20B. Note that the light-emitting element is omitted in this diagram.

[0062] In Figure 3(B), the pixel electrode 24 shown in Figure 3(A) is indicated only by its outline with a dashed line, and an example of the top surface shape of the wiring 23 is shown.

[0063] Wiring 23 functions as a power supply line to the light-emitting element 12 and is supplied with a constant potential. When the pixel electrode 24 functions as an anode, a high power supply potential is supplied to wiring 23, and when it functions as a cathode, a low power supply potential is supplied.

[0064] As shown in Figure 3(B), it is preferable that the wiring 23 has portions extending in the X direction as well as portions extending in the Y direction. This allows the wiring 23 to have a grid-like top surface shape, which reduces electrical resistance and suppresses the effects of voltage drop compared to the case where the top surface shape is striped.

[0065] In Figure 3(C), only the outline of wiring 23 from Figure 3(B) is indicated by a dashed line. In Figure 3(C), wiring 22 and a conductive layer formed by processing the same conductive film as wiring 22 are shown with the same hatching pattern. Similarly, in Figure 3(C), wiring 21 and a conductive layer formed by processing the same conductive film as wiring 21 are shown with the same hatching pattern.

[0066] In Figure 3(D), the wiring 21 in Figure 3(C) and the conductive layer formed by processing the same conductive film are indicated only by their outlines with dashed lines. Similarly, in Figure 3(E), the wiring 22 in Figure 3(D) and the conductive layer formed by processing the same conductive film are indicated only by their outlines with dashed lines.

[0067] Figures 3(C) and 3(D) show transistors 30a and 30b. Figure 3(D) also shows the semiconductor layer 31a of transistor 30a and the semiconductor layer 31b of transistor 30b. Transistor 30a functions as a selection transistor, controlling the selection and deselection of subpixels. Transistor 30b functions as a drive transistor, controlling the current flowing through the light-emitting element.

[0068] In transistor 30a, the wiring 22 forms part of the gate, one of the source and drain is electrically connected to the wiring 21, and the other is electrically connected to the gate of transistor 30b. In transistor 30b, one of the source and drain is electrically connected to the wiring 23, and the other is electrically connected to the pixel electrode 24.

[0069] Here, we show an example in which the top surface shapes of semiconductor layer 31a and semiconductor layer 31b each have a pair of thicker portions where contacts are located and a thinner portion that forms a channel. Forming the semiconductor layers of two transistors to have substantially the same top surface shape in this way is preferable because it allows their respective electrical characteristics to be matched, simplifying the design. Alternatively, a transistor can be constructed by combining semiconductor layers with the same pattern to obtain the desired electrical characteristics. For example, a configuration can be used in which multiple semiconductor layers are arranged and connected in parallel so that the channel width of one transistor is an integer multiple of that of the other transistor. Alternatively, a configuration can be used in which multiple semiconductor layers are arranged and connected in series so that the channel length of one transistor is an integer multiple of that of the other transistor.

[0070] Furthermore, in the display device 10A, the semiconductor layer 31a of transistor 30a and the semiconductor layer 31b of transistor 30b are arranged such that current flows in the Y direction, that is, parallel to the extension direction of the wiring 21. In other words, transistors 30a and 30b are arranged such that the channel length direction is parallel to the Y direction and the channel width direction is parallel to the X direction. Aligning the direction of current flow for multiple transistors constituting a pixel in this way is preferable because it suppresses variations in electrical characteristics and simplifies the design.

[0071] Here, it is preferable that multiple dummy layers 32 are provided, as shown in Figure 3(D), etc. The dummy layers 32 can be formed by processing the same film as semiconductor layers 31a and 31b, and can have the same composition as them. In Figures 3(A) to 3(E), different hatching patterns are applied to the semiconductor layers 31a and 31b and the dummy layers 32 to distinguish them.

[0072] The upper surface shape of the dummy layer 32 is preferably the same as the upper surface shape of the semiconductor layer 31a and semiconductor layer 31b, or a shape that periodically combines them. In the display device 10A, one of the dummy layers 32 has an upper surface shape having two or more thick portions and a thin portion connecting the two thick portions in the Y direction. Each dummy layer 32 is arranged so that its longitudinal direction is parallel to the Y direction. In addition, one dummy layer 32 is arranged across multiple pixels arranged in the Y direction.

[0073] In this way, by placing a dummy layer 32 in the region where semiconductor layers 31a and 31b are not provided, variations in the processed shape of semiconductor layers 31a and 31b can be reduced, and as a result, variations in the electrical characteristics of transistors 30a and 30b can be reduced. A dummy layer is a layer provided in an empty space for purposes such as stabilizing the manufacturing process and reducing processing variations, and is basically not considered as a component of the circuit. Therefore, the dummy layer is either electrically floating or has a constant voltage applied to it. It is also preferable to provide dummy layers in layers other than semiconductor layers.

[0074] It is preferable to arrange the dummy layer 32 so as much as possible in the areas where semiconductor layers 31a and 31b are not provided. In the display device 10A, an example is shown in which the dummy layer 32 is arranged while avoiding the areas where wiring 21 is provided, but the dummy layer 32 may also be arranged overlapping with the wiring 21.

[0075] In this example, two transistors are shown in a single sub-pixel, but the configuration is not limited to this, and configurations with three or more transistors are also possible. In this case, it is preferable that the semiconductor layer has the same pattern for all transistors provided in the sub-pixel, and that the direction of the current flowing through the semiconductor layer is aligned.

[0076] The above is an explanation of Configuration Example 2-1.

[0077] The following describes configuration examples that differ in some aspects from those described above, with reference to the drawings. Note that explanations of parts that overlap with those described above may be omitted. Furthermore, in the drawings shown below, configurations with the same function will be given the same hatching pattern and reference numerals, and explanations may be omitted.

[0078] [Configuration Example 2-2] Figures 4(A) to 4(E) show schematic top views of the sub-pixels 20X of the display device 10B. The display device 10B differs from the display device 10A mainly in that the orientation of the semiconductor layer 31a, semiconductor layer 31b, and dummy layer 32 is different.

[0079] The semiconductor layers 31a and 31b are arranged such that current flows in the X direction, that is, parallel to the direction of extension of the wiring 22. In other words, transistors 30a and 30b are arranged such that their channel length direction is parallel to the X direction and their channel width direction is parallel to the Y direction.

[0080] Furthermore, the dummy layer 32 is arranged so that its longitudinal direction is parallel to the X direction. The dummy layer 32 is arranged across multiple pixels that are aligned in the X direction.

[0081] In addition, the display device 10B shows an example in which the dummy layer 32 is provided so as to have a portion that overlaps with the wiring 21.

[0082] [Configuration Example 2-3] Figures 5(A) to 5(E) show schematic top views of the sub-pixels 20X of the display device 10C. The display device 10C mainly differs from the display device 10A in that it does not have a dummy layer 32.

[0083] In addition, the display device 10B exemplified in the above configuration example 2-2 may also be configured without a dummy layer 32, similar to the display device 10C.

[0084] [Configuration Example 3] The following describes a configuration example of a display device different from the above-described configuration example 2. Note that parts that overlap with the above are denoted by the same reference numerals, and their explanation may be omitted.

[0085] [Example of pixel arrangement] Figure 6(A) shows a schematic top view of a part of the display device 10D. Figure 6(A) shows an example of how to arrange the six light-emitting elements. The display device 10D has a pixel section in which the configuration shown in Figure 6(A) is used as a single unit, and this unit is repeatedly arranged in the X and Y directions.

[0086] Figure 6(A) shows six pixel electrodes 24, two light-emitting elements 12R, two light-emitting elements 12G, and two light-emitting elements 12B. The regions where two sub-pixels 20R, two sub-pixels 20G, and two sub-pixels 20B are provided are indicated by dashed lines.

[0087] Each light-emitting element is positioned within a densely packed hexagonal region. When considering a single light-emitting element, it is positioned so that it is surrounded by six other light-emitting elements. Furthermore, light-emitting elements of the same color are not adjacent to each other. For example, when considering light-emitting element 12R, three light-emitting elements 12G and three light-emitting elements 12B are arranged alternately around it.

[0088] Furthermore, it is preferable that the light-emitting region of the light-emitting element also has a hexagonal top surface shape. Similarly, it is preferable that the pixel electrode 24 also has a hexagonal top surface shape.

[0089] Figures 6(B) and 6(C) show examples of the top surface shape of the light-emitting region of the light-emitting element 12, respectively.

[0090] In both Figures 6(B) and 6(C), the light-emitting element 12X has a length L such that the distance between a pair of vertices located in the Y direction and the distance between a pair of sides extending in the Y direction are equal. This makes it possible to make the pixel array periods in the X and Y directions equal. However, if a close-packed arrangement using a regular hexagon is used, it becomes difficult to make the array periods in the X and Y directions equal, so it is preferable not to use a regular hexagon.

[0091] Furthermore, in the light-emitting element 12X shown in Figure 6(B), the interior angles (angle θ1) of a pair of vertices located in the Y direction are equal, and the interior angles (angle θ2) of the other four vertices are equal. Here, angle θ1 is greater than 120°, and angle θ2 is less than 120°.

[0092] Furthermore, the light-emitting element 12X shown in Figure 6(C) has six interior angles of 120°. Also, the length of the pair of sides extending in the Y direction is shorter than the other sides.

[0093] In practice, the top surface shape of the light-emitting element 12X often has rounded corners at its vertices; therefore, the above angles and side lengths should be applied to a hexagonal figure that approximates the light-emitting element 12X.

[0094] Furthermore, although the shape of the light-emitting element 12X has been described here, it is preferable that the pixel electrodes have a similar shape. In this case, the light-emitting region can be provided so as to overlap with the pixel electrodes and be located inside the pixel electrodes in a plan view.

[0095] Figure 6(D) shows the positions of three adjacent light-emitting elements (light-emitting element 12R, light-emitting element 12G, and light-emitting element 12B). As shown in Figure 6(D), it is preferable to arrange the three light-emitting elements so that each is located at the vertex of an isosceles triangle. In this case, it is preferable that the angle of the vertex located in the Y direction of the isosceles triangle is greater than the angles of the vertices located at both ends of the side parallel to the X direction.

[0096] [Configuration Example 3-1] Next, we will explain some more specific examples of pixel configurations.

[0097] Figure 7 shows a schematic top view of the display device 10E. Figure 7 shows the area containing 2x2 subpixels. Figure 7 shows subpixel 20G, subpixel 20B, and two subpixels 20R.

[0098] Figure 8(A) shows a schematic top view of one sub-pixel 20X of the display device 10E. Sub-pixel 20X can be replaced by sub-pixel 20R, sub-pixel 20G, or sub-pixel 20B in Figure 7. In Figure 8(A), the pixel electrode 24 is shown with a dashed outline only.

[0099] Figures 8(B) to 8(F) show the layout of each layer that makes up the sub-pixel 20X. Figure 8(B) shows the layer located closest to the surface being formed, and Figure 8(F) shows the two layers located closest to the pixel electrode 24.

[0100] Figure 8(B) shows the wiring 22 and a layer having a conductive layer obtained by processing the same conductive film as the wiring 22. Some of these function as one of the gate electrodes (also called the bottom gate electrode, first gate electrode, etc.) of transistor 30a or transistor 30b.

[0101] Figure 8(C) shows a layer having a semiconductor layer 31a, a semiconductor layer 31b, and a plurality of dummy layers 32. Here, the case where the channel length direction is parallel to the Y direction is shown, but as in the configuration example 2-2 above, the layout may be such that the channel length direction is parallel to the X direction.

[0102] Figure 8(D) shows a layer having multiple conductive layers 25. A portion of the conductive layer 25 functions as the gate electrode (also called the top gate electrode, second gate electrode, etc.) of the other transistor 30a or transistor 30b. In addition, there may be a conductive layer 25 that is electrically floating as a dummy layer. By providing a dummy layer, variations in the processed shape of the conductive layer 25 and the like can be reduced.

[0103] Figure 8(E) shows the wiring 21 and a layer having multiple conductive layers obtained by processing the same conductive film. Some of the multiple conductive layers shown in Figure 8(E) function as one of the source and drain electrodes of transistor 30a or transistor 30b. Also, some of the multiple conductive layers shown in Figure 8(E) function as one electrode of a capacitive element.

[0104] Figure 8(F) shows a layer having a conductive layer 27, a wiring 23 located above it, and a layer having a conductive layer obtained by processing the same conductive film. A pixel electrode 24 is provided above the wiring 23. A portion of the conductive layer 27 functions as the other electrode of the capacitive element. In addition, a portion of the conductive layer obtained by processing the same conductive film as the wiring 23 functions as a relay wiring that electrically connects the pixel electrode 24 and the transistor 30b.

[0105] [Configuration Example 3-2] The above described the configuration of a subpixel with two transistors; below, we will describe an example configuration of a subpixel with four transistors. Note that in the following, we will refer to and omit explanations of parts that overlap with configuration example 3-1, etc.

[0106] Figures 9(A) to 9(F) show examples of the configuration of a display device 10F that includes sub-pixels 20X having four transistors.

[0107] The sub-pixel 20X has transistors 30a, 30b, 30c, and 30d.

[0108] As shown in Figure 9(B), three gate wires (wires 22a, 22b, and 22c) and a wire 22d to which a constant potential is supplied are provided. A portion of wire 22a functions as one gate electrode of transistor 30a. A portion of wire 22b functions as one gate electrode of transistor 30c. A portion of wire 22c functions as one gate electrode of transistor 30d.

[0109] As shown in Figure 9(C), the semiconductor layer 31c of transistor 30c and the semiconductor layer 31d of transistor 30d are arranged so that current flows in the Y direction, similar to semiconductor layers 31a and 31b. The dummy layer 32 is provided in the gaps between each semiconductor layer and is arranged so that its longitudinal direction is parallel to the Y direction. Here, the case where the channel length direction is parallel to the Y direction is shown, but as in the above configuration example 2-2, the layout may be such that the channel length direction is parallel to the X direction.

[0110] As shown in Figures 9(B) to 9(D), transistors 30a, 30b, 30c, and 30d are transistors each having a pair of gate electrodes. Alternatively, one or more of the four transistors may be single-gate transistors (with only one gate), and the remaining transistors may be dual-gate transistors (with a pair of gates).

[0111] [Pixel circuit] The following describes examples of pixel circuit configurations and driving methods applicable to a display device according to one aspect of the present invention.

[0112] [Example of pixel circuit configuration] The pixel circuit PIX1 shown in Figure 10(A) includes transistors M1 and M2, capacitor C1, and light-emitting element EL. Wirings SL, GL, AL, and CL are electrically connected to the pixel circuit PIX1.

[0113] Transistor M1's gate is electrically connected to wiring GL, one of its source and drain is electrically connected to wiring SL, and the other of its source and drain is electrically connected to the gate of transistor M2 and one of the electrodes of capacitor C1. Transistor M2's source and drain are electrically connected to wiring AL, and the other of its source and drain is electrically connected to the anode of light-emitting element EL. Capacitor C1's other electrode is electrically connected to the anode of light-emitting element EL. Light-emitting element EL's cathode is electrically connected to wiring CL.

[0114] Transistor M1 can also be called a selection transistor and functions as a switch to control the selection and deselection of pixels. Transistor M2 can also be called a drive transistor and has the function of controlling the current flowing to the light-emitting element EL. Capacitor C1 functions as a holding capacitor and has the function of holding the gate potential of transistor M2. Capacitor C1 may be a capacitive element such as an MIM capacitor, or the capacitance between the wiring or the gate capacitance of the transistor may be used as capacitor C1.

[0115] The source signal is supplied to wiring SL. The gate signal is supplied to wiring GL. Constant potentials are supplied to wiring AL and wiring CL, respectively. The anode side of the light-emitting element EL can be made to a high potential, and the cathode side to a lower potential than the anode side.

[0116] The pixel circuit PIX2 shown in Figure 10(B) is configured by adding transistor M3 to the pixel circuit PIX1. Furthermore, wiring V0 is electrically connected to the pixel circuit PIX2.

[0117] Transistor M3 has its gate electrically connected to wiring GL, and one of its source and drain is electrically connected to the anode of the light-emitting element EL, while the other is electrically connected to wiring V0.

[0118] Wiring V0 provides a constant potential when writing data to the pixel circuit PIX2. This suppresses variations in the gate-source potential of transistor M2.

[0119] The pixel circuit PIX3 shown in Figure 10(C) is an example where transistors with a pair of electrically connected gates are applied to transistors M1 and M2 of the pixel circuit PIX1. Similarly, the pixel circuit PIX4 shown in Figure 10(D) is an example where the same transistors are applied to pixel circuit PIX2. This increases the current that the transistors can supply. While transistors with a pair of electrically connected gates were used here, this is not the only option. Furthermore, transistors with a pair of gates that are electrically connected to different wirings may also be used. For example, reliability can be improved by using a transistor in which one of the gates and the source are electrically connected.

[0120] The pixel circuit PIX5 shown in Figure 11(A) is configured by adding transistor M4 to the above-mentioned pixel circuit PIX2. Furthermore, three wires (wires GL1, GL2, and GL3) that function as gate lines are electrically connected to the pixel circuit PIX5.

[0121] Transistor M4 has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor M2, while the other is electrically connected to wiring V0. Also, the gate of transistor M1 is electrically connected to wiring GL1, and the gate of transistor M3 is electrically connected to wiring GL2.

[0122] By simultaneously making transistors M3 and M4 conduct, the source and gate of transistor M2 become at the same potential, making transistor M2 non-conducting. This allows the current flowing to the light-emitting element EL to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0123] The pixel circuit PIX6 shown in Figure 11(B) is an example of adding a capacitor C2 to the pixel circuit PIX5 described above. Capacitor C2 functions as a retaining capacitor.

[0124] The pixel circuit PIX7 shown in Figure 11(C) and the pixel circuit PIX8 shown in Figure 11(D) are examples of applying a pair of transistors with gates to the above-mentioned pixel circuit PIX5 or pixel circuit PIX6, respectively. Transistors M1, M3, and M4 are transistors in which a pair of gates are electrically connected, while transistor M2 is a transistor in which one of its gates is electrically connected to the source.

[0125] [Example of driving method] The following describes an example of a driving method for a display device to which the pixel circuit PIX5 is applied. Note that the same driving method can be applied to the pixel circuits PIX6, PIX7, and PIX8.

[0126] Figure 12 shows a timing chart for the driving method of a display device to which the pixel circuit PIX5 is applied. Here, the potential changes of the gate lines of the k-th row, wiring GL1[k], wiring GL2[k], and wiring GL3[k], and the gate lines of the k+1-th row, wiring GL1[k+1], wiring GL2[k+1], and wiring GL3[k+1] are shown. Figure 12 also shows the timing of the signal applied to wiring SL, which functions as a source line.

[0127] This example shows a driving method that divides one horizontal period into an on-time period and an off-time period. Also, the horizontal period in row k and the horizontal period in row k+1 are shifted by the gate line selection period.

[0128] During the k-th row's illumination period, a high-level potential is first applied to wires GL1[k] and GL2[k], and a source signal is applied to wire SL. This causes transistors M1 and M3 to conduct, and the potential corresponding to the source signal is written from wire SL to the gate of transistor M2. Subsequently, a low-level potential is applied to wires GL1[k] and GL2[k], causing transistors M1 and M3 to become non-conductive, and the gate potential of transistor M2 is maintained.

[0129] Next, the process transitions to the illumination period of row k+1, and data is written using the same procedure as described above.

[0130] Next, we will explain the off-period. During the off-period of the k-th row, a high-level potential is applied to wirings GL2[k] and GL3[k]. This causes transistors M3 and M4 to conduct, and as the same potential is supplied to the source and gate of transistor M2, almost no current flows through transistor M2. As a result, the light-emitting element EL turns off. All subpixels located in the k-th row turn off. The subpixels in the k-th row remain off until the next on-period.

[0131] Next, the process transitions to the blackout period for row k+1, and as described above, all subpixels in row k+1 become black.

[0132] Thus, a driving method that includes periods of the light being off during a horizontal display period, rather than remaining lit the entire time, can also be called duty cycle driving. By using duty cycle driving, the afterimage phenomenon when displaying videos can be reduced, thus enabling the creation of display devices with high video display performance. In particular, in VR devices, reducing afterimages can alleviate so-called VR sickness.

[0133] In duty cycle operation, the ratio of the lighting period to the horizontal period can be called the duty cycle. For example, a duty cycle of 50% means that the lighting period and the off period are of equal length. The duty cycle can be freely set and can be adjusted as appropriate within a range of, for example, higher than 0% and less than or equal to 100%.

[0134] The above is an explanation of the example of the drive method.

[0135] [Example of cross-sectional configuration] Next, an example of a cross-sectional configuration of a display device according to one aspect of the present invention will be described.

[0136] Figure 13 is a schematic cross-sectional view of the display device 200A. The display device 200A has light-emitting elements 250R, 250G, transistors 210, 220, and capacitive elements 240 between substrates 201 and 202.

[0137] The transistor 210 is a transistor in which a channel formation region is formed on a substrate 201. The substrate 201 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 210 includes a portion of the substrate 201, a conductive layer 211, a low-resistance region 212, an insulating layer 213, an insulating layer 214, etc. The conductive layer 211 functions as a gate electrode. The insulating layer 213 is located between the substrate 201 and the conductive layer 211 and functions as a gate insulating layer. The low-resistance region 212 is a region of the substrate 201 doped with impurities and functions as either a source or a drain. The insulating layer 214 is provided covering the side surface of the conductive layer 211 and functions as an insulating layer.

[0138] Furthermore, an element isolation layer 215 is provided between two adjacent transistors 210 so as to be embedded in the substrate 201.

[0139] A wiring layer 203 is provided between transistors 210 and 220. The wiring layer 203 has a structure in which layers with one or more wirings are stacked. Each layer has a conductive layer 271, and an interlayer insulating layer 273 is provided between two layers. Furthermore, a plug 272 provided in the interlayer insulating layer 273 electrically connects the conductive layers 271 of different layers.

[0140] A transistor 220 is provided on the wiring layer 203. The transistor 220 is a transistor in which a metal oxide (also called an oxide semiconductor) is applied to the semiconductor layer where the channel is formed.

[0141] The transistor 220 includes a semiconductor layer 221, an insulating layer 223, a conductive layer 224, a pair of conductive layers 225, an insulating layer 226, a conductive layer 227, and the like.

[0142] An insulating layer 231 is provided on the wiring layer 203. The insulating layer 231 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the wiring layer 203 side to the transistor 220, and prevents oxygen from detaching from the semiconductor layer 221 to the wiring layer 203 side. As the insulating layer 231, for example, a film that is less permeable to hydrogen or oxygen than a silicon oxide film, such as an aluminum oxide film, hafnium oxide film, or silicon nitride film, can be used.

[0143] A conductive layer 227 is provided on an insulating layer 231, and an insulating layer 226 is provided covering the conductive layer 227. The conductive layer 227 functions as the first gate electrode of the transistor 220, and a portion of the insulating layer 226 functions as the first gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, for at least the portion of the insulating layer 226 that is in contact with the semiconductor layer 221.

[0144] The semiconductor layer 221 is provided on the insulating layer 226. Preferably, the semiconductor layer 221 has a metal oxide (also called an oxide semiconductor) film having semiconductor properties.

[0145] When the semiconductor layer 221 is an In-M-Zn oxide, possible atomic ratios of metal elements in the sputtering target used to deposit the In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc.

[0146] Furthermore, using a target containing a polycrystalline oxide as the sputtering target is preferable because it facilitates the formation of a crystalline semiconductor layer 221. The atomic ratio of the deposited semiconductor layer 221 includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 221 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the deposited semiconductor layer 221 may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0147] Furthermore, when the atomic ratio is stated as In:Ga:Zn=4:2:3 or nearby, it includes the case where, when In is set to 4, Ga is between 1 and 3, and Zn is between 2 and 4. Also, when the atomic ratio is stated as In:Ga:Zn=5:1:6 or nearby, it includes the case where, when In is set to 5, Ga is greater than 0.1 and 2 or less, and Zn is between 5 and 7. Also, when the atomic ratio is stated as In:Ga:Zn=1:1:1 or nearby, it includes the case where, when In is set to 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0148] Furthermore, the semiconductor layer 221 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wider energy gap than silicon in this way, the off-current of the transistor can be reduced.

[0149] Furthermore, the semiconductor layer 221 is preferably a non-single-crystal structure. Non-single-crystal structures include, for example, the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described later. Among non-single-crystal structures, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density.

[0150] The following section describes CAAC (c-axis aligned crystal). CAAC represents one example of a crystal structure.

[0151] CAAC structure is a type of crystalline structure found in thin films and other materials that have multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). In this structure, each nanocrystal has its c-axis oriented in a specific direction, while its a-axis and b-axis are not oriented, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films with a CAAC structure tend to have the c-axis of each nanocrystal oriented in the direction of the film's thickness, the direction normal to the surface it is formed on, or the direction normal to the surface of the film.

[0152] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. Furthermore, because clear grain boundaries cannot be observed in CAAC-OS, it is less susceptible to the reduction in electron mobility caused by grain boundaries. Also, since the crystallinity of oxide semiconductors can decrease due to impurities and defects, CAAC-OS can be considered an oxide semiconductor with fewer impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Consequently, oxide semiconductors containing CAAC-OS are highly heat-resistant and reliable.

[0153] In crystallography, it is common to define a unit cell with a specific axis designated as the c axis, among the three axes (crystal axes) a, b, and c that constitute the unit cell. In particular, in crystals with a layered structure, it is common to define the two axes parallel to the plane direction of the layer as the a and b axes, and the axis intersecting the layer as the c axis. A typical example of such a layered crystal is graphite, which is classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the cleavage planes, and the c axis is perpendicular to the cleavage planes. For example, the crystal of InGaZnO4, which has a layered YbFe2O4 type crystal structure, can be classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0154] In oxide semiconductor films with a microcrystalline structure (microcrystalline oxide semiconductor films), the crystalline regions may not be clearly visible in TEM observation images. The crystalline regions in microcrystalline oxide semiconductor films are often between 1 nm and 100 nm in size, or between 1 nm and 10 nm. In particular, oxide semiconductor films containing nanocrystals (nc) that are microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm, are called nc-OS (nanocrystalline oxide semiconductor) films. Furthermore, in nc-OS films, the grain boundaries may not be clearly visible in TEM observation images, for example.

[0155] nc-OS films exhibit periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). Furthermore, nc-OS films show no regularity in crystal orientation between different crystalline regions. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. For example, when structural analysis of an nc-OS film is performed using an XRD instrument with an X-ray diameter larger than that of the crystalline region, out-of-plane analysis does not detect peaks indicating crystal planes. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the crystalline region (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal region (for example, 1 nm to 30 nm), a region of high brightness is observed in a circular (ring-shaped) pattern, and multiple spots may be observed within this ring-shaped region.

[0156] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-OS films lack regularity in crystal orientation between different crystalline regions. Therefore, nc-OS films have a higher defect level density compared to CAAC-OS films. Consequently, nc-OS films may have a higher carrier density and higher electron mobility compared to CAAC-OS films. Therefore, transistors using nc-OS films may exhibit high field-effect mobility.

[0157] nc-OS films can be formed by reducing the oxygen flow rate ratio during deposition compared to CAAC-OS films. Furthermore, nc-OS films can also be formed by lowering the substrate temperature during deposition compared to CAAC-OS films. For example, nc-OS films can be deposited at relatively low substrate temperatures (e.g., below 130°C) or even without heating the substrate, making them suitable for use with large glass or resin substrates and increasing productivity.

[0158] An example of a metal oxide crystal structure is described below. Metal oxides formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) at a substrate temperature between 100°C and 130°C tend to adopt either an nc (nano crystal) structure or a CAAC structure, or a mixed structure of both. On the other hand, metal oxides formed at room temperature (RT) tend to adopt an nc crystal structure. Note that room temperature (RT) here includes the temperature when the substrate is not intentionally heated.

[0159] A pair of conductive layers 225 are provided in contact with the semiconductor layer 221 and function as source and drain electrodes.

[0160] Furthermore, an insulating layer 232 is provided covering the top and side surfaces of the pair of conductive layers 225, as well as the side surfaces of the semiconductor layer 221, and an insulating layer 261 is provided on top of the insulating layer 232. The insulating layer 232 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 221 from the interlayer insulating layer, and prevents oxygen from detaching from the semiconductor layer 221. An insulating film similar to that used for the insulating layer 231 can be used for the insulating layer 232.

[0161] The insulating layer 232 and the insulating layer 261 are provided with openings that reach the semiconductor layer 221. Inside these openings, an insulating layer 223 is embedded in contact with the insulating layer 261, the insulating layer 232, the sides of the conductive layer 225, and the upper surface of the semiconductor layer 221, and a conductive layer 224 is embedded on the insulating layer 223. The conductive layer 224 functions as a second gate electrode, and the insulating layer 223 functions as a second gate insulating layer.

[0162] The upper surfaces of the conductive layer 224, the insulating layer 223, and the insulating layer 261 are flattened so that their heights are approximately the same, and the insulating layer 233 is provided covering them. An opening is provided in the laminated structure between the insulating layer 233 and the insulating layer 231, and a portion of the insulating layer 233 is in contact with the insulating layer 231 at this opening. The insulating layer 261 functions as an interlayer insulating layer. The insulating layer 233 also functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from above. As the insulating layer 233, an insulating film similar to that of the insulating layer 231 can be used.

[0163] A capacitive element 240 is provided on the insulating layer 233.

[0164] The capacitive element 240 has a conductive layer 241, a conductive layer 242, and an insulating layer 243 located between them. The conductive layer 241 functions as one electrode of the capacitive element 240, the conductive layer 242 functions as the other electrode of the capacitive element 240, and the insulating layer 243 functions as the dielectric of the capacitive element 240.

[0165] An insulating layer 234 is provided covering the capacitive element 240. The insulating layer 234 can be made of the same insulating film as the insulating layer 231. An insulating layer 262 is provided on the insulating layer 231 via an interlayer insulating layer and wiring, and light-emitting elements 250R and 250G are provided on the insulating layer 262.

[0166] The light-emitting element 250R includes a conductive layer 251, a conductive layer 252R, an EL layer 253W, and a conductive layer 254, etc.

[0167] The conductive layer 251 is reflective to visible light, and the conductive layer 252R is transmissive to visible light. The conductive layer 254 is both reflective and transmissive to visible light. The conductive layer 252R functions as an optical adjustment layer to adjust the optical distance between the conductive layer 251 and the conductive layer 254. The optical adjustment layer can have different thicknesses between light-emitting elements of different colors. The conductive layer 252R on the light-emitting element 250R and the conductive layer 252G on the light-emitting element 250G have different thicknesses.

[0168] An insulating layer 256 is provided to cover the ends of the conductive layer 252R and the ends of the conductive layer 252G.

[0169] The EL layer 253W and the conductive layer 254 are provided in common across multiple pixels. The EL layer 253W has an emissive layer that emits white light.

[0170] A colored layer 255R is provided on the light-emitting element 250R via an insulating layer 235. A colored layer 255G is also provided on the light-emitting element 250G. Figure 13 shows a portion of the colored layer 255B.

[0171] For example, the colored layer 255R transmits red light, the colored layer 255G transmits green light, and the colored layer 255B transmits blue light. This increases the color purity of the light from each light-emitting element, enabling a display device with higher display quality. Furthermore, by forming each colored layer on the insulating layer 235, the alignment of each light-emitting element and each colored layer is easier compared to the case where the colored layer is formed on the substrate 202 side before bonding the substrate 201 and substrate 202, enabling the realization of an extremely high-definition display device.

[0172] A lens array 257 is provided on the colored layer 255R and the colored layer 255G. Light emitted from the light-emitting element 250R is colored by the colored layer 255R and emitted to the outside via the lens array 257. The lens array 257 may be omitted if it is not needed.

[0173] The display device 200A has a substrate 202 on the viewing side. Substrate 202 and substrate 201 are bonded together. As substrate 202, a translucent substrate such as a glass substrate, quartz substrate, sapphire substrate, or plastic substrate can be used.

[0174] This configuration makes it possible to realize a display device with extremely high resolution and high display quality.

[0175] Figure 14 shows a schematic cross-sectional view of display device 200B, which has some configuration differences from the display device 200A described above.

[0176] The light-emitting element 250R has an EL layer 253R that emits red light. The light-emitting element 250G has an EL layer 253G that emits green light.

[0177] Furthermore, this example shows a display device 200B that does not have a colored layer.

[0178] Furthermore, the EL layer 253R and the EL layer 253G are processed so that they do not come into contact with each other between two adjacent light-emitting elements. In other words, the ends of the EL layer 253R and the ends of the EL layer 253G are positioned opposite each other on the insulating layer 256 between two adjacent light-emitting elements. The EL layer 253R and the EL layer 253G may be fabricated separately by a deposition method using a fine metal mask, but it is preferable that they are each finely processed by a photolithography method.

[0179] The above is an explanation of the cross-sectional configuration examples.

[0180] [Protection circuit] The following describes an example of a protection circuit configuration applicable to a display device.

[0181] Active matrix display devices have many source and gate lines arranged in a matrix. Therefore, if ESD (Electrostatic Discharge) occurs in the source or gate lines during the manufacturing process of the display device or during the integration process of electronic equipment, it can lead to display defects. For this reason, it is preferable to provide protective circuits on the source and gate lines to mitigate the effects of ESD.

[0182] Furthermore, during pre-shipment inspections or sampling inspections of display devices, inspection circuits, terminals, or electrodes may be provided to check whether the pixels are functioning correctly.

[0183] Figure 15(A) shows an example of a circuit PC1 for inputting the potential input from terminal PRE to source line SL.

[0184] Circuit PC1 has transistors Tr1, Tr2, and Tr3. Each transistor has a pair of gates. The gate located below the semiconductor layer is called the back gate, and the gate located above it is called the top gate.

[0185] Transistor Tr1 is electrically connected as follows: its top gate is connected to terminal Sig, its back gate to terminal VBG1, and one of its source and drain wires is connected to source wire SL, while the other is connected to terminal PRE.

[0186] A signal for controlling transistor Tr1 is supplied to terminal Sig. A bias potential is supplied to terminal VBG1. When transistor Tr1 becomes conductive, the potential of terminal PRE is supplied to wiring SL.

[0187] Here, transistors Tr2 and Tr3 are electrically connected between the top gate of transistor Tr1 and terminal Sig. Transistors Tr2 and Tr3 function as protection circuits. Transistors Tr2 and Tr3 are diode-connected transistors. Terminal VDD is electrically connected to transistor Tr2, and terminal VSS is electrically connected to transistor Tr3. In addition, terminal VBG2 is electrically connected to the back gate of transistor Tr2, and terminal VBG3 is electrically connected to the back gate of transistor Tr3.

[0188] The circuit PC2 shown in Figure 15(B) is an example where the number of terminals and transistors are reduced compared to circuit PC1.

[0189] Circuit PC2 has a transistor Tr1. Transistor Tr1 is electrically connected to the wiring SL at its top gate, to terminal Sig at its back gate, and to terminal PRE and wiring SL at the other end of its source and drain.

[0190] In this way, by connecting the Sig terminal, which receives the control signal, to the back gate of transistor Tr1 instead of the top gate, a protection circuit for terminal Sig is not required, and the circuit can be simplified. Depending on the electrical characteristics of transistor Tr1, it may be possible to swap the top gate and back gate of transistor Tr1.

[0191] The circuit PC3 shown in Figure 15(C) is an example where two transistors, Tr1a and Tr1b, are used instead of transistor Tr1 in circuit PC2. The back gates of transistors Tr1a and Tr1b are electrically connected to terminal Sig.

[0192] Furthermore, the circuit PC4 shown in Figure 15(D) is an example where the terminals (terminal Sig1 and terminal Sig2) are connected separately to transistors Tr1a and Tr1b, respectively.

[0193] By applying the configurations shown in Figures 15(B), 15(C), and 15(D), the number of terminals can be significantly reduced, enabling the realization of a compact display device.

[0194] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0195] (Embodiment 2) This embodiment describes a display device and a display system that are aspects of the present invention.

[0196] <Example of display device configuration> Figure 16 is a schematic block diagram showing an example configuration of a display device 510, which is a display device according to one aspect of the present invention. The display device 510 has a layer 520 and a layer 530, the layer 530 of which can be laminated, for example, on top of the layer 520. An interlayer insulator or a conductor for making an electrical connection between different layers can be provided between the layer 520 and the layer 530.

[0197] The transistor provided in layer 520 can be, for example, a transistor having silicon in its channel formation region (also called a Si transistor), or a transistor having single-crystal silicon in its channel formation region. In particular, using a transistor having single-crystal silicon in its channel formation region as the transistor provided in layer 520 allows for a large on-current of the transistor. Therefore, it is preferable because it allows the circuit of layer 520 to be driven at high speed. Furthermore, since Si transistors can be formed with microfabrication such as a channel length of 3 nm to 10 nm, they can be used in a display device 510 equipped with an accelerator such as a CPU or GPU, an application processor, etc.

[0198] The transistor provided in layer 530 can be, for example, an OS transistor. In particular, it is preferable to use an OS transistor having an oxide containing at least one of indium, element M (where element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region. Such an OS transistor has the characteristic of having a very low off-current. Therefore, it is preferable to use an OS transistor as a transistor provided in the pixel circuit of the display unit in particular, because it can retain the analog data written to the pixel circuit for a long period of time.

[0199] Layer 520 is provided with a drive circuit 540 and a function circuit 550. Since layer 520 is provided with Si transistors with high on-current, each circuit in layer 520 can be driven at high speed.

[0200] Layer 530 is provided with a display unit 560 having multiple pixels 561. Each pixel 561 is provided with pixel circuits 562R, 562G, and 562B that control red, green, and blue light emission. Pixel circuits 562R, 562G, and 562B function as sub-pixels of pixel 561. Since pixel circuits 562R, 562G, and 562B have OS transistors, they can retain analog data written to the pixel circuits for a long period of time. Each pixel 561 in layer 530 is also provided with a backup circuit 582. Note that the backup circuit may also be called a storage circuit or memory circuit.

[0201] The drive circuit 540 includes a gate line drive circuit, a source line drive circuit, etc., for driving the pixels 561 (pixel circuits 562R, 562G, 562B) of the display unit 560. By arranging the drive circuit 540 in a layer 520 different from the layer 530 on which the display unit is provided, the area occupied by the display unit in layer 530 can be increased. The drive circuit 540 may also include an LVDS (Low Voltage Differential Signaling) circuit or a D / A (Digital to Analog) conversion circuit, etc., which function as an interface for receiving data such as image data from outside the display device 510. The Si transistors in layer 520 can have a high on-current. Depending on the operating speed of each circuit, the channel length or channel width of the Si transistors may be varied.

[0202] The functional circuit 550 has a processor (e.g., a CPU) used for data processing. The CPU has multiple CPU cores. The CPU cores have flip-flops. The flip-flops have multiple scan flip-flops. Flip-flop 580 inputs and outputs the data (backup data) from the scan flip-flops to and from the backup circuit 582. In Figure 16, the backup data BD is shown as the data signal held by the backup circuit 582.

[0203] For the backup circuit 582, a memory having an OS transistor is preferable, for example. Using an OS transistor with an extremely low off-current in the backup circuit has advantages such as being able to maintain the voltage of the analog data written to the backup circuit for a long period of time and consuming almost no power to retain the data. The backup circuit 582 having an OS transistor can be provided in the display unit 560 where multiple pixels 561 are arranged. Figure 16 illustrates how the backup circuit 582 is provided for each pixel 561.

[0204] The backup circuit 582, composed of OS transistors, can be stacked with the layer 520 having Si transistors. The backup circuit 582 may be arranged in a matrix similar to the subpixels within the pixel 561, or it may be arranged for each of multiple pixels. In other words, the backup circuit 582 can be placed within the layer 530 without being constrained by the arrangement of the pixels 561. Therefore, it is possible to increase the degree of freedom of the display unit / circuit layout, and to place it without increasing the circuit area, thereby increasing the memory capacity of the backup circuit 582 required for calculation processing.

[0205] <Example configuration of pixel circuit and backup circuit> Figures 17 and 18 illustrate an example of the arrangement of the backup circuit 582 and the sub-pixels, pixel circuits 562R, 562G, and 562B, within the display unit 560.

[0206] Figure 17 illustrates a configuration in the display unit 560 in which multiple pixels 561 are arranged in a matrix. Each pixel 561 has pixel circuits 562R, 562G, and 562B, as well as a backup circuit 582. As mentioned above, both the backup circuit 582 and the pixel circuits 562R, 562G, and 562B can be made of OS transistors and therefore can be placed within the same pixel.

[0207] <Block diagram of the display device> Next, Figure 18 shows a block diagram illustrating the various components of the display device 510. The display device includes a drive circuit 540, a function circuit 550, and a display unit 560.

[0208] The drive circuit 540 includes, for example, a gate driver 541 and a source driver 542. The gate driver 541 has the function of driving multiple gate lines GL for outputting signals to pixel circuits 562R, 562G, and 562B. The source driver 542 has the function of driving multiple source lines SL for outputting signals to pixel circuits 562R, 562G, and 562B. The drive circuit 540 also supplies voltage for displaying on pixel circuits 562R, 562G, and 562B to the pixel circuits 562R, 562G, and 562B via multiple wires.

[0209] The functional circuit 550 has a CPU 551. The CPU 551 has a CPU core 553. The CPU core 553 has a flip-flop 580 for temporarily holding data used in arithmetic processing. The flip-flop 580 has a plurality of scan flip-flops 581, and each scan flip-flop 581 is electrically connected to a backup circuit 582 provided in the display unit 560.

[0210] The display unit 560 has multiple pixels 561, each of which is provided with pixel circuits 562R, 562G, 562B and a backup circuit 582. As explained in Figure 17, the backup circuit 582 does not necessarily have to be placed within the repeating unit of pixel 561. It can be freely arranged depending on the shape of the display unit 560, the shape of the pixel circuits 562R, 562G, 562B, etc.

[0211] <Example of pixel circuit configuration> Figures 19(A) and 19(B) show examples of the configuration of the pixel circuit 562 applicable to the pixel circuits 562R, 562G, and 562B, and the light-emitting element 570 connected to the pixel circuit 562. Figure 19(A) is a diagram showing the connections of each element, and Figure 19(B) is a diagram schematically showing the hierarchical relationship between the drive circuit 540, the pixel circuit 562, and the light-emitting element 570.

[0212] In this specification, the term "element" may sometimes be replaced with "device." For example, display elements, light-emitting elements, and liquid crystal elements may be replaced with, for example, display devices, light-emitting devices, and liquid crystal devices.

[0213] The pixel circuit 562 shown as an example in Figures 19(A) and 19(B) comprises a switch SW21, a switch SW22, a transistor M21, and a capacitor C21. Switches SW21 and SW22, and transistor M21 can be composed of OS transistors. Preferably, each OS transistor of switch SW21, switch SW22, and transistor M21 has a gate electrode and a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode.

[0214] Transistor M21 comprises a gate electrode electrically connected to switch SW21, a first electrode electrically connected to light-emitting element 570, and a second electrode electrically connected to wiring ANO. Wiring ANO is a wire that provides a potential for supplying current to the light-emitting element 570.

[0215] Switch SW21 has a first terminal electrically connected to the gate electrode of transistor M21 and a second terminal electrically connected to the source line SL. Switch SW21 also has a function to control the conduction state or non-conduction state based on the potential of the gate line GL1.

[0216] Switch SW22 has a first terminal electrically connected to wiring V0 and a second terminal electrically connected to the light-emitting element 570. Switch SW22 also has a function to control the conduction state or non-conduction state based on the potential of the gate wire GL2. Wiring V0 is wiring for supplying a reference potential and wiring for outputting the current flowing through the pixel circuit 562 to the drive circuit 540 or the function circuit 550.

[0217] Capacitor C21 comprises a conductive film electrically connected to the gate electrode of transistor M21 and a conductive film electrically connected to the second terminal of switch SW22.

[0218] The light-emitting element 570 includes a first electrode electrically connected to the first electrode of the transistor M21 and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is supplied with a potential for supplying current to the light-emitting element 570.

[0219] This allows the intensity of light emitted by the light-emitting element 570 to be controlled according to the image signal applied to the gate electrode of transistor M21. Furthermore, the amount of current flowing through the light-emitting element 570 can be increased by the reference potential of the wiring V0 provided via switch SW22. By monitoring the current flowing through wiring V0 with an external circuit, the amount of current flowing through the light-emitting element can be estimated. This allows for the detection of pixel defects and other issues.

[0220] In the configuration shown as an example in Figure 19(B), the wiring electrically connecting the pixel circuit 562 and the drive circuit 540 can be shortened, thereby reducing the wiring resistance. As a result, data writing becomes faster, and the display device 510 can be driven at high speed. This ensures a sufficient frame duration even if the display device 510 has a large number of pixels 561, and increases the pixel density of the display device 510. Furthermore, increasing the pixel density of the display device 510 improves the resolution of the image displayed by the display device 510. For example, the pixel density of the display device 510 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 510 can be used as a display device for AR or VR, and can be suitably applied to electronic devices such as HMDs where the distance between the display unit and the user is close.

[0221] In Figure 19(B), gate lines GL1 and GL2, wiring ANO, wiring VCOM, wiring V0, and source line SL are shown to be supplied with signals from the drive circuit 540 located below the pixel circuit 562 via wiring. However, the present invention is not limited to this. For example, the wiring that supplies signals and voltages from the drive circuit 540 may be routed to the outer periphery of the display unit 560 and electrically connected to each pixel circuit 562 arranged in a matrix on layer 530. In this case, it is effective to provide the gate driver 541 of the drive circuit 540 on layer 530. That is, it is effective to use an OS transistor for the gate driver 541. It is also effective to provide part of the function of the source driver 542 of the drive circuit 540 on layer 530. For example, it is effective to provide a demultiplexer on layer 530 that distributes the signals output by the source driver 542 to each source line. It is also effective to use an OS transistor for the demultiplexer.

[0222] <Example of a display correction system configuration> A display system according to one aspect of the present invention may include a display correction system. The display correction system includes a current I flowing through the light-emitting element 570. EL By correcting these issues, display defects caused by faulty pixels such as bright spots or dark spots can be reduced.

[0223] The circuit diagram shown in Figure 20(A) is an excerpt illustrating a portion of the pixel circuit 562 shown in Figure 19(A). In the case of a defective pixel that causes bright spots or dark spots, the current I flowing through the light-emitting element 570 is different compared to a normal pixel. EL It becomes extremely large or extremely small.

[0224] CPU551 monitors the current I flowing through switch SW23. MONI The data is acquired periodically. The monitor current I MONIThe current is converted into digital data that can be handled by the CPU 551, and the CPU 551 performs calculations using this digital data. The calculations in the CPU 551 estimate the defective pixels, and the CPU 551 performs corrections to make the display defects caused by the defective pixels less visible. For example, if pixel 561D shown in Figure 20(B) is a defective pixel, the current I flowing through the light-emitting element 570 of the adjacent pixel 561N EL Correct it.

[0225] The amount of this correction can be estimated by performing calculations based on artificial neural networks such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs).

[0226] As a result of the above correction, the current I flowing through the pixel 561N adjacent to the defective pixel EL Current I EL_C The image is corrected as follows: By displaying the image as pixel 561G, which is a composite of the defective pixel and pixel 561N, display defects caused by defective pixels, such as bright spots or dark spots, become less visible, resulting in a normal display.

[0227] Furthermore, the display correction system, which corrects the current flowing through the pixels, can continuously retain data in progress as backup data during calculations. Therefore, it is particularly effective when performing computationally intensive tasks such as those based on artificial neural networks. By using the CPU 551 as an application processor, it is possible to combine calculations with variable frame frequency driving and other functions to reduce display defects and lower power consumption.

[0228] Figure 21 shows modified examples of each configuration of the display device 510 described above.

[0229] The block diagram of the display device 510A shown in Figure 21 corresponds to a configuration in which an accelerator 552 is added to the functional circuit 550 of the display device 510 in Figure 18.

[0230] In the display correction system described above, when calculations based on an artificial neural network are performed, the configuration involves repeatedly performing multiply-accumulate operations. The accelerator 552 functions as a dedicated calculation circuit for the multiply-accumulate operations of the artificial neural network NN. Calculations using the accelerator 552 can perform processes such as correcting the display defects described above, or correcting the image contours by upconverting the display data. Furthermore, power consumption can be reduced by configuring the CPU 551 to be power-gated while the accelerator 552 is performing calculations.

[0231] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0232] (Embodiment 3) This embodiment describes a light-emitting element (light-emitting device) that can be used in a display device according to one aspect of the present invention.

[0233] In this specification, devices fabricated using a metal mask or an FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or an FMM may be referred to as MML (Metal Maskless) structured devices.

[0234] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. A white light-emitting device can be combined with a colored layer (for example, a color filter) to become a full-color display light-emitting device.

[0235] Furthermore, light-emitting devices can be broadly classified into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and it is preferable that this light-emitting unit includes one or more light-emitting layers. To obtain white light emission, one should select light-emitting layers such that the light emitted from each of the two or more layers is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0236] A tandem device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, the device should be configured such that the light from the light-emitting layers of the multiple light-emitting units is combined to produce white light emission. The configuration for obtaining white light emission is the same as that for a single-structure device. In a tandem device, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0237] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem structure) with SBS structure light-emitting devices, SBS structure light-emitting devices can consume less power than white light-emitting devices. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting devices. On the other hand, white light-emitting devices are preferable because their manufacturing process is simpler than that of SBS structure light-emitting devices, which can lead to lower manufacturing costs or higher manufacturing yields.

[0238] <Example configuration of light-emitting element 570> The EL layer 686 of the light-emitting element 570 can be composed of multiple layers, such as layer 4420, light-emitting layer 4411, and layer 4430, as shown in Figure 22(A). Layer 4420 may include, for example, a layer containing a material with high electron injection properties (electron injection layer) and a layer containing a material with high electron transport properties (electron transport layer). Light-emitting layer 4411 may contain, for example, a light-emitting compound. Layer 4430 may include, for example, a layer containing a material with high hole injection properties (hole injection layer) and a layer containing a material with high hole transport properties (hole transport layer).

[0239] A configuration having a layer 4420, an emissive layer 4411, and a layer 4430 provided between a pair of electrodes can function as a single emissive unit, and in this specification, the configuration shown in Figure 22(A) is referred to as a single structure.

[0240] Furthermore, as shown in Figure 22(B), a configuration in which multiple light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0241] Furthermore, as shown in Figure 22(C), a configuration in which multiple light-emitting units (EL layers 686a, 686b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure in this specification. In this specification, the configuration shown in Figure 22(C) is referred to as a tandem structure, but it is not limited to this, and for example, a tandem structure may also be called a stack structure. By using a tandem structure, a light-emitting element capable of high-brightness light emission can be made.

[0242] The light-emitting color of the light-emitting element 570 can be red, green, blue, cyan, magenta, yellow, or white, depending on the material constituting the EL layer 686. Furthermore, the color purity can be further enhanced by adding a microcavity structure to the light-emitting element 570.

[0243] A light-emitting element that emits white light preferably has a configuration that includes two or more types of light-emitting materials in its light-emitting layer. To obtain white light emission, it is sufficient to select light-emitting materials such that the light emitted by each of the two or more materials is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary in color, a light-emitting element that emits white light as a whole can be obtained. The same applies to light-emitting elements that have three or more light-emitting layers.

[0244] The light-emitting layer preferably contains two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, it is preferable that the layer contains two or more light-emitting materials, and the light emitted by each light-emitting material contains spectral components of two or more colors from R, G, and B.

[0245] <Method for forming the light-emitting element 570> The following describes a method for forming the light-emitting element 570 provided on the pixel circuit 562.

[0246] Figure 23(A) shows a schematic top view of a display device according to one embodiment of the present invention. The display unit 560 has a plurality of red light-emitting elements 570R, a green light-emitting element 570G, and a blue light-emitting element 570B. In Figure 23(A), the labels R, G, and B are added within the light-emitting area of ​​each light-emitting element to simplify the distinction between them. The configuration of the display unit 560 shown in Figure 23(A) may also be called an SBS (Side By Side) structure. Furthermore, although the configuration shown in Figure 23(A) is exemplified as having three colors, red (R), green (G), and blue (B), it is not limited to this. For example, a configuration having four or more colors is also possible.

[0247] The light-emitting elements 570R, 570G, and 570B are each arranged in a matrix. Figure 23(A) shows a so-called stripe arrangement, in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this; other arrangement methods such as delta arrangement and zigzag arrangement may be applied, and pentile arrangement can also be used.

[0248] It is preferable to use organic EL devices such as OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) as the light-emitting elements 570R, 570G, and 570B. Examples of light-emitting materials for the EL elements include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0249] Figure 23(B) is a schematic cross-sectional view corresponding to the dashed line A1-A2 in Figure 23(A).

[0250] Figure 23(B) shows cross-sections of the light-emitting element 570R, light-emitting element 570G, and light-emitting element 570B. Each of the light-emitting elements 570R, 570G, and 570B is provided on the substrate 351 and has a conductor 672 that functions as a pixel electrode and a conductor 688 that functions as a common electrode.

[0251] The light-emitting element 570R has an EL layer 686R between the conductor 672 and the conductor 688. The EL layer 686R has a light-emitting organic compound that emits light with intensity in at least the red wavelength range. The EL layer 686G of the light-emitting element 570G has a light-emitting organic compound that emits light with intensity in at least the green wavelength range. The EL layer 686B of the light-emitting element 570B has a light-emitting organic compound that emits light with intensity in at least the blue wavelength range.

[0252] Each of the EL layers 686R, 686G, and 686B may have, in addition to a layer containing a light-emitting organic compound (light-emitting layer), one or more of the following: an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0253] A conductor 672 is provided for each light-emitting element. A conductor 688 is provided as a continuous layer common to all light-emitting elements. A conductive film that is transparent to visible light is used for either conductor 672 or conductor 688, and a conductive film that is reflective is used for the other. By making conductor 672 transparent and conductor 688 reflective, a bottom-emission type display device can be made. Conversely, by making conductor 672 reflective and conductor 688 transparent, a top-emission type display device can be made. Furthermore, by making both conductor 672 and conductor 688 transparent, a dual-emission type display device can be made.

[0254] An insulating layer 372 is provided to cover the end of the conductor 672. Preferably, the end of the insulating layer 372 is tapered.

[0255] Each of the EL layers 686R, 686G, and 686B has a region in contact with the upper surface of the conductor 672 and a region in contact with the surface of the insulating layer 372. The edges of the EL layers 686R, 686G, and 686B are located on the insulating layer 372.

[0256] As shown in Figure 23(B), a gap is provided between the two EL layers between light-emitting elements of different colors. In this way, it is preferable that EL layers 686R, 686G, and 686B are arranged so that they do not touch each other. This effectively prevents current from flowing through two adjacent EL layers and causing unintended light emission (also known as crosstalk). As a result, contrast can be increased, and a display device with high display quality can be realized.

[0257] EL layer 686R, EL layer 686G, and EL layer 686B can be fabricated separately using methods such as vacuum deposition with a shadow mask like a metal mask. Alternatively, they may be fabricated separately using photolithography. By using photolithography, it is possible to realize a display device with high resolution that is difficult to achieve when using a metal mask.

[0258] Furthermore, a protective layer 371 is provided on the conductive material 688, covering the light-emitting elements 570R, 570G, and 570B. The protective layer 371 has the function of preventing impurities such as water from diffusing to each light-emitting element from above.

[0259] As the protective layer 371, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film can be adopted. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used as the protective layer 371. Note that the protective layer 371 may be formed using an ALD method, a CVD method, or a sputtering method. Although the configuration including an inorganic insulating film is exemplified as the protective layer 371, it is not limited thereto. For example, the protective layer 371 may have a laminated structure of an inorganic insulating film and an organic insulating film.

[0260] FIG. 23(C) shows an example different from the above.

[0261] In FIG. 23(C), there is a light-emitting element 570W that exhibits white light. The light-emitting element 570W has an EL layer 686W that exhibits white light between a conductor 672 and a conductor 688.

[0262] As the EL layer 686W, for example, a configuration in which two or more light-emitting layers are laminated and selected such that their respective emission colors are in a complementary color relationship can be adopted. Alternatively, a laminated EL layer in which a charge generation layer is sandwiched between the light-emitting layers may be used.

[0263] FIG. 23(C) shows three light-emitting elements 570W arranged side by side. A coloring layer 364R is provided above the left light-emitting element 570W. The coloring layer 364R functions as a band-pass filter that transmits red light. Similarly, a coloring layer 364G that transmits green light is provided above the central light-emitting element 570W, and a coloring layer 364B that transmits blue light is provided above the right light-emitting element 570W. Thereby, the display device can display a color image.

[0264] Here, between two adjacent light-emitting elements 570W, the EL layer 686W and the conductor 688 are separated from each other. As a result, in two adjacent light-emitting elements 570W, current can flow through the EL layer 686W, and unintentional light emission can be suitably prevented from occurring. In particular, when a stacked EL element in which a charge generation layer is provided between two light-emitting layers is used as the EL layer 686W, the higher the fineness, that is, the smaller the distance between adjacent pixels, the more prominent the influence of crosstalk becomes, and there is a problem that the contrast decreases. Therefore, by adopting such a configuration, a display device having both high fineness and high contrast can be realized.

[0265] The separation of the EL layer 686W and the conductor 688 is preferably performed by a photolithography method. As a result, the interval between the light-emitting elements can be narrowed, and for example, a display device with a high aperture ratio can be realized as compared with the case of using a shadow mask such as a metal mask.

[0266] In the case of a bottom emission type light-emitting element, a coloring layer may be provided between the conductor 672 and the substrate 351.

[0267] The above is the description of the light-emitting element.

[0268] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0269] (Embodiment 4) In this embodiment, a configuration example of an electronic device to which a display device according to an aspect of the present invention is applied will be described.

[0270] A display device and display module according to one aspect of the present invention can be applied to the display section of an electronic device having a display function. Examples of such electronic devices include electronic devices with relatively large screens such as television sets, notebook personal computers, monitors, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and sound playback devices.

[0271] In particular, the display device and display module according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because they can increase the resolution. Examples of such electronic devices include wearable devices that can be worn on the head, such as wristwatch-type and bracelet-type information terminals (wearable devices), VR devices such as head-mounted displays, and AR devices such as glasses.

[0272] Figure 24(A) shows a perspective view of a spectacle-type electronic device 700. The electronic device 700 includes a pair of display panels 701, a pair of housings 702, a pair of optical members 703, a pair of mounting parts 704, and the like.

[0273] The electronic device 700 can project an image displayed on the display panel 701 onto the display area 706 of the optical element 703. Furthermore, because the optical element 703 is translucent, the user can view the image displayed on the display area 706 superimposed on the transmitted image seen through the optical element 703. Therefore, the electronic device 700 is an electronic device capable of AR display.

[0274] Furthermore, one of the housings 702 is equipped with a camera 705 capable of capturing images of the area in front. Although not shown, one of the housings 702 is also equipped with a wireless receiver or a connector to which a cable can be connected, allowing video signals and the like to be supplied to the housing 702. Additionally, by equipping the housing 702 with an acceleration sensor such as a gyro sensor, the orientation of the user's head can be detected and an image corresponding to that orientation can be displayed in the display area 706. Furthermore, it is preferable that the housing 702 is equipped with a battery, which can be charged wirelessly or via a wired connection.

[0275] Next, using Figure 24(B), the method for projecting an image onto the display area 706 of the electronic device 700 will be explained. Inside the housing 702, a display panel 701, a lens 711, and a reflector 712 are provided. In addition, the portion of the optical element 703 corresponding to the display area 706 has a reflective surface 713 that functions as a half-mirror.

[0276] Light 715 emitted from the display panel 701 passes through the lens 711 and is reflected towards the optical element 703 by the reflector 712. Inside the optical element 703, the light 715 undergoes total internal reflection repeatedly at the end face of the optical element 703 and reaches the reflective surface 713, thereby projecting an image onto the reflective surface 713. As a result, the user can see both the light 715 reflected by the reflective surface 713 and the transmitted light 716 that has passed through the optical element 703 (including the reflective surface 713).

[0277] Figure 24 shows an example where the reflector 712 and the reflective surface 713 each have curved surfaces. This increases the degree of freedom in optical design and allows for a thinner optical component 703 compared to when they are flat. However, the reflector 712 and the reflective surface 713 may also be flat.

[0278] As the reflector 712, a material having a mirror surface can be used, and it is preferable that it has a high reflectivity. Also, as the reflective surface 713, a half-mirror that utilizes the reflection of a metal film may be used, but using a prism that utilizes total internal reflection can increase the transmittance of the transmitted light 716.

[0279] Here, it is preferable that the housing 702 has a mechanism for adjusting the distance between the lens 711 and the display panel 701, or the angle between them. This makes it possible to adjust the focus, enlarge or reduce the image, etc. For example, one or both of the lens 711 or the display panel 701 may be configured to move in the optical axis direction.

[0280] Furthermore, it is preferable that the housing 702 has a mechanism that allows the angle of the reflector 712 to be adjusted. By changing the angle of the reflector 712, the position of the display area 706 on which the image is displayed can be changed. This makes it possible to position the display area 706 in an optimal position according to the user's eye position.

[0281] A display device or display module according to one aspect of the present invention can be applied to the display panel 701. Therefore, an electronic device 700 capable of displaying extremely high resolution can be created.

[0282] Figures 25(A) and 25(B) show perspective views of the goggle-type electronic device 750. Figure 25(A) is a perspective view showing the front, top, and left side of the electronic device 750, while Figure 25(B) is a perspective view showing the rear, bottom, and right side of the electronic device 750.

[0283] The electronic device 750 includes a pair of display panels 751, a housing 752, a pair of mounting parts 754, a cushioning member 755, a pair of lenses 756, and the like. The pair of display panels 751 are each provided inside the housing 752 in a position where they can be seen through the lenses 756.

[0284] The electronic device 750 is an electronic device for VR. When a user wears the electronic device 750, they can view the image displayed on the display panel 751 through the lens 756. Furthermore, by displaying different images on a pair of display panels 751, a three-dimensional display using parallax can also be performed.

[0285] On the back side of the housing 752, an input terminal 757 and an output terminal 758 are provided. A cable for supplying a video signal from a video output device or the like, or power for charging a battery provided in the housing 752 can be connected to the input terminal 757. As the output terminal 758, for example, it functions as an audio output terminal and can connect earphones, headphones, etc. Note that when configured to be able to output audio data by wireless communication or when outputting audio from an external video output device, the audio output terminal may not be provided.

[0286] Also, the housing 752 preferably has a mechanism capable of adjusting the left and right positions of the lens 756 and the display panel 751 so that they are in the optimal positions according to the position of the user's eyes. Further, it preferably has a mechanism for adjusting focus by changing the distance between the lens 756 and the display panel 751.

[0287] The display device or display module according to an aspect of the present invention can be applied to the display panel 751. Therefore, an electronic device 750 capable of extremely high-precision display can be obtained. As a result, a high sense of immersion can be given to the user.

[0288] The cushioning member 755 is the part that comes into contact with the user's face (forehead, cheeks, etc.). By ensuring that the cushioning member 755 is in close contact with the user's face, light leakage can be prevented, thereby enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 755 so that it comes into close contact with the user's face when the user wears the electronic device 750. For example, materials such as rubber, silicone rubber, urethane, and sponge can be used. Furthermore, if the surface of a sponge or similar material is covered with cloth, leather (genuine leather or synthetic leather), gaps are less likely to form between the user's face and the cushioning member 755, effectively preventing light leakage. In addition, using such materials is preferable because it feels good against the skin and does not make the user feel cold when worn in cold seasons. It is preferable that the components that come into contact with the user's skin, such as the cushioning member 755 or the mounting part 754, be removable, as this makes cleaning or replacement easier.

[0289] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Examples]

[0290] In this embodiment, a display device according to one aspect of the present invention was fabricated. For the pixels of the fabricated display device, refer to the display device 10F exemplified in Figure 9(A) of Embodiment 1. For the cross-sectional configuration of the transistors and display elements of the fabricated display device, refer to Figure 13.

[0291] First, the electrical characteristics of the transistor applied to the display device are shown. A schematic perspective view of the transistor is shown in Figure 26. The fabricated transistor is a Trench-gate-self-aligned structure (TGSA structure) fabricated using an LSI process node, and the top gate electrode is formed to cover the oxide semiconductor (OS) channel. This improves the electric field control capability by the top gate electrode, making it a structure suitable for miniaturization.

[0292] The transistor in question is an OS transistor (OS transistor) that uses an oxide semiconductor as the semiconductor in which the channel is formed. The measured transistor has a channel length of approximately 200 nm and a channel width of approximately 60 nm.

[0293] Figure 27(A) shows the Id-Vg characteristics. Figure 27(A) shows two Id-Vg characteristics together, one with a drain voltage of 0.1V and the other with a drain voltage of 1.2V. Despite being a tiny transistor, as shown in Figure 27(A), it exhibits normally-off characteristics, and the off-current is below the detection limit of the measuring instrument (1 × 10⁻¹⁰). 12 A) It was below that.

[0294] Figure 27(B) shows the Id-Vd characteristics. Figure 27(B) also shows four Id-Vd characteristics for gate voltages of 0.5V, 1.0V, 1.5V, and 2.0V. Despite being a miniature transistor, it exhibits high saturation as shown in Figure 27(B).

[0295] The fabricated display panel has a stacked structure consisting of silicon transistors, OS transistors, and OLED elements. Figure 28 shows an optical microscope image of the chip after the silicon transistor manufacturing process is complete. Within the display area indicated by the dashed line, it can be seen that a source driver, digital-to-analog converter (DAC), scan driver, and interface (IF) are located. By using this monolithic structure with stacked silicon transistors, OS transistors, and OLED elements, the bezel area can be reduced.

[0296] The specifications of the fabricated panel are as follows: The display area size is 0.51 inches diagonally, the resolution is 1920 x 1920 pixels, the pixel size is 4.8 μm, the pixel density is 5291 ppi, the aperture ratio is 23.8%, and the color method is a white tandem OLED with a color filter. The light-emitting element is a top-emission type.

[0297] Using a white tandem element as the OLED element requires a higher voltage compared to a single element. In this embodiment, the display device uses OS transistors with high voltage resistance for the pixel transistors, enabling good display even with a white tandem element.

[0298] Figure 29 shows a photograph of the display state of the display device. As shown in Figure 29, the display is working well. It was also confirmed that the display device is capable of duty cycle operation. [Explanation of symbols]

[0299] 10: Display device 10A: Display device 10B: Display device 10C: Display device 10D: Display device 10E: Display device 10F: Display device 11: Pixel circuit 12: Light-emitting element 12B: Light-emitting element 12G: Light-emitting element 12R: Light-emitting element 12X: Light-emitting element 20: Pixel 20B: Sub-pixel 20G: Sub-pixel 20R: Sub-pixel 20X: Sub-pixel 21: Wiring 22: Wiring 22a: Wiring 22b: Wiring 22c: Wiring 22d: Wiring 23: Wiring 24: Pixel electrode 25: Conductive layer 27: Conductive layer 30: Transistor 30a: Transistor 30b: Transistor 30c: Transistor 30d: Transistor 31a: Semiconductor layer 31b: Semiconductor layer 31c: Semiconductor layer 31d: Semiconductor layer 32: Dummy layer

Claims

1. A liquid crystal display device comprising a plurality of pixels arranged in a matrix, Among the plurality of pixels, at least a first pixel includes first to third transistors, a light emitting element, a source line, a first gate line, a second gate line, a power supply line, and a first wiring; one of a source and a drain of the first transistor is electrically connected to the source line; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; a gate of the first transistor is electrically connected to the first gate line; one of a source and a drain of the second transistor is electrically connected to the power supply line; the other of the source and the drain of the second transistor is electrically connected to a pixel electrode of the light-emitting element; one of a source and a drain of the third transistor is electrically connected to the first wiring having a function of supplying a first potential to the first pixel; a light-emitting device in which the other of the source and the drain of the third transistor is electrically connected to a pixel electrode of the light-emitting element, a first conductive film that is disposed in a first layer, overlaps with a channel formation region of the first transistor, and functions as the first gate line; a second conductive film that is disposed in the first layer, overlaps with a channel formation region of the third transistor, and functions as the second gate line; a third conductive film disposed on the first layer and having a function as the first wiring; a fourth conductive film disposed in a second layer stacked above the first layer and having a function as the source line; a fifth conductive film disposed in the second layer and having a function as the power supply line; a sixth conductive film disposed in the second layer and having a function as the first wiring; a seventh conductive film disposed in a third layer laminated above the second layer and having a function as the power supply line; an eighth conductive film disposed in the third layer and electrically connected to the other of the source and the drain of the third transistor; a ninth conductive film disposed in a fourth layer laminated above the third layer, electrically connected to the eighth conductive film, and having a function as the pixel electrode; the first conductive film extends along a first direction so as to span a second pixel adjacent to the first pixel; the second conductive film extends along the first direction so as to span the second pixel; the fourth conductive film extends along a second direction intersecting the first direction so as to span a third pixel adjacent to the first pixel; the seventh conductive film extends along the first direction to reach the second pixel, and extends along the second direction to reach the third pixel; the seventh conductive film has a region between the fourth conductive film and the ninth conductive film; Light emitting device.

2. A liquid crystal display device comprising a plurality of pixels arranged in a matrix, Among the plurality of pixels, at least a first pixel includes first to third transistors, a light emitting element, a source line, a first gate line, a second gate line, a power supply line, and a first wiring; one of a source and a drain of the first transistor is electrically connected to the source line; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; a gate of the first transistor is electrically connected to the first gate line; one of a source and a drain of the second transistor is electrically connected to the power supply line; the other of the source and the drain of the second transistor is electrically connected to a pixel electrode of the light-emitting element; one of a source and a drain of the third transistor is electrically connected to the first wiring having a function of supplying a first potential to the first pixel; a light-emitting device in which the other of the source and the drain of the third transistor is electrically connected to a pixel electrode of the light-emitting element, a first conductive film that is disposed in a first layer, overlaps with a channel formation region of the first transistor, and functions as the first gate line; a second conductive film that is disposed in the first layer, overlaps with a channel formation region of the third transistor, and functions as the second gate line; a third conductive film disposed on the first layer and having a function as the first wiring; a fourth conductive film disposed in a second layer stacked above the first layer and having a function as the source line; a fifth conductive film disposed in the second layer and having a function as the power supply line; a sixth conductive film disposed in the second layer and having a function as the first wiring; a seventh conductive film disposed in a third layer laminated above the second layer and having a function as the power supply line; an eighth conductive film disposed in the third layer and electrically connected to the other of the source and the drain of the third transistor; a ninth conductive film disposed in a fourth layer laminated above the third layer, electrically connected to the eighth conductive film, and having a function as the pixel electrode; the first conductive film extends along a first direction so as to span a second pixel adjacent to the first pixel; the second conductive film extends along the first direction so as to span the second pixel; the fourth conductive film extends along a second direction intersecting the first direction so as to span a third pixel adjacent to the first pixel; the seventh conductive film extends along the first direction to reach the second pixel, and extends along the second direction to reach the third pixel; the seventh conductive film has a region between the fourth conductive film and a conductive film having a function as a pixel electrode of a light-emitting element included in the second pixel; Light emitting device.

3. A pixel sensor having a plurality of pixels arranged in a matrix, Among the plurality of pixels, at least a first pixel includes first to third transistors, a light emitting element, a source line, a first gate line, a second gate line, a power supply line, and a first wiring; one of a source and a drain of the first transistor is electrically connected to the source line; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; a gate of the first transistor is electrically connected to the first gate line; one of a source and a drain of the second transistor is electrically connected to the power supply line; the other of the source and the drain of the second transistor is electrically connected to a pixel electrode of the light-emitting element; one of a source and a drain of the third transistor is electrically connected to the first wiring having a function of supplying a first potential to the first pixel; a light-emitting device in which the other of the source and the drain of the third transistor is electrically connected to a pixel electrode of the light-emitting element, a first conductive film that is disposed in a first layer, overlaps with a channel formation region of the first transistor, and functions as the first gate line; a second conductive film that is disposed in the first layer, overlaps with a channel formation region of the third transistor, and functions as the second gate line; a third conductive film disposed on the first layer and having a function as the first wiring; a fourth conductive film disposed in a second layer stacked above the first layer and having a function as the source line; a fifth conductive film disposed in the second layer and having a function as the power supply line; a sixth conductive film disposed in the second layer and having a function as the first wiring; a seventh conductive film disposed in a third layer laminated above the second layer and having a function as the power supply line; an eighth conductive film disposed in the third layer and electrically connected to the other of the source and the drain of the third transistor; a ninth conductive film disposed in a fourth layer laminated above the third layer, electrically connected to the eighth conductive film, and having a function as the pixel electrode; the first conductive film extends along a first direction so as to span a second pixel adjacent to the first pixel; the second conductive film extends along the first direction so as to span the second pixel; the fourth conductive film extends along a second direction intersecting the first direction so as to span a third pixel adjacent to the first pixel; the seventh conductive film extends along the first direction to reach the second pixel, and extends along the second direction to reach the third pixel; the seventh conductive film has a region between the fourth conductive film and a conductive film having a function as a pixel electrode of a light-emitting element included in the third pixel; Light emitting device.

Images