Indicating device

Abstract

To provide a novel display device.SOLUTION: A display device has: a first layer provided with a plurality of pixel circuits; a second layer provided on the first layer; and a plurality of optical lenses provided on the second layer. The display device has a display region and a plurality of light-receiving regions. The display region has a first pixel circuit provided on the first layer, and a light-emitting element provided on the second layer. Each light-receiving region has: a second pixel circuit provided on the first layer; and a light-receiving element provided on the second layer. The plurality of light-receiving regions are provided around the display region. The optical lenses are provided at positions overlapped with the light-receiving regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One aspect of the present invention relates to a display device and an electronic device. 1. Field of the Invention One aspect of the present invention relates to a wearable electronic device including a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] In recent years, electronic devices for virtual reality (VR) or augmented reality (AR) have been attracting attention. Furthermore, electronic devices for VR or AR equipped with eye-tracking functions have been developed. Electronic devices for VR or AR equipped with eye-tracking functions can be applied to, for example, consumer behavior analysis, image processing, avatar creation, and gaze-based operation.

[0004] For example, Patent Document 1 discloses a head-mounted electronic device that performs gaze tracking using an image of light from an infrared light source reflected by the cornea. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2019-512726 Summary of the Invention [Problem to be solved by the invention]

[0006] In the head-mounted electronic device described above, an optical sensor for tracking the gaze is provided separately from the display device, which poses a problem of increasing the size of the electronic device.

[0007] Furthermore, in a display device of a head-mounted electronic device, a light-receiving element of an optical sensor for tracking the gaze may be integrated with a light-emitting element of the display device. In this case, in order to capture a clear image of the eyeball, it is preferable to place an optical lens between the display device and the light-receiving element. However, in a display device having a light-emitting element as well as a light-receiving element, if an optical lens for capturing an image is placed, the light emitted from the light-emitting element will be blocked by the optical lens. Therefore, it may be difficult to simultaneously display an image with excellent display quality and capture a clear image.

[0008] An object of one embodiment of the present invention is to provide a display device and an electronic device that are miniaturized. Another object of one embodiment of the present invention is to provide a display device and an electronic device that can display an image with excellent display quality and capture a clear image. Another object of one embodiment of the present invention is to provide a novel display device and an electronic device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a display device including a first layer in which a plurality of pixel circuits are provided, a second layer provided over the first layer, and a plurality of optical lenses provided over the second layer, the display region having a display area and a plurality of light-receiving regions, the display region having a light-emitting element provided in the second layer, the light-receiving region having a plurality of light-receiving elements provided in the second layer, the plurality of light-receiving regions being provided around the display region, and the optical lenses being provided in a position overlapping with the light-receiving region.

[0011] One embodiment of the present invention is a display device including a first layer, a second layer provided over the first layer, and a plurality of optical lenses provided over the second layer, the display region including a first pixel circuit provided in the first layer and a light-emitting element provided in the second layer, the light-receiving region including a second pixel circuit provided in the first layer and a light-receiving element provided in the second layer, the plurality of light-receiving regions provided around the display region, and the optical lenses provided so as to overlap with the light-receiving region.

[0012] In one embodiment of the present invention, the display device is preferably such that the spacing between the wirings for driving the second pixel circuits provided in the light-receiving region is smaller than the spacing between the wirings for driving the first pixel circuits provided in the display region.

[0013] In one embodiment of the present invention, the resolution of an image captured by a light-receiving element provided in the light-receiving region is preferably higher than the resolution of an image displayed by a light-emitting element provided in the display region.

[0014] In one embodiment of the present invention, the display device preferably has a rectangular display region, and the light receiving regions are disposed at the four corners of the rectangular region.

[0015] One embodiment of the present invention is preferably a display device having a first layer, a second layer provided over the first layer, and a plurality of optical lenses provided over the second layer, and having a display region and a plurality of light-receiving regions, in which the display region has a first pixel circuit provided in the first layer and a light-emitting element provided in the second layer, the light-receiving region has a second pixel circuit provided in the first layer and a light-receiving element provided in the first layer, the plurality of light-receiving regions are provided around the display region, and the optical lenses are provided in a position overlapping with the light-receiving region.

[0016] In one embodiment of the present invention, the display device preferably includes a third layer, the third layer includes a driver circuit, and the driver circuit is disposed so as to overlap with a display region.

[0017] In one embodiment of the present invention, the third layer preferably has an arithmetic circuit, and the arithmetic circuit preferably has a function of tracking the gaze based on image data captured by the plurality of light-receiving regions.

[0018] In one embodiment of the present invention, the display device preferably includes a first transistor having a semiconductor layer including silicon in a channel formation region, and a first pixel circuit including the first transistor.

[0019] In one embodiment of the present invention, the display device preferably includes a second transistor in which the first layer includes a semiconductor layer having a metal oxide in a channel formation region.

[0020] In one embodiment of the present invention, the metal oxide preferably includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.

[0021] In one embodiment of the present invention, the light-receiving element is a display device having an organic semiconductor.

[0022] One aspect of the present invention is an electronic device having a housing and the above-mentioned display device, wherein the housing has the display device in a position where it can capture an image of a user's eye, and the light-receiving area has the function of capturing an image of the user's eye and / or the area around the eye.

[0023] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0024] According to one embodiment of the present invention, it is possible to provide a display device and an electronic device that are miniaturized, or a display device and an electronic device that can display an image with excellent display quality and capture a clear image, or a novel display device and an electronic device.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0026] [Figure 1] 1A and 1B are diagrams illustrating an example of the configuration of a display device. [Figure 2] 2A and 2B are diagrams illustrating an example of the configuration of an electronic device having a display device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a display device. [Figure 4] 4A and 4B are diagrams illustrating an example of the configuration of a display device. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a display device. [Figure 6] 6(A) and 6(B) are diagrams illustrating an example of the configuration of a display device. [Figure 7] 7A and 7B are diagrams illustrating an example of the configuration of a display device. [Figure 8] 8(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 9] 9(A) and 9(B) are diagrams illustrating an example of the configuration of a display device. [Figure 10] 10(A) and 10(B) are diagrams illustrating an example of the configuration of a display device. [Figure 11] 11(A) and (B) are diagrams illustrating an inference process based on a neural network NN. [Figure 12] 12(A) and 12(B) are diagrams illustrating an example of the configuration of a display device. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of a display device. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of a display device. [Figure 15]15A to 15C are diagrams illustrating a configuration example of a display device. [Figure 16] 16A to 16C are diagrams illustrating a configuration example of a display device. [Figure 17] 17(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 18] 18(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 19] 19A to 19D are diagrams illustrating a configuration example of a display device. [Figure 20] 20A to 20D are diagrams illustrating configuration examples of display devices. [Figure 21] 21A to 21E are diagrams illustrating configuration examples of display devices. [Figure 22] FIG. 22 is a diagram illustrating an example of the configuration of a display device. [Figure 23] FIG. 23 is a diagram illustrating an example of the configuration of a display device. [Figure 24] 24A to 24C are diagrams illustrating a configuration example of a display device. [Figure 25] Figure 25(A) is a diagram explaining the classification of IGZO crystal structures, Figure 25(B) is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 25(C) is a diagram explaining the micro-electron beam diffraction pattern of a CAAC-IGZO film. [Figure 26] 26A to 26D are diagrams illustrating configuration examples of display devices. [Figure 27] 27A to 27D are diagrams illustrating configuration examples of display devices. [Figure 28] 28A to 28D are diagrams illustrating examples of the configuration of a display device. [Figure 29] 29(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 30] 30(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 31]31A to 31G are diagrams illustrating examples of the configuration of a display device. [Figure 32] FIG. 32 is a diagram illustrating an example of the configuration of a display device. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0028] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0029] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state) when a voltage V between the gate and the source of an n-channel transistor is applied. gs is the threshold voltage V th (For p-channel transistors, V th This refers to a state of being (higher than)

[0030] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0031] (Embodiment 1) In one embodiment of the present invention, a display device and an electronic device according to one embodiment of the present invention are described. The display device according to one embodiment of the present invention can be suitably used as a display device included in a wearable electronic device for VR and AR applications.

[0032] <Display device configuration example 1> 1A is a perspective view illustrating a structural example of a display device according to one embodiment of the present invention. FIG. 1B is a top view illustrating a structural example of a display device according to one embodiment of the present invention. The display device 10 includes a layer 11, a layer 12, and an optical lens 17. The display device 10 includes a display region 13 and a light-receiving region 14.

[0033] The display area 13 is an area where light-emitting elements 61 are provided and where an image is displayed by emitting light toward the user (viewer). As shown in FIG. 1(B), the display area 13 can be arranged near the center of the rectangular display device 10 to ensure a large display area 13 in the display device 10. The display area 13 is preferably a rectangular area, and more preferably has a shape with four notched corners, as will be described later. Note that, in this embodiment, a rectangular display area 13 is illustrated, but is not limited to this. For example, the present invention can also be applied to display areas with non-rectangular shapes (typically, hexagonal, octagonal, and circular).

[0034] In the display region 13, a pixel circuit (not shown) for controlling the light intensity of the light-emitting element 61 is provided in the layer 11, and the light-emitting element 61 is provided in the layer 12. This pixel circuit may be referred to as a first pixel circuit or a pixel circuit for light-emission control. The pixel circuit for controlling light emission has a plurality of transistors, capacitors, etc. The transistors and capacitors of the pixel circuit for controlling light emission are provided in an area overlapping with the light-emitting element 61. The display region 13 may also be configured to include circuits other than the pixel circuits, such as a drive circuit for driving the pixel circuits and an arithmetic circuit for performing arithmetic processing of signals.

[0035] The light-emitting element 61 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 61 is not limited to this, and may be, for example, an inorganic EL element made of an inorganic material. Note that "organic EL element" and "inorganic EL element" may be collectively referred to as "EL element." The light-emitting element 61 may have an inorganic compound such as quantum dots. For example, quantum dots may be used in the light-emitting layer to function as a light-emitting material.

[0036] The light receiving area 14 is an area where a light receiving element 62 is provided and generates a signal by receiving light from the user side. The light receiving element 62 is an element that converts optical energy into electrical energy and is sometimes called a photoelectric conversion element. As shown in FIG. 1(B), the light receiving area 14 is preferably arranged in an area where the four corners of the display area 13 provided in the rectangular display device 10 are cut out. In other words, it is preferable to configure the light receiving area 14 so that multiple light receiving areas 14 are provided around the display area 13. By reducing the area of ​​the light receiving area 14, the display area 13 can be made approximately rectangular.

[0037] If the display device 10 has a shape other than a rectangle, such as a polygon or ellipse, the light receiving areas 14 are preferably provided around the display area 13, such as at the corners or edges of the display area 13. This configuration allows multiple light receiving areas 14 to be arranged without affecting the display of the display area 13.

[0038] Furthermore, in the light receiving region 14, a pixel circuit (not shown) for controlling imaging data (also referred to as a readout signal, etc.) obtained by receiving light from the light receiving element 62 is provided in layer 11, and the light receiving element 62 is provided in layer 12. This pixel circuit is sometimes referred to as a second pixel circuit or a pixel circuit for controlling light reception. The pixel circuit for controlling light reception has a plurality of transistors, capacitors, etc. The transistors and capacitors of the pixel circuit for controlling light reception are provided in an area overlapping with the light receiving element 62. Furthermore, the light receiving region 14 may be configured to include circuits other than the pixel circuit, such as a drive circuit for driving the pixel circuit and an arithmetic circuit for performing arithmetic processing of signals.

[0039] The light-receiving element 62 may be, for example, a photodiode having spectral sensitivity characteristics in the visible light wavelength range. The active layer of the photodiode includes a semiconductor. Examples of such semiconductors include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. Using an organic semiconductor for the active layer of the light-receiving element 62 allows the light-emitting layer of the light-emitting element 61 and the active layer of the light-receiving element 62 to be formed by the same method (e.g., vacuum deposition), which is preferable because it allows for common manufacturing equipment. Furthermore, the light-emitting layer of the light-emitting element 61 and the active layer of the light-receiving element 62 can be formed without using a metal mask or a fine metal mask (FMM), as will be described in detail in a later embodiment. This allows the light-emitting element 61 and the light-receiving element 62 to be arranged with increased precision.

[0040] In this specification and the like, the term “element” may be replaced with “device” in some cases. For example, a display element, a light-emitting element, and a liquid crystal element may be replaced with a display device, a light-emitting device, and a liquid crystal device, for example.

[0041] The display device 10 also has a terminal unit for supplying various signals and power supply potentials to the display device 10. In FIGS. 1A and 1B, a terminal unit 15 provided in the layer 11 is illustrated. Although FIGS. 1A and 1B illustrate the layers 11 and 12 as layers included in the display device 10, a configuration in which layers other than the layers 11 and 12 are provided may also be used. The above-described driver circuit and / or arithmetic circuit may be provided in a layer other than the layers 11 and 12.

[0042] In the display device 10, a plurality of optical lenses 17 are provided on the layer 12 in an area overlapping with the plurality of light-receiving regions 14. The optical lenses 17 may be optical elements that refract, diverge, or focus light. Preferably, the optical lenses 17 are spherical lenses, aspherical lenses, or Fresnel lenses. By arranging the optical lenses 17 so that they overlap the light-receiving regions 14, the optical path of reflected light from the subject (e.g., the user's pupil) can be adjusted, and light can be focused by refracting light in accordance with the density of the plurality of light-receiving elements 62 that serve as the focal point. A suitable gap may be provided between the layer 12 and the optical lenses 17.

[0043] FIG. 2(A) is a diagram illustrating a configuration example in which the display device 10 described in FIGS. 1(A) and 1(B) is applied to a head-mounted electronic device 100. The example illustrated in FIG. 2(A) illustrates a perspective view of the head-mounted electronic device 100. In the electronic device 100 illustrated in FIG. 2(A), a pair of display devices 10_L and 10_R are provided in a housing 101. FIG. 2(A) also illustrates the eyes 102 (eyeballs) of a user wearing the electronic device 100. As illustrated in FIG. 2(A), the pair of display devices 10_L and 10_R are positioned, for example, so as to overlap with the eyes 102. Note that the housing 101 may be provided with an acceleration sensor such as a gyro sensor to detect the orientation of the user's head and display an image according to that orientation.

[0044] The display devices 10_L and 10_R can capture images of the user's eye 102 as well as movements around the eyeball, such as the eyelid, the space between the eyebrows, the inner corner of the eye, and the outer corner of the eye, in the light-receiving region 14. As shown in FIG. 2(A), the diagonal length (panel size) of the display devices 10_L and 10_R is preferably approximately the same as the length of the eye 102 when it is wide open. In this case, the panel size of the display devices 10_L and 10_R is 0.1 inches to 5 inches diagonally, preferably 0.5 inches to 3 inches diagonally, more preferably 1 inch to 2 inches diagonally, more preferably 1.3 inches to 1.7 inches diagonally, and even more preferably 1.5 inches to 1.6 inches diagonally. This configuration allows a display region 13 corresponding to the size of the eye 102 and a light-receiving region 14 corresponding to the size of the eye 102 to be provided. In other words, when the display device 10 is brought close to the user's eye 102, information about the user's eye 102 and its surroundings can be obtained by the light receiving area 14, and the field of view of the image displayed in the display area 13 can be enlarged.

[0045] In this specification, for example, when describing matters common to the display devices 10_L and 10_R, or when there is no need to distinguish between them, the display device may simply be referred to as "display device 10."

[0046] FIG. 2(B) is a schematic diagram illustrating a case where a display device 10 including the display region 13 and the light-receiving region 14 described in FIGS. 1(A) and 1(B) is provided near a user's eye 102. Note that FIG. 2(B) illustrates an example of the arrangement of the display region 13 and the light-receiving region 14, with the display region 13 being disposed between the light-receiving regions 14. Also, in FIG. 2(B), it is preferable to provide another optical lens, such as an optical lens 18, between the layer 12 and the eye 102. The optical lens 18 is preferably a spherical lens, an aspherical lens, or a Fresnel lens. This configuration allows an image corresponding to the light emitted from the display region 13 to be enlarged and viewed by the eye 102, thereby improving visibility when viewing the display device 10 on the electronic device 100.

[0047] The user's eye 102 can view an image using light from the light-emitting elements 61 in the display region 13. The light emitted by the light-emitting elements 61 may include not only visible light but also infrared light and other light.

[0048] Furthermore, light (also referred to as reflected light) from the user's eye 102 and / or its surroundings is converted into an electrical signal by the light receiving element 62 in the light receiving area 14 via the optical lens 18 and the optical lens 17. The information acquired by the light receiving area 14 may be an image of the eyeball (or the state of the pupil) for gaze tracking, or an image of movement around the eyeball (for example, the eyelid, between the eyebrows, inner corner of the eye, outer corner of the eye, etc.).

[0049] As described above, the display device of one embodiment of the present invention can have a structure in which the light-emitting element in the display region and the light-receiving element in the light-receiving region are integrated by being provided in the same layer. Therefore, compared to a structure in which the display device and the light-receiving device are provided as separate devices, the number of components can be reduced, and thus the size and weight of an electronic device including the display device can be reduced.

[0050] A display device according to one embodiment of the present invention has a configuration in which a light-receiving region is provided in a region surrounding the display region, and an optical lens overlaps with the light-receiving region. Therefore, even when the distance to a subject, such as when capturing an image of a user's eye, is short, a clear image can be captured. In one embodiment of the present invention, when an optical lens for capturing an image is disposed in a region overlapping with the light-receiving region, light emitted from a light-emitting element in the display region can be prevented from being blocked by the optical lens. In one embodiment of the present invention, the light-receiving region and the optical lens can overlap, enabling capture of a clear image and achieving both display of an image with high display quality and capture of a clear image, such as displaying an image with high display quality in the display region.

[0051] FIG. 3(A) is a perspective view that schematically shows the configuration of the layer 11 and the layer 12 in the display device 10 shown in FIG. 1(B).

[0052] The layer 11 is provided with a pixel circuit 51 and a pixel circuit 52. The layer 12 is provided with a light emitting element 61 and a light receiving element 62.

[0053] The pixel circuit 51 and the light-emitting element 61 function as a unit element that controls the intensity of light. Here, the unit element that controls the intensity of light refers to a "sub-pixel," which is the smallest unit that operates independently within one "pixel." In some cases, the "pixel" may be replaced with "region" and the "pixel" may be replaced with "sub-pixel." In FIG. 3A, a pixel provided in the display region 13 having the pixel circuit 51 and the light-emitting element 61 is illustrated as pixel 71.

[0054] The pixel circuit 52 and the light receiving element 62 function as a unit element that controls the capture of reflected light. Here, the unit element that controls the capture of reflected light refers to a "sub-pixel," which is the smallest unit that operates independently within a single "pixel." In some cases, the "pixel" may be replaced with "region" and the "pixel" may be replaced with "sub-pixel." In FIG. 3A, a pixel provided in the light receiving region 14 having the pixel circuit 52 and the light receiving element 62 is illustrated as pixel 72.

[0055] The pixel circuit 51 and the pixel circuit 52 included in the layer 11 each include a transistor 31 (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in a channel formation region 32. The pixel circuit 51 and the pixel circuit 52 can each include an OS transistor. Note that the layer 12 can also be formed by stacking layers including an OS transistor.

[0056] By using an organic semiconductor for the active layer of the light-receiving element 62, the light-emitting layer of the light-emitting element 61 and the active layer of the light-receiving element 62 can be formed by the same method (e.g., vacuum deposition), and the pixels 71 and 72 can be arranged at an extremely high density. For example, in the display region 13 of the display device 10, pixels can be arranged at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, but 20,000 ppi or less, or 30,000 ppi or less. Because of its extremely high resolution, such a display device 10 can be suitably used in VR devices such as head-mounted displays or eyeglass-type AR devices.

[0057] 3B shows a block diagram of each component of the layer 11, the layer 12, and the optical lens 17 in FIG. 3A. The pixel circuit 51 in the layer 11 supplies a current I according to image data to the light-emitting element 61 in the layer 12. EL The light emitting element 61 outputs a current I EL The light receiving element 62 in the layer 12 receives the light 14A through the optical lens 17, and emits a light 13A corresponding to the light 14A. IMG flows to the pixel circuit 52, and the pixel circuit 52 receives a photocurrent I IMG The read data generated by the above is output.

[0058] FIG. 4(A) shows a perspective view of a display device 10A in which the configuration of the layer 11 and the layer 12 is different from that of the display device 10 shown in FIG. 3(A).

[0059] The layer 11 is provided with a pixel circuit 51 and a pixel circuit 52. The layer 12 is provided with a light emitting element 61 and a light receiving element 62.

[0060] The pixel circuit 51 and the light-emitting element 61 function as a unit element that controls the intensity of light. Here, the unit element that controls the intensity of light refers to a "sub-pixel," which is the smallest unit that operates independently within one "pixel." In some cases, the "pixel" may be replaced with "region" and the "pixel" may be replaced with "sub-pixel." In FIG. 4A, a pixel provided in the display region 13 having the pixel circuit 51 and the light-emitting element 61 is illustrated as pixel 71.

[0061] The pixel circuit 52 and the light receiving element 62 function as a unit element that controls the capture of reflected light. Here, the unit element that controls the capture of reflected light refers to a "sub-pixel," which is the smallest unit that operates independently within a single "pixel." In some cases, the "pixel" may be replaced with "region" and the "pixel" may be replaced with "sub-pixel." In FIG. 4A, a pixel provided in the light receiving region 14 having the pixel circuit 52 and the light receiving element 62 is illustrated as a pixel 72.

[0062] The pixel circuit 51 and the pixel circuit 52 included in the layer 11 each include a transistor 33 having silicon in a channel formation region 34 (also referred to as a Si transistor).

[0063] The transistor 33 can be, for example, a transistor having single crystal silicon in a channel formation region (also referred to as a "c-Si transistor"). In particular, when a transistor having single crystal silicon in a channel formation region is used as the transistor provided in the layer 11, the on-state current of the transistor can be increased. Therefore, it is preferable because the circuit included in the layer 11 can be driven at high speed. Furthermore, since a c-Si transistor can be formed by microfabrication to have a channel length of 3 nm to 10 nm, it can be used in the display device 10 in which an accelerator such as a CPU or a GPU, an application processor, or the like is integrally provided with the display portion.

[0064] Furthermore, a transistor having polycrystalline silicon in a channel formation region (also referred to as a "Poly-Si transistor") may be used as the transistor provided in the layer 11. Low temperature polysilicon (LTPS) may be used as the polycrystalline silicon. Note that a transistor having LTPS in a channel formation region is also referred to as an "LTPS transistor."

[0065] Layer 11 may include a Si transistor. For example, pixel circuit 51 and pixel circuit 52 may include transistors having single crystal silicon or polycrystalline silicon in their channel formation regions. LTPS may be used as the polycrystalline silicon. For example, a layer having a Si transistor may be formed on a separate substrate and then bonded to layer 11 of display device 10.

[0066] Furthermore, for example, the pixel circuits 51 and 52 may be configured with multiple types of transistors using different semiconductor materials. When the pixel circuits 51 and 52 are configured with multiple types of transistors using different semiconductor materials, the transistors made of different semiconductor materials may be provided in different layers. For example, when the pixel circuits 51 and 52 are configured with Si transistors and OS transistors, the Si transistors and the OS transistors may be provided stacked. By providing the transistors stacked, the area occupied by the pixel circuits 51 and 52 is reduced. This allows for an improvement in the resolution of the display device 10. Note that a configuration combining LTPS transistors and OS transistors is sometimes referred to as LTPO.

[0067] By using an organic semiconductor for the active layer of the light-receiving element 62, the light-emitting layer of the light-emitting element 61 and the active layer of the light-receiving element 62 can be formed by the same method (e.g., vacuum deposition), and the pixels 71 and 72 can be arranged at an extremely high density. For example, in the display region 13 of the display device 10, pixels can be arranged at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, but 20,000 ppi or less, or 30,000 ppi or less. Because of its extremely high resolution, such a display device 10 can be suitably used in VR devices such as head-mounted displays or eyeglass-type AR devices.

[0068] 4B shows a block diagram of each component of the layer 11, the layer 12, and the optical lens 17 in FIG. 4A. The pixel circuit 51 in the layer 11 supplies a current I according to image data to the light-emitting element 61 in the layer 12. EL The light emitting element 61 outputs a current I EL The light receiving element 62 in the layer 12 receives the light 14A through the optical lens 17, and emits a light 13A corresponding to the light 14A. IMG flows to the pixel circuit 52, and the pixel circuit 52 receives a photocurrent I IMG The read data generated by the above is output.

[0069] 3A, the pixel circuits 52 and the light receiving elements 62 in the light receiving region 14 are preferably arranged at high density. This configuration increases the resolution of the light receiving elements 62, enabling good imaging.

[0070] The above-mentioned configuration will be described with reference to Fig. 5. The display device 10 shown in Fig. 5 includes a display area 13 and a plurality of light receiving areas 14_1 to 14_4. The wiring SL shown in Fig. 5 DIS 5. The wiring SL shown in FIG. 5 is a signal line electrically connected to the pixel circuit 51 (not shown). IMG5. The wiring GL DIS 5. The wiring GL IMG Schematically represents a scanning line electrically connected to a pixel circuit 52 (not shown).

[0071] As shown in FIG. 5, in one embodiment of the present invention, the wiring GL IMG , S.L. IMG The interval is the wiring GL DIS , S.L. DIS In other words, it is preferable that the resolution of an image captured by the light receiving elements 62 provided in the light receiving regions 14_1 to 14_4 is greater than the resolution of an image displayed by the light emitting elements 61 provided in the display region 13. With this configuration, the density of each element can be varied in each region, thereby increasing the resolution of the light receiving elements 62 and enabling good imaging.

[0072] As described above, the display device of one embodiment of the present invention can have a structure in which the light-emitting element in the display region and the light-receiving element in the light-receiving region are integrated by being provided in the same layer. Therefore, compared to a structure in which the display device and the light-receiving device are provided as separate devices, the number of components can be reduced, and thus the size and weight of an electronic device including the display device can be reduced.

[0073] In one embodiment of the present invention, a display device has a light-receiving region provided in a region surrounding the display region, and an optical lens overlaps the light-receiving region. Therefore, even when the distance to a subject, such as when capturing an image of a user's eye, is short, a clear image can be captured. In one embodiment of the present invention, when an optical lens for capturing an image is disposed in a region overlapping the light-receiving region, light emitted from a light-emitting element in the display region can be prevented from being blocked by the optical lens. In one embodiment of the present invention, the light-receiving region and the optical lens can overlap, enabling capture of a clear image and achieving both high-quality image display and capture of a clear image in the display region.

[0074] <Configuration example 2 of the display device> 6(A) and 6(B), a configuration different from that of the display device 10A shown in FIGS. 4(A) and 4(B) will be described.

[0075] The perspective view of the display device 10B shown in Figure 6(A) illustrates a configuration in which, in addition to the pixel circuit 52, a light receiving element 62S is provided in an area overlapping with the light receiving region 14 of the layer 11 in which the transistor 33, which is a Si transistor, is provided.

[0076] 6A can be a layer provided on a silicon substrate, and therefore, a structure in which the light-receiving element 62S is provided using a Si photodiode or the like can be used. The Si photodiode can be formed by adding an impurity element to a silicon substrate to form a pn diode, a pin diode, or the like. The structure of FIG. 6A can realize a structure according to one embodiment of the present invention without forming the light-emitting layer of the light-emitting element 61 and the active layer of the light-receiving element 62 in the layer 12 by the same method (e.g., vacuum evaporation).

[0077] 6B shows a block diagram of each component of the layer 11, the layer 12, and the optical lens 17 in FIG. 6A. The pixel circuit 51 in the layer 11 supplies a current I according to image data to the light emitting element 61 in the layer 12. ELThe light emitting element 61 outputs a current I EL The light receiving element 62S in the layer 11 receives the light 14A through the layer 12 and the optical lens 17, and thereby a photocurrent I IMG flows to the pixel circuit 52, and the pixel circuit 52 receives a photocurrent I IMG The read data generated by the above is output.

[0078] <Configuration example 3 of the display device> 7(A) and 7(B), a configuration different from that of the display device 10 shown in FIGS. 3(A) and 3(B) will be described.

[0079] 7A is a perspective view of a display device 10C, which is similar to the configuration shown in FIG. 3A, except that a layer 40 is added. The layer 40 includes a drive circuit 41 that outputs various signals for driving the pixel circuits 51.

[0080] 7A includes a driver circuit 41 in a layer 40 having a transistor 33 with silicon in a channel formation region 34. Since the layer 40 can be a layer provided on a silicon substrate, the OS transistor in the layer 11 can be formed directly on the layer 40. The layer 11 and the layer 40 can also be electrically connected using Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conduction by connecting Cu (copper) pads together).

[0081] The driving circuit 41 includes, for example, a gate driver circuit, a source driver circuit, etc. In addition, the driving circuit 41 may include an arithmetic circuit, a memory circuit, a power supply circuit, etc. Since the gate driver circuit, the source driver circuit, and other circuits can be arranged overlapping the display region 13, the width of the non-display region (also called a frame) existing around the periphery of the display region 13 of the display device 10C can be made extremely narrow compared to when these circuits and the display region 13 are arranged side by side, and a compact display device 10C can be realized.

[0082] 7(B) shows a block diagram of each component of the layers 40, 11, 12, and optical lens 17 in FIG. 7(A). The driving circuit 41 in the layer 40 outputs a data signal DS and a scanning signal GS for driving the pixel circuit 51 in the layer 11. The pixel circuit 51 in the layer 11 supplies a current I according to image data to the light emitting element 61 in the layer 12. EL The light emitting element 61 outputs a current I EL The light receiving element 62 in the layer 12 receives the light 14A through the optical lens 17, and emits a light 13A corresponding to the light 14A. IMG flows to the pixel circuit 52, and the pixel circuit 52 receives a photocurrent I IMG The read data generated by the above is output.

[0083] The configuration of layer 40 described in Figures 7(A) and 7(B) can be applied to the display device 10A shown in Figures 4(A) and 4(B). In this case, the electrical connection between layer 11 and layer 40 can also be achieved by Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conduction by connecting Cu (copper) pads together). An example configuration in this case is shown in Figures 8(A) and (B).

[0084] <Display device configuration example 4> 9(A) and 9(B), a configuration different from that of the display device 10 shown in FIG. 3(A) and FIG. 3(B) will be described.

[0085] 9(A) is a perspective view of a display device 10D, which shows a configuration in which a layer 40 is added to the configuration shown in FIG. 3(A). The layer 40 has a drive circuit 41 that outputs various signals for driving the pixel circuits 52, and an arithmetic circuit 42 that performs arithmetic processing on read data obtained by the pixel circuits 52.

[0086] 9A includes a driver circuit 41 and an arithmetic circuit 42 in a layer 40, each of which has a transistor 33 having silicon in a channel formation region 34. Since the layer 40 can be a layer provided on a silicon substrate, the OS transistor in the layer 11 can be formed directly on the layer 40. The layer 11 and the layer 40 can also be electrically connected using Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conduction by connecting Cu (copper) pads together).

[0087] The drive circuit 41 includes, for example, a gate driver circuit, a source driver circuit, etc. In addition, the drive circuit 41 may include an arithmetic circuit, a memory circuit, a power supply circuit, etc. The gate driver circuit, the source driver circuit, and other circuits can be arranged overlapping the display region 13. This allows the width of the non-display region (also called a frame) around the periphery of the display region 13 of the display device 10D to be made extremely narrow compared to when these circuits and the display region 13 are arranged side by side, thereby enabling a compact display device 10D to be realized.

[0088] The arithmetic circuit 42 is a circuit having a function of executing, for example, product-sum arithmetic processing in an artificial neural network. For example, it is a circuit having a function of performing inference processing based on a hierarchical neural network such as a deep neural network (DNN) or a convolutional neural network (CNN). The arithmetic circuit 42 can track the gaze of an image of a user's pupil by performing arithmetic processing using the current flowing through the light receiving element 62 or the read data obtained by the pixel circuit 52 as input data.

[0089] Note that gaze tracking techniques include the Pupil Center Corneal Reflection method and the Bright / Dark Pupil Effect method, and either method may be applied. Alternatively, in one embodiment of the present invention, a combination of multiple methods, for example, an appropriate combination of the Pupil Center Corneal Reflection method and the pupil method, may be applied. Note that when performing gaze tracking with high accuracy, it is preferable to increase the reflected light, and in this case, it is preferable to place the infrared light source near the eyeball.

[0090] The arithmetic circuit 42 may have a function of correcting the data signal or the like provided to the pixel circuit 51 in accordance with the amount of current flowing through the pixel circuit 51. In other words, the arithmetic circuit 42 may have a function as a correction circuit for monitoring and correcting the amount of current flowing through the pixel circuit 51. For example, the arithmetic circuit 42 may be configured to estimate the amount of current flowing from the pixel circuit 51 when the display device 10D is started up, and correct the signal for controlling the light intensity of the light-emitting element 61 in accordance with that amount of current. This makes it possible to reduce display defects caused by variations in the current flowing through the pixel circuit 51 from one pixel circuit to another.

[0091] 9(B) shows a block diagram of each component of the layer 40, layer 11, layer 12, and optical lens 17 in FIG. 9(A). The driving circuit 41 in the layer 40 outputs a data signal DS and a scanning signal GS for driving the pixel circuit 51 in the layer 11. The pixel circuit 51 in the layer 11 supplies a current I according to image data to the light emitting element 61 in the layer 12. EL The light emitting element 61 outputs a current I EL The light receiving element 62 in the layer 12 receives the light 14A through the optical lens 17, and emits a light 13A corresponding to the light 14A. IMG flows to the pixel circuit 52, and the pixel circuit 52 receives a photocurrent I IMG The read data R generated by D The calculation circuit 42 in the layer 40 outputs the photocurrent I IMG and / or read data R D The configuration can be such that the gaze of the user's pupil is tracked using the above as input data.

[0092] The configuration of layer 40 described in Figures 9(A) and 9(B) can be applied to the display device 10A shown in Figures 4(A) and 4(B). Figures 10(A) and (B) show an example configuration in which layer 11, on which transistor 33 is provided, is placed on layer 40, on which transistor 33 is provided. In the configurations of Figures 10(A) and (B), layer 11 and layer 40 can be electrically connected by applying Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conductivity by connecting Cu (copper) pads together).

[0093] In FIG. 11(A), in the block diagram shown in FIG. 9(B), output data D is output by performing inference processing based on the neural network NN of the arithmetic circuit 42. OUT is illustrated.

[0094] An example of inference processing in the neural network NN will be described with reference to Fig. 11(B). The arithmetic circuit 42 capable of arithmetic processing based on the neural network NN captures an image of the user's eye 102 and its surroundings with the light receiving elements 62 of the light receiving area 14, and outputs the current flowing through the light receiving elements 62 and / or read data R D is used as input data. The arithmetic circuit 42 performs a product-sum operation using weight data and the like stored in the arithmetic circuit 42, and executes arithmetic processing based on a neural network. The output data D obtained by the arithmetic circuit 42 is OUT For example, multiple lines of sight such as "line of sight 1" to "line of sight n" can be inferred from the user's eye 102 and its surroundings.

[0095] Examples of neural networks that can be used include convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders (AEs), variational autoencoders (VAEs), random forests, support vector machines, gradient boosting, and generative adversarial networks (GANs).

[0096] The configurations described in Figures 9(A) and 9(B) can be applied to the display device 10B shown in Figures 6(A) and 6(B). A perspective view of this case is shown in Figure 12(A), and a block diagram corresponding to the perspective view of Figure 12(A) is shown in Figure 12(B). The configuration of the display device 10E shown in Figures 12(A) and 12(B) can also operate in the same manner as the display device 10D shown in Figures 9(A) and 9(B). The electrical connection between layer 11 and layer 40 can also be achieved by Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conduction by connecting Cu (copper) pads together).

[0097] Furthermore, the above-described eye tracking is not limited to calculation processing based on a neural network, but may be configured to be calculated based on image data obtained from a plurality of light receiving areas. As an example, as shown in the schematic diagram of FIG. 13, image data R obtained from each of a plurality of light receiving areas 14_1 to 14_4 arranged around the display area 13 may be calculated. D_1 ~R D_4 The eye image data R is obtained from the plurality of eye images 102_1 to 102_4 obtained based on the syn The image may be synthesized to obtain an image of the eye 102, and the image may be analyzed in the arithmetic circuit 42 to perform gaze tracking.

[0098] <Display Device Configuration Example 5> 14 to 16, a modified example of the display device 10C described in Fig. 7A will be described. To reduce repetition of the description, differences from the display device 10C will be mainly described.

[0099] In the perspective view of the display device 10Cp shown in FIG. 14, a section 51p of a pixel circuit section 51P and a section 41p of a drive circuit section 41P are provided so as to overlap each other. The pixel circuit section 51P is an area where a plurality of pixel circuits 51 described in FIG. 7(A) are provided. The drive circuit section 41P is an area where a drive circuit 41 described in FIG. 7(A) is provided. In the display device 10Cp, the pixel circuit section 51P is divided into a plurality of sections 51p, and the drive circuit section 41P is divided into a plurality of sections 41p. Each of the plurality of sections 41p has a source driver circuit 43 and a gate driver circuit 44.

[0100] FIG. 15(A) shows a configuration example of a pixel circuit unit 51P included in the display device 10Cp. FIG. 15(B) shows a configuration example of a drive circuit unit 41P included in the display device 10Cp. The partitions 51p and the partitions 41p are each arranged in a matrix of m rows and n columns (m and n are each integers equal to or greater than 1). In this specification, the partition 51p in the first row and first column is referred to as partition 51[1,1], and the partition 51p in the mth row and nth column is referred to as partition 51[m,n]. Similarly, the partition 41p in the first row and first column is referred to as partition 41[1,1], and the partition 41p in the mth row and nth column is referred to as partition 41[m,n]. FIGS. 15(A) and 15(B) show a case where m is 4 and n is 8. That is, the pixel circuit unit 51P and the drive circuit unit 41P are each divided into 32 sections.

[0101] Each of the plurality of sections 51p has a plurality of pixel circuits 51, a plurality of wirings SL, and a plurality of wirings GL. In each of the plurality of sections 51p, one of the plurality of pixel circuits 51 is electrically connected to one of the plurality of wirings SL and one of the plurality of wirings GL.

[0102] One of the sections 51p and one of the sections 41p are arranged to overlap (see FIG. 15(C)). For example, the section 51[i,j] (i is an integer between 1 and m, inclusive, and j is an integer between 1 and n, inclusive) and the section 41[i,j] are arranged to overlap. The source driver circuit 43 of the section 41[i,j] is electrically connected to the wiring SL of the section 51[i,j]. The gate driver circuit 44 of the section 41[i,j] is electrically connected to the wiring GL of the section 51[i,j]. The gate driver circuit 44 of the section 41[i,j] has the function of controlling the multiple pixel circuits 51 of the section 41[i,j].

[0103] By overlapping the section 51[i,j] and the section 41[i,j], the connection distance (wiring length) between the pixel circuit 51 in the section 51[i,j] and the source driver circuit 43 and gate driver circuit 44 in the section 41[i,j] can be made extremely short. As a result, the wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. In addition, power consumption can be reduced.

[0104] Furthermore, the display device 10Cp has a configuration in which each section 41p has a source driver circuit 43 and a gate driver circuit 44. Therefore, the display area 13 can be divided into sections 51p corresponding to the sections 41p, and images can be rewritten. For example, it is possible to rewrite image data only in sections of the display area 13 where changes have occurred in the image, and to retain image data in sections where no changes have occurred, thereby reducing power consumption.

[0105] In the present embodiment and other embodiments, one of the display areas 13 divided into sections 51p is referred to as a sub-display section 19. FIG. 16(A) shows a case where the display area 13 is divided into 32 sub-display sections 19 in the display device 10Cp described with reference to FIGS. 14 and 15(A) to 15(C). The sub-display sections 19 include a plurality of pixels 71. Specifically, one sub-display section 19 includes one of the sections 51p including a plurality of pixel circuits 51 and a plurality of light-emitting elements 61. Furthermore, one section 41p has the function of controlling the plurality of pixels 71 included in one sub-display section 19.

[0106] Furthermore, the display device 10Cp can arbitrarily set the drive frequency (such as frame frequency) for displaying an image for each sub-display unit 19 by using a timing controller that controls the drive circuit 41. Therefore, the drive frequency can be arbitrarily set for each sub-display unit 19.

[0107] In the display device of one embodiment of the present invention, pixel circuits and driver circuits are stacked and the drive frequency of each sub-display portion 19 is made different depending on the movement of the line of sight, thereby achieving low power consumption.

[0108] FIG. 16A shows a display area 13 having sub-display units 19 arranged in four rows and eight columns. FIG. 16A also shows a first area S1 to a third area S3 centered around a point of gaze G. The sub-display units 19 in the display area 13 are divided into a first section 29A that overlaps with the first area S1 or the second area S2, and a second section 29B that overlaps with the third area S3. In this case, the first section 29A that overlaps with the first area S1 or the second area S2 near the user's point of gaze G is the sub-display unit 19 at and near the point of gaze G, and the second section 29B is the sub-display unit 19 located outside the first section 29A and far from the user's point of gaze G (see FIG. 16B).

[0109] The operation of the drive circuits (source driver circuit 43 and gate driver circuit 44) of each of the multiple sections 41p is controlled by a timing controller. For example, by setting the drive frequency of the second section 29B lower than that of the first section 29A, it is possible to reduce the power consumption required for displaying an image at a location far from the gaze point G where the user's visibility is low. This allows for low power consumption of the display device 10Cp. By reducing the frequency of rewriting image data for each section, it is possible to reduce power consumption.

[0110] The drive frequency of the first section 29A is 30 Hz to 500 Hz, preferably 60 Hz to 500 Hz. The drive frequency of the second section 29B is preferably equal to or lower than the drive frequency of the first section 29A, more preferably equal to or lower than half the drive frequency of the first section 29A, and more preferably equal to or lower than one-fifth the drive frequency of the first section 29A.

[0111] Furthermore, among the sub-display units 19 that overlap with the third region S3, the sub-display unit 19 that is located farther from the gaze point G may be set as the third section 29C, and rewriting (updating) of the image data of the sub-display unit 19 included in the third section 29C may be stopped (see FIG. 16(C)). By stopping the rewriting of the image data, power consumption can be further reduced.

[0112] When such a driving method is used, it is preferable to use a transistor with an extremely low off-state current as the transistor that constitutes pixel circuit 51. For example, it is preferable to use an OS transistor as the transistor that constitutes pixel circuit 51. Because the OS transistor has an extremely low off-state current, it can hold image data supplied to pixel circuit 51 for a long period of time.

[0113] <Configuration example of electronic device equipped with display device> FIG. 17(A) is a perspective view showing the rear, bottom, and right side of an electronic device 100 having the display device 10 described above.

[0114] 17(A), a housing 101 of an electronic device 100 includes, as an example, a mounting portion 106, a buffer member 107, and a pair of lenses 108 in addition to a pair of display devices 10_L and 10_R. Display areas 13 of the pair of display devices 10_L and 10_R are provided in positions inside the housing 101 that can be viewed through the lenses 108.

[0115] The light receiving areas 14 of the pair of display devices 10_L and 10_R are provided at positions where information about the user's eye 102 and its surroundings can be acquired. Note that acquisition of information about the user's eye 102 and its surroundings in the light receiving areas 14 may be performed via a lens 108 inside the housing 101 or may be performed without using the lens 108.

[0116] 17(A) is provided with an input terminal 109 and an output terminal 110. A cable can be connected to the input terminal 109 to supply an image signal (image data) from a video output device or the like, or power for charging a battery provided within the housing 101. The output terminal 110 functions as, for example, an audio output terminal, and earphones, headphones, etc. can be connected.

[0117] Furthermore, the housing 101 preferably has a mechanism for adjusting the left-right positions of the lens 108 and the display devices 10_L and 10_R so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that the housing 101 has a mechanism for adjusting the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0118] The cushioning member 107 is a portion that comes into contact with the user's face (forehead, cheeks, etc.). The cushioning member 107 makes close contact with the user's face, thereby preventing light leakage and enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it can come into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels good on the skin and does not make the user feel cold when worn in cold seasons, etc. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the wearing part 106, removable, as this makes cleaning or replacement easier.

[0119] The electronic device according to one embodiment of the present invention may further include earphones 106A. The earphones 106A have a communication unit (not shown) and have a wireless communication function. The earphones 106A can output audio data using the wireless communication function. The earphones 106A may also have a vibration mechanism to function as bone conduction earphones.

[0120] 17(B), the earphone 106A can be configured to be directly connected to the wearing unit 106 or connected by wire. The earphone 106B and the wearing unit 106 may have a magnet. This allows the earphone 106B to be fixed to the wearing unit 106 by magnetic force, which is preferable as it makes storage easier.

[0121] <Three-dimensional structure of driving circuits, pixel circuits, and light-emitting elements> 18(A) and 18(B) show a configuration example of a pixel circuit 51 and a light-emitting element 61 connected to the pixel circuit 51. Fig. 18(A) is a diagram showing the connection of each element, and Fig. 18(B) is a diagram schematically showing the hierarchical relationship between a layer 40 including a drive circuit 41, a layer 11 including a plurality of transistors included in the pixel circuit 51, and a layer 12 including the light-emitting element 61.

[0122] 18(A) and 18(B) includes a transistor 55A, a transistor 55B, a transistor 55C, and a capacitor 56. The transistors 55A, 55B, and 55C can be OS transistors. Each of the OS transistors 55A, 55B, and 55C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from that of the gate electrode.

[0123] The transistor 55B includes a gate electrode electrically connected to the transistor 55A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to a wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0124] Transistor 55A has a first terminal electrically connected to the gate electrode of transistor 55B, a second terminal electrically connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0125] The transistor 55C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light-emitting element 61, and a gate electrode that controls the conductive state or non-conductive state based on the potential of the wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the drive circuit 41 or the arithmetic circuit 42.

[0126] The capacitor 56 includes a conductive film electrically connected to the gate electrode of the transistor 55B and a conductive film electrically connected to the second electrode of the transistor 55C.

[0127] The light-emitting element 61 includes a first electrode electrically connected to the first electrode of the transistor 55B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0128] This makes it possible to control the intensity of light emitted by the light-emitting element 61 in accordance with an image signal applied to the gate electrode of the transistor 55B. Also, the reference potential of the wiring V0 applied via the transistor 55C can suppress variations in the gate-source voltage of the transistor 55B.

[0129] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 55B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the arithmetic circuit 42 or the like.

[0130] In the configuration shown as an example in FIG. 18(B), the wiring electrically connecting the pixel circuit 51 and the driver circuit 41 can be shortened, thereby reducing the wiring resistance of the wiring. Therefore, data can be written at high speed, allowing the display device 10 to be driven at high speed. This allows a sufficient frame period to be secured even if the display device 10 has a large number of pixel circuits 51, thereby increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 increases the resolution of the image displayed by the display device 10. Therefore, the display device 10 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices such as HMDs, in which the display area is close to the user.

[0131] 18(A) and 18(B), the layer 11, the layer 12, and the layer 40 may also be provided with the above-mentioned arithmetic circuit 42, pixel circuit 52, and light-receiving element 62. Specifically, the light-receiving element 62 may be provided in the layer 11, the pixel circuit 52 may be provided in the layer 12, and the arithmetic circuit 42 may be provided in the layer 40.

[0132] 18A and 18B show an example of the pixel circuit 51 including three transistors in total, but one embodiment of the present invention is not limited to this. Below, a configuration example of a pixel circuit that can be applied to the pixel circuit 51 will be described.

[0133] The pixel circuit 51A shown in Fig. 19A includes a transistor 55A, a transistor 55B, and a capacitor 56. Fig. 19A also illustrates a light-emitting element 61 connected to the pixel circuit 51A. Fig. 19A also illustrates a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM.

[0134] The transistor 55A has a gate electrically connected to the wiring GL, one of its source and drain electrically connected to the wiring SL, and the other electrically connected to the gate of the transistor 55B and one electrode (conductive film) of the capacitor 56. The transistor 55B has one of its source and drain electrically connected to the wiring ANO, and the other electrically connected to the anode of the light-emitting element 61. The capacitor 56 has the other electrode electrically connected to the anode of the light-emitting element 61. The light-emitting element 61 has a cathode electrically connected to the wiring VCOM.

[0135] 19B has a configuration in which a transistor 55C is added to the pixel circuit 51A. A wiring V0 is electrically connected to the pixel circuit 51B.

[0136] A pixel circuit 51C shown in FIG. 19(C) is an example in which transistors each having a pair of gates are used as the transistors 55A and 55B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 19(D) is an example in which the same transistors are used in the pixel circuit 51B. This allows the current that the transistors can pass to be increased. Note that, although transistors each having a pair of gates are used for all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0137] 20A is configured by adding a transistor 55D to the pixel circuit 51B. The pixel circuit 51E is electrically connected to three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines.

[0138] The gate of the transistor 55D is electrically connected to the wiring GL3, one of the source and the drain of the transistor 55B is electrically connected to the wiring V0, and the gate of the transistor 55A is electrically connected to the wiring GL1, and the gate of the transistor 55C is electrically connected to the wiring GL2.

[0139] By simultaneously turning on transistors 55C and 55D, the source and gate of transistor 55B have the same potential, making it possible to turn off transistor 55B. This makes it possible to forcibly cut off the current flowing through light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0140] 20B is an example in which a capacitor 56A is added to the pixel circuit 51E. The capacitor 56A functions as a storage capacitor.

[0141] 20(C) and 20(D) are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or the pixel circuit 51F, respectively. Transistors each having a pair of gates electrically connected to each other are applied to the transistor 55A, the transistor 55C, and the transistor 55D, and a transistor each having one gate electrically connected to its source is applied to the transistor 55B.

[0142] Next, pixel circuits 52A to 52E are shown in Figures 21(A) to 21(E) as examples of pixel circuit configurations applicable to the pixel circuit 52 electrically connected to the light-receiving element 62. Also shown in Figures 21(A) to 21(E) are wiring SE, wiring RS, wiring WX, and wiring TX. For example, wiring SE is a wiring that transmits a selection signal for reading data from the pixel circuit. For example, wiring RS is a wiring that transmits a reset signal that initializes the pixel circuit. For example, wiring WX is a wiring that transmits a signal read from the pixel circuit. For example, wiring TX is a wiring that transmits a transfer signal that controls the current flowing through the light-receiving element 62. The pixel circuit 52 is also connected to wiring that transmits a constant potential.

[0143] A pixel circuit 52A shown in Fig. 21A has transistors 57A, 57B, and 57C, and a capacitor 58, and the transistors and capacitors are connected as shown in Fig. 21A. Fig. 21A also shows a light-receiving element 62 connected to the pixel circuit 52A.

[0144] A pixel circuit 52B shown in Figure 21(B) has a configuration in which the transistor 57B in the pixel circuit 52A is replaced with a transistor having a pair of gates. A pixel circuit 52C shown in Figure 21(C) is an example in which transistors having a pair of gates are used as the transistors 57A to 57C in the pixel circuit 52A. A pixel circuit 52D shown in Figure 21(D) is an example in which the arrangement of the transistor 57C is changed. A pixel circuit 52E shown in Figure 21(E) is an example in which a transistor 57D is added.

[0145] As described above, the display device of one embodiment of the present invention can have a structure in which the light-emitting element in the display region and the light-receiving element in the light-receiving region are integrated by being provided in the same layer. Therefore, compared to a structure in which the display device and the light-receiving device are provided as separate devices, the number of components can be reduced, and thus the size and weight of an electronic device including the display device can be reduced.

[0146] In one embodiment of the present invention, a display device has a light-receiving region provided in a region surrounding the display region, and an optical lens overlaps with the light-receiving region. Therefore, even when the distance to a subject, such as when capturing an image of a user's eye, is short, a clear image can be captured. In one embodiment of the present invention, when an optical lens for capturing an image is disposed in a region overlapping with the light-receiving region, light emitted from a light-emitting element in the display region can be prevented from being blocked by the optical lens. In one embodiment of the present invention, the light-receiving region and the optical lens can overlap, enabling clear image capture and achieving both high-quality image display and clear image capture, such as displaying an image with excellent display quality in the display region.

[0147] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0148] (Embodiment 2) In this embodiment, details of each component of a display device 10 according to one embodiment of the present invention will be described.

[0149] <Examples of cross-sectional configurations of light-emitting elements and transistors> 22 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 has a substrate 121 and a substrate 122, and the substrates 121 and 122 are bonded together with a sealant 712.

[0150] For example, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used as the substrate 121. Note that a semiconductor substrate other than a single crystal semiconductor substrate may also be used as the substrate 121.

[0151] The transistor 441 and the transistor 601 are provided over the substrate 121. The transistor 441 and the transistor 601 can be the transistor provided in the layer 40 described in Embodiment 1 (for example, the transistor 33).

[0152] The transistor 441 includes a conductor 443 serving as a gate electrode, an insulator 445 serving as a gate insulator, and a part of the substrate 121. The transistor 441 also includes a semiconductor region 447 including a channel formation region, a low-resistance region 449a serving as one of a source region and a drain region, and a low-resistance region 449b serving as the other of the source region and the drain region. The transistor 441 may be either a p-channel type or an n-channel type.

[0153] The transistor 441 is electrically isolated from other transistors by an element isolation layer 403. Fig. 22 shows a case where the transistor 441 and the transistor 601 are electrically isolated by the element isolation layer 403. The element isolation layer 403 can be formed by a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

[0154] 22 has a convex semiconductor region 447. A conductor 443 is provided to cover the side surface and the top surface of the semiconductor region 447 with an insulator 445 interposed therebetween. Note that the conductor 443 covering the side surface of the semiconductor region 447 is not shown in FIG. A material that adjusts the work function can be used for the conductor 443.

[0155] A transistor having a convex semiconductor region, such as the transistor 441, can be called a fin transistor because it utilizes the convex portion of a semiconductor substrate. Note that an insulator that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Also, while FIG. 22 shows a configuration in which the convex portion is formed by processing a part of the substrate 121, a semiconductor having a convex portion may be formed by processing an SOI substrate.

[0156] 22 is just an example, and is not limited to this configuration, and may be an appropriate configuration depending on the circuit configuration, the operation method of the circuit, etc. For example, the transistor 441 may be a planar transistor.

[0157] The transistor 601 can have a structure similar to that of the transistor 441 .

[0158] In addition to the element isolation layer 403, the transistor 441, and the transistor 601, an insulator 405, an insulator 407, an insulator 409, and an insulator 411 are provided on the substrate 121. A conductor 451 is embedded in the insulator 405, the insulator 407, the insulator 409, and the insulator 411. Here, the height of the top surface of the conductor 451 and the height of the top surface of the insulator 411 can be made approximately the same.

[0159] An insulator 421 and an insulator 214 are provided on the conductor 451 and the insulator 411. A conductor 453 is embedded in the insulator 421 and the insulator 214. Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 can be made approximately the same.

[0160] An insulator 216 is provided on the conductor 453 and the insulator 214. A conductor 455 is embedded in the insulator 216. Here, the height of the top surface of the conductor 455 and the height of the top surface of the insulator 216 can be made approximately the same.

[0161] Insulators 222, 224, 254, 280, 274, and 281 are provided on conductor 455 and insulator 216. Conductor 305 is embedded in insulators 222, 224, 254, 280, 274, and 281. Here, the height of the top surface of conductor 305 and the height of the top surface of insulator 281 can be made approximately the same.

[0162] An insulator 361 is provided on the conductor 305 and on the insulator 281. The conductor 317 and the conductor 337 are embedded in the insulator 361. Here, the height of the top surface of the conductor 337 and the height of the top surface of the insulator 361 can be made approximately the same.

[0163] An insulator 364 is provided on the conductor 337 and on the insulator 361. The conductors 347, 353, 355, and 357 are embedded in the insulator 364. Here, the height of the upper surfaces of the conductors 353, 355, and 357 can be made approximately the same as the height of the upper surface of the insulator 364.

[0164] Connection electrodes 760 are provided on the conductors 353, 355, 357, and insulator 364. An anisotropic conductor 780 is provided so as to be electrically connected to the connection electrodes 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 10 from outside the display device 10 via the FPC 716.

[0165] 22 , the low-resistance region 449b, which functions as the other of the source region and the drain region of the transistor 441, is electrically connected to the FPC 716 through the conductor 451, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780. Here, although FIG. 22 shows three conductors, the conductor 353, the conductor 355, and the conductor 357, as conductors that electrically connect the connection electrode 760 and the conductor 347, one embodiment of the present invention is not limited thereto. The number of conductors that electrically connect the connection electrode 760 and the conductor 347 may be one, two, or four or more. By providing a plurality of conductors that electrically connect the connection electrode 760 and the conductor 347, contact resistance can be reduced.

[0166] A transistor 750 is provided over the insulator 214. The transistor 750 can be the transistor provided in the layer 11 described in Embodiment 1 (for example, the transistor 31). For example, the transistor 750 can be the transistor provided in the pixel circuit 51. An OS transistor can be suitably used as the transistor 750. An OS transistor has an extremely low off-state current. Therefore, the retention time of image data and the like can be extended, thereby reducing the frequency of a refresh operation. Therefore, the power consumption of the display device 10 can be reduced.

[0167] Conductor 301a and conductor 301b are embedded in insulator 254, insulator 280, insulator 274, and insulator 281. Conductor 301a is electrically connected to one of the source and drain of transistor 750, and conductor 301b is electrically connected to the other of the source and drain of transistor 750. Here, the height of the top surfaces of conductor 301a and conductor 301b and the height of the top surface of insulator 281 can be made approximately the same.

[0168] The conductor 311, the conductor 313, the conductor 331, the capacitor 790, the conductor 333, and the conductor 335 are embedded in the insulator 361. The conductor 311 and the conductor 313 are electrically connected to the transistor 750 and function as wirings. The conductor 333 and the conductor 335 are electrically connected to the capacitor 790. Here, the height of the top surfaces of the conductor 331, the conductor 333, and the conductor 335 can be made approximately the same as the height of the top surface of the insulator 361.

[0169] Conductor 341, conductor 343, and conductor 351 are embedded in insulator 364. Here, the height of the top surface of conductor 351 and the height of the top surface of insulator 364 can be made approximately the same.

[0170] The insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 364 function as interlayer films and may also function as planarizing films that cover the uneven shapes below them. For example, the top surface of the insulator 364 may be planarized by planarization treatment using chemical mechanical polishing (CMP) or the like to improve flatness.

[0171] 22, the capacitor 790 has a lower electrode 721 and an upper electrode 725. An insulator 723 is provided between the lower electrode 721 and the upper electrode 725. That is, the capacitor 790 has a layered structure in which the insulator 723, which functions as a dielectric, is sandwiched between a pair of electrodes. Note that while FIG. 22 shows an example in which the capacitor 790 is provided on the insulator 281, the capacitor 790 may be provided on an insulator different from the insulator 281.

[0172] FIG. 22 shows an example in which conductors 301a, 301b, and 305 are formed in the same layer. It also shows an example in which conductors 311, 313, 317, and the lower electrode 721 are formed in the same layer. It also shows an example in which conductors 331, 333, 335, and 337 are formed in the same layer. It also shows an example in which conductors 341, 343, and 347 are formed in the same layer. It also shows an example in which conductors 351, 353, 355, and 357 are formed in the same layer. Forming multiple conductors in the same layer can simplify the manufacturing process of the display device 10, thereby reducing the manufacturing cost of the display device 10. These conductors may be formed in different layers and may be made of different types of materials.

[0173] 22 includes a light-emitting element 61. The light-emitting element 61 includes a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0174] Examples of materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, while examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0175] The conductor 772 is electrically connected to the other of the source and the drain of the transistor 750 through the conductor 351, the conductor 341, the conductor 331, the conductor 313, and the conductor 301b. The conductor 772 is formed over the insulator 364 and functions as a pixel electrode.

[0176] A material that is transparent to or reflective to visible light can be used for the conductor 772. For example, an oxide material containing indium, zinc, tin, or the like can be used as the light-transmitting material. For example, a material containing aluminum, silver, or the like can be used as the reflective material.

[0177] Although not shown in FIG. 22, the display device 10 can be provided with optical members (optical substrates) such as a polarizing member, a phase difference member, an anti-reflection member, and the like.

[0178] A light-shielding layer 738 and an insulator 734 in contact with the light-shielding layer 738 are provided on the substrate 122 side. The light-shielding layer 738 has a function of blocking light emitted from an adjacent region. Alternatively, the light-shielding layer 738 has a function of blocking external light from reaching the transistor 750 and the like.

[0179] 22, an insulator 730 is provided over an insulator 364. Here, the insulator 730 can be configured to cover part of a conductor 772. Furthermore, the light-emitting element 61 includes a light-transmitting conductor 788 and can be a top-emission light-emitting element.

[0180] The light-shielding layer 738 is provided so as to have a region overlapping with the insulator 730. The light-shielding layer 738 is covered with the insulator 734. The space between the light-emitting element 61 and the insulator 734 is filled with the sealing layer 732.

[0181] Furthermore, structure 778 is disposed between insulator 730 and EL layer 786. Structure 778 is also disposed between insulator 730 and insulator 734.

[0182] FIG. 23 shows a modified example of the display device 10 shown in FIG. 22. The display device 10 shown in FIG. 23 differs from the display device 10 shown in FIG. 22 in that a colored layer 736 is provided. The colored layer 736 is provided so as to have an area overlapping with the light-emitting element 61. By providing the colored layer 736, the color purity of the light extracted from the light-emitting element 61 can be increased. This allows the display device 10 to display a high-quality image. Furthermore, since all of the light-emitting elements 61 of the display device 10 can be light-emitting elements that emit white light, it is not necessary to form the EL layer 786 by different colors, and the display device 10 can have high definition.

[0183] The light emitting element 61 can have a micro-optical resonator (microcavity) structure. This allows light of a predetermined color (for example, RGB) to be extracted without providing a colored layer, and the display device 10 can perform color display. By configuring the display device 10 without providing a colored layer, it is possible to suppress light absorption by the colored layer. This allows the display device 10 to display high-brightness images and reduce the power consumption of the display device 10. Note that even when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, formed by coloring, it is also possible to configure the display device 10 without providing a colored layer. Note that the luminance of the display device 10 can be, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 More than 10000cd / m 2 or less, more preferably 2000 cd / m 2 More than 5000cd / m 2 It can be as follows:

[0184] <Configuration example of OS transistor> FIG. 24(A), FIG. 24(B), and FIG. 24(C) are top views and cross-sectional views of a transistor 750 that can be used in a display device according to an aspect of the present invention, and the periphery of the transistor 750. The transistor 750 can be applied to a display device according to an aspect of the present invention.

[0185] FIG. 24(A) is a top view of the transistor 750. FIGS. 24(B) and FIG. 24(C) are cross-sectional views of the transistor 750. Here, FIG. 24(B) is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 24(A), and is also a cross-sectional view in the channel length direction of the transistor 750. FIG. 24(C) is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 24(A), and is also a cross-sectional view in the channel width direction of the transistor 750. In the top view of FIG. 24(A), some elements are omitted for clarity of the drawing.

[0186] As shown in FIG. 24 , the transistor 750 includes a metal oxide 230a disposed on a substrate (not shown), a metal oxide 230b disposed on the metal oxide 230a, a conductor 242a and a conductor 242b disposed spaced apart from each other on the metal oxide 230b, an insulator 280 disposed on the conductors 242a and 242b and having an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed among the metal oxide 230b, the conductors 242a, 242b, and the insulator 280, and the conductor 260, and a metal oxide 230c disposed among the metal oxide 230b, the conductors 242a, 242b, the insulator 280, and the insulator 250. 24(B) and 24(C), it is preferable that the top surface of the conductor 260 substantially coincides with the top surfaces of the insulators 250, 254, metal oxide 230c, and 280. Note that, hereinafter, the metal oxides 230a, 230b, and 230c may be collectively referred to as metal oxide 230. Furthermore, the conductors 242a and 242b may be collectively referred to as conductor 242.

[0187] 24, the side surfaces of the conductors 242a and 242b facing the conductor 260 have a substantially vertical shape. Note that the transistor 750 shown in FIG. 24 is not limited to this, and the angle formed between the side surface and the bottom surface of the conductors 242a and 242b may be 10° or more and 80° or less, preferably 30° or more and 60° or less. Furthermore, the opposing side surfaces of the conductors 242a and 242b may have multiple surfaces.

[0188] 24, it is preferable that an insulator 254 be disposed between the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductor 242a, the conductor 242b, and the metal oxide 230c and the insulator 280. Here, it is preferable that the insulator 254 be in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224, as shown in FIGS.

[0189] Although the transistor 750 has a three-layer structure of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c in and around a region where a channel is formed (hereinafter also referred to as a channel formation region), the present invention is not limited to this. For example, a two-layer structure of the metal oxide 230b and the metal oxide 230c or a stacked structure of four or more layers may be provided. Furthermore, the transistor 750 has a two-layer structure of the conductor 260, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may have a stacked structure of two or more layers.

[0190] For example, when metal oxide 230c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of metal oxide 230b, and the second metal oxide has a composition similar to that of metal oxide 230a.

[0191] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source and drain electrodes, respectively. As described above, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260, 242a, and 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 750, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 260 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 750. This allows for a high-resolution display device. Furthermore, the display device can have a narrow frame.

[0192] As shown in FIG. 24, the conductor 260 preferably has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0193] The transistor 750 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. A metal oxide 230a is preferably disposed on the insulator 224.

[0194] An insulator 274, which functions as an interlayer film, and an insulator 281 are preferably disposed over the transistor 750. Here, the insulator 274 is preferably disposed in contact with top surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280.

[0195] It is preferable that insulators 222, 254, and 274 have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that insulators 222, 254, and 274 have lower hydrogen permeability than insulators 224, 250, and 280. It is also preferable that insulators 222 and 254 have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, it is preferable that insulators 222 and 254 have lower oxygen permeability than insulators 224, 250, and 280.

[0196] Here, insulator 224, metal oxide 230, and insulator 250 are separated by insulators 280 and 281, and by insulators 254 and 274. Therefore, impurities such as hydrogen and excess oxygen contained in insulators 280 and 281 can be prevented from being mixed into insulator 224, metal oxide 230a, metal oxide 230b, and insulator 250.

[0197] It is preferable that a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 750 and functioning as a plug be provided. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 functioning as a plug. That is, the insulator 241 is provided in contact with the inner wall of the opening of the insulators 254, 280, 274, and 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inside. Here, the height of the top surface of the conductor 240 and the height of the insulator 281 can be made approximately the same. Note that, in the transistor 750, a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is described, but the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, it may be distinguished by assigning an ordinal number to the order of formation.

[0198] The transistor 750 preferably uses a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 230 including the channel formation region (the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c). For example, the metal oxide that serves as the channel formation region of the metal oxide 230 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more.

[0199] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). Furthermore, it is preferable that it contains an element M in addition to these. The element M can be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that the element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is more preferable that the element M contains either or both of Ga and Sn.

[0200] 24(B), the film thickness of the metal oxide 230b in the region that does not overlap with the conductor 242 may be thinner than the film thickness of the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is formed on the upper surface of the metal oxide 230b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent a channel from being formed in that region.

[0201] The detailed structure of a transistor 750 that can be used in a display device according to one embodiment of the present invention will be described.

[0202] The conductor 205 is disposed so as to have an overlapping region with the metal oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216.

[0203] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 216. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0204] Conductor 205a and conductor 205c are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0205] By using a conductive material capable of reducing hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the metal oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material capable of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0206] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0207] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed independently of the potential applied to the conductor 260, thereby controlling the V th In particular, applying a negative potential to conductor 205 can control the V th It is possible to make the off-state current smaller by making the potential greater than 0 V. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no potential is applied.

[0208] The conductor 205 is preferably provided to be larger than the channel formation region of the metal oxide 230. In particular, as shown in Fig. 24(C), it is preferable that the conductor 205 also extends to a region outside the end portion intersecting with the channel width direction of the metal oxide 230. In other words, it is preferable that the conductor 205 and the conductor 260 overlap with each other with an insulator interposed therebetween on the outside of the side surface of the metal oxide 230 in the channel width direction.

[0209] With the above structure, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260 that functions as a first gate electrode and the electric field of the conductor 205 that functions as a second gate electrode.

[0210] 24(C), the conductor 205 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor that functions as a wiring may be provided below the conductor 205.

[0211] The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the substrate side. Therefore, the insulator 214 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., the impurities are less likely to permeate through the insulator). Alternatively, the insulator 214 is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through the insulator).

[0212] For example, aluminum oxide, silicon nitride, or the like is preferably used for the insulator 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 214 to the transistor 750 side. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing from the insulator 214 to the substrate side.

[0213] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as the insulators 216, 280, and 281 as appropriate.

[0214] The insulators 222 and 224 function as gate insulators.

[0215] Here, the insulator 224 in contact with the metal oxide 230 preferably releases oxygen upon heating. In this specification, oxygen released upon heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced, and the reliability of the transistor 750 can be improved.

[0216] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0217] 24(C), the thickness of the insulator 224 in a region that does not overlap with the insulator 254 and the metal oxide 230b may be thinner than the thickness of the other regions. It is preferable that the thickness of the insulator 224 in a region that does not overlap with the insulator 254 and the metal oxide 230b is a thickness that allows sufficient diffusion of the oxygen.

[0218] Like the insulator 214 and the like, the insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, the insulator 250, and the like with the insulators 222, 254, and 274, impurities such as water or hydrogen can be prevented from entering the transistor 750 from the outside.

[0219] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. The insulator 222 preferably has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the metal oxide 230 toward the substrate side. Furthermore, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 or the metal oxide 230.

[0220] The insulator 222 may be an insulator containing an oxide of one or both of insulating materials, aluminum and hafnium. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the metal oxide 230 and the intrusion of impurities such as hydrogen from the periphery of the transistor 750 into the metal oxide 230.

[0221] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0222] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0223] The insulator 222 and the insulator 224 may have a layered structure of two or more layers. In this case, the layered structure is not limited to layers made of the same material, and may be layers made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0224] The metal oxide 230 includes a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. By providing the metal oxide 230a below the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b. Furthermore, by providing the metal oxide 230c on the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the metal oxide 230c to the metal oxide 230b.

[0225] The metal oxide 230 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide 230 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 230a to the number of atoms of all elements constituting the metal oxide 230a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. The atomic ratio of the element M contained in the metal oxide 230a to In is also preferably higher than the atomic ratio of the element M contained in the metal oxide 230b to In. Here, the metal oxide 230c can be any metal oxide that can be used for the metal oxide 230a or the metal oxide 230b.

[0226] The energy of the conduction band minimum of the metal oxide 230a and the metal oxide 230c is preferably higher than the energy of the conduction band minimum of the metal oxide 230b. In other words, the electron affinity of the metal oxide 230a and the metal oxide 230c is preferably lower than the electron affinity of the metal oxide 230b. In this case, the metal oxide 230c is preferably a metal oxide that can be used for the metal oxide 230a. Specifically, the ratio of the number of atoms of the element M contained in the metal oxide 230c to the number of atoms of all elements constituting the metal oxide 230c is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. Furthermore, the atomic ratio of the element M contained in the metal oxide 230c to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 230b to In.

[0227] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c. In other words, the energy level of the conduction band minimum at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c.

[0228] Specifically, the metal oxide 230a and the metal oxide 230b, and the metal oxide 230b and the metal oxide 230c, can form a mixed layer with a low defect level density by having a common element other than oxygen (as a main component). For example, when the metal oxide 230b is an In-Ga-Zn oxide, the metal oxide 230a and the metal oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like. The metal oxide 230c may also have a layered structure. For example, a layered structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a layered structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide, can be used. In other words, the metal oxide 230c may have a layered structure of an In-Ga-Zn oxide and an oxide that does not contain In.

[0229] Specifically, metal oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. Metal oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. Metal oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the metal oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide, etc. The atomic ratios described above and in the following explanation include not only the atomic ratios shown as examples but also ratios of values ​​close to them.

[0230] In this case, the main carrier path is the metal oxide 230b. By configuring the metal oxide 230a and the metal oxide 230c as described above, the defect state density at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 750 to achieve a high on-state current and high frequency characteristics. Note that when the metal oxide 230c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the metal oxide 230b and the metal oxide 230c, it is expected that the diffusion of constituent elements of the metal oxide 230c toward the insulator 250 can be suppressed. More specifically, by configuring the metal oxide 230c as a stacked structure and positioning an oxide that does not contain In above the stacked structure, it is possible to suppress In that may diffuse toward the insulator 250. Because the insulator 250 functions as a gate insulator, diffusion of In can cause poor transistor characteristics. Therefore, by forming the metal oxide 230c into a laminated structure, it is possible to provide a highly reliable display device.

[0231] Conductors 242 (conductors 242a and 242b) functioning as a source electrode and a drain electrode are provided on the metal oxide 230b. Conductor 242 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0232] By providing the conductor 242 so as to be in contact with the metal oxide 230, the oxygen concentration may decrease in the vicinity of the conductor 242 of the metal oxide 230. Furthermore, a metal compound layer containing the metal contained in the conductor 242 and components of the metal oxide 230 may be formed in the vicinity of the conductor 242 of the metal oxide 230. In such a case, the carrier density increases in the region of the metal oxide 230 in the vicinity of the conductor 242, and this region becomes a low-resistance region.

[0233] Here, the region between the conductor 242a and the conductor 242b is formed to overlap the opening of the insulator 280. This allows the conductor 260 to be arranged in a self-aligned manner between the conductor 242a and the conductor 242b.

[0234] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the metal oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0235] The insulator 250 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0236] A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. This makes it possible to suppress oxidation of the conductor 260 due to oxygen in the insulator 250.

[0237] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 250 and the metal oxide, it is possible to achieve a stacked structure that is thermally stable and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0238] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0239] Although the conductor 260 is shown as having a two-layer structure in FIG. 24, it may have a single-layer structure or a laminated structure of three or more layers.

[0240] The conductor 260a is preferably made of a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0241] Conductor 260a has the function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of conductor 260b caused by oxygen contained in insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0242] Conductor 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0243] 24(A) and 24(C), in a region of the metal oxide 230b that does not overlap with the conductor 242, in other words, in the channel formation region of the metal oxide 230, the conductor 260 is arranged to cover the side surface of the metal oxide 230. This makes it easier for the electric field of the conductor 260, which functions as the first gate electrode, to act on the side surface of the metal oxide 230. This increases the on-state current of the transistor 750, thereby improving the frequency characteristics.

[0244] Like the insulator 214, the insulator 254 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the insulator 280 side. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 24(B) and 24(C), the insulator 254 preferably contacts the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224. This configuration can prevent hydrogen contained in the insulator 280 from entering the metal oxide 230 from the top or side surfaces of the conductor 242a, the conductor 242b, the metal oxide 230a, the metal oxide 230b, and the insulator 224.

[0245] Furthermore, it is preferable that the insulator 254 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0246] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 by sputtering in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near the region where the insulator 254 is in contact with the insulator 254. This allows oxygen to be supplied from this region to the metal oxide 230 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 toward the substrate. In this way, oxygen is supplied to the channel formation region of the metal oxide 230. This reduces oxygen vacancies in the metal oxide 230 and suppresses the transistor from becoming normally on.

[0247] For example, an insulator containing one or both of an oxide of aluminum and hafnium may be formed as the insulator 254. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

[0248] By covering the insulator 224, the insulator 250, and the metal oxide 230 with the insulator 254, which has a barrier property against hydrogen, the insulator 280 is separated from the insulator 224, the metal oxide 230, and the insulator 250 by the insulator 254. This can prevent impurities such as hydrogen from penetrating from the outside of the transistor 750, thereby providing the transistor 750 with good electrical characteristics and reliability.

[0249] The insulator 280 is provided on the insulator 224, the metal oxide 230, and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0250] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 280. The top surface of the insulator 280 may be flattened.

[0251] Similar to the insulator 214, the insulator 274 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. may be used.

[0252] An insulator 281 functioning as an interlayer film is preferably provided over the insulator 274. Like the insulator 224, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen.

[0253] The conductor 240a and the conductor 240b are arranged in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 240a and the conductor 240b are arranged opposite each other with the conductor 260 interposed therebetween. The height of the upper surfaces of the conductor 240a and the conductor 240b may be flush with the upper surface of the insulator 281.

[0254] Note that insulator 241a is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240a is formed in contact with the side surface of insulator 241a. Conductor 242a is located on at least a portion of the bottom of the openings, and conductor 240a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240b is formed in contact with the side surface of insulator 241b. Conductor 242b is located on at least a portion of the bottom of the openings, and conductor 240b is in contact with conductor 242b.

[0255] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0256] When the conductor 240 has a layered structure, it is preferable to use the above-mentioned conductors that have the function of suppressing the diffusion of impurities such as water or hydrogen for the conductors in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a layered structure. The use of such a conductive material can suppress the absorption of oxygen added to the insulator 280 by the conductors 240a and 240b. Furthermore, it can suppress the intrusion of impurities such as water or hydrogen from layers above the insulator 281 into the metal oxide 230 through the conductors 240a and 240b.

[0257] The insulators 241a and 241b may be, for example, insulators that can be used for the insulator 254, etc. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water or hydrogen from the insulator 280, etc., from being mixed into the metal oxide 230 through the conductors 240a and 240b. Furthermore, the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0258] Although not shown, a conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0259] <Transistor constituent materials> The constituent materials that can be used for the transistor will be described.

[0260] [substrate] Substrates for forming transistors may be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having metal nitrides and substrates having metal oxides. Examples of substrates include an insulating substrate with a conductor or semiconductor provided thereon, a semiconductor substrate with a conductor or insulator provided thereon, and a conductive substrate with a semiconductor or insulator provided thereon. Alternatively, these substrates may be used with elements provided thereon. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0261] [Insulator] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0262] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials based on the insulator's function.

[0263] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0264] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0265] The electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulator (such as the insulator 214, the insulator 222, the insulator 254, and the insulator 274) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0266] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be compensated for.

[0267] [conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0268] A plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0269] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure of a combination of a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0270] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0271] <Classification of crystal structures in oxide semiconductors> Classification of crystal structures of oxide semiconductors will be described with reference to Fig. 25A, which illustrates classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0272] As shown in Figure 25(A), oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0273] The structure within the bold frame shown in Figure 25(A) is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0274] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 25(B) shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 25(B) will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 25(B) is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 25(B) is 500 nm.

[0275] As shown in Figure 25(B), a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 25(B), the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0276] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 25(C). Figure 25(C) is a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 25(C) is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0277] As shown in FIG. 25(C), multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0278] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 25A when focusing on their crystal structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0279] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0280] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0281] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0282] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0283] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0284] For example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0285] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by the substitution of metal atoms.

[0286] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current and field-effect mobility of transistors. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in transistor semiconductor layers. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0287] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for an OS transistor enables greater flexibility in the manufacturing process.

[0288] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of these microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when electron diffraction (also known as selected-area electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0289] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0290] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0291] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0292] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0293] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0294] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0295] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0296] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0297] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0298] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0299] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0300] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0301] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0302] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0303] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0304] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0305] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0306] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by SIMS (Secondary Ion Mass Spectrometry)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0307] When an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0308] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0309] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0310] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0311] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0312] (Embodiment 3) A light-emitting element 61 and a light-receiving element 62 that can be used in a display device according to one embodiment of the present invention will be described.

[0313] <Layer structure of light-emitting element> As shown in FIG. 26A, the light-emitting element 61 includes an EL layer 172 between a pair of electrodes (conductive layers 171 and 173). The EL layer 172 can be composed of a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with high electron-injecting properties (electron-injecting layer) and a layer containing a substance with high electron-transporting properties (electron-transporting layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer containing a substance with high hole-injecting properties (hole-injecting layer) and a layer containing a substance with high hole-transporting properties (hole-transporting layer).

[0314] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 26A is referred to as a single structure in this specification and the like.

[0315] 26(B) shows a modified example of the EL layer 172 included in the light-emitting element 61 shown in Fig. 26(A). Specifically, the light-emitting element 61 shown in Fig. 26(B) includes a layer 4430-1 on the conductive layer 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductive layer 173 on the layer 4420-2. For example, when the conductive layer 171 is an anode and the conductive layer 173 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductive layer 171 is used as a cathode and the conductive layer 173 is used as an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0316] Note that a structure in which a plurality of light-emitting layers (a light-emitting layer 4411, a light-emitting layer 4412, and a light-emitting layer 4413) are provided between the layer 4420 and the layer 4430 as shown in FIG. 26C is also an example of a single structure.

[0317] 26(D), a configuration in which a plurality of light-emitting units (EL layers 172a and 172b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure or a stack structure in this specification and the like. Note that the tandem structure makes it possible to realize a light-emitting element capable of emitting light with high brightness.

[0318] 26(D), the EL layers 172a and 172b may emit the same light. For example, the EL layers 172a and 172b may both emit green light.

[0319] Note that a full-color display can be achieved by using a light-emitting element 61 emitting red light (R), a light-emitting element 61 emitting green light (G), and a light-emitting element 61 emitting blue light (B) as sub-pixels to form one pixel. When the display region 13 includes three types of sub-pixels, R, G, and B, the light-emitting elements may be arranged in tandem. Specifically, the EL layer 172a and the EL layer 172b of the R sub-pixel each contain a material capable of emitting red light, the EL layer 172a and the EL layer 172b of the G sub-pixel each contain a material capable of emitting green light, and the EL layer 172a and the EL layer 172b of the B sub-pixel each contain a material capable of emitting blue light. In other words, the light-emitting layer 4411 and the light-emitting layer 4412 may be made of the same material. By making the EL layer 172a and the EL layer 172b emit the same light, the current density per unit of luminance can be reduced. Therefore, the reliability of the light emitting element 61 can be improved.

[0320] The light-emitting element can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 172. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0321] The light-emitting layer may contain two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. It is preferable that a light-emitting element that emits white light has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission, light-emitting materials can be selected such that the respective emissions of the two or more light-emitting materials have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary colors, a light-emitting element that emits white light as a whole can be obtained. The same applies to a light-emitting element that has three or more light-emitting layers.

[0322] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0323] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). TADF materials may also be materials that are in thermal equilibrium between the singlet excited state and the triplet excited state. Because such TADF materials have a short emission lifetime (excitation lifetime), they can suppress a decrease in efficiency in the high-brightness region of light-emitting elements.

[0324] <Method for forming light-emitting element> An example of a method for forming the light emitting element 61 will be described below.

[0325] FIG. 27(A) shows a schematic top view of a display device having a light-emitting element 61. The display device has a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, and a plurality of light-emitting elements 61B that emit blue light. In FIG. 27(A), the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements. The configuration of the light-emitting element 61 shown in FIG. 27(A) may be referred to as an SBS (Side By Side) structure. Although FIG. 27(A) illustrates a configuration having three emitted colors, red (R), green (G), and blue (B), the present invention is not limited to this. For example, a configuration having four or more colors may also be used.

[0326] The light-emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 27(A) shows a stripe arrangement in which light-emitting elements of the same color are arranged in one direction, but the arrangement of the light-emitting elements is not limited to this. The light-emitting elements may be arranged in a delta arrangement, a zigzag arrangement, an S-Stripe RGB arrangement, a pentile arrangement, or the like.

[0327] As the light-emitting elements 61R, 61G, and 61B, it is preferable to use organic EL devices such as OLEDs (Organic Light Emitting Diodes) or QOLEDs (Quantum-dot Organic Light Emitting Diodes). Examples of light-emitting materials that the EL elements have include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials).

[0328] FIG. 27(B) is a schematic cross-sectional view corresponding to the dashed line A1-A2 in FIG. 27(A). FIG. 27(B) shows cross sections of the light-emitting elements 61R, 61G, and 61B. The light-emitting elements 61R, 61G, and 61B are each provided on an insulating layer 363 and include a conductive layer 171 functioning as a pixel electrode and a conductive layer 173 functioning as a common electrode. The insulating layer 363 can be an inorganic insulating film or an organic insulating film, or both. The inorganic insulating film is preferably used as the insulating layer 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films, such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.

[0329] The light-emitting element 61R has an EL layer 172R between the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having an intensity at least in the red wavelength range. The EL layer 172G of the light-emitting element 61G contains a light-emitting organic compound that emits light having an intensity at least in the green wavelength range. The EL layer 172B of the light-emitting element 61B contains a light-emitting organic compound that emits light having an intensity at least in the blue wavelength range.

[0330] The EL layer 172R, the EL layer 172G, and the EL layer 172B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0331] The conductive layer 171 functioning as a pixel electrode is provided for each light-emitting element. The conductive layer 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductive layer 171 functioning as a pixel electrode or the conductive layer 173 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-reflective, a bottom-emission display device can be obtained. Conversely, by making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-transmitting, a top-emission display device can be obtained. Note that by making both the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0332] For example, when the light emitting element 61R is a top emission type, the light 175R emitted from the light emitting element 61R is emitted toward the conductive layer 173. When the light emitting element 61G is a top emission type, the light 175G emitted from the light emitting element 61G is emitted toward the conductive layer 173. When the light emitting element 61B is a top emission type, the light 175B emitted from the light emitting element 61B is emitted toward the conductive layer 173.

[0333] An insulating layer 272 is provided to cover an edge portion of the conductive layer 171 functioning as a pixel electrode. The edge portion of the insulating layer 272 is preferably tapered. The insulating layer 272 can be formed using a material similar to that of the insulating layer 363.

[0334] The insulating layer 272 is provided to prevent erroneous light emission due to unintentional electrical short circuit between adjacent light-emitting elements 61. In addition, when a metal mask is used to form the EL layer 172, the insulating layer 272 also functions to prevent the metal mask from coming into contact with the conductive layer 171.

[0335] The EL layer 172R, the EL layer 172G, and the EL layer 172B each have a region in contact with the upper surface of the conductive layer 171 that functions as a pixel electrode, and a region in contact with the surface of the insulating layer 272. In addition, the ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulating layer 272.

[0336] As shown in Figure 27(B), a gap is provided between two EL layers between light-emitting elements of different colors. In this way, it is preferable that the EL layer 172R, the EL layer 172G, and the EL layer 172B are arranged so as not to contact each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This allows for increased contrast, resulting in a display device with high display quality.

[0337] The EL layer 172R, the EL layer 172G, and the EL layer 172B can be separately fabricated by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they may be separately fabricated by photolithography. By using photolithography, it is possible to realize a high-definition display device that is difficult to achieve using a metal mask.

[0338] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure. Because a display device with an MML structure is fabricated without using a metal mask, it has a higher degree of design freedom for pixel arrangement, pixel shape, etc. than a display device with an MM structure.

[0339] Moreover, a protective layer 271 is provided on the conductive layer 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0340] The protective layer 271 may have, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide (IGZO) may be used for the protective layer 271. Note that the protective layer 271 may be formed by an ALD method, a CVD method, or a sputtering method. Note that, although the protective layer 271 includes an inorganic insulating film, the present invention is not limited to this. For example, the protective layer 271 may have a laminated structure of an inorganic insulating film and an organic insulating film.

[0341] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "Oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford Backscattering Spectrometry (RBS).

[0342] When indium gallium zinc oxide is used as the protective layer 271, it can be processed using a wet etching method or a dry etching method. For example, when IGZO is used as the protective layer 271, a chemical solution such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also called a mixed acid aluminum etching solution)) can be used. The mixed acid aluminum etching solution can have a volume ratio of phosphoric acid:acetic acid:nitric acid:water of approximately 53.3:6.7:3.3:36.7.

[0343] 27C shows a different example. Specifically, FIG. 27C shows a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 172W that emits white light between a conductive layer 171 that functions as a pixel electrode and a conductive layer 173 that functions as a common electrode.

[0344] The EL layer 172W may be configured by stacking two or more light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.

[0345] FIG. 27(C) shows three light-emitting elements 61W lined up. A colored layer 264R is provided on the top of the left light-emitting element 61W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. This allows the display device to display color images.

[0346] Here, the EL layer 172W and the conductive layer 173 functioning as a common electrode are separated between two adjacent light-emitting elements 61W. This prevents unintended light emission due to current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when a stacked EL layer in which a charge-generating layer is provided between two light-emitting layers is used as the EL layer 172W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using this configuration, a display device that combines high resolution and high contrast can be realized.

[0347] The EL layer 172W and the conductive layer 173 functioning as a common electrode are preferably separated by photolithography, which allows the distance between the light-emitting elements to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0348] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductive layer 171 functioning as a pixel electrode and the insulating layer 363 .

[0349] FIG. 27(D) shows an example different from the above. Specifically, FIG. 27(D) shows a configuration in which an insulating layer 272 is not provided between the light-emitting elements 61R, 61G, and 61B. This configuration allows a display device with a high aperture ratio. Furthermore, by not providing the insulating layer 272, the unevenness of the light-emitting elements 61 is reduced, thereby improving the viewing angle of the display device. Specifically, the viewing angle can be set to 150° or more and less than 180°, preferably 160° or more and less than 180°.

[0350] Furthermore, the protective layer 271 covers the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. This configuration can suppress impurities (typically, water, etc.) that can enter from the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. Furthermore, since the leakage current between adjacent light-emitting elements 61 is reduced, the color saturation and contrast ratio are improved and power consumption is reduced.

[0351] 27(D), the top surfaces of the conductive layer 171, the EL layer 172R, and the conductive layer 173 generally coincide with each other. This structure can be formed collectively by using a resist mask or the like after the conductive layer 171, the EL layer 172R, and the conductive layer 173 are formed. This process can also be called self-aligned patterning because the EL layer 172R and the conductive layer 173 are processed using the conductive layer 173 as a mask. Note that although the EL layer 172R has been described here, the EL layer 172G and the EL layer 172B can also have a similar structure.

[0352] 27(D) shows a structure in which a protective layer 273 is further provided on the protective layer 271. For example, the protective layer 271 is formed using an apparatus (typically, an ALD apparatus) capable of depositing a film with high coverage, and the protective layer 273 is formed using an apparatus (typically, a sputtering apparatus) capable of depositing a film with lower coverage than the protective layer 271, thereby making it possible to provide a region 275 between the protective layer 271 and the protective layer 273. In other words, the region 275 is located between the EL layer 172R and the EL layer 172G, and between the EL layer 172G and the EL layer 172B.

[0353] The region 275 contains, for example, one or more selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). The region 275 may also contain, for example, a gas used when forming the protective layer 273. For example, when the protective layer 273 is formed by sputtering, the region 275 may contain one or more of the above Group 18 elements. When the region 275 contains a gas, the gas can be identified by gas chromatography or the like. Alternatively, when the protective layer 273 is formed by sputtering, the gas used during sputtering may also be contained in the film of the protective layer 273. In this case, when the protective layer 273 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like, elements such as argon may be detected.

[0354] Furthermore, when the refractive index of region 275 is lower than the refractive index of protective layer 271, light emitted from EL layer 172R, EL layer 172G, or EL layer 172B is reflected at the interface between protective layer 271 and region 275. This may prevent light emitted from EL layer 172R, EL layer 172G, or EL layer 172B from entering adjacent pixels. This prevents light of different colors from being mixed in with neighboring pixels, thereby improving the display quality of the display device.

[0355] 27(D), the area between light-emitting element 61R and light-emitting element 61G or the area between light-emitting element 61G and light-emitting element 61B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of EL layer 172R and the side surface of EL layer 172G or the distance between the side surface of EL layer 172G and the side surface of EL layer 172B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0356] Furthermore, for example, when the region 275 contains gas, it is possible to isolate the light emitting elements while suppressing color mixing or crosstalk of the light from each light emitting element.

[0357] Alternatively, the region 275 may be filled with a filler. Examples of the filler include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Alternatively, a photoresist may be used as the filler. The photoresist used as the filler may be a positive photoresist or a negative photoresist.

[0358] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device with an SBS structure, the light-emitting device with an SBS structure can consume less power than the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device with an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device with an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0359] FIG. 28A shows a different example. Specifically, the configuration shown in FIG. 28A differs from the configuration shown in FIG. 27D in the configuration of the insulating layer 363. The insulating layer 363 has a recess formed by removing a portion of its upper surface during processing of the light-emitting elements 61R, 61G, and 61B. A protective layer 271 is formed in the recess. In other words, the insulating layer 363 has a region where the lower surface of the protective layer 271 is located lower than the lower surface of the conductive layer 171 in a cross-sectional view. By providing this region, impurities (typically, water, etc.) that may enter the light-emitting elements 61R, 61G, and 61B from below can be suitably suppressed. Note that the recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements 61R, 61G, and 61B are removed by wet etching or the like during processing. After removing the residue, the side surfaces of the light-emitting elements are covered with the protective layer 271, thereby achieving a highly reliable display device.

[0360] FIG. 28(B) shows a different example. Specifically, the configuration shown in FIG. 28(B) includes an insulating layer 276 and a microlens array 277 in addition to the configuration shown in FIG. 28(A). The insulating layer 276 functions as an adhesive layer. If the refractive index of the insulating layer 276 is lower than that of the microlens array 277, the microlens array 277 can condense light emitted from the light-emitting elements 61R, 61G, and 61B. This improves the light extraction efficiency of the display device. This is particularly advantageous because it allows a user to view a bright image when viewing the display surface of the display device from directly in front of the display surface. The insulating layer 276 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet-curable adhesive), a reactive-curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0361] FIG. 28(C) shows a different example. Specifically, the configuration shown in FIG. 28(C) has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 28(A). An insulating layer 276 is provided above the three light-emitting elements 61W, and colored layers 264R, 264G, and 264B are provided above the insulating layer 276. Specifically, a colored layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a colored layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the display device to display a color image. The configuration shown in FIG. 28(C) is also a modified example of the configuration shown in FIG. 27(C).

[0362] 28(D) shows an example different from the above. Specifically, in the configuration shown in FIG. 28(D), a protective layer 271 is provided adjacent to the side surfaces of the conductive layer 171 and the EL layer 172. The conductive layer 173 is provided as a continuous layer common to each light-emitting element. In the configuration shown in FIG. 28(D), it is preferable that the region 275 is filled with a filler material.

[0363] The color purity of the emitted color can be improved by providing a micro-optical resonator (microcavity) structure to the light-emitting element 61. To provide a microcavity structure to the light-emitting element 61, the product (optical path length) of the distance d between the conductive layers 171 and 173 and the refractive index n of the EL layer 172 should be configured to be m times half the wavelength λ (m is an integer equal to or greater than 1). The distance d can be calculated using Equation 1.

[0364] d=m×λ / (2×n) ··· Equation 1.

[0365] According to Equation 1, the distance d of the light emitting element 61 having a microcavity structure is determined according to the wavelength (emission color) of the emitted light. The distance d corresponds to the thickness of the EL layer 172. Therefore, the EL layer 172G may be provided thicker than the EL layer 172B, and the EL layer 172R may be provided thicker than the EL layer 172G.

[0366] Strictly speaking, distance d is the distance from the reflective region of conductive layer 171, which functions as a reflective electrode, to the reflective region of conductive layer 173, which functions as a semi-transmissive and semi-reflective electrode. For example, if conductive layer 171 is a laminate of silver and a transparent conductive film, ITO (Indium Tin Oxide), and the ITO is on the EL layer 172 side, distance d can be set according to the emitted color by adjusting the film thickness of the ITO. In other words, even if EL layer 172R, EL layer 172G, and EL layer 172B have the same thickness, distance d appropriate for the emitted color can be obtained by changing the thickness of the ITO.

[0367] However, it may be difficult to precisely determine the positions of the reflective regions in the conductive layers 171 and 173. In this case, it is assumed that the microcavity effect can be fully obtained by assuming that any position on the conductive layers 171 and 173 is the reflective region.

[0368] The light-emitting element 61 is composed of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. Detailed configuration examples of the light-emitting element 61 will be described in other embodiments. To increase the light extraction efficiency in the microcavity structure, it is preferable to set the optical distance from the conductive layer 171, which functions as a reflective electrode, to the light-emitting layer to an odd multiple of λ / 4. To achieve this optical distance, it is preferable to appropriately adjust the thickness of each layer that constitutes the light-emitting element 61.

[0369] Furthermore, when light is emitted toward the conductive layer 171, it is preferable that the reflectance of the conductive layer 173 is greater than the transmittance. The light transmittance of the conductive layer 173 is preferably 2% to 50%, more preferably 2% to 30%, and even more preferably 2% to 10%. By reducing the transmittance of the conductive layer 173 (increasing the reflectance), the effect of the microcavity can be enhanced.

[0370] Fig. 29(A) shows an example different from the above. Specifically, in the configuration shown in Fig. 29(A), the EL layer 172 extends beyond the edge of the conductive layer 171 in each of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. For example, in the light-emitting element 61R, the EL layer 172R extends beyond the edge of the conductive layer 171. In addition, in the light-emitting element 61G, the EL layer 172G extends beyond the edge of the conductive layer 171. In the light-emitting element 61B, the EL layer 172B extends beyond the edge of the conductive layer 171.

[0371] In each of the light-emitting elements 61R, 61G, and 61B, the EL layer 172 and the protective layer 271 have an overlapping region with the insulating layer 270 interposed therebetween. In addition, an insulating layer 278 is provided on the protective layer 271 in the region between adjacent light-emitting elements 61.

[0372] Examples of materials for the insulating layer 278 include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Photoresist may also be used for the insulating layer 278. The photoresist used for the insulating layer 278 may be a positive photoresist or a negative photoresist.

[0373] Furthermore, a common layer 174 is provided on the light-emitting elements 61R, 61G, and 61B and the insulating layer 278, and a conductive layer 173 is provided on the common layer 174. The common layer 174 has a region in contact with the EL layer 172R, a region in contact with the EL layer 172G, and a region in contact with the EL layer 172B. The common layer 174 is shared by the light-emitting elements 61R, 61G, and 61B.

[0374] The common layer 174 may be one or more of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron transport layer, and an electron injection layer. For example, the common layer 174 may be a carrier injection layer (hole injection layer or electron injection layer). The common layer 174 may also be considered a part of the EL layer 172. The common layer 174 may be provided as needed. When the common layer 174 is provided, it is not necessary to provide a layer included in the EL layer 172 that has the same function as the common layer 174.

[0375] In addition, a protective layer 273 is provided over the conductive layer 173 , and an insulating layer 276 is provided over the protective layer 273 .

[0376] FIG. 29(B) shows another example. Specifically, the configuration shown in FIG. 29(B) has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 29(A). An insulating layer 276 is provided above the three light-emitting elements 61W, and colored layers 264R, 264G, and 264B are provided above the insulating layer 276. Specifically, a colored layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a colored layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the display device to display a color image. The configuration shown in FIG. 29(B) is also a variation of the configuration shown in FIG. 28(C).

[0377] <Configuration example of light emitting element and light receiving element> A display device according to one embodiment of the present invention is a top-emission display device that emits light in a direction opposite to a substrate on which a light-emitting element is formed. In this embodiment, a display device including a top-emission light-emitting element and a light-receiving element will be described as an example.

[0378] In this specification, unless otherwise specified, even when describing a configuration having a plurality of elements (e.g., light-emitting elements, light-emitting layers), when describing matters common to each element, the alphabet will be omitted. For example, when describing matters common to light-emitting layer 383R and light-emitting layer 383G, etc., they may be referred to as light-emitting layer 383.

[0379] The display device 380A shown in Figure 30(A) has a light receiving element 370PD, a light emitting element 370R that emits red (R) light, a light emitting element 370G that emits green (G) light, and a light emitting element 370B that emits blue (B) light.

[0380] Each light-emitting element has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​a light-emitting layer, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order. Light-emitting element 370R has a light-emitting layer 383R, light-emitting element 370G has a light-emitting layer 383G, and light-emitting element 370B has a light-emitting layer 383B. Light-emitting layer 383R contains a light-emitting material that emits red light, light-emitting layer 383G contains a light-emitting material that emits green light, and light-emitting layer 383B contains a light-emitting material that emits blue light.

[0381] The light emitting element is an electroluminescent element that emits light toward the common electrode 375 when a voltage is applied between the pixel electrode 371 and the common electrode 375 .

[0382] The light receiving element 370PD has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order.

[0383] The light receiving element 370PD is a photoelectric conversion element that receives light incident from outside the display device 380A and converts it into an electrical signal.

[0384] In this embodiment, in both the light-emitting element and the light-receiving element, the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. In other words, by applying a reverse bias between the pixel electrode 371 and the common electrode 375 and driving the light-receiving element, the light-receiving element can detect light incident on the light-receiving element, generate electric charges, and extract the electric charges as a current.

[0385] In the display device of this embodiment, an organic compound is used for the active layer 373 of the light-receiving element 370PD. The layers of the light-receiving element 370PD other than the active layer 373 can be configured in common with the light-emitting element. Therefore, by simply adding a step of forming the active layer 373 to the manufacturing process of the light-emitting element, the light-receiving element 370PD can be formed in parallel with the formation of the light-emitting element. Furthermore, the light-emitting element and the light-receiving element 370PD can be formed on the same substrate. Therefore, the light-receiving element 370PD can be built into the display device without significantly increasing the number of manufacturing steps.

[0386] In the display device 380A, the light receiving element 370PD and the light emitting element have a common configuration, except that the active layer 373 of the light receiving element 370PD and the light emitting layer 383 of the light emitting element are fabricated separately. However, the configuration of the light receiving element 370PD and the light emitting element is not limited to this. The light receiving element 370PD and the light emitting element may have layers fabricated separately from each other, in addition to the active layer 373 and the light emitting layer 383. It is preferable that the light receiving element 370PD and the light emitting element have one or more layers used in common (common layers). This allows the light receiving element 370PD to be incorporated into the display device without significantly increasing the number of manufacturing steps.

[0387] A conductive film that transmits visible light is used for the electrode from which light is extracted, between the pixel electrode 371 and the common electrode 375. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.

[0388] The light-emitting element included in the display device of this embodiment preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light-emitting element preferably has an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other preferably has an electrode that is reflective to visible light (reflective electrode). When the light-emitting element has a microcavity structure, light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0389] The semi-transmitting / semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode that is transparent to visible light (also called a transparent electrode).

[0390] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the light emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is 1×10 -2 When the light-emitting element emits near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less), the transmittance or reflectance of these electrodes for near-infrared light preferably satisfies the above-mentioned numerical range, similar to the transmittance or reflectance for visible light.

[0391] The light-emitting element has at least a light-emitting layer 383. The light-emitting element may further have, in addition to the light-emitting layer 383, a layer containing a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole-blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, an electron-blocking material, a bipolar substance (a substance having a high electron-transporting property and a high hole-transporting property), or the like.

[0392] For example, the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer in common, or the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer formed differently from each other.

[0393] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound or a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0394] In a light-emitting element, the hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. In a light-receiving element, the hole transport layer is a layer that transports holes generated in the active layer based on incident light to the anode. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 -6 cm 2 A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0395] In a light-emitting element, the electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. In a light-receiving element, the electron transport layer is a layer that transports electrons generated in the active layer based on incident light to the cathode. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a 1×10 -6 cm 2 A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0396] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0397] The light-emitting layer 383 is a layer containing a light-emitting substance. The light-emitting layer 383 can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0398] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0399] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0400] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0401] The light-emitting layer 383 may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used. Furthermore, as the one or more organic compounds, a bipolar material or a TADF material can be used.

[0402] The light-emitting layer 383 preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This structure allows efficient emission using Exciplex-Triplet Energy Transfer (ExTET), which is energy transfer from an exciplex to a light-emitting substance (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting substance, the energy transfer becomes smooth, allowing efficient emission. This structure simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0403] As a combination of materials that form an exciplex, it is preferable that the HOMO level (highest occupied molecular orbital level) of the hole-transporting material is equal to or higher than the HOMO level of the electron-transporting material. It is also preferable that the LUMO level (lowest unoccupied molecular orbital level) of the hole-transporting material is equal to or higher than the LUMO level of the electron-transporting material. The LUMO level and HOMO level of the material can be derived from the electrochemical properties (reduction potential and oxidation potential) of the material measured by cyclic voltammetry (CV).

[0404] The formation of exciplexes can be confirmed, for example, by comparing the emission spectra of the hole-transporting material, the electron-transporting material, and the mixed film of these materials and observing the phenomenon that the emission spectrum of the mixed film is shifted to longer wavelengths than the emission spectra of each material (or has a new peak at longer wavelengths). Alternatively, it can be confirmed by comparing the transient photoluminescence (PL) of the hole-transporting material, the transient PL of the electron-transporting material, and the mixed film of these materials and observing differences in transient response, such as the transient PL lifetime of the mixed film having a longer-lived component or a larger proportion of delayed components than the transient PL lifetimes of the individual materials. The above-mentioned transient PL can also be interpreted as transient electroluminescence (EL). In other words, the formation of exciplexes can also be confirmed by comparing the transient EL of the hole-transporting material, the transient EL of the electron-transporting material, and the mixed film of these materials and observing differences in transient response.

[0405] The active layer 373 includes a semiconductor. Examples of the semiconductor include an inorganic semiconductor such as silicon and an organic semiconductor including an organic compound. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer 373 is shown. By using an organic semiconductor, the light-emitting layer 383 and the active layer 373 can be formed by the same method (for example, vacuum evaporation), which is preferable because a common manufacturing device can be used.

[0406] The active layer 373 has an n-type semiconductor material, such as fullerene (e.g., C 60 , C 70Examples of electron-accepting organic semiconductor materials include fullerene derivatives and other fullerenes. Fullerenes have a soccer ball-like shape, which is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Because fullerenes have a deep LUMO level, they have extremely high electron-accepting (acceptor) properties. Normally, when the π-electron conjugation (resonance) spreads across a plane, as in benzene, the electron-donating (donor) properties increase, but fullerenes have a spherical shape, so they have high electron-accepting properties despite the wide spread π-electron conjugation. High electron-accepting properties allow charge separation to occur quickly and efficiently, making them useful as light-receiving elements. C 60 , C 70 Both have a wide absorption band in the visible light region, especially C 70 is C 60 It is preferable because it has a larger π-electron conjugated system and a broad absorption band in the long wavelength region compared to [6,6]-Phenyl-C71-butyric acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butyric acid methyl ester (abbreviation: PC60BM), and 1',1'',4',4''-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2',3',56,60:2'',3''][5,6]fullerene-C60 (abbreviation: ICBA).

[0407] Furthermore, examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0408] Examples of the p-type semiconductor material of the active layer 373 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0409] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, etc. Examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, etc.

[0410] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0411] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material and a planar organic semiconductor material as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, the energy levels of their molecular orbitals become close, which can improve carrier transport properties.

[0412] For example, the active layer 373 is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor, or alternatively, the active layer 373 may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0413] The light-emitting element and the light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element and the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), a transfer method, a printing method, an inkjet method, or a coating method.

[0414] For example, polymer compounds such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (PEDOT / PSS) and inorganic compounds such as molybdenum oxide and copper iodide (CuI) can be used as hole-transporting materials, and inorganic compounds such as zinc oxide (ZnO) can be used as electron-transporting materials.

[0415] Furthermore, a polymer compound such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c']dithiophene-1,3-diyl]]polymer (abbreviated as PBDB-T) or a PBDB-T derivative, which functions as a donor, can be used for the active layer 373. For example, a method of dispersing an acceptor material in PBDB-T or a PBDB-T derivative can be used.

[0416] Furthermore, three or more types of materials may be mixed in the active layer 373. For example, in order to expand the wavelength range, a third material may be mixed in addition to an n-type semiconductor material and a p-type semiconductor material. In this case, the third material may be a low-molecular-weight compound or a high-molecular-weight compound.

[0417] A display device 380B shown in FIG. 30(B) differs from the display device 380A in that the light receiving element 370PD and the light emitting element 370R have the same configuration.

[0418] The light receiving element 370PD and the light emitting element 370R have the active layer 373 and the light emitting layer 383R in common.

[0419] Here, it is preferable that light receiving element 370PD has the same configuration as a light emitting element that emits light of a longer wavelength than the light to be detected. For example, light receiving element 370PD configured to detect blue light can have the same configuration as one or both of light emitting element 370R and light emitting element 370G. For example, light receiving element 370PD configured to detect green light can have the same configuration as light emitting element 370R.

[0420] By using a common structure for the light-receiving element 370PD and the light-emitting element 370R, the number of film-forming steps and the number of masks can be reduced compared to a structure in which the light-receiving element 370PD and the light-emitting element 370R have separate layers, thereby reducing the manufacturing steps and manufacturing costs of the display device.

[0421] Furthermore, by using a common configuration for the light receiving element 370PD and the light emitting element 370R, the margin for misalignment can be narrowed compared to a configuration in which the light receiving element 370PD and the light emitting element 370R have separate layers. This allows for an increased pixel aperture ratio and improved light extraction efficiency of the display device. This also extends the life of the light emitting element. Furthermore, the display device can display high brightness. Furthermore, it also allows for higher resolution of the display device.

[0422] Light-emitting layer 383R includes a light-emitting material that emits red light. Active layer 373 includes an organic compound that absorbs light with a wavelength shorter than red (for example, one or both of green light and blue light). Active layer 373 preferably includes an organic compound that does not easily absorb red light and absorbs light with a wavelength shorter than red. This allows red light to be extracted efficiently from light-emitting element 370R, and light-receiving element 370PD to detect light with a wavelength shorter than red with high accuracy.

[0423] Furthermore, in the display device 380B, an example is shown in which the light emitting element 370R and the light receiving element 370PD have the same configuration, but the light emitting element 370R and the light receiving element 370PD may have optical adjustment layers of different thicknesses.

[0424] 31(A) and 31(B) includes a light receiving / emitting element 370SR that emits red (R) light and has a light receiving function, a light emitting element 370G, and a light emitting element 370B. The configuration of the light emitting element 370G and the light emitting element 370B can be based on the configuration of the display device 380A described above.

[0425] The light emitting / receiving element 370SR has, stacked in this order, a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, a light emitting layer 383R, an electron transport layer 384, an electron injection layer 385, and a common electrode 375. The light emitting / receiving element 370SR has the same configuration as the light emitting element 370R and the light receiving element 370PD exemplified in the display device 380B.

[0426] 31(A) shows a case where the light emitting / receiving element 370SR functions as a light emitting element. In FIG. 31(A), an example is shown in which the light emitting element 370B emits blue light, the light emitting element 370G emits green light, and the light emitting / receiving element 370SR emits red light.

[0427] Fig. 31(B) shows a case where the light receiving / emitting element 370SR functions as a light receiving element. Fig. 31(B) shows an example where the light receiving / emitting element 370SR receives blue light emitted by the light emitting element 370B and green light emitted by the light emitting element 370G.

[0428] The light emitting element 370B, the light emitting element 370G, and the light emitting / receiving element 370SR each have a pixel electrode 371 and a common electrode 375. In this embodiment, a case will be described in which the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. The light emitting / receiving element 370SR is driven by applying a reverse bias between the pixel electrode 371 and the common electrode 375, so that the light emitting / receiving element 370SR can detect light incident on the light emitting / receiving element 370SR, generate electric charges, and extract the charges as a current.

[0429] The light emitting / receiving element 370SR can be said to have a configuration in which an active layer 373 is added to a light emitting element. In other words, the light emitting / receiving element 370SR can be formed in parallel with the formation of the light emitting element by simply adding a step of forming the active layer 373 to the manufacturing process of the light emitting element. Furthermore, the light emitting element and the light emitting / receiving element can be formed on the same substrate. Therefore, it is possible to provide the display unit with either or both of an imaging function and a sensing function without significantly increasing the manufacturing process.

[0430] There are no limitations on the stacking order of the light-emitting layer 383R and the active layer 373. Figures 31(A) and 31(B) show an example in which the active layer 373 is provided on the hole-transporting layer 382, ​​and the light-emitting layer 383R is provided on the active layer 373. The stacking order of the light-emitting layer 383R and the active layer 373 may be reversed.

[0431] Furthermore, the light emitting / receiving element may not have at least one layer selected from the hole injection layer 381, the hole transport layer 382, ​​the electron transport layer 384, and the electron injection layer 385. The light emitting / receiving element may also have other functional layers such as a hole blocking layer and an electron blocking layer.

[0432] In the light emitting / receiving element, a conductive film that transmits visible light is used for the electrode on the light extraction side, and a conductive film that reflects visible light is preferably used for the electrode on the non-light extraction side.

[0433] The functions and materials of the layers constituting the light emitting / receiving element are similar to those of the layers constituting the light emitting element and the light receiving element, and therefore detailed description thereof will be omitted.

[0434] 31C to 31G show examples of stacked structures of light emitting and receiving elements.

[0435] The light emitting / receiving element shown in FIG. 31C includes a first electrode 377, a hole injection layer 381, a hole transport layer 382, ​​a light emitting layer 383R, an active layer 373, an electron transport layer 384, an electron injection layer 385, and a second electrode 378.

[0436] FIG. 31C shows an example in which a light-emitting layer 383R is provided on a hole-transporting layer 382, ​​and an active layer 373 is stacked on the light-emitting layer 383R.

[0437] As shown in FIGS. 31(A) to 31(C), the active layer 373 and the light emitting layer 383R may be in contact with each other.

[0438] A buffer layer is preferably provided between the active layer 373 and the light-emitting layer 383R. In this case, the buffer layer preferably has hole-transporting and electron-transporting properties. For example, a bipolar substance is preferably used for the buffer layer. Alternatively, the buffer layer may be at least one layer selected from a hole-injection layer, a hole-transport layer, an electron-transport layer, an electron-injection layer, a hole-blocking layer, an electron-blocking layer, and the like. Figure 31(D) shows an example in which a hole-transporting layer 382 is used as the buffer layer.

[0439] By providing a buffer layer between the active layer 373 and the light-emitting layer 383R, it is possible to suppress the transfer of excitation energy from the light-emitting layer 383R to the active layer 373. In addition, the buffer layer can be used to adjust the optical path length (cavity length) of the microcavity structure. Therefore, a light-emitting / receiving element having a buffer layer between the active layer 373 and the light-emitting layer 383R can obtain high light-emitting efficiency.

[0440] FIG. 31(E) shows an example of a laminated structure in which a hole transport layer 382-1, an active layer 373, a hole transport layer 382-2, and an emitting layer 383R are laminated in this order on a hole injection layer 381. The hole transport layer 382-2 functions as a buffer layer. The hole transport layer 382-1 and the hole transport layer 382-2 may contain the same material or different materials. Alternatively, the hole transport layer 382-2 may be replaced with a layer that can be used as a buffer layer. Alternatively, the positions of the active layer 373 and the emitting layer 383R may be interchanged.

[0441] 31(F) differs from the light-emitting / receiving element shown in Fig. 31(A) in that it does not have the hole transport layer 382. In this way, the light-emitting / receiving element may not have at least one layer among the hole injection layer 381, the hole transport layer 382, ​​the electron transport layer 384, and the electron injection layer 385. Furthermore, the light-emitting / receiving element may have other functional layers such as a hole blocking layer or an electron blocking layer.

[0442] The light emitting / receiving device shown in FIG. 31(G) differs from the light emitting / receiving device shown in FIG. 31(A) in that it does not have an active layer 373 and a light emitting layer 383R, but has a layer 389 that serves as both a light emitting layer and an active layer.

[0443] The layer that serves as both the light-emitting layer and the active layer can be, for example, a layer containing three materials: an n-type semiconductor that can be used for the active layer 373, a p-type semiconductor that can be used for the active layer 373, and a light-emitting substance that can be used for the light-emitting layer 383R.

[0444] It is preferable that the lowest energy absorption band in the absorption spectrum of the mixed material of n-type and p-type semiconductors does not overlap with the maximum peak in the emission spectrum (PL spectrum) of the luminescent substance, and it is more preferable that they are sufficiently separated from each other.

[0445] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0446] <Configuration example of light emitting element and light receiving element> 32 is a cross-sectional view showing a configuration example of the display device 10. The display device 10 has a configuration in which a transistor 310 having a channel formed in a substrate 301 and a transistor 320 having a channel formed in a semiconductor layer containing a metal oxide are stacked.

[0447] An insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. An insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided over the insulating layer 262. The conductive layers 251 and 252 each function as wirings. An insulating layer 263 and an insulating layer 332 are provided to cover the conductive layer 252, and the transistor 320 is provided over the insulating layer 332. An insulating layer 265 is provided to cover the transistor 320, and a capacitor 246 is provided over the insulating layer 265. The capacitor 246 and the transistor 320 are electrically connected to each other by a plug 284.

[0448] The transistor 320 can be used as a transistor that forms a pixel circuit or a transistor that forms a memory cell. The transistor 310 can be used as a transistor that forms a memory cell, a transistor that forms a driver circuit for driving the pixel circuit, or a transistor that forms an arithmetic circuit. The transistors 310 and 320 can be used as transistors that form various circuits such as an arithmetic circuit or a memory circuit.

[0449] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 306, a low-resistance region 312, an insulating layer 307, and an insulating layer 314. The conductive layer 306 functions as a gate electrode. The insulating layer 307 is located between the substrate 301 and the conductive layer 306 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 306 and functions as an insulating layer.

[0450] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0451] The transistor 320 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0452] The transistor 320 includes a semiconductor layer 321 , an insulating layer 323 , a conductive layer 324 , a pair of conductive layers 325 , an insulating layer 326 , and a conductive layer 327 .

[0453] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 263 side to the transistor 320 side and prevents oxygen from being released from the semiconductor layer 321 to the insulating layer 332 side. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0454] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0455] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor properties. The semiconductor layer 321 preferably includes a metal oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. An OS transistor using such a metal oxide for a channel formation region has a characteristic of extremely low off-state current. Therefore, it is preferable to use an OS transistor as a transistor provided in a pixel circuit because analog data written to the pixel circuit can be retained for a long period of time. Similarly, it is preferable to use an OS transistor as a transistor used in a memory cell because analog data written to the memory cell can be retained for a long period of time.

[0456] A pair of conductive layers 325 is provided over and in contact with the semiconductor layer 321 and functions as a source electrode and a drain electrode.

[0457] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like to the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321. The insulating layer 328 can be formed using an insulating film similar to the insulating layer 332.

[0458] An opening is provided in the insulating layer 328 and the insulating layer 264, reaching the semiconductor layer 321. An insulating layer 323 and a conductive layer 324 are buried inside the opening and are in contact with the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325, as well as the top surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0459] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are approximately the same, and insulating layers 329 and 265 are provided to cover them.

[0460] The insulating layer 264 and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 320. The insulating layer 329 can be formed using an insulating film similar to the insulating layer 328 and the insulating layer 332.

[0461] A plug 284 electrically connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265 , the insulating layer 329 , and the insulating layer 264 .

[0462] Capacitor 246 has conductive layer 244, conductive layer 245, and insulating layer 243 positioned therebetween. Conductive layer 244 functions as one electrode of capacitor 246, conductive layer 245 functions as the other electrode of capacitor 246, and insulating layer 243 functions as a dielectric of capacitor 246.

[0463] The conductive layer 245 is provided over the insulating layer 265 and is buried in the insulating layer 253. The conductive layer 244 is electrically connected to one of the source and drain of the transistor 310 by a plug 283 buried in the insulating layer 261. The insulating layer 243 is provided to cover the conductive layer 245. The conductive layer 245 is provided in a region overlapping with the conductive layer 244 with the insulating layer 243 interposed therebetween.

[0464] An insulating layer 255 is provided to cover the capacitor 246, and a light emitting element 61, a light receiving element 62, and the like are provided on the insulating layer 255. A protective layer 91 is provided on the light emitting element 61 and the light receiving element 62, and a substrate 420 is bonded to the upper surface of the protective layer 91 by a resin layer 419. The substrate 420 can be a light-transmitting substrate.

[0465] The pixel electrode 84 of the light-emitting element 61 and the pixel electrode 84PD of the light-receiving element 62 are electrically connected to either the source or drain of the transistor 310 by a plug 256 embedded in the insulating layer 255, a conductive layer 244 embedded in the insulating layer 253, and a plug 283 embedded in the insulating layer 261.

[0466] By adopting such a configuration, it is possible to arrange the transistors that constitute the pixel circuit directly below the light receiving element and the light emitting element, and it is also possible to arrange the driving circuit, the calculation circuit, etc., so that it is possible to miniaturize a display device that has been improved in performance.

[0467] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0468] <Additional notes regarding the present specification etc.> The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0469] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0470] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0471] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0472] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0473] In addition, in the block diagrams in this specification, components are classified by function and shown as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0474] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0475] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and drain of a transistor can be appropriately changed to source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0476] Furthermore, in this specification and the like, terms such as "electrode" and "wiring" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" and "wiring" also include cases where multiple "electrodes," "wirings," etc. are formed as a single unit.

[0477] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0478] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0479] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0480] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0481] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0482] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0483] 10 Display device 11 layers 12 layers 13 Display area 14 Light receiving area 15 Terminal section 17 Optical Lenses 31 Transistor 32 Channel formation region 33 Transistor 34 Channel formation region 40 layers 41 Drive circuit 42 Arithmetic circuit 51 Pixel circuit 52 pixel circuit 100 Electronic equipment

Claims

1. A display device having a first layer provided with a plurality of pixel circuits, a second layer provided on the first layer, and a plurality of optical lenses provided on the second layer, having a display area and a plurality of light receiving areas, wherein the display area has a light emitting element provided in the second layer, wherein the light receiving areas have a plurality of light receiving elements provided in the second layer, wherein the plurality of light receiving areas are provided around the display area, and wherein the optical lenses are provided at positions overlapping the light receiving areas.

2. A display device having a first layer, a second layer provided on the first layer, and a plurality of optical lenses provided on the second layer, having a display area and a plurality of light receiving areas, wherein the display area has a first pixel circuit provided in the first layer and a light emitting element provided in the second layer, wherein the light receiving areas have a second pixel circuit provided in the first layer and a light receiving element provided in the second layer, wherein the plurality of light receiving areas are provided around the display area, and wherein the optical lenses are provided at positions overlapping the light receiving areas.

3. The display device according to claim 2, wherein the pitch of the wiring for driving the second pixel circuit provided in the light receiving area is smaller than the pitch of the wiring for driving the first pixel circuit provided in the display area.

4. The display device according to claim 1, wherein the resolution of the image captured by the light receiving element provided in the light receiving area is larger than the resolution of the image displayed by the light emitting element provided in the display area.

5. The display device according to claim 1, wherein the display area is a rectangular area, The light-receiving region is disposed at four corners of the rectangular region, a display device. **Claim 6** In claim 2, The display device has a third layer, The third layer has a drive circuit, The drive circuit is disposed at a position overlapping the display region, a display device. **Claim 7** In claim 6, The third layer has an arithmetic circuit, The arithmetic circuit has a function of performing gaze tracking based on image data captured by a plurality of the light-receiving regions, a display device.

Images