Pixel circuit for controlling light-emitting element

Abstract

To suppress image retention in a display device.SOLUTION: A drive transistor controls a drive current to a light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the drive transistor. A first switch transistor switches connection / disconnection between an intermediate node between the first capacitive element and the second capacitive element and a data line. A second switch transistor switches connection / disconnection between the gate and a drain of the drive transistor. A third switch transistor switches connection / disconnection between the intermediate node and a reference power supply line. A fourth switch transistor switches supply / non-supply of the drive current from the drive transistor to the light-emitting element. A fifth switch transistor switches connection / disconnection between an anode of the light-emitting element and a reset power supply line.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit for controlling a light-emitting element.

Background Art

[0002] Since an OLED (Organic Light-Emitting Diode) element is a current-driven self-emitting element, it does not require a backlight and has advantages such as low power consumption, a wide viewing angle, and a high contrast ratio, and is expected in the development of flat panel displays.

[0003] An active matrix (AM) type OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistor in the OLED display device is a TFT (Thin Film Transistor), and generally, an LTPS (Low Temperature Poly-silicon) TFT is used.

[0004] TFTs have variations in threshold voltage and charge mobility. Since the driving transistor determines the light emission intensity of the OLED display device, such variations in electrical characteristics cause uneven brightness and the like. Therefore, a correction circuit for correcting variations and fluctuations in the threshold voltage of the driving transistor is implemented in a general OLED display device.

[0005] In an OLED display device, image retention may occur, and this phenomenon is called image retention. For example, after displaying a black and white checkerboard pattern for a specific time and then trying to display an intermediate gradation across the entire screen, afterimages of the checkerboard pattern with different brightness levels are displayed for a while.

[0006] This is caused by the history effect of the driving transistor. The history effect refers to a phenomenon in a field-effect transistor where the drain current when the voltage between the gate and the source changes from a high voltage to a low voltage and the drain current when the voltage changes from a low voltage to a high voltage are different.

[0007] In other words, the drain current when switching from black to an intermediate grayscale is different from the drain current when switching from white to an intermediate grayscale, resulting in a difference in the light emission intensity of the OLED display device. Furthermore, because this difference in drain current continues for several frames or more, it is perceived as an afterimage. This behavior of the drain current is evident from the current transient response characteristics due to the hysteresis effect. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0389157 [Patent Document 2] Japanese Patent Publication No. 2004-246204 [Overview of the project] [Problems that the invention aims to solve]

[0009] After displaying a black and white checkerboard pattern, image retention can result in afterimages where the previously black areas are relatively darker or relatively brighter. The same applies to white areas. Image retention is caused by the current transient response characteristics due to the hysteresis effect of the driving TFT and the threshold voltage correction characteristics of the driving TFT by the pixel circuit. Therefore, a technology that can reduce image retention in the pixel circuit is desired. [Means for solving the problem]

[0010] One aspect of the present disclosure is a pixel circuit for controlling the emission of light-emitting elements, comprising: a light-emitting element; a drive transistor for controlling a drive current to the light-emitting element; a first capacitor element and a second capacitor element connected in series between the gate and source of the drive transistor; a first switch transistor for switching the connection / disconnection between an intermediate node between the first capacitor element and the second capacitor element and a data line; a second switch transistor for switching the connection / disconnection between the gate and drain of the drive transistor; a third switch transistor for switching the connection / disconnection between the intermediate node and a reference power line; a fourth switch transistor for switching the supply of drive current from the drive transistor to the light-emitting element; and a fifth switch transistor for switching the connection / disconnection between the anode of the light-emitting element and a reset power line. During the initialization period, the first switch transistor is OFF, and the second, third, fourth, and fifth switch transistors are ON. During the threshold correction period following the initialization period, the first and fourth switch transistors are OFF, and the second, third, and fifth switch transistors are ON. During the data writing period after the threshold correction period, the first switch transistor is ON, and the second, third, fourth, and fifth switch transistors are OFF. During the light emission period after the data writing period, the fourth switch transistor is ON, and the first, second, third, and fifth switch transistors are OFF.

[0011] Another aspect of the present disclosure is a pixel circuit for controlling the emission of light-emitting elements, comprising: a light-emitting element; a drive transistor for controlling a drive current to the light-emitting element; a third capacitor and a fourth capacitor connected in series between the gate and source of the drive transistor; a sixth switch transistor for switching the connection / disconnection between the gate of the drive transistor and a data line; a seventh switch transistor for switching the supply of current from the positive power line to the drive transistor; a connecting line connecting an intermediate node between the drive transistor and the seventh switch transistor and an intermediate node between the third capacitor and the fourth capacitor; an eighth switch transistor for switching the connection / disconnection between the gate of the drive transistor and a reference power line; a ninth switch transistor for switching the supply of current from the drive transistor to the light-emitting element; and a tenth switch transistor for switching the connection / disconnection between the intermediate node between the drive transistor and the ninth switch transistor and a reset power line. During the initialization period, the sixth switch transistor is OFF, and the seventh switch transistor, the eighth switch transistor, the ninth switch transistor and the tenth switch transistor are ON. During the threshold correction period following the initialization period, the 8th switch transistor and the 10th switch transistor are ON, and the 6th switch transistor, the 7th switch transistor, and the 9th switch transistor are OFF. During the data writing period following the threshold correction period, the 6th switch transistor is ON, and the 7th switch transistor, the 8th switch transistor, the 9th switch transistor, and the 10th switch transistor are OFF. During the light emission period following the data writing period, the 7th switch transistor and the 9th switch transistor are ON, and the 6th switch transistor, the 8th switch transistor, and the 10th switch transistor are OFF.

[0012] Another aspect of the present disclosure is a pixel circuit for controlling the emission of light-emitting elements, comprising: a light-emitting element; a drive transistor for controlling a drive current to the light-emitting element; a fifth capacitor and a sixth capacitor connected in series between the gate and source of the drive transistor; an eleventh switch transistor for switching between connection and disconnection between an intermediate node between the fifth capacitor and the sixth capacitor and a data line; a twelfth switch transistor for switching between supplying current from the positive power line to the light-emitting element; a thirteenth switch transistor for switching between connection and disconnection between an intermediate node between the drive transistor and the twelfth switch transistor and an intermediate node between the fifth capacitor and the sixth capacitor; a fourteenth switch transistor for switching between connection and disconnection between the gate of the drive transistor and a reference power line; and a fifteenth switch transistor for switching between connection and disconnection between the anode of the light-emitting element and a reset power line. During the initialization period, the eleventh switch transistor is OFF, and the twelfth, thirteenth, fourteenth, and fifteenth switch transistors are ON. During the threshold correction period following the initialization period, the 11th and 12th switch transistors are OFF, and the 13th, 14th, and 15th switch transistors are ON. During the data writing period following the threshold correction period, the 11th switch transistor is ON, and the 12th, 13th, 14th, and 15th switch transistors are OFF. During the light emission period following the data writing period, the 12th switch transistor is ON, and the 11th, 13th, 14th, and 15th switch transistors are OFF. [Effects of the Invention]

[0013] According to one aspect of this disclosure, image retention in a display device can be suppressed.

Brief Description of Drawings

[0014] [Figure 1] A configuration example of an OLED display device, which is a display device, is schematically shown. [Figure 2] A configuration example of a pixel circuit and control signals according to an embodiment of this specification is shown. [Figure 3] A timing chart of signals for controlling the pixel circuit shown in FIG. 2 in one frame period is shown. [Figure 4A] Transistors that are ON in the pixel circuit during the initialization period, potentials of some nodes, and current flows are shown. [Figure 4B] Transistors that are ON in the pixel circuit during the Vth correction period, potentials of some nodes, and current flows are shown. [Figure 4C] Transistors that are ON in the pixel circuit during the data writing period and potentials of some nodes are shown. [Figure 5A] The time change of selection signals for consecutive pixel rows is shown. [Figure 5B] The time change of other selection signals for consecutive pixel rows is shown. [Figure 5C] The time change of emission control signals for consecutive pixel rows is shown. [Figure 6] A pixel circuit of another configuration example according to an embodiment of this specification is shown. [Figure 7A] Transistors that are ON during the initialization period are shown. [Figure 7B] Transistors that are ON in the pixel circuit shown in FIG. 6 during the Vth correction period, potentials of some nodes, and current flows are shown. [Figure 8] A pixel circuit of another configuration example according to an embodiment of this specification is shown. [Figure 9] A pixel circuit of another configuration example according to an embodiment of this specification is shown. [Figure 10] A timing chart of signals for controlling the pixel circuit shown in FIG. 9 in one frame period is shown. [Figure 11A]Shows the ON transistors and the potentials of several nodes in the pixel circuit shown in FIG. 9 during the initialization period. [Figure 11B] Shows the ON transistors and the potentials of several nodes in the pixel circuit shown in FIG. 9 during the Vth correction period. [Figure 11C] Shows the ON transistors and the potentials of several nodes in the pixel circuit shown in FIG. 9 during the data writing period. [Figure 12A] Shows a configuration example of a pixel circuit and control signals according to an embodiment of the present specification. [Figure 12B] Shows a timing chart of signals for controlling the pixel circuit shown in FIG. 12A. [Figure 13A] Shows a configuration example of a pixel circuit and control signals according to an embodiment of the present specification. [Figure 13B] It is a diagram for explaining the effect of suppressing the through current flowing between power supplies in the pixel circuit of FIG. 13A. [Figure 14] Shows a timing chart of signals for controlling the pixel circuit shown in FIG. 13A in one frame period. [Figure 15] Schematically shows a layout example of a circuit for providing control signals for the pixel circuit shown in FIG. 13A. [Figure 16] Shows the change in the driving current (transient current) of a pixel in negative image retention. [Figure 17] Shows a graph of measurement values of the relationship between the correction period of the threshold Vth of the driving transistor and the ratio |ΔIR| / L of the difference in transient current. [Figure 18] Shows an example of the phase difference between the selection signal and the data signal. [Figure 19A] Shows the simulation results of the time changes of the gate voltage Vg of the driving transistor, the selection signal S2, and the data signal Vdata in a related example. [Figure 19B] Shows the simulation results of the time changes of the gate voltage Vg of the driving transistor, the selection signal S2, and the data signal Vdata in this embodiment. [Figure 20A]The simulation results showing the phase difference dependence of the gate voltage in related examples are shown. [Figure 20B] The simulation results showing the phase difference dependence of the gate voltage in this embodiment are shown. [Figure 21A] This shows the current flow in the pixel circuit during the initialization period. [Figure 21B] The equivalent circuit of the circuit in Figure 21A is shown. [Figure 22] Examples of potentials for selection signals and light emission control signals are shown. [Modes for carrying out the invention]

[0015] The embodiments will be described in detail below with reference to the drawings. Common components in each drawing are denoted by the same reference numerals. For the sake of clarity, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0016] The following discloses a technology for improving drive current control in light-emitting display devices that use light-emitting elements that emit light in response to a drive current, such as OLED (Organic Light-Emitting Diode) display devices. More specifically, it discloses a technology for suppressing image retention in light-emitting display devices.

[0017] [Display device configuration] Figure 1 schematically shows an example of the configuration of an OLED display device 10. In Figure 1, the horizontal direction is the X-axis direction, and the vertical direction is the Y-axis direction perpendicular to the X-axis direction. The OLED display device 10 is composed of a TFT (Thin Film Transistor) substrate 100 on which OLED elements (light-emitting elements) are formed, and a sealing substrate 150 that encapsulates the organic light-emitting elements.

[0018] An inert gas, such as dry nitrogen, is sealed between the TFT substrate 100 and the sealing substrate 150. Other sealing structures may be used, for example, a sealing structure that uses a thin film seal instead of the sealing substrate 150.

[0019] Scanning circuits 131, 132, a driver IC 134, and a demultiplexer 136 are arranged around the cathode electrode formation area 114 outside the display area 125 of the TFT substrate 100. The driver IC 134 is connected to an external device via an FPC (Flexible Printed Circuit) 135. Scanning circuits 131 and 132 drive the scan lines of the TFT substrate 100.

[0020] The driver IC 134 is mounted, for example, using an anisotropic conductive film (ACF). The driver IC 134 supplies power and timing signals (control signals) to the scanning circuits 131 and 132. Furthermore, the driver IC 134 supplies data signals to the demultiplexer 136.

[0021] The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (where d is an integer greater than or equal to 2). The demultiplexer 136 drives d times the number of output pins of the driver IC 134 by switching the data line to which the data signal from the driver IC 134 is output d times within the scanning period.

[0022] The display area 125 includes a plurality of OLED elements (pixels) and a plurality of pixel circuits that control the light emission of each of the plurality of pixels. In a color OLED display device, each OLED element emits light of one of the following colors, for example, red, blue, or green. The plurality of pixel circuits constitute a pixel circuit array.

[0023] As described later, each pixel circuit includes a drive TFT (driver transistor) and a holding capacitor that holds the signal voltage that determines the drive current of the drive TFT. The data signal transmitted by the data line is corrected by the threshold voltage Vth of the drive transistor and stored in the holding capacitor. The voltage of the holding capacitor determines the gate voltage (Vgs) of the drive TFT. The corrected control voltage of the holding capacitor changes the conductance of the drive TFT analogously, supplying a forward bias current corresponding to the light emission gradation to the OLED element.

[0024] [Pixel circuit configuration] Figure 2 shows an example configuration of a pixel circuit 200 and a control signal according to one embodiment of this specification. The pixel circuit 200 is included in the k-th (k is an integer) pixel circuit row. The pixel circuit 200 includes six transistors (TFTs) P1 to P6, each having a gate, source, and drain. In this example, all transistors P1 to P6 are P-type TFTs. A P-type TFT is, for example, a low-temperature polysilicon TFT. Transistors P2, P3, P4, P5, and P6 are the first, second, third, fourth, and fifth switch transistors, respectively.

[0025] Transistor P1 is a drive transistor that controls the amount of current supplied to the OLED element E1. The source of drive transistor P1 is connected to power line 241, which transmits the positive power supply potential VDD. Drive transistor P1 controls the amount of current supplied to the OLED element E1 from power line 241 according to the voltage held by series-connected retention capacitors C1 and C2. Retention capacitors C1 and C2 hold the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to power line 204, which transmits the negative power supply potential VEE from the cathode power supply. Retention capacitors C1 and C2 are the first and second capacitor elements, respectively.

[0026] Capacitors C1 and C2 are connected in series between the power line 241, which transmits the positive power supply potential VDD, and the gate of the drive transistor P1. Power line 241 is connected to one end of capacitor C1. One end of capacitor C2 is connected to the other end of capacitor C1. The gate of drive transistor P1 is connected to the other end of capacitor C2. The source / drain of transistor P4 and the source / drain of transistor P2 are connected to the intermediate node between capacitors C1 and C2.

[0027] The combined capacitance of the series-retaining capacitance elements C1 and C2 retains the voltage between the gate and source of the drive transistor P1, which is the power supply line 241. The source of the drive transistor P1 is connected to the power supply line 241, and the source potential is the positive power supply potential VDD. Therefore, the retaining capacitance elements C1 and C2 retain the gate-source voltage of the drive transistor P1.

[0028] Transistor P5 is a light emission control switch transistor that controls the supply of drive current to the OLED element E1 and the resulting ON / OFF of light emission. The source of transistor P5 is connected to the drain of drive transistor P1. Transistor P5 switches the current supply to the OLED element E1 connected to its drain ON / OFF. The gate of transistor P5 is connected to control signal line 233, which transmits the light emission control signal Em, and transistor P5 is controlled by the light emission control signal Em from the scanning circuit. The light emission control signal is a selection signal that controls the light emission of the OLED element E1.

[0029] Transistor P6 operates to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of transistor P6 is connected to the power line 242 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1. The reset potential Vrst may be at the same potential as, for example, the negative power supply potential VEE. This allows the transmission line (power line) for the reset potential Vrst and the negative power supply potential VEE to be shared.

[0030] The gate of transistor P6 is connected to the control signal line 231 that transmits the selection signal S1, and transistor P6 is controlled by the selection signal S1. When transistor P6 is turned ON by the selection signal S1 from the scanning circuit 131, it supplies the reset potential Vrst transmitted by the power line 242 to the anode of the OLED element E1. In addition, transistors P5 and P6 supply the reset potential Vrst to the gate of the drive transistor P1 via transistor P3.

[0031] Transistor P3 is a switch transistor (threshold compensation transistor) that writes the voltage for threshold correction (threshold compensation) of the drive transistor P1 to the holding capacitance elements C1 and C2, and is a transistor that resets the gate potential of the drive transistor P1. The source and drain of transistor P3 are connected to the gate and drain of the drive transistor P1. Therefore, when transistor P3 is ON, the drive transistor P1 is in a diode connection state.

[0032] Transistor P4 is used to write the voltage for threshold compensation of the drive transistor P1 to the holding capacitance elements C1 and C2. Transistor P4 controls whether or not a reference potential Vref is supplied to the holding capacitance elements C1 and C2. The reference potential Vref may be, for example, the same potential as the positive power supply potential VDD. This allows the transmission line (power line) for the reference potential Vref and the positive power supply potential VDD to be shared. One end of the source / drain of transistor P4 is connected to the power line 202 that transmits the reference potential Vref, and the other end is connected to the intermediate node of the capacitance elements C1 and C2. The gate of transistor P4 is connected to the control signal line 231 that transmits the selection signal S1, and transistor P4 is controlled by the selection signal S1 input to the gate from the scanning circuit 131.

[0033] Transistors P3, P6, and P4 are controlled by the selection signal S1. Therefore, these transistors P3, P6, and P4 are switched ON / OFF simultaneously. While they are ON, transistor P5 is turned ON to reset the gate potential of the drive transistor P1, and then transistor P5 is turned OFF. When transistors P3 and P4 are ON, transistor P1 constitutes a diode-connected transistor. Based on the positive power supply potential VDD and the reference potential Vref, threshold compensation voltages are written to the retaining capacitance elements C1 and C2.

[0034] Transistor P2 is a switch transistor that selects the pixel circuit to supply the data signal and writes the data signal (data signal voltage) Vdata to the retaining capacitance elements C1 and C2. One end of the source / drain of transistor P2 is connected to the retaining capacitance elements C1 and C2, and the other end is connected to the data line 237 that transmits the data signal Vdata.

[0035] The gate of transistor P2 is connected to control signal line 232, which transmits selection signal S2 from scanning circuit 131. Transistor P2 is controlled by selection signal S2. Selection signal S2 is a different selection signal from selection signal S1. In the pixel circuit 200, selection signal S2 is a selection signal that controls the supply of data signal Vdata to retention capacitance elements C1 and C2. When transistor P2 is ON, transistor P2 supplies data signal Vdata, supplied from driver IC 134 via data line 237, to retention capacitance elements C1 and C2.

[0036] [Pixel circuit operation] Figure 3 shows the timing chart of the signals that control the pixel circuit 200 shown in Figure 2 during one frame period. Figure 3 shows the timing chart for selecting the k-th row and writing the data signal to the pixel circuit 200. Specifically, Figure 3 shows the selection signal S1, selection signal S2, light emission control signal Em, and data signal Vdata.

[0037] The period before time T1 is the light emission period. Selection signals S1 and S2 are High, and the light emission control signal Em is Low. During this period, transistor P5 is ON, and all other transistors are OFF. Therefore, the voltage held in the series combined capacitance of retention capacitors C1 and C2 provides a drive current to the OLED element E1 from the power line 241 via drive transistors P1 and P5, causing the OLED element E1 to emit light.

[0038] The period from time T1 to T2 is the initialization period. At time T1, the selection signal S1 changes from High to Low. The selection signal S2 remains High, and the light emission control signal Em remains Low. At time T1, transistors P3, P4, and P6 are ON. Transistor P2 remains OFF, and transistor P5 remains ON.

[0039] Figure 4A shows the transistors that are ON, the potentials of several nodes, and the current flow within the pixel circuit 200 during the initialization period. Current flows from the transmission line 202 at the reference potential Vref to the transmission line 242 at the reset potential Vrst via transistors P3, P5, and P6. Current flows from the transmission line 241 at the positive power supply potential VDD to the transmission line 242 at the reset potential Vrst via transistors P1, P5, and P6.

[0040] The intermediate node potential between capacitive elements C1 and C2 changes to the reference potential Vref. The charge held in capacitive element C2 discharges, and the gate potential of the drive transistor P1 is initialized (reset). The gate potential of the drive transistor P1 changes to the reset potential Vrst. By applying the reset potential Vrst to the gate of the drive transistor P1 every frame, the voltage corresponding to the gradation of the previous frame is reset, and the effects of hysteresis can be reduced. In addition, the anode potential of the OLED element is initialized. The anode potential drops to the reset potential Vrst. This prevents abnormal light emission of the OLED element E1 outside of the light emission period.

[0041] Returning to Figure 3, at time T2, the light emission control signal Em changes from Low to High. The selection signal S1 remains Low, and the selection signal S2 remains High. Transistor P5 turns OFF in response to the change in the light emission control signal Em. This state is maintained from time T2 to time T3. From time T2 to time T3 is the correction period for the threshold voltage Vth of the drive transistor P1.

[0042] Figure 4B shows the ON transistors, potentials of several nodes, and current flow within the pixel circuit 200 during the Vth correction period (threshold correction period). Transistor P3 remains ON, and the drain and gate of the drive transistor P1 are connected. The drive transistor P1 is in a diode connection state. Current flows from the transmission line 241 of the positive power supply potential VDD to the capacitive element C2 via transistors P1 and P3.

[0043] The gate-source voltage of the drive transistor P1 drops to the threshold voltage, and the current stops. The source potential of the drive transistor P1 is the positive power supply potential VDD, and the gate potential is VDD + Vth. The node potential between capacitor element C2 and capacitor element C1 is the reference potential Vref.

[0044] Returning to Figure 3, at time T3, selection signal S1 changes from Low to High, and selection signal S2 changes from High to Low. The light emission control signal Em remains High. Transistors P3, P4, and P6 turn OFF in response to the change in selection signal S1. Transistor P2 turns ON in response to the change in selection signal S2. Since the light emission control signal Em remains High, transistor P5 remains OFF. From time T3 to time T4 is the data writing period, during which data signals are written to the retaining capacitance elements C1 and C2.

[0045] Figure 4C shows the potentials of the ON transistors and several nodes within the pixel circuit 200 during the data writing period. Only transistor P2 is ON. A data signal (data potential) Vdata is applied to the intermediate node between capacitive elements C1 and C2, and its potential changes from the reference potential Vref to the data signal Vdata. The gate potential of the driving transistor P1 is (VDD + Vth + Vdata - Vref) according to the law of conservation of charge.

[0046] Returning to Figure 3, at time T4, the selection signal S2 changes from Low to High, and the light emission control signal Em changes from High to Low. The selection signal S1 remains High. Transistor P2 turns OFF in response to the change in selection signal S2. Transistor P5 turns ON in response to the change in light emission control signal Em. Transistors P3, P4, and P6 remain OFF.

[0047] The period from time T4 onwards is the light emission period. The drive transistor P1 supplies a drive current to the OLED element E1 via transistor P5, according to the voltage between the positive power supply potential VDD and the above potential (VDD + Vth + Vdata - Vref). This state continues until time T1 of the next frame.

[0048] In the example shown in Figure 3, the data writing period (also called the 1H period) is the reference period, the initialization period is the same as the reference period, and the Vth correction period is longer than the reference period and has an integer multiple of its length. In the example in Figure 3, the Vth correction period is six times the length of the reference period. In this circuit, it is possible to adjust the length of the Vth correction period without changing the data writing period. By adjusting the Vth correction period, image retention can be effectively suppressed.

[0049] The initialization period can be set to, for example, 1H to 3H, and the Vth correction period can be set to, for example, 3H to 40H. In other words, the Vth correction period can be set to more than 3 times and less than 40 times the data writing period. As mentioned above, 1H is the length of the data writing period, for example, about 3μs.

[0050] Figure 5A shows the time evolution of the selection signal S1 for consecutive pixel rows. The selection signal S1 is output sequentially to each pixel row from the shift register circuit in the scanning circuit 131. Figure 5A shows the time evolution of the start pulse ST of the shift register circuit, the selection signal S1_1 for the first row, and the selection signal S1_2 for the second row. The selection signal S1 for each row is shifted by a unit of time (1H period). The length of the selection signal S1 is the same as in the example shown in Figure 3.

[0051] Figure 5B shows the time evolution of the selection signal S2 for consecutive pixel rows. The selection signal S2 is output sequentially to each pixel row from the shift register circuit in the scanning circuit 131. Figure 5B shows the time evolution of the start pulse ST of the shift register circuit, the selection signal S2_1 for the first row, and S2_2 for the second row. The selection signal S2 for each row is shifted by a unit of time (1H period). The length of the selection signal S2 is the same as in the example shown in Figure 3.

[0052] Figure 5C shows the time variation of the light emission control signal Em for consecutive pixel rows. The light emission control signal Em is output sequentially to each pixel row from the shift register circuit in the scanning circuit 132. Figure 5C shows the time variation of the start pulse ST of the shift register circuit, the light emission control signal Em_1 for the first row, and the light emission control signal Em_2 for the second row. The light emission control signals Em for each row are shifted by a unit of time (1H period). The length of the light emission control signals Em is the same as in the example shown in Figure 3.

[0053] The pixel circuit described with reference to Figures 3 to 5C consists of six transistors P1 to P6 and two capacitive elements C1 and C2. The pixel circuit is controlled by three types of control signals S1, S2, and Em. Therefore, while effectively suppressing image retention, a narrow bezel and high resolution can be achieved with a small pixel circuit size and fewer control signals.

[0054] As described above, the pixel circuit 200 resets the anode potential of the OLED element E1 using the reset potential Vrst. This prevents abnormal light emission during the non-emitting period of the OLED element E1 and enables high contrast.

[0055] Furthermore, the pixel circuit 200 can adjust the Vth correction period regardless of the data writing period. By setting the Vth correction period to an appropriate length, appropriate Vth correction and the resulting suppression of image retention can be achieved. This is particularly effective when driving at high frame rates.

[0056] The pixel circuit 200 described above includes two capacitive elements C1 and C2 connected in series between the gate and source of the drive transistor P1. These series-connected capacitive elements C1 and C2 hold a control voltage that controls the amount of drive current flowing through the drive transistor P1. As described above, the gate potential of the drive transistor P1 after data writing does not depend on the capacitance values ​​of the capacitive elements C1 and C2. Therefore, it is possible to avoid the influence of manufacturing variations of the capacitive elements C1 and C2 on the drive current of the OLED element.

[0057] Furthermore, in pixel circuits using series-connected capacitive elements, the slope of the change in the OLED element's current Ioled relative to the data signal Vdata (Ioled-Vdata characteristic) is large. Therefore, by narrowing the range of the data signal Vdata used, low power consumption can be achieved. Conversely, high brightness can be achieved within a narrow range of the data signal Vdata.

[0058] [Other pixel circuits] Next, we will describe examples of other pixel circuits. Figure 6 shows a pixel circuit 300 of another configuration example according to one embodiment of this specification. The pixel circuit 300 consists of six transistors P11 to P16 and two retaining capacitance elements C11 and C12. Transistors P11 to P16 are P-type TFTs.

[0059] Transistors P12, P13, P14, P15, and P16 are the 6th, 7th, 8th, 9th, and 10th switch transistors, respectively. The pixel circuit corresponding to the pixel circuit shown in Figure 6 may be constructed using N-type TFTs. The retaining capacitance elements C11 and C12 are the 3rd and 4th capacitance elements, respectively.

[0060] Transistor P11 is a drive transistor that controls the amount of current supplied to the OLED element E1. The drive transistor P11 controls the amount of current supplied to the OLED element E1 from the power supply providing the positive power supply potential VDD, according to the voltage held by the retention capacitor C12. This is because both ends of C11 are connected at VDD. The retention capacitor C12 holds the written voltage throughout one frame period.

[0061] Generally, if the potential of the data line oscillates with each horizontal period, the parasitic capacitance between the data line and the gate node of the drive transistor changes the gate node potential of the drive transistor, causing a change in brightness (crosstalk). When the capacitance is maintained by the series combined capacitance of C1 and C2, the holding capacitance value is small, and crosstalk is likely to occur. On the other hand, in contrast to this, a single-capacitor circuit like C12 in Figure 6 has a larger holding capacitance, and therefore is less likely to cause crosstalk. The holding capacitance element C11 contributes to threshold voltage correction. The cathode of the OLED element E1 is connected to the power line 304 that transmits the negative power supply potential VEE from the cathode power supply.

[0062] In the configuration example shown in Figure 6, the capacitive elements C11 and C12 are connected in series between the power line 341, which transmits the positive power supply potential VDD, and the gate of the drive transistor P11. One end of the retaining capacitance element C11 is connected to the power line 341. One end of the retaining capacitance element C12 is connected to the gate of the drive transistor P11. The intermediate nodes of the retaining capacitance elements C11 and C12 are connected to the source of the drive transistor P11.

[0063] The voltage across the retaining capacitance elements C11 and C12 is the voltage between the gate of the drive transistor P11 and the power supply line 341. The source of the drive transistor P11 is connected to the power supply line 341 via the switch transistor P13. When transistor P13 is ON, the retaining capacitance element C12 retains the gate-source voltage of the drive transistor P11.

[0064] Transistors P13 and P15 are switch transistors that control the ON / OFF state of the light emission of the OLED element E1. The source of transistor P13 is supplied with a positive power supply potential VDD, and its drain is connected to the source of the drive transistor P11. The source of transistor P15 is connected to the drain of the drive transistor P11. The gates of transistors P13 and P15 are connected to the light emission control line 333, and transistors P13 and P15 are similarly controlled by the light emission control signal Em input to the gate from the scanning circuit 132.

[0065] Transistor P16 operates to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of transistor P16 is connected to the power line 302 that transmits the reset potential Vrst, and the other end is connected between the drain of the drive transistor P11 and the source of the switch transistor P15.

[0066] The gate of transistor P16 is connected to a selection signal line 331 that transmits a selection signal S1, and transistor P16 is controlled by the selection signal S1. When transistor P16 is turned ON by the selection signal S1 input to its gate from the scanning circuit 131, it applies a reset potential Vrst transmitted by the power line 342 to the anode of the OLED element E1 while transistor P15 is ON.

[0067] Transistor P14 is a switch transistor that writes the voltage for threshold compensation of the drive transistor P11 to the retaining capacitance element C12. Transistor P14 controls whether or not a reference potential Vref is supplied to the retaining capacitance element C12.

[0068] One end of the source / drain of transistor P14 is connected to a power line 302 that transmits a reference potential Vref, and the other end is connected to one end of a retaining capacitance element C12. The gate of transistor P14 is connected to a selection signal line 331 that transmits a selection signal S1, and transistor P14 is controlled by the selection signal S1 input to the gate from the scanning circuit 131.

[0069] When transistor P14 is ON, the drive transistor P11 forms a source follower circuit, and its threshold voltage is written to the capacitive element C12 between the gate and source of the drive transistor P11. The voltage of the retaining capacitance element C11 is determined by the voltage between the positive power supply potential VDD and the reference potential Vref, and the threshold voltage of the drive transistor P11.

[0070] Transistor P12 is a switch transistor that selects the pixel circuit to supply the data signal and writes the data signal (data signal voltage) to the gate of the drive transistor P11. One end of the source / drain of transistor P12 is connected to the data line 337 that transmits the data signal Vdata, and the other end is connected to the retaining capacitance element C12.

[0071] The gate of transistor P12 is connected to the selection signal line 332, which transmits the selection signal S2. Transistor P12 is controlled by the selection signal S2 supplied from the scanning circuit 131. When transistor P12 is ON, it supplies the data signal Vdata, supplied from the driver IC 134 via the data line 337, to the gate of the drive transistor P11.

[0072] The retaining capacitance elements C11 and C12 are connected in series between the power line 341, which transmits the positive power supply potential VDD, and the gate of the drive transistor P11. The potential of the node between retaining capacitance elements C11 and C12 is applied to the source of the drive transistor P11. The potential of the node between retaining capacitance elements C11 and C12 is based on the data signal Vdata, the reference potential Vref, the threshold voltage Vth of the drive transistor P11, and the capacitance values ​​of retaining capacitance elements C11 and C12. Specifically, it is expressed as (Vdata * C1 / (C1 + C2) - Vth + Vref * C1 / (C1 + C2)).

[0073] Subsequently, when Em goes low, the current node becomes Vdd, but the voltage held by the retaining capacitance element C12 is maintained. Therefore, the potential of the gate node of the drive transistor P11 becomes ((Vdata-Vref)*C1 / (C1+C2)+Vdd+Vth). In other words, during the light emission period, the gate-source voltage of the drive transistor P11 is maintained at ((Vdata-Vref)*C1 / (C1+C2)+Vth).

[0074] During one frame period, the timing chart of the signals controlling the pixel circuit 300 shown in Figure 6 is the same as the timing chart shown in Figure 3. Figure 7A shows the transistors that are ON during the initialization period. During the initialization period, transistors P16 and P15 are ON. Therefore, a reset potential Vrst is applied to the anode of the OLED element E1. This prevents abnormal light emission of the OLED element E1 during the non-light emission period. Transistor P14 turns ON, and the gate of the drive transistor P11 is reset at Vref.

[0075] Figure 7B shows the ON transistors, potentials of several nodes, and current flow within the pixel circuit 300 during the Vth correction period. Transistors P14 and P16 are ON, while the other transistors are OFF.

[0076] Transistor P14 is ON, and the gate of the drive transistor P11 is supplied with a reference potential Vref. Transistor P16 is ON, and the drain of the drive transistor P11 is supplied with a reset potential Vrst. The potential of the source of the drive transistor P11, i.e., the potential of the node between the retaining capacitance elements C11 and C12, is Vref-Vth. The retaining capacitance element C12 holds the threshold voltage Vth of the drive transistor P11. After the Vth correction period, the data signal Vdata is supplied to the gate of the drive transistor P11 and the retaining capacitance element C12.

[0077] As described above, the pixel circuit 300 resets the anode potential of the OLED element E1 with the reset potential Vrst. This prevents abnormal light emission during the non-light-emitting period of the OLED element E1 and enables high contrast.

[0078] Furthermore, the pixel circuit 300 can adjust the Vth correction period regardless of the data writing period. By setting the Vth correction period to an appropriate length, appropriate Vth correction and the resulting suppression of image retention can be achieved. In particular, in high frame rate driving, the problem becomes more pronounced when the 1 horizontal period 1H is short, so this can have a significant effect.

[0079] The pixel circuit 300 above applies a low reset potential Vrst to the drain of the drive transistor P11 during the Vth correction period. Therefore, the drain-source voltage of the drive transistor P11 is always sufficiently large. Even if the drive transistor P11 has normally-on characteristics and the gate-source voltage becomes positive, the drain potential is fixed at Vrst, so current flows through the drive transistor P11, making it possible to perform Vth correction.

[0080] Next, we will describe examples of other pixel circuits. Figure 8 shows a pixel circuit 400 of another configuration example according to one embodiment of this specification. The pixel circuit 400 consists of six transistors P21 to P26 and two capacitive elements C21 and C22. Transistors P21 to P26 are P-type TFTs.

[0081] Transistors P22, P23, P24, P25, and P26 are the 11th, 12th, 13th, 14th, and 15th switch transistors, respectively. The pixel circuit corresponding to the pixel circuit shown in Figure 8 may be constructed using N-type TFTs. The retaining capacitance elements C21 and C22 are the 5th and 6th capacitance elements, respectively.

[0082] Transistor P21 is a drive transistor that controls the amount of current supplied to the OLED element E1. The drive transistor P21 controls the amount of current supplied to the OLED element E1 from the power supply that provides the positive power supply potential VDD, according to the voltages held by the retaining capacitance elements C21 and C22. The retaining capacitance elements C21 and C22 hold the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to power line 404, which transmits the negative power supply potential VEE from the cathode power supply.

[0083] In the configuration example shown in Figure 8, the retaining capacitance elements C21 and C22 are connected in series between the power line 441, which transmits the positive power supply potential VDD, and the gate of the drive transistor P21. One end of retaining capacitance element C21 is connected to the power line 441. One end of retaining capacitance element C22 is connected to the gate of the drive transistor P21. The intermediate nodes of retaining capacitance elements C21 and C22 are connected to the source / drain of transistor P25.

[0084] The voltage across the retaining capacitance elements C21 and C22 is the voltage between the gate of the drive transistor P21 and the positive power supply line 441. The source of the drive transistor P21 is connected to the positive power supply line 441 via the switch transistor P23. When transistor P23 is ON, the retaining capacitance elements C21 and C22 retain the gate-source voltage of the drive transistor P21.

[0085] Transistor P23 is a switch transistor that controls the ON / OFF state of the light emission of the OLED element E1. The source of transistor P23 is supplied with a positive power supply potential VDD, and its drain is connected to the source of the drive transistor P21. The gate of transistor P23 is connected to the light emission control line 433, and transistor P23 is controlled by the light emission control signal Em input to the gate from the scanning circuit 132.

[0086] Transistor P26 operates to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of transistor P26 is connected to the power line 442 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0087] The gate of transistor P26 is connected to a selection signal line 431 that transmits a selection signal S1, and transistor P26 is controlled by the selection signal S1. When transistor P26 is turned ON by the selection signal S1 input to its gate from the scanning circuit 131, it applies a reset potential Vrst transmitted by the power line 442 to the anode of the OLED element E1.

[0088] Transistors P24, P25, and P26 are switch transistors for writing the voltage for threshold compensation of the drive transistor P21 to the retaining capacitance element C22. Transistor P24 controls whether or not a reference potential Vref is supplied to the retaining capacitance element C22. Transistor P26 controls whether or not a reset potential Vrst is supplied to the drain of the drive transistor P21. Transistor P25 switches the connection between the source of the drive transistor P21 and the intermediate nodes of the retaining capacitance elements C21 and C22.

[0089] One end of the source / drain of transistor P24 is connected to a power line 402 that transmits a reference potential Vref, and the other end is connected to one end of a retaining capacitance element C22. The gate of transistor P24 is connected to a selection signal line 431 that transmits a selection signal S1, and transistor P24 is controlled by the selection signal S1 input to the gate from the scanning circuit 131.

[0090] One end of the source / drain of transistor P25 is connected to the source of the drive transistor P21, and the other end is connected to the intermediate node of the retaining capacitance elements C21 and C22. The gate of transistor 25 is connected to a selection signal line 431 that transmits a selection signal S1, and transistor P25 is controlled by the selection signal S1 input to the gate from the scanning circuit 131.

[0091] When transistors P24 and P25 are ON, the drive transistor P21 forms a source follower circuit, and its threshold voltage is written to the capacitive element C22 between the gate and source of the drive transistor P21. The voltage of the retaining capacitance element C21 is determined by the voltage between the positive power supply potential VDD and the reference potential Vref, and the threshold voltage of the retaining capacitance element C22. Here, the gate potential of the drive transistor P21 is Vref, and the intermediate node between retaining capacitance elements C21 and C22 is (Vref-Vth).

[0092] Transistor P22 is a switch transistor that selects the pixel circuit to supply the data signal and writes the data signal to the retaining capacitance elements C21 and C22. One end of the source / drain of transistor P22 is connected to the data line 437 that transmits the data signal Vdata, and the other end is connected to the intermediate node of the retaining capacitance elements C21 and C22.

[0093] The gate of transistor P22 is connected to the selection signal line 432, which transmits the selection signal S2. Transistor P22 is controlled by the selection signal S2 supplied from the scanning circuit 131. When transistor P22 is ON, it supplies the data signal Vdata, supplied from the driver IC 34 via the data line 437, to the retaining capacitance elements C21 and C22. The intermediate node between retaining capacitance elements C21 and C22 is at Vdata, and the potential of the gate of the driving transistor P21 is (Vdata + Vth).

[0094] When the light emission period begins, transistor P23 turns on, and the source of the drive transistor P21 is connected to the positive power supply potential Vdd. However, the gate potential of the drive transistor P21 is maintained at (Vdata + Vth) because it is held by the series equivalent capacitance of the retaining capacitance elements C21 and C22.

[0095] During one frame, the timing chart of the signals controlling the pixel circuit 400 shown in Figure 8 is the same as the timing chart shown in Figure 3. During the light emission period, transistor P25 is OFF and transistor P23 is ON. The voltages held by the retention capacitive elements C21 and C22 are applied between the gate and source of the drive transistor P21, and the drive transistor P21 supplies a drive current to the OLED element E1 corresponding to that voltage.

[0096] As described above, the pixel circuit 400 resets the anode potential of the OLED element E1 with the reset potential Vrst. This prevents abnormal light emission during the non-light-emitting period of the OLED element E1 and enables high contrast.

[0097] Furthermore, the pixel circuit 400 can adjust the Vth correction period regardless of the data writing period. By setting the Vth correction period to an appropriate length, appropriate Vth correction and the resulting suppression of image retention can be achieved. This is particularly effective when driving at high frame rates.

[0098] The gate potential of the drive transistor P21 after data writing does not depend on the capacitance values ​​of the capacitive elements C21 and C22. Therefore, it is possible to avoid the influence of manufacturing variations of the capacitive elements C21 and C22 on the drive current of the OLED element.

[0099] Furthermore, because the pixel circuit 400 has a large slope of change in the OLED element current Ioled relative to the data signal Vdata (Ioled-Vdata characteristic), narrowing the range of the data signal Vdata used allows for a smaller amplitude of the data line potential when the displayed image changes, such as in video, and a smaller charge for charging and discharging the capacitor coupled to the data line, thus achieving low power consumption. This is because the gate-source voltage of the drive transistor P21 is (Vdata + Vth - Vdata) and is not affected by the values ​​of the retaining capacitor elements 21 and 22. Conversely, high brightness can be achieved within a narrow range of the data signal Vdata.

[0100] The pixel circuit 400 described above applies a low reset potential Vrst to the drain of the drive transistor P21 during the Vth correction period. Therefore, the drain-source voltage of the drive transistor P21 is always sufficiently large. Even if the drive transistor P21 has normally-on characteristics, current flows through the drive transistor P21, making it possible to perform Vth correction.

[0101] Next, we will describe examples of other pixel circuits. Figure 9 shows a pixel circuit 500 of another configuration example according to one embodiment of this specification. In the following, we will mainly describe the differences from the pixel circuit 200 shown in Figure 2. The pixel circuit 500 consists of six transistors N1 to N6 and two capacitive elements C31 and C32. Transistors N2, N3, N4, N5, and N6 are the first, second, third, fourth, and fifth switch transistors, respectively.

[0102] Transistors N1 to N6 are N-type TFTs. N-type TFTs are, for example, oxide semiconductor TFTs. Pixel circuit 500 has a circuit configuration in which the P-type transistors in pixel circuit 200 shown in Figure 2 are replaced with N-type transistors. Retaining capacitance elements C31 and C32 correspond to retaining capacitance elements C1 and C2, respectively. Retaining capacitance elements C31 and C32 are the first capacitance element and the second capacitance element, respectively.

[0103] Figure 10 shows the timing chart of the signals that control the pixel circuit 500 shown in Figure 9 during one frame period. The control signals S11, S21, and Em1 show time variations with opposite polarity to the control signals S1, S2, and Em shown in Figure 3, respectively. As a result, transistors N1 to N6 operate in the same way as transistors P1 to P6 in the pixel circuit 200 shown in Figure 2. The pixel circuit 500 can achieve the effects described above for the pixel circuit 200 shown in Figure 2.

[0104] Power lines 502, 504, 541, and 542 transmit the reference potential Vref, reset potential Vrst, positive power supply potential VDD, and negative power supply potential VEE, respectively. Signal line 537 transmits the data signal Vdata, control lines 531 and 532 transmit the selection signals S11 and S21, respectively, and control line 533 transmits the light emission control signal Em1.

[0105] Figures 11A to 11C show the ON transistors and the potentials of several nodes in the pixel circuit 500 during the initialization period, Vth correction period, and data writing period, respectively.

[0106] As shown in Figure 11A, transistors N3 to N6 are ON during the initialization period. The drain and gate potentials of the drive transistor N1 are at the positive power supply potential VDD. The intermediate nodes of the holding capacitance elements C31 and C32 are at the reference potential Vref, and the anode of the OLED element E1 is at the reset potential Vrst.

[0107] As shown in Figure 11B, transistors N3, N4, and N6 are ON during the Vth correction period. The gate potential of the drive transistor N1 is Vrst + Vth. The intermediate nodes of the holding capacitance elements C31 and C32 are at the reference potential Vref, and the anode of the OLED element E1 is at the reset potential Vrst.

[0108] As shown in Figure 11C, transistor N2 is ON during the data writing period. The intermediate nodes of the holding capacitance elements C31 and C32 are at the data signal (potential) Vdata, and the anode of the OLED element E1 is at the reset potential Vrst. The gate potential of the driving transistor N1 is (Vdata - Vref + Vrst + Vth). During the light emission period, the gate potential of the driving transistor N1 is maintained at (Vdata - Vref + Vrst + Vth).

[0109] Next, examples of other pixel circuits will be described. Figure 12A shows an example configuration of a pixel circuit 600 and control signal according to one embodiment of this specification. The main differences from the pixel circuit 200 shown in Figure 2 will be explained. The pixel circuit 600 includes N-type transistors N12, N13, N14, and N16 instead of the P-type transistors P2, P3, P4, and P6 of the pixel circuit 200. The N-type transistors N12, N13, N14, and N16 are, for example, oxide semiconductor transistors. The P-type transistors P1 and P5 are, for example, low-temperature polysilicon thin-film transistors. During the light emission period, the gate voltage Vgs of the driving transistor P1 is (Vdata - Vref + Vth).

[0110] The sources and drains of transistors N12, N13, and N14 are connected to holding capacitors, respectively. Oxide semiconductor transistors have low off-leak currents, allowing them to maintain the voltage (charge) held by the holding capacitors for extended periods. In low-frequency driving, the duration of one frame is long, meaning the light emission period is also long. As a result, brightness changes are large until the image is refreshed, such as by writing a video signal, and flicker (blinking or flickering) becomes a problem. This configuration suppresses flicker in low-frequency driving.

[0111] In the circuit configuration example shown in Figure 12A, transistor N16 has the same conductivity type as transistors N13 and N14. The number of control signals can be reduced by controlling the three transistors N13, N14, and N16 with a single S1 signal (three signals in Figure 12A).

[0112] The control signals for the pixel circuit 600 include selection signals S31 and S32, and light emission control signal Em. Figure 12B shows a timing chart of the signals that control the pixel circuit 600 shown in Figure 12A during one frame period. Figure 12B shows a timing chart for selecting the k-th row and writing the data signal to the pixel circuit 600. Specifically, Figure 12B shows selection signals S31 and S32, and light emission control signal Em.

[0113] The period before time T11 is the light emission period. The selection signal S31, selection signal S32, and light emission control signal Em are Low. During this period, transistor P5 is ON, and the other transistors are OFF. Therefore, the voltage held in the series combined capacitance of retention capacitors C1 and C2 provides a drive current to the OLED element E1 from the power line 241 via drive transistors P1 and P5, causing the OLED element E1 to emit light.

[0114] The initialization period is from time T11 to T12. At time T11, the selection signal S31 changes from Low to High. The selection signal S32 remains Low, and the light emission control signal Em remains Low. At time T11, transistors N13, N14, and N16 are turned ON. Transistor N12 remains OFF, and transistor P5 remains ON.

[0115] At time T12, the light emission control signal Em changes from Low to High. The selection signal S31 remains High, and the selection signal S32 remains Low. Transistor P5 turns OFF in response to the change in the light emission control signal Em. This state is maintained from time T12 to time T13. From time T12 to time T13 is the correction period for the threshold voltage Vth of the drive transistor P1. In the example shown in Figure 12B, the Vth correction period is 7H (7 horizontal periods). 1H is, for example, 3μs at a frame frequency of 120Hz.

[0116] At time T13, the selection signal S31 changes from High to Low. The light emission control signal Em remains High. Transistors N13, N4, and N6 turn OFF in response to the change in the selection signal S31.

[0117] A few hours after time T13, 5 hours after the example in Figure 12B, at time T14, the selection signal S32 changes from Low to High. The selection signal S31 remains Low, and the light emission control signal Em remains High. Transistor N12 turns ON in response to the change in selection signal S32. Since the light emission control signal Em remains High, transistor P5 remains OFF. From time T14 to time T15 is the data writing period (1H) during which data signals are written to the holding capacitance elements C1 and C2.

[0118] At time T15, the selection signal S32 changes from High to Low. The selection signal S1 remains Low, and the light emission control signal Em remains High. In response to the change in the selection signal S2, transistor N12 turns OFF.

[0119] A few hours after time T13, 5 hours after the example in Figure 12B, at time T16, the light emission control signal Em changes from High to Low. Selection signals S31 and S32 remain Low. Transistor P5 turns ON in response to the change in the light emission control signal Em. Transistors N12, N13, N14 and N16 remain OFF.

[0120] The period from time T16 onwards is the light emission period. The drive transistor P1 supplies a drive current to the OLED element E1 via transistor P5, according to the above voltage (Vdata - Vref + Vth). This state continues until time T11 of the next frame.

[0121] The relationship between pixel circuit 600 and pixel circuit 200 can be applied to pixel circuit 300 or 400 to change some of the P-type transistors to N-type transistors. For example, in pixel circuit 300, transistors P12, P14, and P16 may be changed to N-type transistors, or in pixel circuit 400, transistors P22, P24, P25, and P26 may be changed to N-type transistors.

[0122] Next, we will describe examples of other pixel circuits. Figure 13A shows an example configuration of a pixel circuit 700 and a control signal according to one embodiment of this specification. We will mainly describe the differences from the pixel circuit 200 shown in Figure 2. In addition to the configuration of the pixel circuit 200, the pixel circuit 700 includes a P-type switch transistor P7. Transistor P7 is located between the drive transistor P1 and the power line 241, with its source connected to the power line 241 and its drain connected to the source of the drive transistor P1.

[0123] Transistor P7 is OFF during the initialization period, disconnecting the pixel circuit 700 from the power line 241. This prevents shoot-through current from flowing between the power supply VDD and power supply Vrst. This will be explained in more detail with reference to Figure 13B. When transistor P7 is OFF, the retained charge flows to the reset power line 242, and the current flowing through the drive transistor P1 gradually decreases. As the anode potential of the OLED element E1 decreases, the black brightness decreases, and power consumption also decreases by preventing shoot-through current.

[0124] Figure 14 shows the timing chart of the signals controlling the pixel circuit 700 shown in Figure 13A during one frame period. The main point to explain is the difference from the timing chart shown in Figure 3. In addition to the time variation of the selection signals S1 and S2 and the light emission control signal EM shown in Figure 3, a second light emission control signal Em2 is applied to the gate of transistor P7. The second light emission control signal Em2 is High during the initialization period (T1 to T2) and Low during other periods. Transistor P7 is OFF during the initialization period and ON during other periods.

[0125] Figure 15 schematically shows an example of a circuit layout that provides control signals S1, S2, Em, and Em2 to the pixel circuit 700. Two scanning circuits 131A and 131B are located on the left side of the display area, and two scanning circuits 132A and 132B are located on the right side. Each scanning circuit includes a shift register. Scanning circuits 131A and 131B output selection signals S1 and S2, respectively. Scanning circuits 132A and 132B output light emission control signals Em and Em2, respectively.

[0126] [Vth correction period] The Vth correction period will be explained below. According to the inventors' research, it has been found that by keeping the Vth correction period within a predetermined range, image retention can be reduced to a negligible level. First, an example of image retention will be explained.

[0127] For example, if a fixed pattern of black and white checkerboard is displayed on an OLED display device, and then the entire display is switched to an image with the same intermediate grayscale, an afterimage influenced by the fixed pattern will be displayed for a while. The intensity (brightness difference) and duration of the afterimage depend on the display time (stress time) of the fixed pattern, and the afterimage decreases over time. Image retention afterimages can be negative (opposite polarity), showing the opposite brightness and darkness to the fixed pattern, or positive (same polarity), showing the same brightness and darkness to the fixed pattern.

[0128] Figure 16 shows the change in pixel drive current (transient current) in negative image retention. The drive current is the current flowing through the OLED element, and the larger the drive current, the higher the brightness of the OLED element. In Figure 16, the horizontal axis represents time, and the vertical axis represents the drive current. Current LB represents the drive current of a pixel changing from black (lowest grayscale) to an intermediate grayscale. Current LA represents the drive current of a sub-pixel changing from white (highest grayscale) to an intermediate grayscale.

[0129] At time T0, the data signal to the pixels switches from the initial image value to the target image value. The drive current LB of the pixels displaying black increases beyond the target drive current L (overshoot), and then gradually decreases toward the target drive current L. Conversely, the drive current LA of the sub-pixels displaying white decreases beyond the target drive current L (undershoot), and then gradually increases toward the target drive current L.

[0130] In positive-type image retention, the drive current LB of a subpixel displaying black rapidly increases to a value smaller than the target drive current L, and then gradually increases toward the target drive current L. Conversely, the drive current LA of a subpixel displaying white rapidly decreases to a value larger than the target drive current L, and then gradually decreases toward the target drive current L.

[0131] The current difference |ΔIR| = |IA - IB| is defined for transient currents. The current difference |ΔIR| is the absolute value of the difference between current LA and current LB at time T0.

[0132] The inventors studied the relationship between image retention and the difference in transient current and found that when the ratio of the difference in transient current to the target current L, |ΔIR| / L, is small, image retention becomes undetectable. Specifically, when the ratio of the difference in transient current, |ΔIR| / L, is 1% (0.01) or less, the effect of image retention could be ignored.

[0133] Figure 17 shows a graph of measured values ​​relating the Vth correction period to the ratio of the difference in transient currents, |ΔIR| / L. The horizontal axis represents the length of the Vth correction period, and the vertical axis represents the ratio of the difference in transient currents, |ΔIR| / L. It was found that the ratio of the difference in transient currents, |ΔIR| / L, is maintained at 1% or less when the Vth correction period is in the range of 10 microseconds (μs) to 120 μs. Therefore, by setting the Vth correction period within the range of 10 μs to 120 μs, it is possible to effectively suppress image retention.

[0134] [Control signal] The control signals for the pixel circuit will be described below. In one embodiment of this specification, the phase difference θ between the selection signal S2 (scanning signal) and the data signal Vdata is defined. The selection signal S2 is a control signal that turns ON / OFF transistors P2, P12, P22, etc., which control the writing of the data signal to the pixel circuit.

[0135] In one embodiment of this specification, the phase difference θ between two signals is defined as follows: where f is the frame frequency and t is the time difference between the two signals. -π / 3≦θ≦0 (If f=120Hz, -2μs≦t≦0)

[0136] Figure 18 schematically shows the phase relationship between the selection signal S2 and the data signal Vdata. The phase of the two signals is defined at the midpoint between the falling and rising edges of the pulse (the center point of the low level). The phase difference is negative when the phase of the selection signal S2 is leading the phase of the data signal Vdata, and positive when it is lagging. Figure 18 shows the selection signal S2 and the data signal Vdata with phase differences θ of -2π, -π / 3, and 0, from top to bottom. The phase difference of -2π is the same as the phase difference of 0.

[0137] As described above, the control sequence of the pixel circuit is time-division multiplexed for Vth correction and data writing. On the other hand, in the example of a related pixel circuit of a 7-transistor 1-capacitor element (7T1C), Vth correction and data writing are simultaneous, and it takes time for the gate voltage Vg of the drive transistor P1 to converge. In this embodiment, Vth correction is completed when data is written, and only the data voltage (video signal) is written. As a result, the gate voltage of the drive transistor P1 changes immediately as the S2 pulse falls.

[0138] Thus, a difference arises in the phase difference dependence of the gate voltage between the related example and this embodiment. In this embodiment, the phase difference margin is wide, and in Figure 18, the phase difference margin is biased to the left. By setting the phase difference within the above range, the intrusion of data signals for adjacent lines can be prevented, and display defects can be suppressed. The above explanation of the phase difference is the same for pixel circuits including N-type transistors.

[0139] Figure 19A shows the simulation results of the time evolution of the gate voltage Vg of the drive transistor, the selection signal S2, and the data signal Vdata in an example of a related pixel circuit for 7T1C. Lines 601, 602, and 603 show the simulation results of the time evolution of the selection signal S2, the data signal Vdata, and the gate voltage Vg, respectively.

[0140] Figure 19B shows the time evolution of the gate voltage Vg of the drive transistor, the selection signal S2, and the data signal Vdata in this embodiment. Lines 611, 612, and 613 show the time evolution of the selection signal S2, the data signal Vdata, and the gate voltage Vg, respectively. Comparing Figures 19A and 19B, the gate voltage in this embodiment changes simultaneously with the falling edge of the S2 pulse.

[0141] Figure 20A shows the simulation results illustrating the phase difference dependence of the gate voltage in an example of a related pixel circuit for 7T1C. Figure 20B shows the simulation results illustrating the phase difference dependence of the gate voltage in this embodiment. Comparing Figures 20A and 20B, the phase margin in this embodiment is large.

[0142] Next, the potential of the control signals will be explained. In one embodiment of this specification, the Low potential of the selection signal S1 is set to a low value. The selection signal S1 is a control signal that turns ON / OFF transistors P6, P16, P26, etc., which supply the reset potential Vrst to the anode of the OLED element E1. The following explanation will use transistor P6 as an example, but a similar explanation can be applied to transistors P16 and P26.

[0143] For example, the Low potential Vgl of the selection signal S1 is set to (VEE-6.3)V or less. If the cathode power supply potential VEE is -2.7V, the Low potential Vgl of the selection signal S1 is set to -9V or less.

[0144] Figure 21A shows the current flow in the pixel circuit 200 during the initialization period. Some components are omitted. Figure 21B shows the equivalent circuit of the circuit in Figure 21A. The operation during the initialization period was explained with reference to Figure 4A. During the initialization period, the current in transistor P6 is constant, so the gate-source voltage of transistor P6 is constant. Since the source of transistor P6 is also the anode of OLED element E1, as the Low potential Vgl of the selection signal S1 decreases, the anode potential Vanode of OLED element E1 also decreases, and the voltage of OLED element E1 decreases. According to the inventors' experiments, by setting the Low potential Vgl of the selection signal S1 within the above range, abnormal light emission of OLED element E1 during the initialization period was suppressed and the black brightness was reduced.

[0145] Instead of lowering the low potential Vgl of the selection signal S1, lowering the threshold voltage Vth of transistor P6 can suppress abnormal light emission from the OLED element E1 and reduce black brightness. Here, the threshold voltage Vth is defined as Vth = Vgs @ Id = 1e-7A, where Id is the current flowing through transistor P6. According to the inventors' experiments, setting the threshold voltage Vth of transistor P6 to (VEE-1.3) or less suppressed abnormal light emission from the OLED element E1 and reduced black brightness. When the cathode power supply potential VEE is -2.7V, the threshold voltage Vth of transistor P6 is set to -4V or less.

[0146] Figure 22 shows an example of the potentials of the selection signals S1 and S2 and the light emission control signal Em. The high potential of the selection signals S1 and S2 and the light emission control signal Em is 8V and is common to all. The low potential of the selection signal S2 and the light emission control signal Em is -7V, while the low potential of the selection signal S1 is set to -9V or lower.

[0147] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0148] 10 OLED display device 100 TFT substrates 125 Display area 131, 132 Scanning circuits 134 Driver ICs 136 Demultiplexer 200, 300, 400, 500 pixel circuits N1-N6, P1-P26 Thin-Film Transistors C1, C2, C11, C12, C21, C22, C31, C32 Capacitive elements E1 OLED element

Claims

1. A pixel circuit for controlling light emission of a light-emitting element, A light-emitting element; a driving transistor for controlling a driving current to the light-emitting element; a first capacitance element and a second capacitance element connected in series between the gate and the source of the driving transistor; a first switch transistor that switches between connection and disconnection between an intermediate node between the first capacitive element and the second capacitive element and a data line; a second switch transistor that switches between connection and disconnection between the gate and the drain of the drive transistor; a third switch transistor that switches between connection and disconnection between the intermediate node and a reference power supply line; a fourth switch transistor that switches between supplying and not supplying a drive current from the drive transistor to the light emitting element; a fifth switch transistor that switches between connection and disconnection between the anode of the light-emitting element and a reset power line; Including, during an initialization period, the first switch transistor is OFF, and the second switch transistor, the third switch transistor, the fourth switch transistor, and the fifth switch transistor are ON; during a threshold correction period after the initialization period, the first switch transistor and the fourth switch transistor are OFF, and the second switch transistor, the third switch transistor, and the fifth switch transistor are ON, during a data writing period after the threshold correction period, the first switch transistor is ON, and the second switch transistor, the third switch transistor, the fourth switch transistor, and the fifth switch transistor are OFF, during a light emission period after the data writing period, the fourth switch transistor is ON, and the first switch transistor, the second switch transistor, the third switch transistor, and the fifth switch transistor are OFF; Pixel circuit.

2. 2. The pixel circuit of claim 1, the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, and the fifth switch transistor are P-type thin film transistors; the first capacitance element and the second capacitance element are connected in series between a positive power supply line of the light-emitting element and a gate of the driving transistor; Pixel circuit.

3. 2. The pixel circuit of claim 1, the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, and the fifth switch transistor are N-type thin film transistors; the first capacitance element and the second capacitance element are connected in series between the anode of the light-emitting element and the gate of the driving transistor; Pixel circuit.

4. A pixel circuit for controlling light emission of a light-emitting element, A light-emitting element; a driving transistor for controlling a driving current to the light-emitting element; a third capacitance element and a fourth capacitance element connected in series between the gate and the source of the driving transistor; a sixth switch transistor that switches between connection and disconnection between the gate of the driving transistor and a data line; a seventh switch transistor that switches between supplying and not supplying current from a positive power supply line to the drive transistor; a connection line connecting an intermediate node between the drive transistor and the seventh switch transistor and an intermediate node between the third capacitance element and the fourth capacitance element; an eighth switch transistor that switches between connection and disconnection between the gate of the drive transistor and a reference power supply line; a ninth switch transistor that switches between supplying and not supplying current from the drive transistor to the light emitting element; a tenth switch transistor that switches between connection and disconnection between an intermediate node between the drive transistor and the ninth switch transistor and a reset power line; Including, during an initialization period, the sixth switch transistor is OFF, and the seventh switch transistor, the eighth switch transistor, the ninth switch transistor, and the tenth switch transistor are ON; during a threshold correction period after the initialization period, the eighth switch transistor and the tenth switch transistor are ON, and the sixth switch transistor, the seventh switch transistor, and the ninth switch transistor are OFF, during a data writing period after the threshold correction period, the sixth switch transistor is ON, and the seventh switch transistor, the eighth switch transistor, the ninth switch transistor, and the tenth switch transistor are OFF, during a light emission period after the data writing period, the seventh switch transistor and the ninth switch transistor are ON, and the sixth switch transistor, the eighth switch transistor, and the tenth switch transistor are OFF; Pixel circuit.

5. 5. The pixel circuit of claim 4, the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, the ninth switch transistor, and the tenth switch transistor are P-type thin film transistors; Pixel circuit.

6. A pixel circuit for controlling light emission of a light-emitting element, A light-emitting element; a driving transistor for controlling a driving current to the light-emitting element; a fifth capacitance element and a sixth capacitance element connected in series between the gate and the source of the driving transistor; an eleventh switch transistor that switches between connection and disconnection between an intermediate node between the fifth capacitive element and the sixth capacitive element and a data line; a twelfth switch transistor that switches between supplying and not supplying current from a positive power supply line to the light emitting element; a thirteenth switch transistor that switches between connection and disconnection between an intermediate node between the drive transistor and the twelfth switch transistor and an intermediate node between the fifth capacitive element and the sixth capacitive element; a fourteenth switch transistor that switches between connection and disconnection between the gate of the drive transistor and a reference power supply line; a fifteenth switch transistor that switches between connection and disconnection between the anode of the light-emitting element and a reset power line; Including, during an initialization period, the eleventh switch transistor is OFF, and the twelfth switch transistor, the thirteenth switch transistor, the fourteenth switch transistor, and the fifteenth switch transistor are ON; during a threshold correction period after the initialization period, the eleventh switch transistor and the twelfth switch transistor are OFF, and the thirteenth switch transistor, the fourteenth switch transistor, and the fifteenth switch transistor are ON, during a data writing period after the threshold correction period, the eleventh switch transistor is ON, and the twelfth switch transistor, the thirteenth switch transistor, the fourteenth switch transistor, and the fifteenth switch transistor are OFF, during a light emission period after the data writing period, the twelfth switch transistor is ON, and the eleventh switch transistor, the thirteenth switch transistor, the fourteenth switch transistor, and the fifteenth switch transistor are OFF; Pixel circuit.

7. 7. The pixel circuit of claim 6, the eleventh switch transistor, the twelfth switch transistor, the thirteenth switch transistor, the fourteenth switch transistor, and the fifteenth switch transistor are P-type thin film transistors; Pixel circuit.

8. 7. A pixel circuit according to claim 1, 4 or 6, the threshold correction period is 10 μs or more and 120 μs or less; Pixel circuit.

9. 7. A pixel circuit according to claim 1, 4 or 6, the threshold correction period is 3 times or more and 40 times or less than the data writing period; Pixel circuit.

10. 2. The pixel circuit of claim 1, During the initialization period, a phase difference θ of the control signal of the first switch transistor with respect to the phase of the signal on the data line is expressed as follows: −π / 3≦θ≦0 Satisfy the pixel circuit.

11. 5. The pixel circuit of claim 4, During the initialization period, a phase difference θ of the control signal of the sixth switch transistor with respect to the phase of the signal on the data line is −π / 3≦θ≦0 Satisfy the pixel circuit.

12. 7. The pixel circuit of claim 6, During the initialization period, a phase difference θ of the control signal of the eleventh switch transistor with respect to the phase of the signal on the data line is −π / 3≦θ≦0 Satisfy the pixel circuit.

13. 2. The pixel circuit of claim 1, the fifth switch transistor is a P-type thin film transistor; The low potential of the control signal of the fifth switch transistor is Vgl, and the cathode potential of the light emitting element is VEE, Vgl≦VEE-6.3V A pixel circuit in which

14. 5. The pixel circuit of claim 4, the tenth switch transistor is a P-type thin film transistor; The low potential of the control signal of the tenth switch transistor is Vgl, and the cathode potential of the light emitting element is VEE, Vgl≦VEE-6.3V A pixel circuit in which

15. 7. The pixel circuit of claim 6, the fifteenth switch transistor is a P-type thin film transistor; The low potential of the control signal of the 15th switch transistor is Vgl, and the cathode potential of the light emitting element is VEE, Vgl≦VEE-6.3V A pixel circuit in which

16. 2. The pixel circuit of claim 1, the first, second, third, and fifth switch transistors are oxide semiconductor N-type thin film transistors; the driving transistor and the fourth switch transistor are low-temperature polysilicon P-type thin film transistors; Pixel circuit.

17. 5. The pixel circuit of claim 4, the sixth, eighth, and tenth switch transistors are oxide semiconductor N-type thin film transistors; the drive transistor and the twelfth and fourteenth switch transistors are low-temperature polysilicon P-type thin film transistors; Pixel circuit.

18. 7. The pixel circuit of claim 6, the eleventh, thirteenth, fourteenth, and fifteenth switch transistors are oxide semiconductor N-type thin film transistors; the driving transistor and the twelfth switch transistor are low-temperature polysilicon P-type thin film transistors; Pixel circuit.

19. 2. The pixel circuit of claim 1, further including a sixth switch transistor; the fourth switch transistor is connected between the driving transistor and the light emitting element; the sixth switch transistor is connected between the drive transistor and a power supply line that transmits the drive current; During the initialization period, the sixth switch transistor is OFF, the sixth switch transistor is ON during the threshold correction period, the data writing period, and the light emission period; Pixel circuit.

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