Hardware system for automatic direct memory access data formatting
Patent Information
- Application Number
- JP2022163626
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-10-12
- Filing Date
- 2022-10-12
- Publication Date
- 2025-10-20
AI Technical Summary
Existing data transfer methods in electronic devices require significant CPU processing time and interaction between hardware and software for parsing, transcoding, and memory management, leading to inefficiencies and potential data loss.
A hardware direct memory access (DMA) controller that parses data headers, determines transaction length and format, allocates memory, and performs on-the-fly bit-swizzling and transcoding without CPU intervention, enabling direct data transfer to designated memory locations.
Reduces CPU processing requirements, eliminates redundant software configurations, and prevents FIFO overflow by performing data formatting and management autonomously, enhancing overall system efficiency.
Smart Images
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Abstract
Description
Technical Field
[0001] Direct Memory Access (DMA) is used to transfer data directly without going through the Central Processing Unit (CPU). In order for this transfer to function correctly, it is necessary to properly configure the DMA channel before the data transfer.
[0002] Typically, when a certain protocol is applied to input data, the software running on the CPU analyzes the header of that protocol, extracts the payload of the input data, transcodes the data, performs the necessary data operations, and transfers the input data to the appropriate location within the destination memory.
[0003] The length or amount of the input data is typically not known in advance to the software, and therefore, the software typically has to analyze it, set up and execute jobs accordingly in an Interrupt Request (IRQ) routine.
[0004] This process of analysis, transcoding, and data operations requires a number of interactions between the hardware physical interface and the software. This requires real-time processing of data, consumes CPU processing time, and necessitates the use of a large hardware First-In-First-Out (FIFO) memory to maintain the physical interface data flow without losing data.
Summary of the Invention
[0005] In one implementation, a hardware direct memory access controller is provided. The hardware direct memory access controller includes an input port configured to receive data from an electronic device for direct memory access, an output port configured to provide the data for direct memory access transfer, and processing circuit elements coupled to the input port and the output port.
[0006] The processing circuit element is configured to receive data, including a header and payload, from an electronic device via an input port, parse the header to determine data parameters, including transaction length and input data format, and select a target destination for the data based at least partially on the data parameters.
[0007] The processing circuit element is also configured to allocate memory within the target destination, at least partially based on the transaction length, and to format the payload for direct memory access, at least partially based on the data parameters. The processing circuit element is further configured to transfer the formatted payload for storage in the allocated memory within the target destination via an output port using direct memory access.
[0008] In another implementation, a method is provided for operating a hardware direct memory access controller. This method includes receiving data, including a header and payload, from an electronic device via an input port; parsing the header to determine data parameters, including transaction length and input data format; and selecting a target destination for the data, at least partially based on the data parameters.
[0009] This method further includes allocating memory in a target destination based at least partially on the transaction length, formatting the payload for direct memory access based at least partially on data parameters, and transferring the formatted payload for storage in the allocated memory in the target destination via an output port using direct memory access.
[0010] Further implementations provide an electronic device. The electronic device includes input / output ports configured to transfer data between the electronic device and an external electronic device, memory configured to store data received from the external electronic device, and a hardware direct memory access controller connected to the input / output ports and the memory.
[0011] The hardware direct memory access controller is configured to receive data, including a header and payload, from an external electronic device via input / output ports, parse the header to determine data parameters, including the transaction length and input data format, and select a target destination in memory for the data, at least partially based on the data parameters.
[0012] The hardware direct memory access controller is further configured to allocate memory within the target destination based at least partially on the transaction length, format the payload for direct memory access based at least partially on the data parameters, and transfer the formatted payload for storage in memory via the input / output ports using direct memory access. [Brief explanation of the drawing]
[0013] Many aspects of this disclosure can be better understood by referring to the following drawings. While some implementations are described in relation to these drawings, this disclosure is not limited to the implementations disclosed herein. Rather, it is intended to cover all alternatives, variations, and equivalents.
[0014] [Figure 1] An illustrative embodiment of a system for transferring data, including a hardware DMA data controller, is shown.
[0015] [Figure 2]Another illustrative embodiment of a system for transferring data, including a hardware DMA data controller, is illustrated.
[0016] [Figure 3] Another illustrative embodiment of a system for transferring data, including a hardware DMA data controller, is illustrated.
[0017] [Figure 4] The data formats of two different data formats are illustrated as examples.
[0018] [Figure 5] An example method for operating a hardware DMA controller is illustrated.
[0019] [Figure 6] An example of a hardware DMA controller within an electronic device is illustrated. [Modes for carrying out the invention]
[0020] In today's complex electronic devices, such as system-on-a-chip (SoC) devices, a microcontroller (MCU) is used to manage any direct memory access (DMA) operations within the device. The MCU generates job descriptors for DMA operations that describe the data payload and its location in memory, and then stores data in a store operation or reads data in a read operation. A first-in-one foil (FIFO) is used as a jitter buffer between peripheral devices and internal memory access.
[0021] In the case of the transmission operation, the DMA or MCU duplicates the data into the FIFO, and the peripheral device duplicates the data from the FIFO and transfers it via an interface (e.g., Serial Peripheral Interface (SPI), Secure Digital Input / Output (SDIO), Universal Asynchronous Receiver Transmitter (UART), etc.). In the case of the reception operation, the peripheral device receives the data from the interface and stores it in the FIFO. The MCU or DMA module duplicates the data into the storage memory. This operation of the FIFO overcomes jitter and enables the MCU or DMA module to function at intervals.
[0022] By transferring the necessary DMA management operations from the MCU to the dedicated hardware DMA module within the device, the MCU becomes available to process other instructions not involved in the DMA routine, and as a result, the MCU efficiency is improved.
[0023] FIG. 1 illustrates an exemplary embodiment of a system 100 for transferring data including a hardware DMA data controller 140. In this exemplary embodiment of the present invention, the electronic system 100 includes a host microcontroller 110 and a system-on-chip 120. Here, both the host microcontroller 110 and the system-on-chip 120 are specific examples of electronic devices operating within the overall electronic system. Other exemplary embodiments include other electronic devices, all of which are within the scope of this disclosure.
[0024] In this exemplary embodiment, a microcontroller 130, a hardware DMA controller 140, a serial interface 150, a RAM memory 160, and a bus 121 constitute the system-on-chip (SoC) 120. In this exemplary embodiment, the serial interface 150 further includes a transmit FIFO 152 and a receive FIFO 154.
[0025] The serial interface 150 communicates with the host microcontroller 110 via the physical interface 122. The microcontroller 130, the hardware DMA controller 140, the serial interface 150, and the RAM memory 160 communicate with each other via the bus 121. In this exemplary embodiment, the modules coupled to the bus 121 are either initiator modules or target modules. An initiator module is a node on the bus that can initiate a transaction. The microcontroller 130 is an initiator, while the serial interface 150 is a target. This means that the microcontroller 130 can access the serial interface 150 and read and write data therefrom.
[0026] The hardware DMA controller 140 operates as both an initiator and a target. It operates as a target to enable the microcontroller 130 to control and configure jobs, reads data from the receive FIFO 154 within the serial interface 150, and operates as an initiator to copy that data to the RAM memory 160. It also operates as an initiator to read data from the RAM memory 160 and copy that data to the transmit FIFO 152 within the serial interface 150.
[0027] Note that FIG. 1 is a highly simplified diagram of the system-on-chip 120. In reality, the system-on-chip 120 is much more complex, including data buses and control interfaces between various modules and peripherals, and including numerous modules and peripherals not shown in FIG. 1.
[0028] In this exemplary embodiment, the hardware DMA controller 140 performs on-the-fly DMA transaction data analysis and execution without requiring direct control from the microcontroller 130. When the hardware DMA controller 140 receives input data from the serial interface 150, it analyzes the header of the input data to detect the transaction length and data format, sets the target destination in the RAM memory 160, allocates space in the correct memory pool in the RAM memory 160, and performs any necessary bit swizzling and transcoding of the input data.
[0029] These operations within the hardware DMA controller 140 eliminate the need for predefined configurations, reduce MCU processing requirements and associated software footprints, eliminate redundant software assignments, and avoid the possibility of FIFO overflow.
[0030] In this exemplary embodiment, the hardware DMA controller 140 is configured to perform DMA transactions from peripheral devices to memory, from memory to peripheral devices, and from memory to memory.
[0031] In operation, the system-on-chip receives input data, including headers and payloads, from the host microcontroller 110 via a physical interface 122. The physical interface 122 includes, but is not limited to, any of the wide variety of data interfaces, such as a serial peripheral interface (SPI), secure digital input / output (SDIO), and general-purpose asynchronous receiver-transmitter (UART). The input physical data format is usually unknown to the system-on-chip before the data is received. The hardware DMA controller 140 determines which format the input data contains from a list of possible physical data formats that may be received.
[0032] Once the physical data format is determined, the hardware DMA controller 140 analyzes the header of the input data to determine the correct data parameters to be used when storing the data in the RAM memory 160. For example, the hardware DMA controller 140 determines the transaction length or amount of data to be stored, and the digital format of the input data.
[0033] Based on the header, the hardware DMA controller 140 determines the target destination of the data. Based on the data parameters extracted from the header of the input data, the hardware DMA controller 140 allocates memory within the target destination.
[0034] These data parameters include data format, data volume, etc. The hardware DMA controller 140 determines where to store the data within the target destination based at least partially on these data parameters. Memory allocation involves selecting between memory partitions within the target destination, where memory is partitioned according to data type.
[0035] Next, the hardware DMA controller 140 determines the necessary bit swizzling or required data transcoding before the data is stored in the RAM memory 160, and performs the necessary bit swizzling and / or data transcoding on the payload.
[0036] Bit swizzling is a term or technique used to describe the process of constructing a vector by arbitrarily rearranging and combining the components of other vectors, particularly in computer graphics. Transcoding is a technical term used to describe the process of converting data from one data format to another. Figure 4 illustrates an example of transcoding data between a big-endian data format and a little-endian data format.
[0037] Data formatting, bit swizzling, and transcoding are performed on the fly by the hardware DMA controller 140, which in turn continues to receive, format, bit swizzle, and transcode input data while transferring the formatted payload via the output port using direct memory access for storage in allocated memory within the target destination. These data formatting, bit swizzling, and transcoding operations are typically performed word by word, 32 bits or 64 bits at a time.
[0038] Figure 2 illustrates another exemplary embodiment of a system 200 for transferring data, including a hardware DMA data controller 220. In this exemplary embodiment of the present invention, the electronic system 200 includes a host platform / microcontroller 230 and an electronic device 210. In this exemplary embodiment, input / output (I / O) ports 222, the hardware DMA controller 220, memory 224, and a network processor / MCU 226 constitute the electronic device 210. In this exemplary embodiment, the electronic system 200 is further configured to communicate with other external systems via a Wi-Fi antenna 228.
[0039] I / O port 222 communicates with host 230 via physical interface 242. I / O port 222 exchanges data with hardware DMA controller 220 via link 241, and hardware DMA controller 220 exchanges the transcoded data with memory 224 via link 240. Hardware DMA controller 220 also provides data format to network processor / MCU 226 via link 243.
[0040] Please note that Figure 2 is a highly simplified diagram of the electronic device 210. In reality, the electronic device 210 is far more complex, including data buses and control interfaces between various modules and peripherals, and includes numerous modules and peripherals not shown in Figure 2.
[0041] In this exemplary embodiment, the hardware DMA controller 220 performs on-the-fly DMA transaction data analysis and execution without requiring direct control from the network processor / MCU 226. Upon receiving input data from the I / O port 222, the hardware DMA controller 220 analyzes the header of the input data to detect the transaction length and data format, sets the target destination in memory 224, allocates space in the correct memory pool in memory 224, performs any necessary bit swizzling and transcoding of the input data, and optionally implements an extended scatter-gather mode for data fragmentation and aggregation.
[0042] These operations within the hardware DMA controller 220 eliminate the need for predefined configurations, reduce MCU processing requirements and associated software footprints, eliminate redundant software assignments, and avoid the possibility of FIFO overflow.
[0043] In this exemplary embodiment, the hardware DMA controller 220 is configured to perform DMA transactions from peripherals to memory, from memory to peripherals, and from memory to memory.
[0044] In operation, the electronic device 210 receives input data, including a header and payload, from the host 230 via a physical interface 242. The physical interface 242 includes, but is not limited to, any of the wide variety of data interfaces, including, but not limited to, a serial peripheral interface (SPI), secure digital input / output (SDIO), and a general-purpose asynchronous receiver-transmitter (UART). The input physical data format is usually unknown to the electronic device 210 before the data is received. The hardware DMA controller 220 determines which format the input data contains from a list of possible physical data formats that may be received.
[0045] Once the physical data format is determined, the hardware DMA controller 220 analyzes the header of the input data to determine the correct data parameters to be used when storing the data in the memory 224. For example, the hardware DMA controller 220 determines the transaction length or amount of data to be stored, and the digital format of the input data.
[0046] Based on the header, the hardware DMA controller 220 determines the target destination of the data. This target destination may be memory 224, external memory (not shown), an external device linked via Wi-Fi antenna 228, etc. Based on the data parameters extracted from the header of the input data, the hardware DMA controller 220 allocates memory within the target destination.
[0047] These data parameters include data format, data volume, etc. The hardware DMA controller 220 determines where to store the data within the target destination based at least in part on these data parameters. Memory allocation involves selecting between memory partitions within the target destination, where memory is partitioned according to data type. Optionally, the hardware DMA controller 220 performs data aggregation when receiving data from memory and data fragmentation when allocating data to memory. In some exemplary embodiments of the present invention, this aggregation and fragmentation are performed as a scatter-gather mode for interfacing with the target destination.
[0048] Next, the hardware DMA controller 220 determines the necessary bit swizzling or data transcoding before the data is stored in the memory 224, and performs the necessary bit swizzling and / or data transcoding on the payload.
[0049] Bit swizzling is a term or technique used to describe the process of constructing a vector by arbitrarily rearranging and combining the components of other vectors, particularly in computer graphics. Transcoding is a technical term used to describe the process of converting data from one data format to another. Figure 4 illustrates an example of transcoding data between a big-endian data format and a little-endian data format.
[0050] Data formatting, bit swizzling, and transcoding are performed on the fly by the hardware DMA controller 220, which in turn still receives, formats, bits swizzles, and transcodes input data while transferring the formatted payload via the output port for storage in allocated memory within the target destination using direct memory access. These data formatting, bit swizzling, and transcoding operations are typically performed word by word, 32 bits or 64 bits at a time.
[0051] Figure 3 illustrates another exemplary embodiment of a device 300 for transferring data, including a hardware DMA data controller 340. In this exemplary embodiment of the present invention, the electronic system 300 includes an external controller / device 310 and an electronic device 320. The electronic device 320 is configured to receive data from the external controller / device 310 via a physical interface 312. In this exemplary embodiment, the electronic device 320 includes a hardware DMA controller 340 and memory 360. The hardware DMA controller 340 includes a header analysis module 344 and data processing modules 346-352.
[0052] In this exemplary embodiment, the header processing module 344 and data processing modules 346-352 are instruction modules configured to instruct processing circuit elements within the hardware DMA controller 340 to operate as described herein. Some of the data processing modules 346-352 are optional and are not used in all DMA operations performed by the hardware DMA controller 340. Figure 3 illustrates the data manipulation performed by the hardware DMA controller 340 on data received by the electronic device 320 from the external controller / device 310 via the physical interface 312. Note that the hardware DMA controller 340 also performs other functions necessary for the DMA operations described above with respect to Figure 2.
[0053] The header analysis module 344 instructs the processing circuit elements within the hardware DMA controller 340 to analyze the header 342 of the input data and determine the correct data parameters to be used when storing the data in the memory 360. For example, the header analysis module 344 determines the transaction length or amount of the data to be stored, and the digital format of the input data.
[0054] Based at least partially on the data parameters determined by the header analysis module 344, the hardware DMA controller 340 determines any necessary bit swizzling or data transcoding before the data is stored in the memory 360, and performs the necessary bit swizzling and / or data transcoding on the payload.
[0055] Bit swizzling is a term or technique that describes the process of constructing a vector by arbitrarily rearranging and combining the components of other vectors, particularly in computer graphics. Transcoding is a term that describes the technique of converting data from one data format to another. Figure 4 illustrates an example of transcoding data between a big-endian data format and a little-endian data format.
[0056] If necessary, the data bit swizzling module 346 instructs the processing circuit elements in the hardware DMA controller 340 to perform the necessary bit swizzling. Also, if necessary, the data transcoding module 348 instructs the processing circuit elements in the hardware DMA controller 340 to perform the necessary data transcoding. The data aggregation module 350 instructs the processing circuit elements in the hardware DMA controller 340 to perform any necessary data aggregation in any type of scatter-gather memory operation. The data fragmentation module 352 instructs the processing circuit elements in the hardware DMA controller 340 to perform any necessary data fragmentation in any type of scatter-gather memory operation.
[0057] Once the payload is properly formatted for storage, the hardware DMA controller 340 transfers the formatted payload via the output port for storage in the allocated memory within the target destination 360 using direct memory access.
[0058] Figure 4 illustrates two different data formats as examples. Figure 4 illustrates an example of data format 400 implemented by processing circuit elements within the hardware DMA controller 340.
[0059] In this example, the data in the payload can be in either big-endian or little-endian format. Figure 4 illustrates these two formats for data with lengths of byte [0xAA], short [0xAABB], and long [0xAABBCCDD]. For byte-length data, there is no difference between big-endian 402 and little-endian 404 data. However, for short and long data, the data formats differ in the order in which the individual bytes of the data are stored.
[0060] For short data, data [0xAABB] is stored in memory location order [AA], [BB] as big-endian 406 data, and the same data is stored in memory location order [BB], [AA] as little-endian 408 data. Similarly, for long data, data [0xAABBCCDD] is stored in memory location order [AA], [BB], [CC], [DD] as big-endian 410 data, and the same data is stored in memory location order [DD], [CC], [BB], [AA] as little-endian 412 data.
[0061] The hardware DMA controller 340 formats the data between big-endian and little-endian formats as needed, based on the format of the input data and the format of the data in memory 360. Figure 4 illustrates an example of a data format. The hardware DMA controller 340 is configured to implement other different data formatting methods between data formats as needed.
[0062] Figure 5 illustrates an exemplary method for operating the hardware DMA controller 340. In this exemplary method, the processing circuit elements within the hardware DMA controller 340 are controlled by various modules to perform the following operations.
[0063] In this exemplary embodiment, the hardware DMA controller 340 receives data, including a header and payload, from the electronic device 310 via an input port (operation 500). The hardware DMA controller 340 analyzes the header to determine data parameters, including the transaction length and input data format (operation 502).
[0064] The hardware DMA controller 340 selects a target destination 360 for the data based at least partially on the data parameters (operation 504). The hardware DMA controller 340 allocates memory within the target destination 360 for the data (operation 506).
[0065] The hardware DMA controller 340 formats the payload for direct memory access based at least partially on the data parameters (operation 508). In the exemplary embodiment, this formatting operation is performed in chunks or words and is repeated until the entire payload is received. The hardware DMA controller 340 then transfers the formatted payload for storage in allocated memory within the target destination 360 via the output port using direct memory access (operation 510). In the exemplary embodiment, this transfer operation is also performed in chunks or words and is repeated until the entire payload is stored.
[0066] Figure 6 illustrates an exemplary embodiment of the hardware DMA controller 600 within the electronic device 320. As described above, the hardware DMA controller 600 can take any of the many different configurations. Here, an exemplary configuration for the hardware DMA controller 600 within the electronic device 320 implemented as an ASIC is provided. In some embodiments, the hardware DMA controller 600 is a module within a system-on-a-chip (SoC).
[0067] In this exemplary embodiment, the hardware DMA controller 600 includes an input port 610, a processing circuit element 620, an output port 630, and an internal storage system 640. In one exemplary configuration, the input port 610 includes a circuit element configured to receive input from an electronic device 310 for storage in memory. The output port 630 includes a circuit element configured to send data and instructions to the storage system or memory 360. In some embodiments, the input port 610 and the output port 630 are combined into a single input / output (I / O) port.
[0068] The processing circuit element 620 includes an electronic circuit element configured to perform the tasks of the hardware DMA controller 340 as described above. In some embodiments, the processing circuit element 620 may be embedded in a composite electronic device 320. Examples of the processing circuit element 620 include general-purpose central processing units, application-specific processors, and logic devices, as well as any other types of processing devices, combinations thereof, or variations thereof. The processing circuit element 620 can be implemented within a single processing device, or it can be distributed across multiple processing devices or subsystems that cooperate in executing program instructions.
[0069] In the exemplary embodiment, the hardware DMA controller 600 is implemented as an application-specific module, and the custom processing circuit element 620 is provided to perform the functions described herein via one or more hardware modules, including a header analysis module 621, a data bit swizzling module 622, a data transcoding module 623, a data aggregation module 624, a data fragmentation module 625, and a memory allocation module 626.
[0070] The internal storage system 640 includes any non-temporary computer-readable storage medium on which data can be stored. The internal storage system 640 also includes various data structures 650, including one or more databases, tables, lists, or other data structures, including a list of physical data formats, digital data formats, data buffers, etc., used by the processing circuit elements 620. The internal storage system 640 may include volatile and non-volatile, removable and non-removable media, which are implemented in any way or technique for storing information such as computer-readable instructions, data structures, program modules, or other data.
[0071] The internal storage system 640 can be implemented as a single storage device, but it can also be implemented across multiple storage devices, subsystems, or modules that are jointly or distributed with each other. The internal storage system 640 may include additional elements such as a controller that can communicate with the processing circuit elements 620. Examples of storage media include random access memory, read-only memory, magnetic disks, optical disks, flash memory, virtual and non-virtual memory, magnetic cassettes, magnetic tapes, magnetic disk storage systems or other magnetic storage systems, or any other media that can be used to store desired information and can be accessed by the instruction execution system, as well as any combination or variation thereof.
[0072] In this exemplary embodiment, the internal storage system 640 also includes one or more FIFOs 660, such as the transmit FIFO 152 and receive FIFO 154 from Figure 1. These FIFOs 660 are used to overcome jitter and allow the hardware DMA controller 600 to operate at intervals.
[0073] The header processing module 621 within the processing circuit element 620 parses the data header to determine data parameters, including the transaction length and input data format. The data bit swizzling module 622 within the processing circuit element 620 performs any necessary data bit swizzling. The data transcoding module 623 within the processing circuit element 620 performs any necessary data transcoding. In some examples, the data transcoding module 623 also performs arbitrary data formats, as illustrated in Figure 4.
[0074] The data aggregation module 624 within the processing circuit element 620 performs any necessary data aggregation in scatter-gather type mode. For example, the data aggregation module 624 performs data aggregation on multiple data payloads.
[0075] The data fragmentation module 625 within the processing circuit element 620 performs any necessary data fragmentation in scatter-gather type mode. For example, the data fragmentation module 665 performs data fragmentation on the payload by dividing the payload into multiple data partitions, processing each data partition separately, allocating multiple memory locations within the target destination corresponding to the multiple data partitions, and storing each of the multiple data partitions in one of the multiple memory locations.
[0076] The memory allocation module 626 within the processing circuit element 620 allocates memory for data storage.
[0077] The included descriptions and figures illustrate specific embodiments to instruct those skilled in the art on how to create and use the best mode. For the purpose of teaching the principles of the present invention, some conventional embodiments have been simplified or omitted. Those skilled in the art will understand variations from these embodiments that fall within the scope of the present invention. Furthermore, those skilled in the art will understand that multiple embodiments can be formed by combining the above-described features in various ways. Consequently, the present invention is not limited to the specific embodiments described above, but is limited only by the claims and their equivalents.
Claims
1. 1. A hardware direct memory access controller, comprising: An input port; an output port; a processing circuit element coupled to the input port and the output port, receiving first data including a header and a payload via the input port; determining a format of the first data that is unknown to the processing circuitry prior to receiving the first data; Parsing a header of the first data to determine data parameters including the amount of the payload based on a format of the first data; allocating memory based at least in part on the amount of the payload; formatting the payload based at least in part on a format of the first data; transferring the formatted payload to the allocated memory via the output port using direct memory access; the processing circuitry configured to a hardware direct memory access controller, including:
2. 2. The hardware direct memory access controller of claim 1, The hardware direct memory access controller, wherein the processing circuitry is further configured to perform bit swizzling on the first data.
3. 2. The hardware direct memory access controller of claim 1, The hardware direct memory access controller, wherein the processing circuitry is further configured to allocate the memory using a scatter-gather mode.
4. 4. The hardware direct memory access controller of claim 3, The hardware direct memory access controller, wherein the processing circuitry is further configured to perform data aggregation on multiple data payloads.
5. 4. The hardware direct memory access controller of claim 3, the processing circuitry: a hardware direct memory access controller further configured to perform data fragmentation on the payload by partitioning the payload into a plurality of data partitions, processing each data partition separately, allocating a plurality of memory locations corresponding to the plurality of data partitions, and storing each of the plurality of data partitions in one of the plurality of memory locations.
6. 2. The hardware direct memory access controller of claim 1, The hardware direct memory access controller, wherein the processing circuitry is further configured to allocate the memory based at least in part on a format of the first data.
7. 2. The hardware direct memory access controller of claim 1, A hardware direct memory access controller, wherein the input port and the output port are both included in a composite input / output port.
8. 1. A method for operating a hardware direct memory access controller, comprising: receiving data via an input port, the data including a header and a payload; determining a format of the data that is unknown to the hardware direct memory access controller before receiving the data; parsing a header of the data to determine data parameters including the amount of the payload based on a format of the data; allocating memory based at least in part on the amount of payload; formatting the payload based at least in part on a format of the data; transferring the formatted payload to the allocated memory via an output port using direct memory access; A method comprising:
9. 9. The method of claim 8, The method further comprising performing bit swizzling on the data.
10. 9. The method of claim 8, The method, wherein allocating memory includes allocating memory using a scatter-gather mode.
11. 11. The method of claim 10, The method further includes performing data aggregation on the plurality of data payloads.
12. 11. The method of claim 10, performing data fragmentation on the payload by partitioning the payload into a plurality of data partitions, processing each data partition separately, allocating a plurality of memory locations corresponding to the plurality of data partitions, and storing each of the plurality of data partitions in one of the plurality of memory locations.
13. 9. The method of claim 8, The method, wherein allocating memory includes allocating memory based at least in part on a format of the data.
14. 9. The method of claim 8, The method, wherein the hardware direct memory access controller includes a composite input / output port that includes both an input port and the output port.
15. 1. An electronic device comprising: an input / output port configured to be coupled to an external electronic device; Memory and a hardware direct memory access controller coupled to the input / output ports and the memory, receiving data including a header and a payload via the input / output port; determining a format of the data that is unknown to the hardware direct memory controller before receiving the data; Parsing a header of the data to determine data parameters including the amount of the payload based on a format of the data; allocating the memory based at least in part on the amount of the payload; formatting the payload based at least in part on parameters of the data; transferring the formatted payload to the memory via the input / output port using direct memory access; a hardware direct memory access controller configured to , an electronic device.
16. 16. The electronic device of claim 15, The electronic device, wherein the hardware direct memory access controller is further configured to perform bit swizzling on the data.
17. 16. The electronic device of claim 15, The electronic device, wherein the hardware direct memory access controller is further configured to allocate the memory using a scatter-gather mode.
18. 18. The electronic device of claim 17, The electronic device, wherein the hardware direct memory access controller is further configured to perform data aggregation on multiple data payloads.
19. 18. The electronic device of claim 17, the hardware direct memory access controller, 11. The electronic device, further configured to: perform data fragmentation on the payload by partitioning the payload into a plurality of data partitions, processing each data partition separately, allocating a plurality of memory locations corresponding to the plurality of data partitions, and storing each of the plurality of memory locations in one of the plurality of data partitions.
20. 16. The electronic device of claim 15, The electronic device, wherein the hardware direct memory access controller is further configured to allocate the memory based at least in part on a format of the data.