System for processing integration signal with multiple signal components with arbitrary power allocation, medium, and method

Abstract

To process a GNSS integration signal with multiple signal components with an arbitrary power allocation.SOLUTION: An integration signal processing unit of a GNSS receiver generates a plurality of complex rotated samples in parallel for one sample of an integration signal. The plurality of complex rotated samples (e.g., advanced complex rotated samples, delayed complex rotated samples) are accumulated in parallel in a window of arbitrary width equal to or smaller than number of code chips in a PRN code sequence. The integrated signal processing unit sequentially generates a plurality of complex rotation samples for one sample. The plurality of complex rotated samples (e.g., advanced complex rotated samples, on-time complex rotated samples, delayed complex rotated samples) are accumulated sequentially in the window. The GNSS receiver can utilize the accumulated complex rotated samples to implement a correlation technique, to implement a multipath mitigation technique, and / or to track the integration signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] background Technical field The present invention relates more broadly to a global navigation satellite system (GNSS), and more specifically to a GNSS receiver for processing an integrated signal having multiple signal components having arbitrary power allocations.

[0002] Background information With the development of Global Navigation Satellite Systems (GNSS), an increasing number of GNSS signals are being broadcast to provide diverse services (e.g., positioning, navigation, timing, etc.). To conserve resources when providing such services, it is sometimes necessary to multiplex multiple signals into a single composite signal. Furthermore, the composite signal may have constant envelope properties to mitigate signal distortion that may be caused, for example, by nonlinear amplification.

[0003] ACE-BOC (Asymmetric Constant Envelope Binary Offset Carrier) is a dual-frequency constant envelope multiplexing technique that allows four independent spread spectrum codes to be modulated to two different carrier frequencies of an integral signal with any combination of power ratios. Compared to other constant envelope multiplexing techniques, ACE-BOC can offer greater design flexibility in terms of the number of signal components and the power ratios between components. Such design flexibility can provide diversity in optimizing signal schemes that may be required for various services. However, the design flexibility related to integral signals can consequently lead to complexity in processing integral signals.

[0004] overview In one or more embodiments, the system, medium, and method process an integral signal having multiple signal components with arbitrary power assignments. In one embodiment, an integral signal processing unit can generate multiple complex-rotated samples in parallel for a single sample of the integral signal, thereby accumulating multiple complex-rotated samples for a sample in parallel within any arbitrary window width less than or equal to the number of code chips in the pseudo-random noise (PRN) code sequence. For example, the window can span at least 1.5 code chips (e.g., 2 code chips, 3 code chips, 10 code chips, etc.).

[0005] In one implementation, the integrated signal processing unit of a Global Navigation Satellite System (GNSS) receiver can generate local codes for samples of the integrated signal, and these local codes can correspond to codes within the integrated signal. The integrated signal processing unit can select phase rotation values ​​and code shift values ​​based on the local codes. For example, the phase rotation values ​​and code shift values ​​can be selected from a shift / phase lookup table. Based on the selected phase rotation values, the integrated signal processing unit can generate early-complex-rotated and late-complex-rotated samples in parallel.

[0006] The integrating signal processing unit can use the selected code shift value to generate forward and delayed code phase values ​​in parallel across at least 1.5 code chips (e.g., 2 code chips), in which case the delayed code phase value is temporally offset by the equivalent of one pseudo-random noise (PRN) chip of the code phase. The integrating signal processing unit can use the forward and delayed code phase values ​​to generate a final bin enable output from the forward and delayed bin enable outputs. The integrating signal processing unit can use the final bin enable output generated for a window spanning at least 1.5 code chips (e.g., 2 code chips) to accumulate multiple complex-rotated samples (e.g., a forward complex-rotated sample and a delayed complex-rotated sample) in parallel for a single sample.

[0007] For example, the final bin enable output can be used to accumulate forward-complex-rotated and delayed-complex-rotated samples in parallel within one or two bins of multiple bins spanning at least 1.5 code chips (e.g., 2 code chips). Multiple bins can be used to generate correlation values ​​that may be required to implement one or more correlation techniques and / or one or more multipath relaxation techniques. Additionally or alternatively, weighted bins can utilize the forward-bin enable output and delayed-bin enable output to accumulate forward-complex-rotated and delayed-complex-rotated samples in parallel for a window spanning 1.5 code chips (e.g., 2 code chips) for the purpose of tracking the integrated signal.

[0008] In one embodiment, the integral signal processing unit can sequentially generate multiple complex-rotated samples for a single sample of the integral signal, thereby accumulating multiple complex-rotated samples for a sample sequentially within a window spanning at least 1.5 code chips (e.g., 3 code chips or 10 code chips). In particular, the integral signal processing unit can generate multiple local codes for a single sample of the integral signal, these multiple local codes corresponding to codes in the integral signal. For example, the multiple local codes may include advanced versions of the codes in the integral signal, punctual versions of the codes in the integral signal, and delayed versions of the codes in the integral signal.

[0009] The integrating signal processing unit can feed one of several local codes into the shift / phase lookup table based on the value of a counter that starts at a minimum value and increments to a value corresponding to the number of local codes. Thus, each of the several local codes is fed sequentially into the shift / phase lookup table as the counter increments.

[0010] The integrating signal processing unit can select phase rotation values ​​and code shift values ​​based on the supplied local code. Based on the selected phase rotation values, the integrating signal processing unit can generate complex-rotated samples. Based on the selected code shift values, the integrating signal processing unit can generate code phase values ​​by, if necessary, offsetting the selected code shift values ​​in time based on the value of a counter so that the window spans at least 1.5 code chips (e.g., 3 code chips).

[0011] For example, a code shift value selected based on an advanced version of the code should not be time-offset, as the counter value is 0. A code shift value selected based on a timed version of the code can be time-offset by the equivalent of one PRN chip of the code phase, as the counter value is 1. Furthermore, a code shift value selected based on a delayed version of the code can be time-offset by the equivalent of two PRN chips of the code phase, as the counter value is 2. Therefore, in this example, the window spans three code chips. Consequently, in this example, complex rotation and code phase values ​​are sequentially generated for each of the multiple local codes for a window spanning three code chips.

[0012] The integrating signal processing unit can generate bin enable outputs based on the generated code phase values. The integrating signal processing unit can sequentially accumulate multiple complex-rotated values ​​for a single sample by utilizing the bin enable outputs generated for each window spanning at least 1.5 code chips (e.g., 3 code chips). For example, by utilizing each bin enable output, multiple complex-rotated samples can be sequentially accumulated within multiple bins spanning at least 1.5 code chips (e.g., 3 code chips). Multiple bins can be used to generate correlation values ​​that may be required to implement one or more correlation techniques and / or one or more multipath relaxation techniques. Additionally or alternatively, weighted bins can sequentially accumulate multiple complex-rotated samples for a window spanning 1.5 code chips (e.g., 3 or 10 code chips) for the purpose of tracking the integrating signal by utilizing their respective bin enable outputs.

[0013] The following explanation refers to the attached diagrams. [Brief explanation of the drawing]

[0014] [Figure 1]This is a schematic block diagram of a system according to one or more embodiments described herein. [Figure 2A] This is a schematic block diagram of an integral signal processing unit capable of processing an integral signal by generating multiple complex-rotated samples in parallel for a single sample of the integral signal, according to one or more embodiments described herein. [Figure 2B] This is a schematic block diagram of another integral signal processing unit, which can process an integral signal by generating multiple complex-rotated samples in parallel for a single sample of the integral signal, according to one or more embodiments described herein. [Figure 2C] This is a schematic block diagram of another integral signal processing unit, which can process an integral signal by generating multiple complex-rotated samples in parallel for a single sample of the integral signal, according to one or more embodiments described herein. [Figure 3] This is a schematic block diagram of a shift / phase lookup table according to one or more embodiments described herein. [Figure 4] This is a schematic block diagram of a sample enable decoder according to one or more embodiments described herein. [Figure 5] This is an exemplary flowchart for processing an integral signal by generating multiple complex-rotated samples in parallel for a single sample of the integral signal, according to one or more embodiments described herein. [Figure 6A] This is a schematic block diagram of an integral signal processing unit capable of processing an integral signal by sequentially generating multiple complex-rotated samples for a single sample of the integral signal, according to one or more embodiments described herein. [Figure 6B] This is a schematic block diagram of another integral signal processing unit, which can process an integral signal by sequentially generating multiple complex-rotated samples for a single sample of the integral signal, according to one or more embodiments described herein. [Figure 6C] This is a schematic block diagram of an integral signal processing unit capable of processing an integral signal by sequentially generating multiple complex-rotated samples for a single sample of the integral signal, according to one or more embodiments described herein. [Figure 7A] This is a schematic block diagram of a shift table according to one or more embodiments described herein. [Figure 7B] This is a schematic block diagram of a sample enable decoder according to one or more embodiments described herein. [Figure 8] This is an exemplary flowchart for processing an integral signal by sequentially generating multiple complex-rotated samples for a single sample of the integral signal, according to one or more embodiments described herein.

[0015] Detailed description of the embodiment Referring to Figure 1, the system 100 includes one or more client devices 105 and one or more transmitters, such as one or more Global Navigation Satellite System (GNSS) satellites 110 that transmit one or more navigation signals, for example, GNSS satellite signals (not shown). While a GNSS satellite 110 that transmits GNSS satellite signals may be referred to, it is explicitly assumed that one or more embodiments described herein may be used with any and all different transmitters that transmit any and all different navigation signals, for example, ground transmitters. Therefore, the description of a GNSS satellite 110 that transmits GNSS signals should be for illustrative purposes only.

[0016] The GNSS satellite 110 may be associated with one or more satellite navigation systems, including, but not limited to, Galileo, Beidou Satellite Navigation System (BDS), Global Positioning System (GPS), and / or GLONASS. For example, the GNSS satellite 110 can transmit one or more integral signals, i.e., integral GNSS signals, based on ACE-BOC (Asymmetric Constant Envelope Binary Offset Carrier) multiplexing. According to one or more embodiments described herein, the integral signals may be referred to as ACE-BOC signals. ACE-BOC multiplexing can combine four or fewer signal components at two different frequencies (e.g., four or fewer independent bipolar direct-sequence spread spectrum signals) into a single constant-envelope integral signal, in which case the signal components may have arbitrary power ratios, modulations, and code rates. For example, the four signal components may be E5a-I, E5a-Q, E5b-I, and E5b-Q of the Galileo satellite constellation, or B2a-I, B2a-Q, B2b-I, and B2b-Q of the Beidou satellite constellation.

[0017] The client device 105 is typically portable and includes an antenna 115 and a GNSS receiver 120, i.e., a navigation receiver, the GNSS receiver 120 having one or more processors 125 and memory 130. For example, the client device 105 may be a mobile phone, laptop computer, portable computer, personal digital assistant, etc. In addition, the GNSS receiver 120 may be a single-frequency, dual-frequency, or multi-frequency receiver. The memory 130 can store one or more values ​​related to one or more embodiments described herein.

[0018] One or more processors 125 execute an integral signal processing unit 200 (e.g., 200A, 200B, 200C, 200D, 200E, and 200F), which can process an integral signal that may have arbitrary power allocations between signal components, for example, according to one or more embodiments described herein.

[0019] Figure 2A is a schematic block diagram of an integral signal processing unit 200A, which can process an integral signal by generating multiple complex-rotated samples in parallel for a single sample of the integral signal, according to one or more embodiments described herein.

[0020] According to one or more embodiments described herein, a sample of an integral signal synchronized with a sample clock 204 can be processed by generating, in parallel, a forward-rotated complex-rotated sample 215A and a delayed-rotated complex-rotated sample 215B for each sample 201, as will be further described below with reference to Figures 2A to 4. The complex-rotated samples 215A and 215B for sample 201 can be accumulated in parallel within a number (N) of bins 220 over any arbitrary width less than or equal to the number of code chips in the pseudo-random noise (PRN) code sequence. For example, the window can span at least 1.5 code chips (e.g., 2 code chips). In one implementation, the bins 220 can accumulate (sum up) the complex-rotated samples over some predetermined period of time. The bins may be hardware, software, or a combination thereof.

[0021] The GNSS receiver 120 can use complex-rotated samples (e.g., 215A and 215B) accumulated within selected bins 220 and / or selected groups of bins 220 for multiple samples to generate correlation values ​​that may be required to implement one or more correlation techniques and / or one or more multipath relaxation techniques, and / or track the integral signal, as described in more detail below. Additionally or alternatively, weighting vectors can be used with complex-rotated samples (e.g., 215A and 215B) for multiple samples, as described in more detail below, to generate correlation values ​​that may be used, for example, to track the integral signal.

[0022] In one implementation, the size and / or starting point of bins 220, and / or selected bins 220 in various groupings, can be changed to alter the spacing and position corresponding to the complex-rotated samples. As an illustrative example, assume that bins 220 in Figure 2A contain 20 bins evenly spaced across the span of two code chips. Furthermore, assume that a first set of 10 bins (e.g., bins 0-9) are "early bins" spanning the first code chip, and a second set of 10 bins (e.g., bins 10-19) are "late bins" spanning the second code chip.

[0023] The examples illustrated with reference to Figures 2A to 4 may refer to 20 bins evenly spaced and spanning two code chips, but it is explicitly assumed that one or more embodiments described herein may be used with at least 1.5 chips, less than 1.5 chips, or any number (N) of bins 220 spanning any portion of a complete PRN code period. In one implementation, the bins 220 may be evenly spaced or unevenly spaced. In one implementation, the number of bins 220 may be 18 to 24. In an alternative implementation, the number of bins 220 may be any integer value. In one embodiment, one bin may correspond to one time slot or one slot of code phase value located within a window spanning two or more code chips.

[0024] Referring to Figure 2A, the code phase numerically controlled oscillator (NCO) 203 can utilize the code rate 205 to generate fine code chip phase details used to represent the estimated code phase value. For example, in each pulse of the sample clock 204 from which the integral signal is sampled, the code phase NCO 203 can generate a code phase subchip value that indicates the time slot in the code chip for sample 201. In one implementation, the code phase subchip value is between 0 and 0.99. In one implementation, the code rate 205 may be asynchronous with the sample clock 204.

[0025] The code phase NCO203 or chip count 207 can drive a 4×PRN code generator 202, which can generate a local code, e.g., a pseudo-random noise (PRN) code, for a sample 201 of the integrated signal, and this local code corresponds to one of the codes in the received integrated signal. For example, the first bit of the 4-bit code (e.g., the most significant bit) corresponds to the upper frequency common-mode signal (S) associated with the integrated signal. UI) can be handled. The second bit of the 4-bit code is the lower frequency common-mode signal (S) related to the integral signal. LI ) can be handled. The third bit of the 4-bit code is the upper frequency quadrature phase signal (S) related to the integral signal. UQ ) can correspond to the lower frequency quadrature phase signal (S) of the 4-bit code (for example, the least significant bit). LQ It can handle )

[0026] When the sub-chip value generated by the code phase NCO203 rolls over to 1, the chip count 207 can be incremented, and a signal indicating the start of a new code chip can be sent to the 4×PRN code generator 202. Based on this signal, the 4×PRN code generator 202 can generate the next 4-bit local code. When the chip count reaches the end of its count, for example 10229, the chip count can be rolled back to zero, and a reset signal can be sent to the 4×PRN code generator 202. In this example, the local code may be an advanced version of the code in the received integral signal. The advanced version of the code may precede the code in the received integral signal by, for example, one code chip or half a code chip.

[0027] Next, we assume that in the example where multiple bins 220 contain 20 bins evenly spaced across the windows of two code chips, for a pulse of sample clock 204, the code phase NCO 203 generates a code phase subchip value of 0.99, and the 4×PRN code generator 202 generates the local code

[1010] at this point. In addition, in this example we assume that the local code generated by the 4×PRN code generator 202 for the previous code chip was

[1111] .

[0028] According to one or more embodiments described herein, a shift / phase lookup table 206 can be used by an integral signal processing unit 200A to select code shift values ​​and phase rotation values ​​based on local codes, and using these values, a sample 215A that is advanced complex-rotated relative to sample 201 and a sample 215B that is delayed complex-rotated are generated in parallel, and these complex-rotated samples 215A and 215B are accumulated in parallel in one or two of a plurality of bins 220 across two code chips, for example, 20 bins, as will be described in more detail below.

[0029] In particular, as will be explained in more detail below, the phase rotation value selected from the shift / phase lookup table 206 can be used to generate in parallel a leading complex-rotated sample 215A and a lagging complex-rotated sample 215B relative to sample 201. In addition, as will be explained in more detail below, the code shift value selected from the shift / phase lookup table 206 can be used to (1) enable one or two of the multiple bins 220 (e.g., 20 bins) across two code chips, and (2) determine which complex-rotated sample is supplied to the enabled bin, for example, whether a leading complex-rotated sample 215A or a lagging complex-rotated sample 215B relative to sample 201 is supplied.

[0030] A sample clock 204 can be supplied to the shift / phase lookup table 206, thereby selecting a code shift value and a phase rotation value from the shift / phase lookup table 206 for each sample 201. In addition, as is known to those skilled in the art, the subcarrier mixed with the signal component of the integral signal may have a frequency of 15.345 MHz, while the code rate may be 10.23 MHz. Therefore, for odd-numbered code chips, it may be necessary to adjust the phase rotation value selected from the shift / phase lookup table 206 by 180 degrees. Thus, the least significant bit of the chip count 207 can be supplied to the shift / phase lookup table 206 to indicate whether the code chip is even or odd.

[0031] Figure 3 is a schematic block diagram of a shift / phase lookup table 206 according to one or more embodiments described herein. The processor 125 of the GNSS receiver 120 can initialize the shift / phase lookup table 206 such that each PRN code contained in column 301 has a corresponding phase rotation value in column 302 and a code shift value in column 303. In particular, the shift / phase lookup table 206 may be programmable so that the phase rotation value in column 302 and the code shift value in column 303 corresponding to the PRN codes in column 301 can be changed based on, for example, system requirements or user preferences. For example, the code shift value in column 303 corresponding to the PRN codes in column 301 can be changed based on whether the system should use symmetric shift or positive shift. In addition, the code shift value and phase rotation value corresponding to the PRN codes in column 301 can be changed based on the type of integral signal. For example, the code shift and phase rotation values ​​in the shift / phase lookup table 206 can be changed based on whether the integrated signal is an ACE-BOC type I signal, an ACE-BOC type II signal, or an ACE-BOC type III signal.

[0032] The shift / phase lookup table 206 contains specific values ​​in columns 301, 302, and 303, but it is explicitly assumed that, according to one or more embodiments described herein, the shift / phase lookup table 206 may contain different values. In addition, it is mentioned that code shift values ​​and phase rotation values ​​corresponding to local codes are selected using the shift / phase lookup table 206 in Figure 3, but it is explicitly assumed that code shift values ​​and phase rotation values ​​corresponding to local codes may be selected by any variety of methods.

[0033] As described above, in this example, the 4xPRN code generator 202 generates the local code

[1010] . The local code

[1010] can be supplied to the 4-bit encoder 304 of the shift / phase lookup table 206. Using this local code

[1010] , the row in column 301 corresponding to the local code

[1010] can be identified, and the phase rotation value from column 302 and the code shift value from column 303 can be selected. In this example, the local code

[1010] corresponds to the 11th row of column 301. The phase rotation value of 0.875 in the 11th row of column 302 and the code shift value of 0.250 in the 11th row of column 303, both corresponding to PRN code 1010, can be selected by the 4-bit encoder 304 and supplied from the output of the 4-bit encoder 304. The code shift value of 0.250 can be output from the 4-bit encoder 304 and supplied as the output of the shift / phase lookup table 206. In one implementation, the code shift value may be 10 bits. In another implementation, the code shift value can be sign-extended to 13 bits.

[0034] A phase rotation value of 0.875 can be output from the 4-bit encoder and supplied to the adder 310. If the least significant bit of the chip count 207 supplied to the 1-bit encoder 306 indicates that the code chip is even, the 1-bit encoder 306 outputs a value of 0 to the adder so that the phase rotation value of 0.875 is not modified. However, if the least significant bit of the chip count 207 indicates that the code chip is odd, the 1-bit encoder outputs a value of π so that the phase rotation value is adjusted by 180 degrees by the adder 310. In this example, we assume that the code chip is even. Therefore, the phase rotation value of 0.875 is supplied as the output of the shift / phase lookup table 206 without being adjusted by the adder 310.

[0035] According to one or more embodiments described herein, as will be described in more detail below, a phase rotation value, for example 0.875, output from the shift / phase lookup table 206 can be used to generate in parallel a sample 215A that has advanced complex rotation relative to sample 201 and a sample 215B that has lagged complex rotation.

[0036] Returning to Figure 2A, the carrier phase NCO208 estimates the carrier phase value (e.g., sine and cosine transforms) based on the accumulated carrier Doppler frequency 209. The carrier phase value from the carrier phase NCO208, which is required to correct the signal 201 for the Doppler effect, is added in the adder 210A to the leading phase rotation value (e.g., 0.875 output from the shift / phase lookup table 206). The result of this addition can be the leading complex phase rotation value. The complex mixer 211A can mix the sample 201 (e.g., multibit I and Q samples) with the leading complex phase rotation value to obtain the leading complex rotated sample 215A. The leading complex rotated sample 215A can be supplied to the inputs of each of the multiplexers 225, for example, input A.

[0037] To generate the delayed complex-rotated sample 215B, a phase rotation value, e.g., 0.875, is delayed by 1 PRN. In particular, the phase rotation value of 0.875 is supplied to a 1 PRN delay unit 212A, which can store the phase rotation value for the previous code chip. The phase rotation value of 0.875 supplied to the 1 PRN delay unit 212A can function as a signal to the 1 PRN delay unit 212A indicating that the phase rotation value for the previous code chip should be supplied from the 1 PRN delay unit 212A to the adder 210B. In this example, as described above, the local code for the previous code chip is

[1111] . Based on the shift / phase lookup table 206, the phase rotation value corresponding to the PRN code

[1111] is 0.125. Therefore, based on the phase rotation value of 0.875 supplied from the shift / phase lookup table 206 to the 1PRN delay unit 212A, the 1PRN delay unit 212A supplies a phase rotation value of 0.125 + 0.5 for the previous code chip to the adder 210B, which adds the estimated carrier phase value to the phase rotation value of 0.625 in order to remove the Doppler effect.

[0038] The result of the addition by adder 210B can be obtained as a delayed complex phase rotation value. Complex mixer 211B can mix sample 201 with the delayed complex phase rotation value to obtain a delayed complex rotation sample 215B. The delayed complex rotation sample 215B can be supplied to an input section of each of the multiple multiplexers 225 that is different from the input section to which the advanced complex rotation sample 215A is supplied, for example to input section B.

[0039] Therefore, a single sample 201 is utilized by the integrating signal processing unit 200A to generate a leading complex-rotated sample (215A) and a lagging complex-rotated sample (215B) in parallel. As will be described in more detail below, the complex-rotated samples can be supplied to, for example, two enabled bins out of a plurality of N bins across two code chips from two multiplexers 225, for example, 20 bins. As will be described in more detail below, the determination of which enabled bins the leading and lagging complex-rotated samples are supplied to can be based on code shift values ​​obtained from the shift / phase lookup table 206 and the code phase NCO.

[0040] Using the code shift value output from the shift / phase lookup table 206, multiple sample code phase values ​​across two code chips, such as a leading sample code phase value and a lagging sample code phase value, can be generated in parallel. In this example, a code shift value of 0.250 output by the shift / phase lookup table 206 is supplied to the adder 210D. The adder 210D adds the code shift value of 0.250 to the code phase subchip value of 0.99, which represents the time slot in the code chip for sample 201 and is supplied by the code phase NCO 203, to obtain a leading sample code phase value of 1.24. This leading sample code phase value can be supplied to the leading sample enable decoder 213A. Based on the supplied leading sample code phase value of 1.24, the leading sample enable decoder 213A can determine which of the multiple bins 220 will be enabled. If the forward sample code phase value is less than 1.0, the forward sample code phase value can enable one of the forward bins, e.g., bins 0 to 9, according to one or more embodiments described herein. If the forward sample code phase value is greater than 1.0, the forward sample code phase value can enable one of the delayed bins, e.g., bins 10 to 19, according to one or more embodiments described herein. In this example, the forward sample code phase value of 1.24 is greater than 1.0, and therefore the forward sample code phase value of 1.24 enables the delayed bin, as will be described in more detail below.

[0041] Figure 4 is a schematic block diagram of a sample-enabled decoder 213 according to one or more embodiments described herein, for example, an advanced sample-enabled decoder 213A. The sample-enabled decoder 213 may include starting positions for each of the multiple bins 220, and these starting positions can be initialized by the processor 125. In this example, there are 20 evenly spaced bins spanning two code chips. The following table shows where each of the 20 bins can start, with reference to the window spanning the two code chips in this example. [Table 1]

[0042] The leading sample code phase value can be supplied to the limiter 402 of the sample enable decoder 213 so that any negative values ​​are set to 0. Alternatively, negative values ​​for the leading sample code phase value may be simply excluded (i.e., ignored) by the integral signal processing unit 200A according to one or more embodiments described herein. In this example, the leading sample code phase value is 1.24 and therefore will not be set to, for example, 0. Thus, the leading sample code phase value of 1.24 is supplied to each of a plurality of comparators 405, for example, N comparators, each of which can correspond to a different bin. Thus, in this example, there are 20 comparators, each corresponding to a different bin out of 20 bins. Each of the plurality of comparators 405 can use the leading sample code phase value, for example 1.24, to determine whether the corresponding bin should be enabled. The output of each of the multiple comparators 405, for example Y, can be set to a value of 1 (i.e., ←) if the bin should be enabled, or to a value of 0 (i.e., ←) if the bin should not be enabled (i.e., remain disabled).

[0043] In particular, as shown in Figure 4, x represents the forward sample code phase value, e.g., 1.24. For each comparator except the last one, A represents the starting value for the current bin, and B represents the starting value for the next bin. If the forward sample code phase value, e.g., x, is within the range defined by the starting value of the current bin, e.g., A, and the starting value of the next bin, e.g., B, then it is determined that the current bin should be enabled, and for example, Y is set to a value of 1. In particular, if the forward sample code phase value, e.g., x, is greater than or equal to A and less than B, then the current bin should be enabled, and for example, Y is set to a value of 1; otherwise, the bin is disabled / remains disabled, and for example, Y is set to a value of 0.

[0044] For the last comparator, A can represent the starting value of the last bin, and B can represent the ending value of the last bin. If the forward sample code phase value, e.g., x, is within the range defined by the starting value of the last bin, e.g., A, and the ending value of the last bin, e.g., B, then it is determined that the last bin should be enabled, and for example, Y is set to a value of 1. In particular, if the forward sample code phase value, e.g., x, is greater than or equal to A and less than B, then the last bin should be enabled, and for example, Y is set to a value of 1; otherwise, the last bin is disabled / remains disabled, and for example, Y is set to a value of 0. Alternatively, the last comparator may use only A, which represents the starting value. In this embodiment, if the forward sample code phase value, e.g., x, is greater than or equal to A, then the last bin should be enabled, and for example, Y is set to a value of 1; otherwise, the bin is disabled / remains disabled, and for example, Y is set to a value of 0.

[0045] In this example, each of the 20 comparators 405 uses a leading sample code phase value of 1.24 to determine which bin should be enabled. In particular, in this example, the 13th comparator corresponding to bin 12 determines that the leading sample code phase value of 1.24 is within the range of 1.2(A) to 1.3(B). Therefore, the output of the 13th comparator is the enable signal for bin 12, for example, Y is set to a value of 1. All other comparators, such as comparators 1-12 and 14-20, determine that the leading sample code phase value of 1.24 is not within the range defined for these other comparators. Therefore, the outputs of these other comparators are the disable bin signals, for example, Y is set to a value of 0.

[0046] Therefore, in this example, the output from the enabler 410A of the forward sample enable decoder 213A is the forward bin enable output 216A for enabling bin 12 (the lagging bin) out of the 20 bins. According to one embodiment, the forward bin enable output 216A may be a vector of 0s and 1s, where 1 indicates that the bin should be enabled, and 0 indicates that the bin should not be enabled, for example, to remain disabled. Therefore, the forward bin enable output 216A in this example may be 0000 0001 0000 0000 0000, where the least significant bit of this vector represents bin 0 and the most significant bit represents bin 19. As will be explained in more detail below, the forward bin enable output 216A, output by the forward sample enable decoder 213A, can be used to enable one of the multiple bins 220, and it is also possible to determine which complex-rotated sample is supplied to which enabled bin, for example, whether the forward complex-rotated sample 215A or the lagging complex-rotated sample 215B is supplied.

[0047] Returning to Figure 2A, a code shift value obtained from the shift / phase lookup table 206, for example 0.250, can be delayed by 1 PRN to generate a delayed sample code phase value used to enable one of the multiple bins 220. In particular, the code shift value of 0.250 is supplied to the 1 PRN delay unit 212B, which can store the code shift value for the previous code chip. The code shift value of 0.250 supplied to the 1 PRN delay unit 212B can function as a signal to the 1 PRN delay unit 212B indicating that the code shift value for the previous code chip should be supplied from the 1 PRN delay unit 212B to the adder 210E. In this example, as mentioned above, the local code generated for the previous code chip is

[1111] . Based on the shift / phase lookup table 206, the code shift value corresponding to the PRN code

[1111] is -0.250. Therefore, based on the code shift value of 0.250 supplied from the shift / phase lookup table 206 to the 1PRN delay unit 212B, the 1PRN delay unit 212B can supply the adder 210E with a code shift value of -0.250 for the previous code chip. The adder 210E can add the code shift value of -0.250 to the code phase subchip value of 0.99 and the value of 1 to produce a delayed sample code phase value of 1.74 (e.g., -0.250 + 0.99 + 1). The adder 210E adds a value of 1 to the delayed sample code phase value to offset it in time by the duration of the 1PRN chip (i.e., for the second code chip in a window spanning two code chips).

[0048] This delayed sample code phase value of 1.74 can be supplied to the delayed sample enable decoder 213B. Based on the supplied delayed sample code phase value of 1.74, the delayed sample enable decoder 213B can determine which of the multiple bins 220 will be enabled. If the delayed sample code phase value is less than 1.0, the delayed sample code phase value can enable one of the forward bins, e.g., bins 0 to 9, according to one or more embodiments described herein. If the delayed sample code phase value is greater than 1.0, the delayed sample code phase value can enable one of the delayed bins, e.g., bins 10 to 19, according to one or more embodiments described herein. In this example, the delayed sample code phase value of 1.74 is greater than 1.0, and therefore the delayed sample code phase value of 1.74 enables a delayed bin, as will be described in more detail below.

[0049] In particular, referring to Figure 4, the sample decoder 213, for example, the delayed sample-enable decoder 213B, can utilize the final delayed sample-code phase value of 1.74 in the same manner as described above. In this case, x in Figure 4 represents the delayed sample-code phase value of 1.74, rather than the advanced sample-code phase value, for example, 1.24, as described above for the advanced sample-enable decoder 213A. More specifically, each of the multiple comparators 405 can use the delayed sample-code phase value, for example, 1.74, in the same manner as described above to determine whether the corresponding bin should be enabled. In this example, the 18th comparator corresponding to bin 17 determines that the delayed sample-code phase value of 1.74 is within the range of 1.7(A) to 1.8(B). Therefore, the output of the 18th comparator is the enable signal for bin 17, for example, Y is set to a value of 1. All other comparators, for example, comparators 1 to 17, 19, and 20, determine that the delayed sample-code phase value of 1.74 is not within the range defined for these other comparators. Therefore, the output of these other comparators is a disabled bin signal, for example, when Y is set to a value of 0.

[0050] Therefore, in this example, the output from the enabler 410A of the delayed sample enable decoder 213B is the delayed bin enable output 216B for enabling bin 17. According to one embodiment, the delayed bin enable output 216B may be a vector of 0s and 1s, where 1 indicates that the bin is enabled and 0 indicates that the bin is disabled. Therefore, the delayed bin enable output 216B in this example may be 0010 0000 0000 0000 0000, where the least significant bit of this vector represents bin 0 and the most significant bit represents bin 19.

[0051] As shown in Figure 2A, a forward bin enable output 216A, e.g., 0000 0001 0000 0000 0000, and a delayed bin enable output 216B, e.g., 0010 0000 0000 0000 0000 can be supplied to the OR gate 214 from the forward sample enable decoder 213A and the delayed sample enable decoder 213B, respectively. The OR gate 214 can use the OR operation to generate a final bin enable output 216AB of 0010 0001 0000 0000 0000, where the least significant bit can represent bin 0 and the most significant bit can represent bin 19. The final bin enable output 216AB can be supplied to multiple bins 220 across two code chips, so that none of the multiple bins 220 are enabled, one of the multiple bins 20 is enabled, or two of the multiple bins 220 are enabled. In this example, the final bin enable output 216AB is a vector of 0010 0001 0000 0000 0000 from the OR gate 214, which is fed to bin 220 to enable bins 12 and 17 of a total of 20 bins across two code chips.

[0052] In particular, each bit of the final bin enable output 216AB can be supplied to the corresponding bin, respectively. A bin supplied with a value of 1, e.g., a high signal, is enabled, while a bin supplied with a value of 0, e.g., a low signal, remains disabled. In this example, bins 12 and 17 are supplied with a value of 1, e.g., a high signal, while bins 0-11, 13-16, 18, and 19 are supplied with a value of 0, e.g., a low signal. Therefore, bins 12 and 17 are enabled, while bins 0-11, 13-16, 18, and 19 remain disabled.

[0053] Furthermore, as shown in Figure 2A, the forward bin enable output 216A output from the forward sample enable decoder 213A can be supplied to multiple multiplexers 225 to determine which complex-rotated samples are supplied to the enabled bins, for example, bins 12 and 17, for example, whether the forward complex-rotated sample 215A or the lagging complex-rotated sample 215B is supplied. The number of multiplexers 225 can correspond to the number of bins 220, and each multiplexer 225 can be coupled to a different bin 220, as shown in Figure 2A. For example, as shown in Figure 2A, the first multiplexer is coupled to bin 0, the second multiplexer is coupled to bin 1, and so on. Thus, in this example, each of the 20 different multiplexers 225 is coupled to a different bin out of the 20 bins across two code chips. In one implementation configuration, each multiplexer 225 has an output section Y, an input section A that receives a leading complex-rotated sample 215A, and an input section B that receives a lagging complex-rotated sample 215B.

[0054] As shown in Figure 2A, a forward bin enable output 216A, for example 0000 0001 0000 0000 0000, can be supplied to the multiplexer 225. In particular, each bit of the forward bin enable output 216A, which may be a vector, can be supplied to each different multiplexer 225 corresponding to the appropriate bin. For example, the least significant bit of the forward bin enable output 216A represents bin 0 and is therefore supplied to the first multiplexer 225 coupled to bin 0. The most significant bit of the forward bin enable output 216A represents bin 19 and is therefore supplied to the last multiplexer (e.g., multiplexer 20) coupled to bin 19 (e.g., bin N-1).

[0055] In one implementation, a multiplexer 225 that receives a high signal (e.g., a value of 1) based on the bit of the leading bin enable output 216A supplies the leading complex-rotated sample 215A received at input A as its output (e.g., Y). Furthermore, a multiplexer 225 that receives a low signal (e.g., a value of 0) based on the bit of the leading bin enable output 216A supplies the delayed complex-rotated sample 215B received at input B as its output (e.g., Y). In another implementation, only one multiplexer 225 is supplied with a high signal (e.g., a value of 1), so that only that one multiplexer 225 supplies the leading complex-rotated sample 215A as its output (e.g., Y), while all other multiplexers 225 are supplied with low signals (e.g., a value of 0), so that all other multiplexers 225 supply the delayed complex-rotated sample 215B as their output (e.g., Y).

[0056] In an alternative embodiment, the multiplexer may be configured and operated in the opposite manner (not shown), in which case the leading bin enable output 216A of the leading sample enable decoder 213A is inverted using an inverter (not shown) which would be placed, for example, between the OR gate 214 and the multiplexer 225. Thus, the leading bin enable output 216A of 0000 0001 0000 0000 0000 would be inverted to 1111 1110 1111 1111 1111. Therefore, in this alternative embodiment, the multiplexer 225, having received a low signal (e.g., a value of 0) based on the inverted leading bin enable output, would supply the leading complex-rotated sample received at input A as its output (e.g., Y). Furthermore, upon receiving a high signal (e.g., a value of 1) based on the inverted leading bin enable output 216A, the multiplexer 225 will supply the delayed complex-rotated sample received at input B as its output (e.g., Y).

[0057] Subsequently, the forward-complex-rotated sample 215A and / or the lagging-complex-rotated sample 215B are fed from the output section (e.g., Y) of the multiplexer 225 to the corresponding enabled bins. In this example, as described above, bins 12 and 17 are enabled based on the final bin enable output 216AB, which is a vector of 0010 0001 0000 0000 0000 from the OR gate 214. In addition, in this example, a 13th multiplexer coupled to the enabled bin 12 receives a high signal, e.g., a value of 1, based on the forward-complex-rotated bin enable output 216A, e.g., 0000 0001 0000 0000 0000.

[0058] Therefore, the leading complex-rotated sample 215A received at input A of the 13th multiplexer 225 is supplied as the output of the 13th multiplexer 225, e.g., Y, and is fed into the enabled bin 12, where it is accumulated. Furthermore, in this example, the 18th multiplexer, coupled to the enabled bin 17, receives a low signal, e.g., a value of 0, based on the leading bin enable output 216A. Therefore, the lagging complex-rotated sample 215B received at input B of the 18th multiplexer 225 is supplied as the output of the 18th multiplexer 225, e.g., Y, and is fed into the enabled bin 17, where it is accumulated. The other multiplexers 225, e.g., 1-12, 14-17, 19, and 20, are coupled to the disabled bins, so the outputs from these other multiplexers 225 (e.g., lagging complex-rotated samples 215B) are not accumulated in the disabled bins.

[0059] Therefore, as described above, two complex-rotated samples, for example, a leading complex-rotated sample 215A and a lagging complex-rotated sample 215B, can be generated in parallel for a single sample 201 and accumulated in parallel within a plurality of bins 220 across two code chips. Thus, according to one or more embodiments described herein, a plurality of samples of an integral signal synchronized with a sample clock 204 can be processed by generating a leading complex-rotated sample and a lagging complex-rotated sample in parallel for each of these plurality of samples and accumulating these complex-rotated samples within a plurality of bins 220 across two code chips. The receiver can use the complex-rotated samples accumulated within selected bins 220 and / or selected groups of bins 220 for the plurality of samples to generate correlation values ​​that may be required to implement one or more correlation techniques and / or one or more multipath relaxation techniques.

[0060] More generally, OR gate 214 and multiplexer 225 are just one means for providing the following desired functions:

Number

Number

[0061] Furthermore, the accumulated complex-rotated samples can be used to calculate correlation measurement values that can be utilized, for example, to track an integrated signal. As shown in Figure 2A, the complex-rotated samples 215A i and 215B iThese can be supplied from the complex mixers 211A and 211B to the weighted bins 230A and 230B. In particular, as shown in Figure 2A, the forward complex-rotated sample 215A is supplied from the complex mixer 211A to the first input of weighted bin 230A (e.g., the top arrow) and the last input of weighted bin 230B (e.g., the bottom arrow). Furthermore, as shown in Figure 2A, the lagging complex-rotated sample 215B is supplied from the complex mixer 211B to the second input of weighted bin 230A (e.g., the second arrow from the top) and the third input of weighted bin 230B (e.g., the third arrow from the top).

[0062] Furthermore, the forward bin enable output 216A and the delayed bin enable output 216B can be supplied to the weighted bins 230A and 230B from the forward sample enable decoder 213A and the delayed sample enable decoder 213B. In particular, as shown in Figure 2A, the forward bin enable output 216A is supplied from the forward sample decoder 213A to the input A of the weighted bins 230A and 230B. Furthermore, as shown in Figure 2A, the delayed bin enable output 216B is supplied from the delayed sample decoder 213B to the input B of the weighted bins 230A and 230B.

[0063] In one embodiment, the complex-rotated samples 215A and 215B can be accumulated within a single window spanning at least 1.5 code chips, for example, two code chips, to track the integrated signal.

[0064] In particular, the weighted bin 230A can store a weighted vector, and this weighted vector can be used to generate a punctual signal that can be used for tracking. In one implementation, the processor 125 can initialize the weighted bin 230A so that it stores a weighted vector for the P signal. In one implementation, the values ​​for the P signal for tracking are

number

number

[0065] The summation part of this formula can be implemented in adder 242. Therefore, in this example with 20 bins, w P w may be a vector of length 20, P Each weight value in can correspond to a different bin. For example, w P The first value in (W b1 ) may be the weight for bin 0, w P The second value in (W b2 ) may be the weight for bin 1, and so on. P The weights in this can be based on a variety of factors, including, but are not limited to, the specific type of the integral signal (e.g., ACE-BOC type I signal, ACE-BOC type II signal, or ACE-BOC type III signal), the power ratio of the integral signal, the implementation of the integral signal, etc.

[0066] Continuing with the above example, based on the above formula, sample 215A is rotated using the advanced complex and w corresponds to bin 12. P Using the weighted forward bin enable output 216A from and the delayed complex rotated sample 215B, and the corresponding w bin 17 P Using the delayed bin enable output 216B which has weights from P i It can generate P in adder 242. i The values ​​can be summed up (i.e., accumulated) to generate a P signal.

[0067] Furthermore, the weighted bin 230B can store a weighted vector, which can be used to generate an early-late signal (EL) that can be used for tracking. In one implementation, the processor 125 can initialize the weighted bin 230B so that it stores a weighted vector for the EL signal. In one implementation, the value of the EL signal (EL) for tracking can be generated. i )of,

number

number

[0068] Therefore, in this example with 20 bins, W E-L w may be a vector of length 20, E-L Each weight value in can correspond to a different bin. For example, W E-L The first value in (W b1 ) may be the weight for bin 0, W E-L The second value in (W b2 ) may be the weight for bin 1, and so on. E-L The weights in this can be based on a variety of factors, including, but are not limited to, the specific type of the integral signal (e.g., ACE-BOC type I signal, ACE-BOC type II signal, or ACE-BOC type III signal), the power ratio of the integral signal, the implementation of the integral signal, etc.

[0069] Continuing with the above example, based on the above formula, sample 215A is rotated using the advanced complex and w corresponds to bin 12. E-L Using the weighted forward bin enable output 216A from and the delayed complex rotated sample 215B, and the corresponding w bin 17 E-L Using the delayed bin enable output 216B which has weights from EL, i It can generate EL in adder 244. i The values ​​can be summed (i.e., accumulated) to generate the EL signal. Therefore, adders 242 and 244 generate the P accumulated signal and the EL accumulated signal, respectively, for a predetermined period of time. i Value and ELi The values ​​are accumulated (summed up).

[0070] The P-accumulated and EL-accumulated signals from 242 and 244 can be supplied to a tracking module 252, as shown in Figure 2A, which may be located outside the integrating signal processing unit 200. In one embodiment, the tracking module may include a code tracking loop 253, which may be a delay-locked loop (DLL) that can operate in a conventional manner. In addition, the tracking module may include a carrier tracking loop 254, which may be a phase-locked loop (PLL) or a frequency-locked loop (FLL) that can operate in a conventional manner.

[0071] In one implementation, the tracking module sends a code error signal (Code Error )of,

number

[0072] Similarly, according to one or more embodiments described herein, the in-phase and quadrature-phase components of the timed signal generated by the adder 242 can be supplied to a carrier tracking loop 254 (e.g., a PLL or FLL), and these components can be utilized by the carrier tracking loop 254 (e.g., a PLL or FLL) to generate a new estimate of the carrier Doppler frequency 209, as known to those skilled in the art.

[0073] Figure 2B is a schematic block diagram of another integral signal processing unit 200B, which can process an integral signal by generating multiple complex-rotated samples in parallel for a single sample of the integral signal 201, according to one or more embodiments described herein. Figure 2B is similar to Figure 2A, except that the integral signal processing unit 200B does not include bin 220. Thus, as shown in Figure 2B, the leading complex-rotated sample 215A and the lagging complex-rotated sample 215B, generated in parallel for sample 201, are fed to both weighted bins 230A and 230B to track the integral signal as described above. The integral signal processing unit 200B in Figure 2B does not include bin 220, but can utilize weighted bins 230A and 230B to generate P-accumulated and EL-accumulated signals as described above with reference to Figure 2A. The P-accumulated and EL-accumulated signals are fed to the tracking module 252 to generate Code for tracking as described above with reference to Figure 2A. Error The code rate of 205 and / or the carrier Doppler frequency of 209 can be calculated.

[0074] Figure 2C is a schematic block diagram of another integral signal processing unit 200C, which can process an integral signal by generating a plurality of complex-rotated samples 215A and 215B in parallel for a single sample of the integral signal, according to one or more embodiments described herein. Figure 2C is similar to Figure 2A, except that the integral signal processing unit 200C does not include weighted bins 230A and 230B and adders 242 and 244. Thus, the integral signal processing unit 200C of Figure 2C can accumulate the complex-rotated samples within a selected bin 220 and / or a selected group of bins 220, as described above with reference to Figure 2A, to generate correlation values ​​that may be required to implement one or more correlation techniques, and / or one or more multipath relaxation techniques, and / or one or more techniques for generating a coded rate (e.g., DLL) and a carrier Doppler frequency estimate (e.g., PLL or FLL).

[0075] Figure 5 is an exemplary flowchart for processing an integral signal by generating multiple complex-rotated samples in parallel for a single sample of the integral signal, according to one or more embodiments described herein. Procedure 500 begins in step 505 and proceeds to step 510, in which the integral signal is received by a GNSS antenna. In one embodiment, the integral signal may be based on ACE-BOC multiplexing and may have multiple signal components with arbitrary power assignments.

[0076] The procedure proceeds to step 515, where a local code is generated for sample 201 of the integrated signal, and this local code corresponds to one of the codes in the received integrated signal. In one implementation, this local code may be an advanced version of a code in the integrated signal. The procedure proceeds to step 520, where a phase rotation value and a code shift value are selected based on the local code. For example, the phase rotation value and the code shift value can be selected from the shift / phase lookup table 206 as described above, with reference to Figure 3.

[0077] The procedure proceeds to step 525, where, as described above with reference to Figure 2A, a leading complex-rotated sample 215A and a lagging complex-rotated sample 215B are generated in parallel based on phase rotation values ​​(e.g., leading phase rotation value and lagging phase rotation value from the 1PRN delay unit 212A) and the carrier phase value estimated by the carrier phase NCO208. The procedure proceeds to step 530, where a leading code phase value and a lagging code phase value are generated in parallel using the leading code shift value and lagging code shift value as described above with reference to Figure 2A. In one embodiment, the lagging code shift value is a leading code shift value that is time-offset by the duration of the 1PRN code chip using the 1PRN delay unit 212B, as described above with reference to Figure 2A.

[0078] The procedure proceeds to step 535, where the forward and delayed code phase values ​​are used to generate a final bin enable output 216AB, which may be a vector. Thus, since the forward and delayed code phase values ​​span at least 1.5 code chips (e.g., 2 code chips), the final bin enable output vector spans at least 1.5 code chips (e.g., 2 code chips). The procedure proceeds to step 540, where the final bin enable output 216AB generated for any arbitrary width less than or equal to the number of code chips in the PRN code sequence is used to accumulate multiple complex-rotated samples in parallel for a single sample (e.g., a forward complex-rotated sample 215A and a delayed complex-rotated sample 215B). For example, the window can span at least 1.5 code chips (e.g., 2 code chips).

[0079] For example, the final bin-enable output 216AB can be used to accumulate advanced complex-rotated samples and lagging complex-rotated samples in parallel within one or two bins of a plurality of bins 220 spanning at least 1.5 code chips (e.g., two code chips) (or to avoid accumulating them in any bin). The plurality of bins 220 can be used to generate correlation values ​​that may be required to implement one or more correlation techniques, and / or one or more multipath relaxation techniques, and / or one or more carrier Doppler frequency estimation techniques.

[0080] Additionally or alternatively, using the forward bin enable output 216A and the delayed bin enable output 216B, and using the weighted bins 230A and 230B, the forward complex-rotated sample 215A and the delayed complex-rotated sample 215B can be accumulated in parallel for a window spanning at least 1.5 code chips (2 code chips) relative to sample 201. The weighted bins 230A and 230B are available for accumulating the signal for some predetermined period and are then available to track both the code and carrier of the integrated signal, which feeds the corrected signal to the code rate 205 and carrier Doppler frequency 209.

[0081] Then, the procedure 500 is repeated, returning to step 510, so that multiple complex-rotated samples can be generated and accumulated in parallel for the next single sample of the integrated signal 201.

[0082] As described above with reference to Figures 2A to 2C, in addition to generating and accumulating a leading complex-rotated sample and a lagging complex-rotated sample in parallel for each sample 201, one or more embodiments described herein can also sequentially generate and accumulate multiple complex-rotated samples 615 (e.g., leading complex-rotated sample 215A and / or lagging complex-rotated sample 215B) for each sample 201. Figure 6A is a schematic block diagram of an integral signal processing unit 200D that can process an integral signal by sequentially generating multiple complex-rotated samples 615 for a single sample 201 of the integral signal, according to one or more embodiments described herein.

[0083] According to one or more embodiments described herein, samples of an integral signal 201 synchronized with a sample clock 204 can be processed by sequentially generating multiple complex-rotated samples (e.g., advanced complex-rotated samples, time-stabilized complex-rotated samples, and delayed complex-rotated samples) for each sample 201, as will be further described below with reference to Figure 6A. The complex-rotated samples 615 for sample 201 can be sequentially accumulated within N bins 220 over any arbitrary width less than or equal to the number of code chips in the PRN code sequence. For example, the window can span at least 1.5 code chips (e.g., 3 or 10 code chips).

[0084] As an illustrative example, suppose bin 220 in Figure 6A contains 21 bins evenly spaced across the span of three code chips. Furthermore, suppose that the first seven bins (e.g., bins 0 to 6) are "advancing bins" across the first code chip, the second seven bins (e.g., bins 7 to 13) are "punctual bins" across the second code chip, and the third seven bins (e.g., bins 14 to 20) are "lagging bins" across the third code chip.

[0085] As will be described in more detail below, a forward complex-rotated sample 615 can be generated for sample 201 and accumulated in one of the multiple bins 220 across three code chips. Subsequently, a timely complex-rotated sample can be generated for sample 201 and accumulated in one of the multiple bins 220 across three code chips. Subsequently, a delayed complex-rotated sample can be generated for sample 201 and accumulated in one of the multiple bins 220 across three code chips. Thus, according to one or more embodiments described herein, three complex-rotated samples can be sequentially generated and accumulated for a single sample 201 within a single window across three code chips. The example in Figure 6A includes multiple evenly spaced bins 220 spanning three code chips, but it is explicitly assumed that one or more embodiments described may include multiple bins 220 that are unevenly spaced and span any width less than or equal to the number of code chips in the PRN code sequence. For example, multiple bins may span at least 1.5 code chips or more than 3 code chips (e.g., 10 code chips).

[0086] Referring to Figure 6A, the 4×PRN code generator 202 can generate multiple local codes (e.g., PRN codes) corresponding to the codes in the received integral signal. In one embodiment, the multiple local codes may be an advanced version of the code in the integral signal, a timed version of the code in the integral signal, and a delayed version of the code in the integral signal.

[0087] As mentioned above, the first bit of the 4-bit code (for example, the most significant bit) is the upper frequency common-mode signal (S) related to the integral signal. UI ) can be handled. The second bit of the 4-bit code is the lower frequency common-mode signal (S) related to the integral signal. LI) can be handled. The third bit of the 4-bit code is the upper frequency quadrature phase signal (S) related to the integral signal. UQ ) can correspond to the lower frequency quadrature phase signal (S) of the 4-bit code (for example, the least significant bit). LQ It can handle )

[0088] As shown in Figure 6A, three locally generated codes are supplied to the shift table 233. Furthermore, as shown in Figure 6A, a 3x sample clock 222 is supplied to the shift table 233. The 3x sample clock 222 is supplied so that, as will be described in more detail below, the code shift value and phase rotation value can be sequentially selected from the shift / phase lookup table 206 (of the shift table 233) for each of the advance, chrone, and lag versions of the code for sample 201. Furthermore, similar to the initialization of the shift / phase lookup table 206 (of the shift table 233) as described above, the processor 125 of the GNSS receiver 120 can also initialize the shift table 233.

[0089] Figure 7A is a schematic block diagram of a shift table 233 according to one or more embodiments described herein. As shown in Figure 7A, a 3× sample clock 222 is supplied as input to the counter 601 of the shift table 233. Thus, the counter 601 can sequentially (i.e., continuously) generate three different values ​​(e.g., 0, 1, and 2) for each sample 201 (in Figure 6A). Based on the 3× sample clock 222, the counter 601 is reset to start at 0, increment to 1, increment to 2, and then return to 0 for the next sample 201, so that three different counter values ​​are sequentially generated for each sample 201.

[0090] The value of counter 601 can determine which version of the local code (e.g., advanced version, timed version, or delayed version) is supplied to the shift / phase lookup table 206, as shown in Figure 7A, for sample 201. For example, if counter 601 generates a value of 0, this value of 0 is supplied as input to the 2-bit encoder 602, which generates the binary value 00. In response to the generation of the binary value 00 by the 2-bit encoder 602, the advanced version of the local code can be supplied to the shift / phase lookup table 206 for sample 201. Thus, with respect to the advanced version of the local code, the phase rotation value and code shift value can be selected from the phase / shift lookup table 206, as described above with reference to Figure 3.

[0091] When counter 601 increments to a value of 1, this value of 1 is supplied as input to 2-bit encoder 602, which generates a binary value of 01. In response to the generation of the binary value 01 by 2-bit encoder 602, a fixed version of the local code can be supplied to the phase / shift lookup table 206 for sample 201. Thus, with respect to the fixed version of the local code, a phase rotation value and a code shift value can be selected from the phase / shift lookup table 206 as described above with reference to Figure 3.

[0092] When counter 601 increments to a value of 2, this value of 2 is supplied as input to 2-bit encoder 602, which generates a binary value of 10. In response to the generation of the binary value 10 by 2-bit encoder 602, a delayed version of the local code can be supplied to the phase / shift lookup table 206 for sample 201. Thus, with respect to the delayed version of the local code, a phase rotation value and a code shift value can be selected from the phase / shift lookup table 206, as described above with reference to Figure 3.

[0093] Furthermore, as shown in Figure 7A, the output from the XOR gate 604 is also supplied as input to the phase / shift lookup table 206 to indicate whether the code chip is even or odd, in a similar manner to the method described above with reference to Figure 3. In particular, the output of the counter 601, for example, the least significant bit of the output of the counter 601, can be supplied to the XOR gate 604. Since the multiple bins in this embodiment span three code chips, the least significant bit of the counter 601 can be used in combination with the least significant bit of the chip count 207 to indicate whether the code chip is even or odd. More specifically, the least significant bit of the counter 601 and the least significant bit of the chip count 207 can be supplied to the XOR gate 604. To indicate whether the code chip is even or odd, the output of the XOR gate 604 can be supplied to the shift / phase lookup table 206, thereby adjusting the phase rotation value selected from the shift / phase lookup table by 180 degrees for odd-numbered chips, as described above with reference to Figure 3.

[0094] Therefore, for a single sample 201, three pairs of phase rotation values ​​and code shift values ​​are sequentially generated from the shift / phase lookup table 206 based on three versions of the local code (e.g., an advanced version, a timed version, or a delayed version). As will be explained in more detail below, the complex-rotated sample 615 can be generated using the phase rotation values ​​of the selected pair in addition to the carrier phase value estimated by the carrier phase NCO 208, while the bin enable output 616 can be generated using the code phase value (B) of the selected pair, which itself enables one of the multiple bins 220 across the three code chips.

[0095] In particular, the respective code phase values ​​(B) of each pair can be supplied from the shift / phase lookup table 206 to the adder 210F of the sample-enabled decoder 613, as shown in Figure 7B, which is a schematic block diagram of the sample-enabled decoder 613 according to one or more embodiments described herein. Furthermore, the value (A) from the counter 601 can be combined with the code phase subchip value as two most significant bits, which is supplied by the code phase NCO 203 and represents the time slot in the code chip for sample 201. The value from the counter 601 can be combined with two most significant bits to temporally offset the selected code phase as needed.

[0096] When counter 601 is valued at 0 and an advanced version of the local code is supplied to the shift / phase lookup table 206, "00" (representing the value 0) is combined as the two most significant bits of the code phase subchip value. Because "00" is combined as the two most significant bits, the selected code shift value (for the pair corresponding to the advanced version of the code) is not time-offset when the adder 210F of the sample enable decoder 613 adds the code phase subchip value to the selected code shift value. The output of adder 210F may be an advanced sample code phase value.

[0097] When the counter is valued at 1 and a fixed-time version of the local code is supplied to the shift / phase lookup table 206, "01" (representing the value 1) is combined as the two most significant bits of the code phase subchip value. Since "01" is combined as the two most significant bits, the selected code shift value (for the pair corresponding to the fixed-time version of the code) is time-offset by the equivalent of one PRN chip of the code phase (i.e., for the second code chip in a window spanning three code chips) when the adder 210F of the sample-enable decoder 613 adds the combined value to the selected shift phase value. The output of the adder 210F may be a fixed-time sample code phase value.

[0098] If the counter is value 2 and a delayed version of the local code is supplied to the shift / phase lookup table 206, then "10" is combined as the two most significant bits of the code phase subchip value. Since "10" is combined as the two most significant bits, the selected code shift value (for the pair corresponding to the delayed version of the code) is time-offset by the equivalent of two PRN chips of the code phase (i.e., for the third code chip in a window spanning three code chips) when the adder 210F of the sample-enable decoder 613 adds the combined value to the selected code shift value. The output of adder 210F may be a delayed sample code phase value.

[0099] As described above with reference to Figure 4, the sample code phase values ​​(e.g., leading code phase value, timed code phase value, and delayed code phase value) can be used by each of the multiple comparators 405 of the sample enable decoder 613 in Figure 7B to sequentially determine which of the multiple bins 220 across the three code chips is enabled. In one implementation, if the sample code phase value is less than 1.0, one of the leading bins, e.g., bins 0-6, can be enabled. In another implementation, if the sample code phase value is greater than 1.0 and less than 2.0, one of the timed bins, e.g., bins 7-13, can be enabled. In one implementation, the sample code phase value (e.g., leading code phase value, timed code phase value, and lagging code phase value) can enable one of the lagging bins, e.g., bins 8-20, if the sample code phase value is greater than 2.0.

[0100] In particular, the leading sample code phase value is available to each of the 21 comparators 405, each comparator generating one bit of the bin enable output 616 (e.g., a vector of 0s and 1s), as described above with reference to signal 216A in Figure 4. The bin enable output 616 can be used to enable the bin so that the leading complex rotated sample generated for sample 201, as described below, is accumulated within the enabled bin.

[0101] Similarly, the timed sample code phase value is available to each of the 21 comparators 405, each comparator generating one bit of the bin enable output 616 (e.g., a vector of 0s and 1s) as described above with reference to signal 216B in Figure 4. The bin can be enabled again by utilizing the bin enable output 616 so that the timed complex-rotated sample generated for sample 201, as described below, accumulates within the enabled bin. Furthermore, the delayed sample code phase value is available to each of the 21 comparators 405, each comparator generating one bit of the bin enable output 616 (e.g., a vector of 0s and 1s) as described above. The bin can be enabled again by utilizing the bin enable output 616 so that the delayed complex-rotated sample generated for sample 201, as described below, accumulates within the enabled bin.

[0102] Returning to Figure 6A, the phase rotation value and bin enable output 616 are sequentially supplied as outputs from the shift table 233, based on each version of the local code for sample 201. For the advanced version of the code, the phase rotation value generated from the shift / phase lookup table 206 and the advanced bin enable output 616 are supplied as outputs from the shift table 233. For the timed version of the code, the phase rotation value generated from the shift / phase lookup table 206 and the timed bin enable output 616 are supplied as outputs from the shift table 233. For the delayed version of the code, the phase rotation value generated from the shift / phase lookup table 206 and the delayed bin enable output 616 are supplied as outputs from the shift table 233.

[0103] The bin enable outputs (e.g., forward bin enable output, timed enable output, and delayed bin enable output) can be sequentially supplied from enabler 410B to form the bin enable output 616 (of the shift table 233 in Figure 7B), which enabler 410B is connected to bin 220 in Figure 6A to sequentially enable the bins as described above with reference to Figure 2A. In particular, enabler 655 receives the 3 × sample clock 222 and the enable signal from counter 601 as inputs, so enabler 655 supplies signal (C) to enabler 410B, which then sequentially supplies the bin enable outputs 616 (e.g., three values ​​corresponding to the forward bin enable output, timed enable output, and delayed bin enable output) to sequentially enable three of the bins of bin 220 across three code chips for a single sample 201.

[0104] The respective phase rotation values ​​output from the shift table 233 can be used to generate a complex-rotated sample 615. In particular, to eliminate the Doppler effect as described above (see Figure 2A), each phase rotation value can be supplied to the adder 210A along with the carrier phase value estimated by the carrier phase NCO 208. The result of this addition can be supplied to the complex mixer 211A and mixed with sample 201 (e.g., multi-bit I and Q samples) to obtain the complex-rotated sample 615 as described above (see signals 215A and 216B in Figure 2A).

[0105] For example, using phase rotation values ​​generated based on an advanced version of the code, sample 615 can be generated with a leading complex rotation relative to sample 201. Using phase rotation values ​​generated based on a timed version of the code, sample 615 can be generated with a timed complex rotation relative to sample 201. Using phase rotation values ​​generated based on a delayed version of the code, sample 615 can be generated with a delayed complex rotation relative to sample 201.

[0106] Therefore, the integrating signal processing unit 200D can sequentially generate multiple complex-rotated samples for a single sample 201, and these complex-rotated samples can be sequentially accumulated in multiple bins 220 across three code chips. In particular, the generated advanced complex-rotated samples can be accumulated in bins enabled based on the advanced bin enable data in the bin enable output 616, among the multiple bins 220 across three code chips. Subsequently, the generated time-controlled complex-rotated samples can be accumulated in bins enabled based on the time-controlled bin enable data in the bin enable output 616, among the multiple bins 220 across three code chips. Subsequently, the generated delayed complex-rotated samples can be accumulated in bins enabled based on the delayed bin enable data in the bin enable output 616, among the multiple bins 220 across three code chips. Thus, the advanced complex-rotated samples, time-controlled complex-rotated samples, and delayed complex-rotated samples generated for a single sample 201 can be sequentially generated and accumulated in enabled bins across three code chips according to one or more embodiments described herein.

[0107] More generally, each bin 220 is given by the following formula:

number

number

[0108] Accordingly, according to one or more embodiments described herein, multiple samples of an integral signal synchronized with a sample clock 204 can be processed by sequentially generating a leading complex-rotated sample, a time-stabilized complex-rotated sample, and a delayed complex-rotated sample for each sample 201, and accumulating these complex-rotated samples in multiple bins 220 across three code chips. The GNSS receiver 120 can use the complex-rotated samples accumulated in selected bins 220 and / or selected groups of bins 220 to generate correlation values ​​that may be required to perform one or more correlation techniques, and / or one or more multipath relaxation techniques, and / or carrier Doppler frequency estimation techniques.

[0109] Furthermore, using the complex-rotated samples, for example, using weighted bins 630A and 630B, correlation measurements can be calculated.

[0110] In particular, the weighting bin 630A can store a weighting vector, and this weighting vector can be used to generate a P signal that can be used for tracking. In one implementation, the P signal for tracking shown in Figure 6A ik of,

number

number

[0111] Therefore, in this example with 21 bins, w p w may be a vector of length 21, p Each weight value in can correspond to a different bin. For example, w p The first value in (W b1 ) may be the weight for bin 0, w p The second value in (W b2 ) may be the weight for bin 1, and so on. p The weights in can be based on various factors, which include, but are not limited to, the specific type of the integral signal (e.g., ACE-BOC type I signal, ACE-BOC type II signal, or ACE-BOC type III signal), the power ratio of the integral signal, the implementation of the integral signal, etc. In adder 242, P i The values ​​can be summed up to generate a P signal.

[0112] Furthermore, the weighted bin 630B of FIG. 6A can store a weighted vector, and using this weighted vector, an E-L signal that can be used for tracking can be generated. In one implementation, the E-L of the E-L signal for tracking ik can be [Number] generated as follows, where w E-L =[W b1 ,W b2 ,···,W bN where 615 ik is the complex-rotated sample for sample i, 616 ik is the bin enable output for sample i and chip offset k, K is the number of chips in the sequential process (in this example, K = 3), T is the number of samples to be accumulated, w E-L is the weighted vector applied to the enabled samples, and N is the total number of bins. The dot product "·" is defined as the sum of the products of the corresponding entries of two vectors of equal length, i.e., [Number] defined as, where n is the length of vectors a and b.

[0113] Thus, in this example with 21 bins, w E-L can be a vector of length 21, and each weight value in w E-L can correspond to a different bin. For example, the first value (W E-L ) in w b1 can be the weight for bin 0, and the second value (W E-L ) in w b2 can be the weight for bin 1, and so on. w E-L ​The weights in can be based on various factors, including, but are not limited to, the specific type of the integral signal (e.g., ACE-BOC type I signal, ACE-BOC type II signal, or ACE-BOC type III signal), the power ratio of the integral signal, the implementation of the integral signal, etc. In adder 244, EL i The values ​​can be summed up to generate an EL signal.

[0114] The P signal and / or EL signal are available through the code tracking loop 253 and the carrier tracking loop 254, as described above with reference to Figure 2A.

[0115] Figure 6B is a schematic block diagram of an integral signal processing unit 200E, which can process an integral signal by sequentially generating multiple complex-rotated samples for a single sample of the integral signal, according to one or more embodiments described herein. Figure 6B is similar to Figure 6A, except that the integral signal processing unit 200E does not include bin 220. Thus, as shown in Figure 6B, multiple complex-rotated samples (e.g., advanced complex-rotated sample, time-stabilized complex-rotated sample, and delayed complex-rotated sample) generated sequentially for a sample 201 are fed into both weighted bins 630A and 630B to track the integral signal as described above. The integral signal processing unit 200E in Figure 6B does not include bin 220, but the weighted bins 630A and 630B can be used to sequentially formulate multiple complex-rotated sample vectors (e.g., delayed complex-rotated sample, time-stabilized complex-rotated sample, and delayed complex-rotated sample) to generate the P-accumulated signal and EL-accumulated signal as described above with reference to Figure 6A. The P-cumulative signal and EL-cumulative signal are supplied to the tracking module 252 to track the integrated signal. Error The tracking module 252 can calculate and / or utilize the timed signal to generate a new estimate of the carrier Doppler frequency 209, as described above with reference to Figure 2A.

[0116] Figure 6C is a schematic block diagram of an integral signal processing unit 200F that can process an integral signal by sequentially generating multiple complex-rotated samples 615 for a single sample of the integral signal, according to one or more embodiments described herein. Figure 6C is similar to Figure 6A, except that the integral signal processing unit 200F does not include weighted bins 630A and 630B and adders 242 and 244. Thus, the integral signal processing unit 200F in Figure 6C can sequentially generate and accumulate a leading complex-rotated sample, a time-stabilized complex-rotated sample, and a lagging complex-rotated sample 615 for a single sample 201 within a selected bin 220 and / or a selected group of bins 220. The bins 220 can be used to generate correlation values ​​that may be required to implement one or more correlation techniques, and / or one or more multipath relaxation techniques, and / or carrier Doppler frequency estimation techniques.

[0117] Figure 8 is an exemplary flowchart for processing an integral signal by sequentially generating multiple complex-rotated samples for a single sample of the integral signal, according to one or more embodiments described herein. Procedure 800 begins in step 805 and proceeds to step 810, in which the integral signal is received by a GNSS antenna. In one embodiment, the integral signal may be based on ACE-BOC multiplexing and may have multiple signal components with arbitrary power assignments.

[0118] The procedure proceeds to step 815, where multiple local codes (PRN codes) are generated for sample 201 of the integrated signal, and these local codes correspond to the codes in the received integrated signal. In one implementation, these local codes may be advanced versions of the codes in the integrated signal, timed versions of the codes in the integrated signal, and delayed versions of the codes in the integrated signal.

[0119] The procedure proceeds to step 820, where one of several local codes is supplied to the shift / phase lookup table. For example, referring to Figure 6A, counter 601 generates a counter value of 0, and this counter value of 0 can be used to supply the shift / phase lookup table 206 with an advanced version of the code for sample 201.

[0120] The procedure proceeds to step 825, where a phase rotation value and a code shift value are selected based on the supplied local code, as described above with reference to Figures 6A, 7A, and 7B. The procedure proceeds to step 830, where a complex-rotated sample is generated using the selected phase rotation value and the carrier phase value estimated by the carrier phase NCO208. For example, a forward complex-rotated sample can be generated using a phase rotation value selected based on a forward version of the code, as described above with reference to Figures 6A, 7A, and 7B.

[0121] The procedure proceeds to step 835, where a code phase value is generated based on the selected code shift value by temporally offsetting the code shift value selected based on the value of the counter so that the window spans any width less than or equal to the number of code chips in the PRN code sequence. For example, the window can span at least 1.5 code chips (e.g., 3 code chips or 10 code chips). For example, a code shift value selected based on an advanced version of a code should not be temporally offset, since the counter has a value of 0. Therefore, the selected code shift value can be added to the code phase subchip value to generate an advanced code phase value. However, as described above with reference to Figures 6A, 7A, and 7B, a code shift value selected based on a delayed version of a code can be temporally offset by the equivalent of 2 PRN chips of code phase, since the counter has a value of 2. Therefore, "10" is combined as the two most significant bits of the code phase subchip value, and this combined value is added to the selected code shift value to generate a delayed code phase value.

[0122] The procedure proceeds to step 840, where a bin enable output 616 is generated based on the code phase value. For example, as described above with reference to Figures 6A, 7A, and 7B, the leading code phase value can be used to determine the leading bin enable output 616.

[0123] The procedure proceeds to step 845, where the complex-rotated sample 615 is accumulated for a single sample using the bin enable output 616 for any arbitrary width window less than or equal to the number of code chips in the PRN code sequence. For example, the window can span at least 1.5 code chips (e.g., 3 or 10 code chips). For example, the complex-rotated sample 615 can be accumulated in one of several bins 220 spanning at least 1.5 code chips (e.g., 3 or 10 code chips) using the bin enable output 616. Additionally or alternatively, the complex-rotated sample can be accumulated for a window spanning at least 1.5 code chips (e.g., 3 code chips) using weighted bins 630A and 630B, utilizing the bin enable output 616. Weighted bins 630A and 630B are available for accumulating the signal for some predetermined period of time, and are then available to track both the code and carrier of the integrated signal, which feeds the corrected signal to the code rate 205 and carrier Doppler frequency 209.

[0124] The procedure proceeds to step 850, where it is determined whether the counter has reached its limit. If the counter has not reached its limit, the counter is incremented in step 855, and then the procedure returns to 820, which allows the integrating signal processing unit (e.g., 200D-F) to sequentially generate multiple complex-rotated samples 615 for sample 201. For example, the procedure can return to step 820 to generate and accumulate a time-shifted complex-rotated sample based on the code shift and phase rotation values ​​selected based on the time-shifted version of the code described above. Then, the procedure can return to step 820 again to generate and accumulate a delayed complex-rotated sample based on the code shift and phase rotation values ​​selected based on the delayed version of the code described above. Thus, for any arbitrary width less than or equal to the number of code chips in the PRN code sequence, for example, a window spanning at least 1.5 code chips (3 code chips or 10 code chips), a forward complex-rotated sample, a time-shifted complex-rotated sample, and a delayed complex-rotated sample are sequentially generated and accumulated for a single sample 201.

[0125] If the counter reaches its limit in step 850, the counter can be reset in step 860, and the procedure can return to step 810, thereby sequentially generating and accumulating multiple complex-rotated samples (e.g., advanced complex-rotated samples, timed complex-rotated samples, and delayed complex-rotated samples) for the next sample 201.

[0126] Advantageously, the GNSS receiver 120 can generate correlation values ​​that may be required to implement one or more correlation techniques, and / or one or more multipath relaxation techniques, and / or carrier Doppler frequency estimation techniques, using complex-rotated samples 615 sequentially generated and accumulated within selected bins 220 and / or selected groups of bins 220. Additionally or alternatively, correlation values ​​can be generated using weighted bins 630A and 630B, and these correlation values ​​can be used to track the integrated signal.

[0127] The above-mentioned descriptions of each embodiment are intended to provide examples and explanations, but are not intended to be exhaustive or to limit this disclosure to the exact form disclosed. Modifications and variations are possible in light of the above teachings or obtainable from the practice of this disclosure. For example, while a series of actions have been described above in relation to a flowchart, the order of these actions may be changed in other implementations. Furthermore, actions, behaviors, and steps may be performed by additional or other modules or entities, and these additional or other modules or entities may be combined or separated to form other modules or entities. Furthermore, multiple undependent actions may be performed in parallel. Furthermore, a particular embodiment described herein may be implemented as logic that performs one or more functions. This logic may be hardware-based, software-based, or a combination of hardware-based and software-based. Some or all of the logic may be stored in one or more tangible non-temporary computer-readable storage media, and this logic may include computer-executable instructions that can be executed by a computer. Computer-executable instructions may include instructions that perform one or more embodiments described herein. Tangible, non-temporary, computer-readable storage media may be volatile or non-volatile and may include, for example, flash memory, dynamic memory, removable disks, and non-removable disks. It should be understood, in particular, that the above description is intended to be interpreted as merely an example.

Claims

1. 1. A navigation receiver comprising: For an integrated signal having a plurality of signal components with an arbitrary power allocation among the plurality of signal components, the navigation receiver includes an integrated signal processing unit implemented by a processor; The integral signal processing unit includes: generating at least one local code for samples of the integrated signal; selecting a phase rotation value and a code shift value for each local code of the at least one local code; generating one or more complex rotated samples for the samples based on the phase rotation values; determining one or more time slots of a plurality of time slots for a window spanning at least a portion of a pseudorandom noise (PRN) period based on the code shift value; 4. A navigation receiver comprising:

2. The integral signal processing unit includes: Utilizing the code shift value to enable one or more bins of a plurality of bins spanning the portion of the PRN period. It is further structured as follows: The accumulated complex rotated samples within the plurality of bins are utilized by the GNSS receiver to implement at least one of: (1) one or more correlation techniques; (2) one or more multipath mitigation techniques; and (3) one or more carrier Doppler frequency estimation techniques.

2. The navigation receiver of claim 1.

3. The integral signal processing unit includes: Utilizing one or more weighting vectors along with at least the one or more complex rotated samples to generate at least one of an on-time signal and an early minus late signal. It is further structured as follows: the on-time signal and the lead-minus-lag signal are utilized to track the integral signal; 2. The navigation receiver of claim 1.

4. 2. The navigation receiver of claim 1, wherein the integrated signal is based on Asymmetric Constant Envelope Binary Offset Carrier (ACE-BOC) multiplexing.

5. 2. The navigation receiver of claim 1, wherein the at least one local code corresponds to one or more of: (1) an early version of a code in the integrated signal; (2) an on-time version of a code in the integrated signal; and (3) a late version of a code in the integrated signal.

6. the at least one local code is a single local code; the one or more complex rotated samples include an early complex rotated sample and a late complex rotated sample generated in parallel.

2. The navigation receiver of claim 1.

7. the at least one local code includes three local codes; the one or more complex rotated samples include a sequentially generated early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample.

2. The navigation receiver of claim 1.

8. 1. A method for processing an integrated signal received at an antenna, comprising the steps of: the integrated signal has a plurality of signal components having arbitrary power allocations; The method comprises: generating at least one local code for samples of the integrated signal; selecting a phase rotation value and a code shift value for each local code of the at least one local code; generating one or more complex rotated samples for the samples based on the phase rotation values; determining one or more time slots of a plurality of time slots for a window spanning at least a portion of a pseudorandom noise (PRN) period based on the code shift value; A method comprising:

9. The method comprises: utilizing the code shift value to enable one or more bins of a plurality of bins spanning the portion of the PRN period; Further comprising: the accumulated complex rotated samples within the plurality of bins are utilized by a navigation receiver to implement at least one of: (1) one or more correlation techniques; (2) one or more multipath mitigation techniques; and (3) one or more carrier Doppler frequency estimation techniques. The method of claim 8.

10. The method comprises: utilizing one or more weighting vectors in conjunction with at least the one or more complex rotated samples to generate at least one of an on-time signal and an early-minus-late signal. Further comprising: the on-time signal and the lead-minus-lag signal are utilized to track the integral signal; The method of claim 8.

11. 9. The method of claim 8, wherein the integrated signal is based on Asymmetric Constant Envelope Binary Offset Carrier (ACE-BOC) multiplexing.

12. 9. The method of claim 8, wherein the at least one local code corresponds to one or more of: (1) an early version of a code in the integrated signal; (2) an on-time version of a code in the integrated signal; and (3) a late version of a code in the integrated signal.

13. the at least one local code is a single local code; the one or more complex rotated samples include an early complex rotated sample and a late complex rotated sample generated in parallel. The method of claim 8.

14. the at least one local code includes three local codes; the one or more complex rotated samples include a sequentially generated early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample. The method of claim 8.

15. 9. The method of claim 8, wherein a number of the one or more complex rotated samples generated for the sample is equal to N, where N is less than or equal to a number of PRN code chips.

16. 1. A navigation receiver comprising: For an integrated signal having a plurality of signal components with an arbitrary power allocation among the plurality of signal components, the navigation receiver includes an integrated signal processing unit implemented by a processor; The integral signal processing unit includes: generating at least one local code for samples of the integrated signal; selecting a phase rotation value and a code shift value for each local code of the at least one local code; generating one or more complex rotated samples for the samples based on the phase rotation values; accumulating the one or more complex rotated samples into one or more of a plurality of bins over a window of any arbitrary width less than or equal to the number of code chips in a pseudorandom noise (PRN) code sequence.

4. A navigation receiver comprising:

17. 17. The navigation receiver of claim 16, wherein the integrated signal is based on Asymmetric Constant Envelope Binary Offset Carrier (ACE-BOC) multiplexing.

18. 17. The navigation receiver of claim 16, wherein the accumulated complex rotated samples accumulated in the plurality of bins are utilized by the navigation receiver to implement at least one of: (1) one or more correlation techniques, (2) one or more multipath mitigation techniques, and (3) one or more carrier Doppler frequency estimation techniques.

19. The navigation receiver of claim 16 , wherein the accumulated complex rotated samples accumulated in the plurality of bins are utilized by the GNSS receiver to track the integrated signal.

20. the at least one local code is a single local code, and the one or more complex rotated samples include early complex rotated samples and late complex rotated samples generated in parallel; or or the at least one local code includes three local codes, and the one or more complex rotated samples include a sequentially generated early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample.

17. The navigation receiver of claim 16.

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