Manufacturing method for piezoelectric element array substrate, piezoelectric element array substrate, and polarization device

Abstract

To manufacture a piezoelectric element array substrate suitably.SOLUTION: In a manufacturing method for a piezoelectric element array substrate, a plurality of piezoelectric element control circuits including one or more thin film transistors is formed on a substrate. In the manufacturing method, a plurality of piezoelectric elements is formed on the substrate. In the manufacturing method, after the piezoelectric elements and the piezoelectric element control circuits are formed, while the one or more thin film transistors are kept with the leak current increased, an electric field is applied to piezoelectric material layers of the piezoelectric elements to polarize a piezoelectric material.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a piezoelectric element array substrate, a piezoelectric element array substrate, and a polarization device.

Background Art

[0002]

[0003] [[ID=]]

[0004]

[0005] ​​​​​​​​​​The manufacturing of piezoelectric elements involves a process of polarization, where a piezoelectric material is polarized by applying an electric field higher than the coercive field. Specifically, a high electric field of approximately 100V / μm (actual voltage 1000V) is usually required to exhibit piezoelectric properties. On the other hand, in ultrasonic sensors and the like that drive and control piezoelectric element arrays using TFT arrays, TFTs are connected to the piezoelectric elements. For reading and detecting signals from piezoelectric elements, the OFF current of these TFTs must be small. However, if the leakage current of the TFTs is small, the voltage applied to the TFTs becomes high during the polarization process, making them prone to damage during the polarization process. [Means for solving the problem]

[0006] One aspect of the present disclosure is a method for manufacturing a piezoelectric element array substrate, comprising: forming a plurality of piezoelectric element control circuits, each including one or more thin-film transistors, on the substrate; forming a plurality of piezoelectric elements on the substrate; and, after forming the plurality of piezoelectric elements and the plurality of piezoelectric element control circuits, maintaining the one or more thin-film transistors in a state of increased leakage current, and applying an electric field to the piezoelectric material layers of the plurality of piezoelectric elements to polarize the piezoelectric material.

[0007] One aspect of the present disclosure is a piezoelectric element array substrate comprising a substrate, a piezoelectric element array on the substrate including a plurality of piezoelectric elements, and a thin-film transistor array on the substrate for controlling the plurality of piezoelectric elements, wherein the thin-film transistor array includes a plurality of piezoelectric element control circuits for controlling each of the plurality of piezoelectric elements, and the leakage current of each of the one or more thin-film transistors at 80°C is 0.1A or more per unit area of ​​the piezoelectric element.

[0008] One aspect of the present disclosure is a polarization device for polarization of a piezoelectric material of a piezoelectric element array substrate, wherein the piezoelectric element array substrate includes an insulating substrate, a plurality of piezoelectric element control circuits on the insulating substrate, each including one or more thin-film transistors, and a plurality of piezoelectric elements on the insulating substrate, each including a piezoelectric material layer. The polarization device includes a plasma discharge device, a piezoelectric element array light-transmitting stage that supports the piezoelectric element array substrate from the insulating substrate side, a heating device for heating the piezoelectric element array substrate, and a light source system that irradiates the piezoelectric element array substrate with light from the back side of the light-transmitting stage. The plasma discharge device polarizes the piezoelectric material layers of the plurality of piezoelectric elements by charging the piezoelectric element array while the piezoelectric element array substrate is irradiated with the light and heated. [Effects of the Invention]

[0009] According to one aspect of this disclosure, a piezoelectric element array substrate can be suitably manufactured. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram showing the configuration of the ultrasonic sensor according to the embodiment. [Figure 2] This is a circuit diagram showing the circuit configuration of the pixels of a piezoelectric element array substrate according to the embodiment. [Figure 3] This is a timing chart showing the operation of the ultrasonic sensor of this disclosure for emitting ultrasonic waves and for receiving reflected ultrasonic waves. [Figure 4] A schematic diagram of a cross-sectional structure of an ultrasonic sensor is shown. [Figure 5] A flowchart illustrating an example of an ultrasonic sensor manufacturing method is shown. [Figure 6] The configuration of the pixel circuit in polarization processing is schematically shown. [Figure 7] This shows the relationship between gate voltage and drain current at different temperatures for a P-channel thin-film transistor. [Figure 8] The measurement results of the hysteresis curves (DE hysteresis curves) of the applied electric field E and charge density D to a piezoelectric element at different temperatures are shown. [Figure 9] This shows the relationship between the coercive field Ec of a piezoelectric element and temperature, and the relationship between the residual polarization Pr and temperature. [Figure 10] A schematic diagram illustrates the polarization process under light irradiation. [Figure 11] This shows the relationship between the OFF current of a thin-film transistor on a piezoelectric element array substrate and its breakdown field. [Figure 12] A schematic example of the configuration of a device that performs polarization processing under light irradiation is shown. [Modes for carrying out the invention]

[0011] The image sensor of this disclosure will be described in detail below with reference to the drawings. The size and scale of each component in each drawing have been appropriately modified to ensure the visibility of the figures. In addition, the hatching in each drawing is for distinguishing each component and does not necessarily represent a cross-section. Furthermore, the term "transistor" is used for nonlinear elements used as switching elements or amplifying elements, and this term includes Thin Film Transistors (TFTs).

[0012] The piezoelectric element array substrate of this disclosure can be used, for example, in ultrasonic sensors used in medical or industrial inspection fields, or in ultrasonic sensors for detecting fingerprints or objects. It can also be applied to sound wave generators that can be used in a variety of applications. Currently, ultrasonic sensors in practical use are composed of multiple isolated piezoelectric elements arranged in a grid, but the practical application of active matrix ultrasonic sensors driven by arrays of thin-film transistors is beginning in order to create thin, high-resolution ultrasonic sensors.

[0013] The manufacturing of piezoelectric elements includes a process of polarizing the material by applying an electric field higher than the coercive field to the piezoelectric material. Specifically, in order to generally exhibit piezoelectric performance, a high electric field of about 100 V / μm (actual voltage 1000 V) is required. On the other hand, in a piezoelectric element array substrate that drives and controls a piezoelectric element array by a TFT array, a thin film transistor is connected to the piezoelectric element. In order to read and detect a signal from the piezoelectric element, it is required that the OFF current of these thin film transistors is small. However, if the leakage current of the thin film transistor is small, the voltage applied to the thin film transistor during the polarization process becomes high and it is likely to be damaged.

[0014] One embodiment of this specification configures or manufactures a piezoelectric element array substrate so that a thin film transistor has a desired leakage current in the polarization process of the piezoelectric element. Thereby, the possibility of damage to the thin film transistor in the manufacture of the piezoelectric element array substrate can be greatly reduced.

[0015] [Device Configuration] FIG. 1 is a block diagram showing a configuration example of an ultrasonic sensor according to Embodiment 1. The ultrasonic sensor 10 of the present disclosure includes a piezoelectric element array substrate 11 and a control circuit. The control circuit includes a multiplexer circuit 15, a drive circuit 14, a signal detection circuit 16, and a main control circuit 18.

[0016] The piezoelectric element array substrate 11 includes an insulating substrate (for example, a glass substrate) and a pixel region 12 in which pixels 13 are arranged in a vertical and horizontal matrix on the insulating substrate. The multiplexer circuit 15 is formed on the insulating substrate of the piezoelectric element array substrate 11, is connected to each signal line of the pixel columns arranged in the vertical direction in FIG. 1, and reduces the number of signal lines by time-division conversion in the multiplexer circuit, and then performs detection in the signal detection circuit.

[0017] The drive circuit 14 drives and controls the pixels 13 for the generation and detection of ultrasonic waves by the pixels 13. The multiplexer circuit 15 receives ultrasonic detection signals from the pixels 13 transmitted by the signal lines and outputs them to the signal detection circuit 16. The signal detection circuit 16 detects the signals from each signal line that have been converted into a time series by the multiplexer circuit. The main control circuit 18 controls the drive circuit 14, the multiplexer circuit 15, and the signal detection circuit 16. The drive circuit 14, the signal detection circuit 16, and the main control circuit 18 may be mounted on the piezoelectric element array substrate 11, or as separate components from the piezoelectric element array substrate 11.

[0018] [Pixel circuit] Figure 2 is a circuit diagram showing the configuration of a single pixel 13 and its pixel circuit (piezoelectric element control circuit). Pixel 13 is a piezoelectric element PE. This piezoelectric element PE has both ultrasonic oscillation and reception functions. The upper electrode of the piezoelectric element PE is indicated by the code TX. A voltage VRX is induced in the piezoelectric element PE in response to the received reflected ultrasonic vibration. One pixel circuit of the ultrasonic sensor 10 of this disclosure includes three thin-film transistors TR1, TR2, TR3 and a diode D1. The semiconductor material of the thin-film transistors is, for example, low-temperature polysilicon, oxide semiconductor, or amorphous silicon.

[0019] The cathode terminal of diode D1 is connected to node N1, which is located between the gate terminal of transistor TR1 and the source / drain terminals of transistor TR3. The anode terminal is connected to the diode bias line PA. One of the source / drain terminals of transistor TR1 is connected to the power line PP, and the other source / drain terminal is connected to one of the source / drain terminals of transistor TR2.

[0020] The gate terminal of transistor TR2 is connected to the control line Gn. The source / drain terminals of transistor TR2 are connected to the signal line Dm. The gate terminal of transistor TR3 is connected to the control line Rn. The source / drain terminals of transistor TR3 are connected to the anode and cathode terminals of diode D1.

[0021] Transistor TR1 (amplifying transistor) amplifies the potential at one end of the piezoelectric element PE. Transistor TR2 is a switching element that controls the output from the pixel circuit. Transistor TR3 is a switching element that resets the potential at one end of the piezoelectric element PE and the gate electrode of transistor TR1.

[0022] In the ultrasonic sensor 10 shown in Figure 1, there is one signal line Dm for each pixel row, which consists of multiple pixels 13 arranged vertically. All pixels 13 in the same pixel row are connected to the signal line Dm. This signal line Dm is connected to a multiplexer circuit 15 at the end of the piezoelectric element array substrate 11.

[0023] Figure 3 is a timing chart showing the operation of the ultrasonic sensor 10 of this disclosure for emitting ultrasonic waves and receiving reflected ultrasonic waves. The period from time T1 to time T2 is the ultrasonic wave emission period.

[0024] At time T1, the drive circuit 14 changes the potential of the control line Rn from a low level to a high level. This turns on the transistor TR3. The drive circuit 14 maintains the potential of the diode bias line PA at a low level. As a result, the potential of the lower electrode of the piezoelectric element PE is fixed. After transistor TR3 is turned ON, the drive circuit 14 applies an excitation signal to the upper electrode TX of the piezoelectric element PE. This causes all piezoelectric elements PE to vibrate and ultrasonic waves to be emitted. Subsequently, the drive circuit 14 stops the signal to the upper electrode TX.

[0025] After stopping the signal to the upper electrode TX, at time T2, the drive circuit 14 changes the potential of the control line Rn from a high level to a low level. This turns off transistor TR3.

[0026] From time T2, the piezoelectric element PE receives reflected ultrasonic waves. Since TR3 is in the OFF state, the lower electrode becomes floating, and an induced voltage VRX is generated at the lower electrode due to the reception of ultrasonic waves. In Figure 3, when the piezoelectric element PE is not receiving ultrasonic waves, the induced voltage VRX is 0, and when it is receiving ultrasonic waves, the induced voltage VRX is greater than 0.

[0027] At time T2, the drive circuit 14 changes the potential of the diode bias line PA from a low level to a high level. The diode bias adjusts the induced potential VRX to the optimal bias voltage that transistor TR1 outputs to the signal line Dm.

[0028] At time T2, the drive circuit 14 changes the potential of the control line Gn from a low level to a high level. As a result, transistor TR2 turns ON, and transistor TR1 amplifies the induced potential VRX and outputs it to the signal line Dm.

[0029] At time T3, the drive circuit 14 changes the potential of the control line Gn from a high level to a low level. This turns off the transistor TR2, and the reading of the induced voltage VRX is completed. This timing chart describes the operation of only one pixel, but if there are multiple pixels, multiple control lines Rn and Gn and multiple signal lines Dm are used to read the Vrx of each pixel.

[0030] [Element structure] Figure 4 schematically shows a part of the cross-sectional structure of the ultrasonic sensor 10. In the following description, "up" and "down" refer to the top and bottom in the drawing. The ultrasonic sensor 10 includes an insulating substrate 151 and a medium 200 facing the insulating substrate 151. The medium 200 is, for example, a flexible or impermeable insulating substrate made of resin or glass. In addition to a uniform insulator, a thin display substrate that does not affect ultrasound can also be used. Ultrasonic waves emitted from the ultrasonic sensor 10 are reflected by the surface of the medium 200 that faces the ultrasonic sensor and return to the ultrasonic sensor 10. If, for example, human skin is present on the surface of the medium 200, the reflectivity of the ultrasound changes. The presence or absence of skin can be sensed by the strength of the reflected ultrasound.

[0031] The ultrasonic sensor 10 includes a plurality of lower electrodes 162, a single upper electrode 166, and a piezoelectric material layer 165 on an insulating substrate 151. The piezoelectric material may be organic or inorganic, and for example, polyvinylidene fluoride (PVDF) or lead zirconate titanate (PZT) can be used.

[0032] One lower electrode 162, a portion of the upper electrode 166, and a portion of the piezoelectric material layer 165 constitute one piezoelectric element (also called a pixel). The upper electrode and piezoelectric material layer may be separated for each piezoelectric element. One piezoelectric material layer 165 is placed between the upper electrode 166 and the lower electrode 162. Multiple lower electrodes 162 are arranged on the surface of the planarized film 161, and the piezoelectric material layer 165 is placed on top of the lower electrodes 162.

[0033] The ultrasonic sensor 10 includes multiple circuits, each containing multiple switches. Each of these circuits drives and controls a piezoelectric element and is also called a pixel circuit. The pixel circuit is formed between the insulating substrate 151 and the lower electrode 162 and controls the potential supplied to each of the multiple lower electrodes 162. In the configuration example shown in Figure 2, a common upper electrode 166 for the multiple piezoelectric elements is placed on the side that emits ultrasonic waves and receives reflected waves (upper side of the drawing). The upper electrode 166 has a shape that completely covers the entire surface of the pixel area 12. Note that the stacking positional relationship between the piezoelectric elements and the circuits may be reversed.

[0034] Figure 4 shows transistor TR3 and the gate electrode 157B of transistor TR1 in the pixel circuit. The insulating substrate 151 is made of, for example, glass or resin, and is an inflexible or flexible substrate. In the following description, the side closer to the insulating substrate 151 will be referred to as the lower side, and the side further away will be referred to as the upper side. An insulating underlayment layer 152 of the insulator is formed on the insulating substrate 151, and a semiconductor active layer 155 is laminated thereon. The semiconductor active layer 155 includes a low-resistance source / drain region and a high-resistance channel region between them.

[0035] The semiconductor active layer 155 is covered by a gate insulating layer 156. A gate electrode is formed on the semiconductor active layer 155 via the gate insulating layer 156. Figure 4 shows the gate electrode 157A of transistor TR3 and the gate electrode 157B of transistor TR1. An interlayer insulating film 158 is formed on the layers of gate electrodes 157A and 157B.

[0036] Within the pixel region 12, source / drain electrodes 159 and 160 are formed on the interlayer insulating film 158. The source / drain electrodes 159 and 160 are formed of, for example, an Al-based alloy. The source / drain electrodes 159 and 160 are connected to the semiconductor active layer 155 by contact portions 168 and 169 formed in the contact holes of the interlayer insulating film 158.

[0037] The wiring portion 171 extends from the source / drain electrodes 160 of transistor TR3 and is connected to the gate electrode 157B of transistor TR1 by a contact portion 172 formed in the contact hole of the interlayer insulating film 158. The wiring portion 171 and the source / drain electrodes 160 are contained in the same metal layer and are continuous.

[0038] An insulating planarization film 161 is formed on the source / drain electrodes 159, 160 and the wiring portion 171. A lower electrode 162 is formed on the insulating planarization film 161. The lower electrode 162 is connected to the source / drain electrodes 160 by contact portions formed in the contact holes of the planarization film 161. The pixel circuit is formed on the underside of the lower electrode 162.

[0039] A piezoelectric material layer 165 is formed on the lower electrode 162. The piezoelectric material layer 165 is in contact with the upper surface of the lower electrode 162 and the upper surface of the planarized film. An upper electrode 166 is formed on and in contact with the piezoelectric material layer 165. The laminated film of the lower electrode 162, a portion of the piezoelectric material layer 165, and a portion of the upper electrode 166 constitutes a piezoelectric element.

[0040] [Manufacturing method] An example of a manufacturing method for the ultrasonic sensor 10 is described below. In the following description, elements formed in the same process (simultaneously) are elements of the same layer. Figure 5 shows a flowchart of an example of a manufacturing method for the ultrasonic sensor 10.

[0041] The manufacturing of the ultrasonic sensor 10 begins with forming a TFT array on an insulating substrate 151 (S11). This will be explained in detail. The manufacturing process begins by depositing, for example, silicon nitride or silicon oxide onto the insulating substrate 151 using CVD (Chemical Vapor Deposition) or the like to form an underlying insulating layer 152.

[0042] Next, a layer containing the semiconductor active layer 155 (polysilicon layer) is formed using known low-temperature polysilicon TFT manufacturing techniques. For example, amorphous silicon can be deposited by CVD and crystallized by ELA (Excimer Laser Annealing) to form a polysilicon layer.

[0043] Next, a gate insulating layer 156 is formed on the polysilicon layer containing the semiconductor active layer 155 by depositing, for example, a silicon oxide film using a CVD method. Furthermore, a metal layer containing gate electrodes 157A and 15B is formed by depositing a metal material using a sputtering method or the like and performing patterning.

[0044] The metal layer may include wiring in addition to the gate electrode 157. The metal layer may be formed as a single layer of one material selected from the group consisting of, for example, Mo, W, Nb, MoW, MoNb, Al, Nd, Ti, Cu, Cu alloy, Al alloy, Ag, and Ag alloy, or it may be a single laminate selected from the group consisting of a two-layer structure or more multi-layer structure of low-resistance materials such as Mo, Cu, Al, or Ag to reduce wiring resistance.

[0045] Next, in order to form an N-type TFT, a low-concentration impurity layer is formed in the TFT by doping the semiconductor active layer 155, which has been doped with a high concentration of N-type impurities before the formation of the gate electrodes 157A and 157B, with additional impurity doping using the gate electrode 157A as a mask, thereby forming an LDD (Lightly Doped Drain) structure. Next, in order to form a P-type TFT, a source-drain structure is formed by doping the area other than the area where the N-type TFT was created with P-type impurities, using the gate electrode 157A as a mask. Then, an interlayer insulating film 158 is formed by depositing, for example, a silicon oxide film, using a CVD method or the like.

[0046] Anisotropic etching is performed on the interlayer insulating film 158 and the gate insulating layer 156 to open contact holes. Contact holes for contact portions 168, 169 connecting the source / drain electrodes 159, 160 to the semiconductor active layer 155, and for contact portion 172 connecting the wiring portion 171 to the gate electrode 157B, etc., are formed in the interlayer insulating film 158 and the gate insulating layer 156.

[0047] Next, an aluminum alloy such as Ti / Al / Ti is deposited by sputtering or the like, and then patterned to form a metal layer. The metal layer includes source / drain electrodes 159, electrode 160, wiring section 171, and contact sections 168, 169, and 172. Other wiring is also formed.

[0048] Next, a photosensitive organic material is deposited to form a planarization film 161. Contact holes are opened for connection to the source / drain electrodes 160 of the TFT. A lower electrode 162 is formed on the planarization film 161 with the contact holes. The lower electrode 162 may be a single layer or multilayer made of, for example, ITO, IZO, ZnO, Ag, Mg, Al, Pt, etc. The lower electrode 162 is connected to the source / drain electrodes 160 via a contact portion.

[0049] Once the TFT array is formed as described above, the manufacturing method then proceeds to perform piezoelectric element formation steps S12 to S14. Specifically, the manufacturing method forms a thick piezoelectric material layer (S12). The thick piezoelectric material layer is formed by depositing PVDF using methods such as spin coating, printing, or inkjet printing to create the piezoelectric material layer 165. Note that a piezoelectric material different from PVDF may be deposited using a method suitable for that material.

[0050] Next, the manufacturing method involves forming an upper electrode on the piezoelectric material layer 165 (S13). The formation of the upper electrode involves depositing a metallic material for the upper electrode 166 onto the piezoelectric material layer 165. The layer of the upper electrode 166 is formed, for example, by Al and / or Ag, using sputtering, vapor deposition, printing, or inkjet printing. The piezoelectric material layer 165 and the upper electrode 166 cover the entire surface of the pixel region 12, for example, to the extent that they do not affect wiring outside the pixel region 12.

[0051] Next, the manufacturing method involves performing a polarization treatment on the piezoelectric material layer 165 formed on the substrate (S14). Polarization treatment S14 involves applying a high voltage to the piezoelectric material layer 165 to polarize it in order to bring out the high-voltage properties of the piezoelectric material layer 165. In order to bring out the desired piezoelectric performance, a high electric field (high voltage) of about 100V / μm (actual voltage of about 1000V) is applied.

[0052] Figure 6 schematically shows the configuration of the pixel circuit in the polarization process. All lines of the thin-film transistor array (pixel circuit array) are connected by a common line 31 and grounded. Specifically, the power line PP, control lines Rn and Gn, diode bias line PA, and signal line Dm are grounded. In the polarization process, a high voltage is applied to the upper electrode TX with the wiring of the thin-film transistor array grounded, thereby polarizing the piezoelectric material layer 165.

[0053] Generally, piezoelectric element array substrates are manufactured by forming multiple piezoelectric element array substrates, including pixel arrays and thin-film transistor arrays, on a single motherboard, and then cutting out each of the multiple piezoelectric element array substrates. Polarization is performed by connecting and grounding the wiring of all thin-film transistor arrays on the motherboard.

[0054] As described above, a thin-film transistor array is connected to the piezoelectric element. When a high voltage is applied to the piezoelectric material layer 165, conditions must be met to prevent the thin-film transistors in the thin-film transistor array from being destroyed.

[0055] For reading and detecting signals from piezoelectric elements, it is desirable that the OFF current (leakage current) of the thin-film transistors in the pixel circuit be small. However, a small OFF current for thin-film transistors presents a problem: the voltage applied to the thin-film transistors becomes high during polarization, making them prone to damage.

[0056] One embodiment of this specification involves applying a high voltage to a piezoelectric material layer during polarization treatment under conditions that increase the OFF current of the thin-film transistor. This significantly reduces the possibility of damage to the thin-film transistor during polarization treatment. Methods for increasing the OFF current of the thin-film transistor include, for example, heating or light irradiation.

[0057] Heating a thin-film transistor to a temperature higher than room temperature increases the OFF current, reducing the possibility of damage when applying high voltage for polarization. Figure 7 shows the relationship between gate voltage and drain current at different temperatures for a P-channel thin-film transistor. The horizontal axis represents the gate voltage, and the vertical axis represents the drain current. The drain current of a P-channel thin-film transistor increases as the gate voltage decreases. The drain current at a gate voltage greater than 0 represents the OFF current.

[0058] For ease of explanation, some of the temperature lines in the graph of Figure 7 are indicated by signs. Line 411 shows the relationship between gate voltage and drain current at -40°C. Line 412 shows the relationship between gate voltage and drain current at 0°C. Line 413 shows the relationship between gate voltage and drain current at 20°C. Line 414 shows the relationship between gate voltage and drain current at 50°C. Line 415 shows the relationship between gate voltage and drain current at 80°C. As shown in Figure 7, the OFF current increases with increasing temperature of the thin-film transistor.

[0059] Furthermore, heating can lower the voltage (electric field) required for polarization of the piezoelectric material. As the temperature rises, the molecules of the piezoelectric material become more mobile, thus reducing the voltage (electric field) required for polarization. Figure 8 shows the measurement results of the hysteresis curve (DE hysteresis curve) of the applied electric field E and charge density D to the piezoelectric element at different temperatures. The piezoelectric material used was PVDF. Similar changes are observed for other materials. Figure 8 shows the DE hysteresis curve at room temperature, 60°C, 70°C, 80°C, 90°C, and 100°C.

[0060] For ease of explanation, the DE hysteresis curves at some temperatures are indicated by signs. In Figure 8, line 431 shows the DE hysteresis curve at room temperature. Line 433 shows the DE hysteresis curve at 60°C. Line 435 shows the DE hysteresis curve at 100°C.

[0061] The polarization initiation field (the field at which polarization reverses), called the coercive field Ec, is a positive external field where the charge density D is 0 in the DE hysteresis curve. The residual polarization Pr after polarization, which indicates piezoelectric performance, can be represented by the charge density at an external field of 0 in the DE hysteresis curve. As shown in Figure 8, the absolute value of the coercive field Ec decreases with increasing temperature. In particular, the coercive field Ec decreases significantly from room temperature to 60°C, and the change in the coercive field Ec is small from 60°C to 100°C.

[0062] Figure 9 shows the relationship between the coercive field Ec and temperature, and the relationship between the remanent polarization Pr and temperature, based on the measurements shown in Figure 8. The horizontal axis represents temperature. The left vertical axis represents the coercive field Ec, and the right vertical axis represents the remanent polarization Pr. Solid line 451 shows the measured value of the temperature change of the coercive field Ec. Solid line 453 shows the measured value of the temperature change of the remanent polarization Pr. Dashed line 454 shows the theoretical value of the temperature change of the remanent polarization Pr. The remanent polarization Pr decreases significantly as it approaches the Curie temperature, and becomes 0 at the Curie temperature.

[0063] As can be understood from the explanation with reference to Figures 7 to 9, it is preferable to perform the polarization treatment at a high temperature in order to increase the OFF current of the thin-film transistor and to assist in the polarization of the piezoelectric material. On the other hand, in order to maintain appropriate residual polarization of the piezoelectric material, it is necessary to perform the polarization treatment at a temperature below a certain temperature.

[0064] According to the inventors' research described above, it is possible to suitably achieve both polarization of the piezoelectric element and prevention of damage to the thin-film transistor within a substrate temperature range of 60°C to 100°C (60°C to 100°C). Therefore, in one embodiment of this specification, polarization treatment of the piezoelectric material layer is performed within the substrate temperature range of 60°C to 100°C. For example, by performing the polarization treatment in a heating chamber, polarization treatment within the desired temperature range is possible. Furthermore, from the viewpoint of preventing damage to the thin-film transistor and from the viewpoint of process margin, polarization treatment of the piezoelectric material layer can be performed within a temperature range of 70°C to 90°C (70°C to 90°C).

[0065] In the polarization process S14, non-contact polarization using plasma discharge may be used as a method for applying a high voltage to the piezoelectric material layer. This method applies an electric field by charging the material with corona discharge instead of directly applying a high voltage to the upper electrode. Since no connection is required to apply the high voltage, it offers excellent productivity. In this method as well, it is desirable that the wiring of the thin-film transistor array be grounded. Furthermore, in this non-contact polarization method using plasma discharge, it is common to perform plasma discharge polarization after PVDF formation and before upper electrode formation.

[0066] As mentioned above, in addition to heating, light irradiation of thin-film transistors is another method for increasing the leakage current of thin-film transistors. In one embodiment of this specification, the polarization treatment is performed while the thin-film transistors of the piezoelectric element array are irradiated with light. This increases the OFF current of the thin-film transistors, thereby reducing the possibility of damage to the thin-film transistors during the polarization treatment.

[0067] Figure 10 schematically shows the polarization process under light irradiation. The polarization process involves irradiating the piezoelectric element array substrate with light 501 from the insulating substrate 151 side. Any wavelength of light that increases the OFF current of the thin-film transistor can be used, but for example, light with wavelengths within the green to blue wavelength range can be used. The insulating substrate 151 transmits the irradiated light. By irradiating with light from the insulating substrate 151 side, any material suitable for the piezoelectric element can be selected for the upper electrode 166.

[0068] The polarization treatment step S14 of the piezoelectric material layer may be performed simultaneously with heating and light irradiation. That is, the polarization treatment step involves heating the piezoelectric element array substrate and irradiating the thin-film transistors with light, while applying a voltage for polarization treatment to the piezoelectric element array substrate. This makes it possible to more effectively avoid damage to the thin-film transistors. In addition, the light intensity or heating temperature can be reduced.

[0069] Thin-film transistors in the pixel circuits of piezoelectric elements are required to have a large OFF current during polarization processing. According to the inventors' research, if the thin-film transistors have predetermined characteristics, the possibility of damage during polarization processing can be greatly reduced.

[0070] Figure 11 shows the relationship between the OFF current and the breakdown field of a thin-film transistor on a piezoelectric element array substrate. As shown by the solid line in the experimental results, the breakdown field increases as the OFF current increases. The breakdown field here can be considered as the electric field applied to the piezoelectric element. For proper polarization of the piezoelectric element, an electric field of 100 MV / m or more is required. Considering the manufacturing margin, an OFF current of 2.5E-11(A) or more can effectively prevent the breakdown of the thin-film transistor. Note that at normal operating temperatures (room temperature: e.g., 25°C), the thin-film transistor has an OFF current of 1.0E-12(A) or less.

[0071] The voltage across the thin-film transistor is the voltage at node N1 in the circuit diagram shown in Figure 2. The voltage at node N1 depends on the charge generated in the piezoelectric element PE and the leakage current of the thin-film transistor. If the area of ​​the piezoelectric element (the lower electrode) is small, the amount of charge generated will be small, and the OFF current required for the thin-film transistor will also be small.

[0072] From the area of ​​the piezoelectric element and the value of the OFF current shown in Figure 11, the following relationship can be derived. The voltage at node N1 is determined by the relative ratio of the amount of charge stored in the capacitance of the PVDF due to the voltage applied for polarization and the amount of charge reduced by the leakage current of the thin-film transistor. Since the capacitance of the PVDF is proportional to the pixel area, the voltage is determined at the point where the leakage current of the thin-film transistor and the area are in a certain ratio. The inventors determined the coefficients from the experimental results and revealed that the following equation holds true. Ioff@80℃≧0.01×S Here, Ioff@80℃ is the OFF current at 80℃, and S is the area of ​​the piezoelectric element (lower electrode or pixel electrode). The unit of the OFF current is A, and the unit of the area is m. 2 That is the case.

[0073] As described in the manufacturing of piezoelectric element array substrates, for example, when polarization treatment is performed in the range of 60°C to 100°C, thin-film transistors with the above characteristics can exhibit a sufficient OFF current to prevent damage during polarization treatment. Furthermore, thin-film transistors that exhibit an OFF current of 0.01 × S(A) or 2.5E-11(A) or more during polarization treatment can more reliably avoid damage.

[0074] Figure 12 schematically shows an example configuration of an apparatus for performing polarization processing under light irradiation. The polarization apparatus includes a light source 601, a heated light-transmitting stage 603, and a discharge apparatus 604. The discharge apparatus 604 includes a discharge electrode 605 connected to a high-voltage power supply 608 and a control grid 607 connected to a high-voltage power supply 609. The polarization apparatus shown in Figure 12 performs non-contact polarization using plasma discharge. This method applies an electric field by charging the upper electrode with corona discharge instead of directly applying a high voltage to it. Since it does not require electrode connections to individual devices, it offers excellent productivity.

[0075] The piezoelectric element array substrate 11 is placed on the heated light-transmitting stage 603 with the insulating substrate 151 facing downwards. In the example shown in Figure 12, the terminals within the piezoelectric element array substrate 11 are grounded. The heated light-transmitting stage 603 heats the piezoelectric element array substrate 11. In other words, the heated light-transmitting stage 603 functions as a heating device that heats the piezoelectric element array substrate 11. For example, the heated light-transmitting stage 603 may include a heater or be heated to a high temperature by infrared radiation before polarization treatment. Alternatively, the chamber may be heated by a heating device instead of the stage.

[0076] The polarization device irradiates the piezoelectric element array substrate 11 with light from the light source 601 from the heated light-transmitting stage 603 side. The light source 601 is positioned directly below the heated light-transmitting stage 603. While the light source 601 does not necessarily need to be positioned directly below the heated light-transmitting stage 603, it should be positioned so that light irradiates the area exposed to plasma discharge. The device may include an optical system (light source system) that irradiates the back side of the heated light-transmitting stage 603 with light from the light source 601.

[0077] The heated light-transmitting stage 603 transmits the irradiated light. The light source can be light with a wavelength between 300 nm and 600 nm that passes through the glass substrate and the transmissive stage and is easily absorbed by the semiconductor active layer. The polarization device heats the piezoelectric element array substrate 11 with the heated light-transmitting stage 603 and irradiates the thin-film transistor with light from the light source 601, and then performs a plasma discharge.

[0078] A discharge occurs between the discharge electrode 605 and the piezoelectric element array substrate 11, and negative ions (charges) accumulate on the surface of the piezoelectric element array substrate 11. This applies an electric field to the piezoelectric material. The control grid 607 can suitably control the charge distribution.

[0079] As described above, the plasma polarization device includes a light-transmitting stage with a heating function that supports an insulating substrate on which a piezoelectric material thin film and a switch element are formed, and light is irradiated from the back surface of the light-transmitting stage. The plasma polarization device applies an electric field by plasma discharge to the piezoelectric element array substrate while it is irradiated with light and heated. This polarizes the piezoelectric material.

[0080] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0081] 10 Ultrasonic sensor, 11 Piezoelectric element array substrate, 12 Pixel area, 13 Pixel, 14 Driving circuit, 15 Multiplexer circuit, 16 Signal detection circuit, 18 Main control circuit, TR1, TR2, TR3 Transistors, D1 Diode, Gn, Rn Control lines, Dm Signal line, PE Piezoelectric element, TX Upper electrode, PA Diode bias line, PP Power line, 151 Insulating substrate, 152 Underlying insulating layer, 155 Semiconductor active layer, 156 Gate insulating layer, 157A, 157B Gate gate, 158 Interlayer insulating film, 159, 160 Source / drain electrodes, 162 Lower electrode, 165 Piezoelectric material layer, 171 Wiring section, 200 Medium

Claims

1. A method for manufacturing a piezoelectric element array substrate, comprising the steps of: forming a plurality of piezoelectric element control circuits, each including one or more thin film transistors, on the substrate; forming a plurality of piezoelectric elements on the substrate; After forming the plurality of piezoelectric elements and the plurality of piezoelectric element control circuits, the one or more thin film transistors are maintained in a state in which a leakage current is increased, and an electric field is applied to the piezoelectric material layers of the plurality of piezoelectric elements to polarize the piezoelectric material. A method for manufacturing a piezoelectric element array substrate.

2. A method for manufacturing a piezoelectric element array substrate according to claim 1, comprising the steps of: maintaining the one or more thin film transistors in a state in which the leakage current increases by heating the piezoelectric element array substrate; A method for manufacturing a piezoelectric element array substrate.

3. A method for manufacturing a piezoelectric element array substrate according to claim 2, comprising the steps of: The piezoelectric element array substrate is maintained at a temperature of 60° C. or higher and 100° C. or lower. A method for manufacturing a piezoelectric element array substrate.

4. A method for manufacturing a piezoelectric element array substrate according to claim 3, comprising the steps of: The piezoelectric element array substrate is maintained at a temperature of 70° C. or higher and 90° C. or lower. A method for manufacturing a piezoelectric element array substrate.

5. A method for manufacturing a piezoelectric element array substrate according to claim 1, comprising the steps of: maintaining the one or more thin film transistors in a state in which the leakage current increases by irradiating the one or more thin film transistors with light; A method for manufacturing a piezoelectric element array substrate.

6. A method for manufacturing a piezoelectric element array substrate according to claim 5, comprising the steps of: Irradiating the one or more thin film transistors with light from the substrate side; A method for manufacturing a piezoelectric element array substrate.

7. A method for manufacturing a piezoelectric element array substrate according to claim 1, comprising the steps of: maintaining the one or more thin film transistors in a state in which the leakage current increases by irradiating the one or more thin film transistors with light and heating the piezoelectric element array substrate; A method for manufacturing a piezoelectric element array substrate.

8. A method for manufacturing a piezoelectric element array substrate according to claim 1, comprising the steps of: The increased leakage current is equal to or greater than the area of ​​the piezoelectric element × 0.1 A. A method for manufacturing a piezoelectric element array substrate.

9. A piezoelectric element array substrate, A substrate; a piezoelectric element array on the substrate, the piezoelectric element array including a plurality of piezoelectric elements; a thin film transistor array on the substrate for controlling the plurality of piezoelectric elements; Including, the thin film transistor array includes a plurality of piezoelectric element control circuits each controlling the plurality of piezoelectric elements; A leakage current of each of the one or more thin film transistors at 80° C. is equal to or greater than an area of ​​the piezoelectric element×0.1 A. Piezoelectric element array substrate.

10. 10. The piezoelectric element array substrate according to claim 9, The leakage current of each of the one or more thin film transistors at 80° C. is 2.5E-11 A or more; Piezoelectric element array substrate.

11. A polarization device for polarizing a piezoelectric material of a piezoelectric element array substrate, comprising: The piezoelectric element array substrate includes: An insulating substrate; A plurality of piezoelectric element control circuits, each including one or more thin film transistors, on the insulating substrate; a plurality of piezoelectric elements, each including a layer of piezoelectric material, on the insulating substrate; Including, The polarization device is A plasma discharge device; a light-transmitting stage that supports the piezoelectric element array substrate from the insulating substrate side; a heating device for heating the piezoelectric element array substrate; a light source system that irradiates light onto the piezoelectric element array substrate from the rear side of the light-transmitting stage; Including, the plasma discharge device polarizes the piezoelectric material layers of the plurality of piezoelectric elements by charging the piezoelectric element array substrate while irradiating the piezoelectric element array substrate with the light and heating the substrate; Polarization device.

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