Electro-optical device and electronic apparatus

Abstract

To maintain good output characteristics of a DA conversion circuit without increasing the area of a semiconductor substrate.SOLUTION: An electro-optical device 10 comprises: a data signal output circuit 50 that includes a DA conversion circuit; a plurality of terminals 80; a control circuit 30 that is supplied with a power supply potential VL from at least one terminal of the terminals 80 via power supply wiring 501; and a power supply circuit 15a that generates a power supply potential VPL according to potentials AVDD and AVSS supplied via two or more terminals of the plurality of terminals 80, and supplies the generated power supply potential to power supply wiring 502. The DA conversion circuit 50 includes a plurality of capacitive elements, and the power supply wiring 501 or the power supply wiring 502 is selectively connected to a part of the plurality of capacitive elements.SELECTED DRAWING: Figure 12

Description

Technical field

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] Electro-optical devices using, for example, OLEDs (Organic Light Emitting Diodes) as light-emitting elements are known. In this electro-optical device, a pixel circuit including a transistor and the like for passing current through the light emitting element is provided on a semiconductor substrate in correspondence with each pixel of an image to be displayed. In the electro-optical device, a voltage depending on the brightness is applied to the gate node of the transistor via the data line. Specifically, digital data specifying brightness is converted into an analog voltage by a DA conversion circuit, and the converted voltage is applied to the gate node of the drive transistor via a data line.

[0003] For example, the following techniques are known as techniques applied to such a DA conversion circuit. Specifically, the capacitive element corresponding to the upper bit, the capacitive element corresponding to the lower bit, the switching element provided corresponding to the capacitive element, the other end of the capacitive element corresponding to the upper bit, and the lower bit. A technique is known that includes a junction capacitance provided between the other ends of corresponding capacitive elements (for example, see Patent Document 1). In this technique, the switching element selects the ground potential Gnd or the reference potential Vref depending on the bit, and applies the selected potential to one end of the capacitive element. [Prior art documents] [Patent document]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2002-190738 [Summary of the invention] [Problem to be solved by the invention]

[0005] However, in the above-mentioned DA conversion circuit, the configuration in which the ground potential Gnd is applied to one end of the capacitive element is susceptible to the influence of noise. The reason for this is that the ground potential Gnd is commonly used in circuits other than the DA conversion circuit in the electro-optical device. When a DA conversion circuit is affected by noise, the linearity (gradation) of the output voltage deteriorates, leading to a decrease in display quality. A configuration may be considered in which the power supply potential used in the DA conversion circuit is supplied from outside the electro-optical device, but in such a configuration, the electro-optical device requires a terminal to receive the supply of the power supply potential. This leads to an increase in the area of ​​the semiconductor substrate. As described above, an electro-optical device requires a configuration that does not destroy the output characteristics of the DA conversion circuit without increasing the area of ​​the semiconductor substrate. [Means to solve the problem]

[0006] An electro-optical device according to one aspect of the present disclosure includes a drive circuit including a DA conversion circuit, a plurality of terminals, and a first power supply potential from at least one terminal of the plurality of terminals via a first power supply wiring. A second power supply potential different from the first power supply potential is generated according to the supplied first circuit and the potential supplied through two or more terminals among the plurality of terminals, and the second power supply potential is generated. a power supply circuit that supplies power to the wiring, and the DA conversion circuit includes a plurality of capacitance elements, and the first power supply wiring or the second power supply wiring selectively connects some of the plurality of capacitance elements. Connected. [Brief explanation of drawings]

[0007]

Figure 1

Figure 2

[0008] EMBODIMENT OF THE INVENTION Hereinafter, an electro-optical device according to an embodiment of the present invention will be described with reference to the drawings. In each figure, the dimensions and scale of each part are appropriately different from the actual ones. Furthermore, since the embodiments described below are preferred specific examples, various technically preferable limitations are attached thereto. Unless otherwise specified, the present invention is not limited to these forms.

[0009] FIG. 1 is a perspective view showing an electro-optical device 10. The electro-optical device 10 is a micro-display panel that displays images on, for example, a head-mounted display. The electro-optical device 10 includes a plurality of pixel circuits, a drive circuit that drives the pixel circuits, and the like. The pixel circuit and the drive circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be other semiconductor substrates.

[0010] As shown in this figure, the electro-optical device 10 is housed in a frame-shaped case 192 having an opening 191. One end of an FPC (Flexible Printed Circuits) board 194 is connected to the electro-optical device 10. A plurality of terminals 196 are provided at the other end of the FPC board 194. The plurality of terminals 196 are connected to a host device (not shown). The host device supplies video data and various power supply potentials to the electro-optical device 10 via the FPC board 194. The video data is data indicating a video to be displayed by the electro-optical device 10.

[0011] Furthermore, a capacitive element (capacitor) 198 for smoothing the power supply potential generated by the electro-optical device 10 is mounted on the FPC board 194. Note that this capacitive element 198 may be provided in a host device instead of being mounted on the FPC board 194.

[0012] Note that in the figure, the X direction indicates the horizontal direction of the displayed image in the electro-optical device 10, and the Y direction indicates the vertical direction of the displayed image. Further, a two-dimensional plane defined by the X direction and the Y direction is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X direction and the Y direction, and indicates the direction in which light is emitted from the OLED, which will be described later.

[0013] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 is roughly divided into a power supply circuit 15a, a control circuit 30, a data signal output circuit 50, an initialization circuit 60, a display area 100, and a scanning line drive circuit 120. In the display area 100, m rows of scanning lines 12 are provided along the X direction in the figure, and n columns of data lines 14 are provided along the Y direction and electrically insulated from each scanning line 12. It is set up like this. Note that m and n are integers of 2 or more.

[0014] The pixel circuits 110 are provided corresponding to the intersections of the m rows of scanning lines 12 and the n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows by n columns. Note that the area where the pixel circuits 110 are arranged is an example of the display area 100. Furthermore, in order to distinguish the rows in the matrix arrangement, they are sometimes referred to as 1st, 2nd, 3rd, ..., (m-1), and m-th rows in order from the top in the figure. Similarly, to distinguish the columns of the matrix, they are sometimes referred to as the 1st, 2nd, 3rd, ..., (n-1), and n-th columns from the left in the figure. Note that in order to generalize and explain the scanning line 12, an integer i from 1 to m is used. Similarly, in order to generalize and explain the data line 14, an integer j from 1 to n is used.

[0015] The control circuit 30 controls each section based on video data Vid and synchronization signal Sync supplied from the host device. The video data Vid specifies the gradation level of a pixel in an image to be displayed using, for example, 8 bits for each of the three primary colors. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing for one pixel of the video data. In this embodiment, there is a one-to-one correspondence between the pixels of the image to be displayed and the pixel circuits 110 in the display area 100, but the correspondence does not necessarily have to be one-to-one.

[0016] The brightness characteristics at the gradation level indicated by the video data Vid supplied from the host device and the brightness characteristics of the OLED included in the pixel circuit 110 do not necessarily match. Therefore, in order to cause the OLED to emit light at a brightness corresponding to the gradation level indicated by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits, and converts the video data Vid to 10 bits. Output as Vdata. Therefore, the 10-bit video data Vdata becomes data corresponding to the gradation level specified by the video data Vid.

[0017] Note that for up-conversion, a lookup table is used that stores in advance the correspondence between 8 bits of input video data Vid and 10 bits of output video data Vdata. Further, the control circuit 30 generates various control signals in the form of logic signals in order to control each section, and the details will be described later.

[0018] The scanning line drive circuit 120 is a circuit that outputs various control signals under the control of the control circuit 30 to drive the pixel circuits 110 arranged in m rows and n columns row by row. For example, the scanning line drive circuit 120 sequentially sends scanning signals / Gwr(1), / Gwr(2), ..., / Gwr( m-1), / Gwr(m) is supplied. Generally, the scanning signal supplied to the i-th scanning line 12 is expressed as / Gwr(i). The scanning line drive circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(m), the details of which will be described later.

[0019] The data signal output circuit 50 is a circuit that outputs a data signal of a voltage according to luminance to the pixel circuit 110 located in the row selected by the scanning line drive circuit 120. Specifically, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500. The selection circuit group 52 includes a selection circuit 520 corresponding to each of the n columns, the first latch circuit group 54 includes a first latch circuit L1 corresponding to each of the n columns, and the second latch circuit group 56 includes: It includes a second latch circuit L2 corresponding to each of the n columns.

[0020] That is, a set of selection circuit 520, first latch circuit L1, second latch circuit L2, and DA conversion circuit 500 is provided corresponding to each example. The selection circuit 520 in the j-column instructs the first latch circuit L1 in the j-column to select the video data corresponding to the j-column from among the video data Vdata output from the control circuit 30, and The first latch circuit L1 latches the video data Vdata according to the instruction. The second latch circuit L2 in the j column transfers the video data Vdata latched by the first latch circuit L1 in the j column to the DA converter circuit 500 in the j column in a write period to be described later under the control of the control circuit 30. Output to. The DA conversion circuit 500 in the j column converts the 10-bit video data Vdata output from the second latch circuit L2 in the j column into an analog voltage data signal, and sends the data signal to the data line 14 in the j column. Output. Note that details of the DA conversion circuit 500 will be described later.

[0021] The initialization circuit 60 is a collection of transistors 66 provided in one-to-one correspondence with the data lines 14. One end of the transistor 66 corresponding to the j-th column is electrically connected to the power supply wiring that supplies the power supply potential Vini, and the other end of the transistor 66 is electrically connected to the data line 14 of the j-th column. Furthermore, a control signal / Gini from the control circuit 30 is commonly supplied to the gate nodes of the transistors 62 in each column. In this description, "electrical connection" or simply "connection" means a direct or indirect connection or coupling between two or more elements; for example, in a semiconductor substrate, two or more elements are not directly connected. However, it also includes connecting different wiring lines through contact holes.

[0022] In the figure, the potential of the data line 14 in the 1st, 2nd, ..., (n-1), nth column is sequentially Vd(1), Vd(2), ..., Vd(n-1), Vd(n). Written. Generally, the potential of the data line 14 in the j-th column is expressed as Vd(j). The power supply circuit 15a is an internal power supply of the electro-optical device 10, and generates various power supply potentials and the like. Further, the electro-optical device 10 is provided with various power supply wirings.

[0023] FIG. 3 is a diagram showing the relationship between the power supply potential generated by the power supply circuit 15a and the power supply potential supplied from the outside of the electro-optical device 10. As shown in this figure, the electro-optical device 10 is supplied with power supply potentials AVSS, AVDD, VSS, and VDD from the outside. Although not shown in FIG. 3, the electro-optical device 10 is also supplied with power supply potentials Vel and Vct.

[0024] Power supply circuit 15a generates power supply potentials VL, VPL, and VPH using power supply potentials AVSS and AVDD. Note that the power supply potential VL is supplied to the power supply wiring 501, the power supply potential VPL is supplied to the power supply wiring 502, and the power supply potential VPH is supplied to the power supply wiring 503. These power supply potentials VL, VPL, and VPH are used for the DA conversion circuit 500. Although not shown in FIG. 3, the power supply circuit 15a also generates power supply potentials Vini, Vrst, and Vorst.

[0025] The power supply potential VSS is the ground potential Gnd and is used as the L level of logic level. Therefore, the power supply potential VSS is commonly used not only in various circuits in the electro-optical device 10 but also in external circuits, such as higher-level devices. Further, the power supply potential VDD is used as a logic H level except for a level shifter to be described later. Power supply potential VDD and power supply potential VL are at the same potential in this embodiment. Therefore, in the electro-optical device 10, the terminal to which the power supply potential VDD is supplied from the outside is electrically connected to the power supply wiring 501.

[0026] Note that in this description, a power supply potential refers to a potential that is substantially constant over time, and a power supply wiring refers to a wiring that supplies the power supply potential. Voltage (or potential) refers to a potential difference with respect to ground potential Gnd (=VSS), but may also refer to a potential difference between two specific nodes, such as a threshold voltage described later. Other than that, this explanation does not strictly distinguish between potential and voltage.

[0027] FIG. 4 is a circuit diagram showing the pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to each other. For this reason, the pixel circuit 110 will be described using the pixel circuit 110 located in the i-th row and the j-th column as a representative.

[0028] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-channel transistors 121 to 125, and a capacitor 140. The transistors 121 to 125 are, for example, MOS (Metal-Oxide-Semiconductor field-effect transistor) type. In addition to the scanning signal / Gwr(i), control signals / Gel(i), / Gcmp(i), and / Gorst(i) are supplied to the i-th pixel circuit 110 from the scanning line drive circuit 120. be done.

[0029] The control signal / Gel(i) is the control signal / Gel(1), / Gel(2), ..., / that is supplied in order corresponding to the 1st, 2nd, ..., (m-1), mth row. This is a generalized notation of Gel(m-1) and / Gel(m). Similarly, the control signal / Gcmp(i) is the control signal / Gcmp(1), / Gcmp(2), etc. that is supplied in order corresponding to the 1st, 2nd, ..., (m-1), mth row. , / Gcmp(m-1), / Gcmp(m) are generalized. The same applies to the control signal / Gorst(i), and the control signals / Gorst(1), / Gorst(2), which are supplied in order corresponding to the 1st, 2nd, ..., (m-1), m-th rows, ..., / Gorst(m-1), / Gorst(m) are generalized.

[0030] The OLED 130 is an example of a light emitting element in which a light emitting layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. Pixel electrode 131 functions as an anode, and common electrode 133 functions as a cathode. Note that the common electrode 133 has light reflecting properties and light transmitting properties, and functions as a semi-reflective and semi-transmissive layer. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light emitting layer 132 to generate excitons and generate white light.

[0031] In the case of color display, the generated white light resonates in an optical resonator made up of a reflective layer and a semi-reflective and semi-transmissive layer (not shown), and displays R (red), G (green), B ( It emits light at a resonant wavelength set corresponding to one of the colors (blue). A color filter corresponding to the color is provided on the light output side from the optical resonator. Therefore, the light emitted from the OLED 130 is visible to the viewer after being colored by the optical resonator and the color filter. Note that the optical resonator is not shown. Further, when the electro-optical device 10 simply displays a monochromatic image of only brightness and darkness, the color filter is omitted.

[0032] In the transistor 121 of the pixel circuit 110 in the i-th row and the j-th column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply wiring of the power supply potential Vel, and the drain node d is connected to the transistor 123. and the source node of transistor 124. One end of the capacitive element 140 is connected to the gate node g of the transistor 121, and the other end is connected to the power supply wiring of the power supply potential Vel. Therefore, capacitive element 140 holds the voltage between gate node g and source node s of transistor 121. Note that the other end of the capacitive element 140 may be connected to a power supply wiring other than the power supply potential Vel because it is sufficient that the potential is kept substantially constant.

[0033] In this embodiment, a so-called MOS capacitor, which is formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer and a gate electrode layer of the transistor, is used as the capacitor 140, for example. Note that as the capacitive element 140, a parasitic capacitance of the gate node g of the transistor 121 may be used, or a so-called metal capacitor formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate may be used. good.

[0034] The gate node of the transistor 122 of the pixel circuit 110 in the i-th row and j-th column is connected to the i-th scanning line 12, and the source node is connected to the data line 14 in the j-th column. In the transistor 123 of the pixel circuit 110 in the i-th row and j-th column, the control signal / Gcmp(i) is supplied to the gate node, and the drain node is connected to the data line 14 in the j-th column. In the transistor 124 of the pixel circuit 110 in the i-th row and the j-th column, the control signal / Gel(i) is supplied to the gate node, and the drain node is connected to the pixel electrode 131, which is the anode of the OLED 130, and the drain node of the transistor 125. Ru. In the transistor 125 of the pixel circuit 110 in the i-th row and the j-th column, the control signal / Gorst(i) is supplied to the gate node, and the source node is connected to the power supply wiring of the power supply potential Vorst.

[0035] Note that the power supply potential Vorst is, for example, the ground potential Gnd or a potential close to the ground potential Gnd. Specifically, the power supply potential Vorst is such a potential that no current flows through the OLED 130 when it is supplied to the pixel electrode 131 in the OLED 130. Further, the common electrode 133 functioning as a cathode of the OLED 130 is supplied with a power supply potential Vct via a power supply wiring.

[0036] FIG. 5 is a circuit diagram showing a DA conversion circuit 500 corresponding to the j-th column. Bits D0 to D9 are supplied to the j-th column DA conversion circuit 500 from the j-th column second latch circuit L2. Furthermore, the control signals Enb0 to Enb9 and the control signal / Rst are supplied from the control circuit 30 to the j-th column DA conversion circuit 500. In addition to power supply potential Vrst, power supply potentials VL, VPL, and VPH are supplied to DA conversion circuit 500 in each column from power supply circuit 15a via power supply wirings 501, 502, and 503 in order. Note that in the first embodiment, the power supply potential VPH is, for example, 4.7 volts, the power supply potential VPL is, for example, 3.0 volts, and the power supply potential VL (=VDD) is, for example, 1.8 volts.

[0037] Bits D0 to D9 are 10 bits of the video data Vdata output from the second latch circuit L2 in the j-th column, and are data to be converted by the DA conversion circuit 500. Among the 10 bits, the least significant bit is D0, and the weight increases in order from bit D0 as D1, D2, etc., and the most significant bit is D9. Control signals Enb0 to Enb9 are signals that sequentially specify the timing of capturing bits D0 to D9. The control signal / Rst is a signal for resetting the capacitive element.

[0038] As shown in the figure, DA conversion circuit 500 includes capacitive elements C0 to C9, Cser, switch Rsw, and selection circuits 510 to 519. Capacitive elements C0 to C9 and selection circuits 510 to 519 form pairs as follows so as to correspond to each bit. Specifically, the selection circuit 510 and capacitive element C0 form a pair corresponding to bit D0, the selection circuit 511 and capacitive element C1 form a pair corresponding to bit D1, and in the same manner, bit D9 Correspondingly, selection circuit 519 and capacitive element C9 form a pair. Note that, in this embodiment, of the 10 bits of the video data Vdata, bits D5 to D9 are upper bits, and bits D0 to D4 are lower bits.

[0039] The selection circuits 510 to 514 corresponding to the lower bits select the power supply potential VL or VPL, and supply the selected power supply potential to one end of the corresponding capacitive element. Furthermore, the selection circuits 515 to 519 corresponding to the upper bits select the power supply potential VL or VPH, and supply the selected power supply potential to one end of the corresponding capacitive element. For example, the selection circuit 510 corresponding to bit D0 takes in bit D0 at the timing specified by control signal Enb0, selects power supply potential VL or VPL according to the logic level of the taken-in bit D0, and selects the selected power supply potential. Supplied to one end of capacitive element C0. For example, the selection circuit 516 corresponding to bit D6 takes in bit D6 at the timing specified by control signal Enb6, selects power supply potential VL or VPH according to the logic level of the taken-in bit D6, and selects the selected power supply potential. is applied to one end of capacitive element C6.

[0040] In this embodiment, the capacitance values ​​of the capacitive elements C0 to C9 have the following ratio. Specifically, if the capacitance value of capacitive element C0 is "1", the capacitance values ​​of capacitive elements C2, C3, C4, C5, C6, C7, C8, C9 are "2", "4", "4", They are "8", "16", "1", "2", "4", "8", and "16".

[0041] Considering the total 10 bits, the weights of bits D0 to D9 are "1", "2", "4", "8", "16", "32", "64", "128", " 256” and “512”. Therefore, the capacitance values ​​of the capacitive elements C0 to C9 do not match the weights. However, if bits D0~D9 are divided into lower bits D0~D4 and upper bits D5~D9, and among bits D5~D9, bit D5 is the least significant bit and the weight is considered to be "1". , the weights of bits D5 to D9 become "1", "2", "4", "8", and "16" in order. In this explanation, since it is necessary to consider the case where bits D0 to D9 are divided into lower bits D0 to D4 and upper bits D5 to D9, capacitive elements C0 to C9 have capacitances corresponding to the weights of bits D0 to D9. It is expressed as having a value.

[0042] Further, the capacitance value of the capacitive element Cser is "1" in this embodiment. Note that a certain amount of error is allowed for the capacitance values ​​of the capacitive elements C0 to C9 and Cser as long as linearity is maintained. In this embodiment, since a MOS capacitor is used as the capacitive element 140 in the pixel circuit 110, it is preferable to use a MOS capacitor for the capacitive elements C0 to C9 and Cser, but metal capacitors may also be used.

[0043] Among the capacitive elements C0 to C9, the other ends of the capacitive elements C0 to C4 corresponding to the lower five bits are electrically connected to one end of the capacitive element Cser. For convenience, the connection line between the other ends of the capacitive elements C0 to C4 and one end of the capacitive element Cser is referred to as a relay line 14b. Further, among the capacitive elements C0 to C9, the other ends of the capacitive elements C5 to C9 corresponding to the upper five bits are electrically connected to the data line 14, which is the output terminal Out of the DA conversion circuit 500, and the other end of the capacitive element Cser. connected to.

[0044] The switch Rsw is turned on or off between the power supply wiring at the power supply potential Vrst and the relay line 14b according to the control signal / Rst. Specifically, the switch Rsw is turned on when the control signal / Rst is at L level, and turned off when the control signal / Rst is at H level. In this description, the "on state" of a switch, transmission gate, or transistor means that both ends of the switch, both ends of the transmission gate, or the source node and drain node of the transistor are electrically closed and in a low impedance state. means. Furthermore, the "off state" of a switch, transmission gate, or transistor means that both ends of the switch, both ends of the transmission gate, or between the source node and the drain node are electrically open and in a high impedance state.

[0045] The switch Rsw is preferably configured with a NOT circuit Lg0 that outputs a negative signal of the control signal / Rst, and a transmission gate Tg0. The transmission gate Tg0 is an analog switch that is a combination of an n-type transistor whose gate node is supplied with a negative signal from the NOT circuit Lg0, and a p-type transistor whose gate node is supplied with a control signal / Rst. .

[0046] The selection circuit 510 paired with the capacitive element C0 includes an AND circuit Ds, a level shifter Ls, and a selector Sel. Among these, the AND circuit Ds outputs an AND signal of the bit D0 of the video data Vdata output from the second latch circuit L2 of the j-th column and the control signal Enb0 supplied from the control circuit 30. As shown in the figure, the AND circuit Ds actually includes a NAND circuit Lg1 that outputs a NAND signal of bit D0 and control signal Enb0, and a NOT circuit Lg2 that outputs a NAND signal of the NAND signal. Consisted of.

[0047] The level shifter Ls converts the logic amplitude of the AND signal output by the AND circuit Ds, outputs a normal signal that maintains the logic level of the AND signal from the output terminal Out, and inverts the logic level of the AND signal. Outputs the inverted signal from the output terminal / Out. In the first embodiment, although the power supply of the level shifter Ls is not particularly illustrated, the high level is the power supply potential VPH, and the low level is the power supply potential VL (or VSS). Therefore, in the first embodiment, in the normal rotation signal or the inversion signal output from the level shifter Ls, the H level is the power supply potential VPH, and the L level is the power supply potential VL (or VSS).

[0048] Selector Sel in selection circuit 510 selects power supply potential VPL if the normal signal output from level shifter Ls is at H level and the inverted signal is at L level. That is, the selector Sel selects the power supply potential VPL when the bit D0 is "1" (H level) and the control signal Enb0 is at the H level. Further, the selector Sel selects the power supply potential VL if the normal rotation signal output from the level shifter Ls is at the L level and the inverted signal is at the H level. That is, the selector Sel selects the power supply potential VL if the bit D0 is "0" (L level) or if the control signal Enb0 is L level.

[0049] The selector Sel is actually provided between the transmission gate Tg1, which is provided between the power supply wiring at the power supply potential VPL and one end of the capacitive element C0, and the transmission gate Tg1, which is provided between the power supply wiring at the power supply potential VL and one end of the capacitive element C0. transmission gate Tg2. In this configuration, if the normal rotation signal output from the level shifter Ls is at H level and the inverted signal is at L level, transmission gate Tg1 is turned on and transmission gate Tg2 is turned off, so that the capacitive element Power supply potential VPL is supplied to one end of C0. In addition, in this configuration, if the normal rotation signal output from the level shifter Ls is at L level and the inverted signal is at H level, transmission gate Tg1 is turned off and transmission gate Tg2 is turned on. A power supply potential VL is supplied to one end of the capacitive element C0.

[0050] Here, the selection circuit 510 paired with the capacitive element C0 has been described, but the other selection circuits 511 to 514 corresponding to the lower bits also differ in the bits D1 to D4 of the input signal and the control signals Enb1 to Enb4. Other than that, it has the same configuration as the selection circuit 510. Therefore, in the selection circuits 510 to 514, one ends of the capacitive elements C0 to C4 are configured to be selectively connectable to either the power supply wiring 501 or 502.

[0051] Further, regarding the selection circuits 515 to 519 corresponding to the upper bits, if the normal rotation signal output from the level shifter Ls is at the H level and the inverted signal is at the L level, the power supply potential VPH is selected; The configuration is similar to that of the selection circuits 510 to 514 except that the bits D5 to D9 of the input signal and the control signals Enb5 to Enb9 are different. Therefore, in selection circuits 515 to 519, one ends of capacitive elements C5 to C9 are configured to be selectively connectable to either power supply wiring 501 or 503.

[0052] FIG. 5 is a diagram showing an equivalent circuit in the j-th column DA conversion circuit 500. Selection circuit 510 selects power supply potential VL if the AND signal (D0·Enb0) of bit D0 and control signal Enb0 is at L level, and selects power supply potential VPL if the AND signal is at H level. Described as a single pole double throw switch. Selection circuits 511 to 514 are also expressed as single-pole, double-throw switches similar to selection circuit 510. Selection circuit 515 selects power supply potential VL if the AND signal (D5·Enb5) of bit D5 and control signal Enb5 is at L level, and selects power supply potential VPH if the AND signal is at H level. Described as a single pole double throw switch. Selection circuits 516 to 519 are also expressed as single-pole, double-throw switches similar to selection circuit 515. Note that although the DA conversion circuit 500 in the j-th column has been described in FIGS. 5 and 6, the DA conversion circuits 500 corresponding to other columns have similar configurations.

[0053] The operation of the DA conversion circuit 500 is divided into a reset period and an output period. Note that the reset period of the DA conversion circuit 500 corresponds to an initialization period (a) and a compensation period (b) of the operation period of the electro-optical device 10, which will be described later. This corresponds to the write period (c) of the operating period of the device 10.

[0054] In the DA conversion circuit 500, the switch Rsw is turned on during the reset period, and the selection circuits 510 to 519 each select the power supply potential VL. Furthermore, at the end of the reset period, elements not shown in FIGS. 5 and 6 cause the data line 14, which is the output terminal Out, to be at approximately the same potential as the power supply potential Vrst, specifically, the average voltage of the transistors 121 in each column. It becomes a potential equivalent to a threshold value. Therefore, charge corresponding to the capacitance value is accumulated in the capacitive elements C0 to C9.

[0055] In the output period of the DA conversion circuit 500, the selection circuits 510 to 514 maintain the selection of the power supply potential VL if the corresponding AND signal is at L level, and select the power supply potential VPL if the corresponding AND signal is at H level. Select. Further, during the output period, the selection circuits 515 to 519 maintain selection of the power supply potential VL if the corresponding AND signal is at L level, and select power supply potential VPH if the corresponding AND signal is at H level. As described later, at the end of the output period, control signals Enb0 to Enb9 are at H level, so selection circuits 510 to 519 select power supply potential VL or VPL (or VPH) according to the logic level of bits D0 to D9. I will do it. That is, in the output period, the potential at one end of the capacitive elements C0 to C9 either changes (increases) or is maintained depending on the bits D0 to D9. Therefore, among the capacitive elements C0 to C9, at the other end of the capacitive element C0 to C9 where the potential at one end has changed, the potential at the other end of the capacitive element C0 to C9 increases from the potential at the end of the reset period according to the capacitance value due to the discharge of the accumulated charge. .

[0056] Note that, as described above, in the first embodiment, the power supply potential VPH is 4.7 volts, the power supply potential VPL is 3.0 volts, and the power supply potential VL is 1.8 volts. Therefore, in the first embodiment, the voltage change (VPL-VL) at one end of the capacitive elements C0 to C4 when the corresponding bit is "1" is 1.2 volts. Further, at one end of the upper capacitive elements C5 to C9, the voltage change (VPH-VL) when the corresponding bit is "1" is 2.9 volts.

[0057] At the other ends of the capacitive elements C5 to C9 corresponding to the upper bits, the electric potential of the data line 14 is increased according to the capacitance value. On the other hand, the relay line 14b, which is the other end of the capacitive elements C0 to C4 corresponding to the lower bits, is connected to the data line 14 via the capacitive element Cser. It is compressed at a ratio determined by elements C0 to C4 and Cser, changing the potential of data line 14. When this ratio is expressed as a compression ratio k, this compression ratio k is expressed by the following equation (1). k=Cser / (Cser+C0+C1+C2+C3+C4)…(1) Note that the compression ratio k is 1 / 32 (=1 / (1+1+2+4+8+16)) in the first embodiment.

[0058] In FIG. 6, if a circuit including capacitive elements C5 to C9 and selection circuits 515 to 519 is referred to as an upper DA conversion circuit unit Upb, the upper DA conversion circuit unit Upb transfers voltages corresponding to bits D5 to D9 to data lines. Output to 14. Further, if a circuit including capacitive elements C0 to C4 and selection circuits 510 to 514 is referred to as a lower DA conversion circuit section Lwb, the lower DA conversion circuit section Lwb applies voltages corresponding to bits D0 to D4 to the relay line 14b. Output. However, the voltage change on the trunk line 14b is compressed to 1 / 32 of the compression ratio k and propagated to the data line 14. Therefore, even if bits D0 to D4 are the same as bits D5 to D9 in this order, the voltage change on the data line 14 caused by the lower DA conversion circuit section Lwb will be the same as the voltage change on the data line 14 caused by the upper DA conversion circuit section Upb. It becomes 1 / 32 of the change. Therefore, the DA conversion circuit 500 passed through the upper DA conversion circuit section Upb and the lower DA conversion circuit section Lwb changes the voltage on the data line 14 from the voltage at the end of the reset period by the voltage corresponding to the weight of bits D0 to D9. It turns out.

[0059] FIG. 7 is a timing chart for explaining the operation of the electro-optical device 10. In the electro-optical device 10, m rows of scanning lines 12 are scanned one by one in the order of 1st, 2nd, 3rd, . . . , m-th row during a frame (V) period. In detail, as shown in the figure, the scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) are horizontally scanned by the scanning line drive circuit 120. It becomes L level sequentially and exclusively for each period (H). Note that in this embodiment, among the scanning signals / Gwr(1) to / Gwr(m), the periods in which adjacent scanning signals are at L level are temporally separated. Specifically, after the scanning signal / Gwr(i-1) changes from L level to H level, the next scanning signal / Gwr(i) changes to L level after a period. This period corresponds to the horizontal retrace period.

[0060] In this description, the period of one frame (V) refers to the period required to display one frame of the image specified by the video data Vid. If the length of one frame (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60Hz, it corresponds to one period of the vertical synchronization signal. It is 16.7 milliseconds. In addition, the horizontal scanning period (H) is the time interval during which the scanning signals / Gwr(1) to / Gwr(m) sequentially reach the L level, but in the figure, for convenience, the horizontal scanning period (H) is The start timing of is set approximately at the center of the horizontal retrace period.

[0061] In the electro-optical device 10, one horizontal scanning period (H) is mainly divided into three periods: an initialization period (a), a compensation period (b), and a writing period (c). Furthermore, as for the operation of the pixel circuit 110, a light emitting period (d) is added in addition to the above three periods.

[0062] In the initialization period (a) of each horizontal scanning period (H), the control signal / Gini is at L level, the control signal / Rst is at L level, and the control signal Enb is at L level. Note that the control signal Enb is a signal that collectively refers to the control signals Enb0 to Enb9. The control signals Enb0 to Enb9 sequentially shift in phase during the write period (c) as described later, but have the same waveform during other periods, so they are collectively referred to as the control signal Enb. During the compensation period (b), the control signal / Gini is at H level, and the control signals / Rst and Enb are maintained at L level. During the write period (c), the control signal / Gini maintains the H level, and the control signals / Rst and Enb go to the H level.

[0063] The operation during the horizontal scanning period (H) will be explained using the i-th row as an example. Furthermore, the pixel circuit 110 will be explained using the pixel circuit 110 in the i-th row and the j-th column as an example. In the i-th horizontal scanning period (H), the i-th initialization period (a) starts before the scanning signal / Gwr(i) becomes L level. The initialization period (a) is a period for resetting the charges remaining in each part during the horizontal scanning period (H) of the (i-1)th row.

[0064] FIG. 8 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-column and the DA conversion circuit 500 corresponding to the j-th column data line 14 during the i-th initialization period (a). be. In the initialization period (a), the control signal / Gini goes to L level, turning on the transistor 66, so that the data line 14 is initialized to the power supply potential Vini. Further, in the initialization period (a), the switch Rsw is turned on by the control signal / Rst becoming L level, so that the relay line 14b becomes the power supply potential Vrst. In the initialization period (a), since the control signal Enb is at L level, the logic of each AND circuit Ds in the selection circuits 510 to 519 is The product signal becomes L level. Therefore, selection circuits 510 to 519 each select power supply potential VL.

[0065] Therefore, during the initialization period (a), as shown in FIG. The other end of the capacitive element Cser and the other ends of the capacitive elements C5 to C9 become the power supply potential Vini via the data line 14. In this way, in the initialization period (a), the data line 14 is initialized and the charges accumulated in the capacitive elements C0 to C9 and Cser are initialized.

[0066] Further, in the i-th row initialization period (a), the control signal / Gel(i) becomes H level, and the control signal / Gorst(i) becomes L level. Therefore, in the i-th pixel circuit 110, the transistor 124 is turned off and the transistor 125 is turned on, so that the pixel electrode 131, which is the anode of the OLED 130, becomes the power supply potential Vorst. Therefore, the OLED 130 is turned off and the pixel electrode 131 is reset to the power supply potential Vorst. Note that the reason for resetting the pixel electrode 131 is to eliminate the influence of charges accumulated in the parasitic capacitance in the immediately previous light emission period, since the OLED 130 has a parasitic capacitance.

[0067] After the initialization period (a) ends, the compensation period (b) begins. The compensation period (b) is a period for converging the gate node g of each transistor 121 to a potential equivalent to the threshold voltage of the transistor 121 in the n pixel circuits 110 located in the i-th row.

[0068] FIG. 9 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-column and the DA conversion circuit 500 corresponding to the data line 14 in the j-th column during the i-th compensation period (b). . In the compensation period (b), the control signal / Gini becomes H level, so that the transistor 66 is turned off. In addition, during the compensation period (b), since the control signal / Rst is at the L level, the switch Rsw is kept on, and since the control signal Enb is at the L level, the selection circuits 510 to 519 select the power supply potential VL. is maintained.

[0069] Furthermore, in the i-th row compensation period (b), the scanning signal / Gwr(i) goes to L level, and in this L level state, the control signal / Gcmp(i) goes to L level. Therefore, in the i-th pixel circuit 110, the transistor 122 is turned on, and the transistor 123 is turned on. Therefore, since the transistor 121 is in a diode-connected state, the voltage between the gate node and the source node of the transistor 121 converges to approach the threshold voltage Vth of the transistor 121. Therefore, the potential of the gate node approaches the potential (Vel-Vth) corresponding to the threshold voltage Vth. Note that this potential (Vel-Vth) is expressed as a threshold-equivalent potential for convenience. During the i-th compensation period (b), the transistors 122 and 123 in the pixel circuit 110 are in the on state, so the other end of the capacitive element Cser and the other ends of the capacitive elements C5 to C9 are also connected via the data line 14. Approaches the potential equivalent to the threshold.

[0070] Note that at the beginning of the compensation period (b), current needs to flow from the source node to the drain node in the diode-connected transistor 121. Therefore, the power supply potential Vini supplied to the gate node g during the initialization period (a) before the compensation period (b) is Vini<Vel-Vth This is the relationship.

[0071] Note that during the compensation period (b), one end of the capacitive elements C0 to C9 is maintained at the power supply potential VL by the selection circuits 510 to 519, and one end of the capacitive element Cser and the other end of the capacitive element C0 to C4 are maintained at the power supply potential VL by the selection circuits 510 to 519. The on state maintains the power supply potential Vrst. Furthermore, in the i-th row compensation period (b), in the i-th pixel circuit 110, the off state of the transistor 124 and the on state of the transistor 125 continue from the initialization period (a). The power supply potential Vrst is set to an average potential equivalent to the threshold value of the transistors 121 in each column. Therefore, at the end of the compensation period (b), the voltages across capacitive elements C0 to C4 and the voltages across capacitive elements C5 to C9 are almost the same. Therefore, it can be considered that during the compensation period (b), charges corresponding to the capacitance values ​​are accumulated in the capacitive elements C0 to C9.

[0072] After the compensation period (b) ends, the write-in period (c) begins. In the write period (c), the gate node g of each transistor 121 in the pixel circuit 110 of the n column located in the i-th row is changed from the threshold equivalent potential (Vel-Vth) by a voltage corresponding to the brightness. It is a period for

[0073] FIG. 10 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-column and the DA conversion circuit 500 corresponding to the j-th column data line 14 during the i-th write period (c). be. In the write period (c), the control signal / Rst becomes H level, so the switch Rsw is turned off. Furthermore, in the write period (c), as shown in FIG. 7, after the control signal Enb0 becomes H level, the control signals Enb1 to Enb9 are sequentially delayed by time ΔT and become H level. Furthermore, when control signal Enb0 changes from H level to L level, control signals Enb1 to Enb9 are sequentially delayed by time ΔT and become L level. Note that the control signals Enb0 to Enb9 are all at the H level, and the write period (c) ends at a timing before the control signal Enb0 changes from the H level to the L level.

[0074] Of the video data output from the second latch circuit L2 in the j column, the period during which bit D0 is input to the level shifter Ls of the selection circuit 510 is limited by the AND circuit Ds to the period when the control signal Enb0 is at H level. Ru. Similarly, the period during which the bits D1 to D9 are sequentially input to the level shifters Ls in the selection circuits 511 to 519 is limited by the AND circuit Ds to the period during which the control signals Enb1 to Enb9 are sequentially at H level. Therefore, bits D0 to D9 are not taken into selection circuits 510 to 519 simultaneously, but sequentially with a delay of time ΔT.

[0075] Among the selection circuits 510 to 514, the selection circuit whose bit input to the level shifter Ls is "1" selects the power supply potential VPL, and the selection circuit whose bit is "0" selects the power supply potential VL. Further, among the selection circuits 515 to 519, the selection circuit whose bit input to the level shifter Ls is "1" selects the power supply potential VPH, and the selection circuit whose bit is "0" selects the power supply potential VL. do.

[0076] During the write period (c), the potential at one end of the capacitive element corresponding to the "0" bit input to the level shifter Ls among the capacitive elements C0 to C9 does not change from the compensation period (b), so the data line It does not contribute to the potential increase of 14. Among the capacitive elements C5 to C9 corresponding to the upper five bits, the potential at one end of the capacitive element corresponding to the "1" bit input to the level shifter Ls changes from the power supply potential VL to the power supply potential VPH during the write period (c). Changes to Therefore, among the capacitive elements C5 to C9, the capacitive element corresponding to the "1" bit raises the data line 14 by an amount corresponding to the weight of the capacitance value from the potential equivalent to the threshold in the compensation period (b). let

[0077] Among the capacitive elements C0 to C4 corresponding to the lower 5 bits, the potential at one end of the capacitive element corresponding to the "1" bit input to the level shifter Ls changes from the power supply potential VL to the power supply potential VPL during the write period (c). Changes to However, unlike the other ends of the capacitive elements C5 to C9, the other ends of the capacitive elements C0 to C4 are connected to the data line 14 via the capacitive element Cser. Therefore, among the capacitive elements C0 to C4, the change from the power supply potential VL to the power supply potential VPL at one end of the capacitive element corresponding to the "1" bit is compressed by the compression ratio k, and the potential of the data line 14 is compressed by the compression ratio k. to rise.

[0078] In this way, in the write period (c), the j-th column DA conversion circuit 500 changes the j-th column data line 14 from the threshold equivalent potential (Vel-Vth) to the bit of the video data Vdata in the i row and j column. The voltage corresponding to D0 to D9, that is, the brightness of the OLED in the i row and j column is increased by the specified voltage.

[0079] In this embodiment, in the write period (c), the periods in which the control signals Enb0 to Enb9 reach the H level are sequentially delayed by time ΔT. The reason for this is that when the control signals Enb0 to Enb9 are set to H level all at once, switching from the power supply potential VL to the power supply potential VPL or VPH occurs at the same time, and the spike fluctuations associated with the switching become large and propagate to each part. This is because it particularly propagates to the data line 14 and degrades the DA conversion accuracy. Therefore, in this embodiment, the phases of the control signals Enb0 to Enb9 are sequentially shifted so that switching from the power supply potential VL to VPL or VPH does not occur simultaneously. For this reason, the influence of spikes associated with switching is reduced, and a decrease in DA conversion accuracy is suppressed. Note that the order in which the control signals Enb0 to Enb9 become H level is not necessarily the order in which the control signals Enb0 to Enb9 become high.

[0080] In the i-th write period (c), in the pixel circuit 110 in the i-th row and the j-th column, the transistor 122 maintains the on state and the transistor 123 becomes the off state, so that the gate node g of the transistor 121 also has the j Similar to the data line 14 in the column, it rises from the threshold equivalent potential (Vel-Vth) by the voltage corresponding to bits D0 to D9 of the video data Vdata in the i row and j column. Furthermore, in the i-th row writing period (c), in the i-th pixel circuit 110, the transistor 124 continues to be in the off state and the transistor 125 continues to be in the on state.

[0081] When the scanning signal / Gwr(i) changes to H level, the writing period (c) of the i-th row ends. When the scanning signal / Gwr(i) becomes H level, the transistor 122 in the pixel circuit 110 in the i row and j column is turned off, but the voltage Vgs between the gate node g and the source node of the transistor 121 is lower than the capacitor 140. is maintained. Note that in FIG. 10, the voltage between the gate node g and the source node s is expressed as Vgs. Further, FIG. 10 shows a case where all bits D0 to D9 of the video data output from the second latch circuit L2 are "1".

[0082] After the writing period (c) ends, the light emitting period (d) begins. The light emitting period (d) is a period during which a current corresponding to the voltage Vgs held during the writing period (c) is passed through the OLED 130 to cause it to emit light.

[0083] FIG. 11 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-column during the i-th light emission period (d). Before the i-th light emission period (d), the control signal / Gorst(i) becomes H level, so the transistor 125 is turned off. Furthermore, when the i-th light emission period (d) arrives, the control signal / Gel(i) is inverted to L level, so the transistor 124 is turned on. Therefore, a current Ids corresponding to the voltage Vgs held by the capacitive element 140 flows through the OLED 130 through the transistor 121. Therefore, the OLED 130 enters an optical state corresponding to the current Ids, that is, a state in which it emits light with a brightness corresponding to the current Ids.

[0084] Note that although FIG. 11 shows an example in which the light emitting period (d) is continuous after the selection of the i-th scanning line 12 is completed, the period in which the control signal / Gel(i) is at L level is not intermittent. or may be adjusted according to brightness adjustment. Further, the level of the control signal / Gel(i) during the light emission period (d) may be increased from the L level during the compensation period (b). That is, for the level of the control signal / Gel(i) during the light emission period (d), an intermediate level between the H level and the L level may be used.

[0085] Additionally, during the i-th row light emission period (d), the DA conversion circuit 500 corresponding to the j-th column may operate during the horizontal scanning period (H) for other rows other than the i-th row. Therefore, the DA conversion circuit 500 is omitted in FIG. 11.

[0086] In FIGS. 8 to 10, attention is paid to the DA conversion circuit 500 corresponding to the j-th column and the pixel circuit 110 in the i-th row and j-column in the i-th horizontal scanning period (H), but other than the j-th column Similar operations are performed for the DA conversion circuit 500 and pixel circuit 110 corresponding to the column. In addition, in FIGS. 8 to 11, attention has been paid to the horizontal scanning period (H) of the i-th row, and the operation of the horizontal scanning period (H) has been described. , are sequentially executed for the m-th horizontal scanning period (H).

[0087] In the pixel circuit 110, the voltage Vgs in the write period (c) and the light emitting period (d) is a voltage that is changed from the threshold voltage in the compensation period (b) according to the gradation level of the pixel circuit 110. Similar operations are performed in other pixel circuits 110, so in this embodiment, the threshold voltage of the transistor 121 is compensated for across all pixel circuits 110 in m rows and n columns, and the OLED 130 is current flows. Therefore, in this embodiment, variations in brightness are reduced, resulting in high-quality display.

[0088] FIG. 12 is a schematic plan view showing the relationship between various circuits and power supply wiring in the electro-optical device 10. Since the electro-optical device 10 is diced from a wafer-shaped semiconductor substrate, it has a rectangular shape. Therefore, in the rectangular electro-optical device 10, as shown in the figure, for convenience, the upper side is designated by the symbol Ue, the lower side is designated by the symbol De, the left side is designated by the symbol Le, and the right side is designated by the symbol Re.

[0089] Between the lower side De and the display area 100, a data signal output circuit 50 and a control circuit 30 are provided in this order when viewed from the display area 100. Furthermore, in the electro-optical device 10, a plurality of terminals 80 are provided along the X direction on the lower side De. Note that an initialization circuit 60 is actually provided between the display area 100 and the data signal output circuit 50, but since the initialization circuit 60 does not require a power supply, it is omitted in FIG.

[0090] A scanning line drive circuit 120 is provided between the left side Le and the display area 100, and a power supply circuit 15a is provided between the left side Le and the control circuit 30. Similarly, a scanning line drive circuit 120 is provided between the right side Re and the display area 100, and a power supply circuit 15a is provided between the right side Re and the control circuit 30. In this way, the scanning line drive circuit 120 and the power supply circuit 15a are arranged almost symmetrically with respect to the display area 100, so the configuration is such that the scanning line drive circuit 120 and the power supply circuit 15a are provided asymmetrically on only one side. Compared to this, signal delays and voltage drops due to resistance in power supply wiring can be suppressed.

[0091] In this embodiment, the electro-optical device 10 is supplied with power supply potentials AVDD, AVSS, VDD, VSS, Vel, and Vct from the outside via the FPC board 194 and the terminal 80. Power supply circuit 15a generates power supply potentials VL, VPL, and VPH using power supply potentials AVSS and AVDD, and supplies them to data signal output circuit 50. Among these, power supply potentials VPL and VPH are outputted through the data signal output circuit 50 and the terminal 80, and are smoothed by an external capacitive element 198 as shown by the broken line in the figure. Note that the power supply potential VL is the same as the power supply potential VDD, and the power supply potential VDD (=VL) is smoothed by a capacitive element (not shown) in the host device and supplied to the electro-optical device 10. Therefore, when one end of the FPC board 194 is connected to the terminal 80 and the other end of the FPC board 194 is connected to the host device, the power supply wiring 501 is electrically connected to the smoothing capacitive element in the host device. Therefore, a separate capacitive element 198 is not required.

[0092] Power supply potentials Vel and Vct supplied from the outside via the terminal 80 are supplied to the display area 100. The scanning line drive circuit 120 uses power supply potentials AVSS, AVDD, VDD, and VSS to generate scanning signals / Gwr(1)~ / Gwr(m), control signals / Gcmp(1)~ / Gcmp(m), / Gorst. (1)~ / Gorst(m) and / Gel(1)~ / Gel(m) are generated and supplied to the display area 100. Further, the control circuit 30 generates control signals Enb0 to Enb9, / Rst, / Gini using the power supply potentials VDD and VSS, supplies them to the display area 100, and controls the scanning line drive circuit 120 and the data signal output circuit 50. Various control signals for control are generated using logic signals.

[0093] Here, before explaining the advantages of this embodiment, the configuration of a comparative example will be explained. FIG. 18 is a diagram showing the relationship between the power supply potential generated by the power supply circuit 15a of the electro-optical device 10d according to the comparative example and the power supply potential supplied from the outside of the electro-optical device 10d. As shown in this figure, the electro-optical device 10d according to the comparative example is similar to the embodiment in that power supply potentials AVSS, AVDD, VSS, and VDD are supplied from the outside, and the power supply circuit 15a is This embodiment is also similar to the embodiment in that power supply potentials VL, VPL, and VPH are generated using potentials AVSS and AVDD. In the comparative example, unlike the embodiment, power supply potentials VL and VDD are separated. Therefore, in the comparative example, power supply potentials VL and VDD do not necessarily need to be the same, and may be different.

[0094] FIG. 19 is a schematic plan view showing the relationship between various circuits and power supply wiring in an electro-optical device 10d according to a comparative example. In the comparative example, since the power supply potential VL is separated from the power supply potential VDD, it is necessary to smooth the power supply potential VL generated by the power supply circuit 15a, and a terminal 80 for connecting to the external capacitive element 198 is provided separately. It becomes necessary. In a configuration in which the electro-optical device is formed of a semiconductor substrate, the need for the terminal 80 separately increases the area of ​​the semiconductor substrate, leading to higher costs. In contrast, in this embodiment, the power supply potential VL generated by the power supply circuit 15a is the same as the power supply potential VDD, and is supplied to the electro-optical device 10 through the power supply wiring 501, so that the terminal 80 for smoothing is Not necessary. Therefore, in this embodiment, it is possible to suppress an increase in the area of ​​the semiconductor substrate.

[0095] Alternatively, the power supply circuit 15a may generate the power supply potential VL without receiving the power supply potential VDD from the outside, and supply the power supply potential VL to the control circuit 30 etc. as the power supply potential VDD, or the power supply circuit 15a may generate the power supply potential VL as the power supply potential VDD. A configuration is also possible in which the power supply potential VDD supplied from the outside is supplied as the power supply potential VL without generating the potential VL. However, in this configuration, when the load fluctuation of the power supply potential VDD used as a logic signal is large, the power supply potential VL that can be supplied to one end of the capacitive elements C0 to C9 is affected by the load fluctuation. If the power supply potential VL is affected, it will also affect the charge accumulated in the capacitive elements C0 to C9, which may impair the output characteristics of the DA converter circuit 500, that is, the linearity of the output voltage for bits D0 to D9, or cause crosstalk. Talk may cause deterioration in display quality. On the other hand, in this embodiment, the power supply potential VL generated by the power supply circuit 15a is supplied to each part of the electro-optical device 10 as the power supply wiring 501 together with the power supply potential VDD supplied from the outside. The power supply potential VL is not easily affected by the load fluctuation. Therefore, in this embodiment, the output characteristics of the DA conversion circuit 500 are good, and deterioration in display quality due to crosstalk can be suppressed.

[0096] Note that in the first embodiment, the power supply potential VL is an example of the first power supply potential, and the power supply wiring 501 is an example of the first power supply wiring. Further, the power supply potential VPL is an example of the second power supply potential, the power supply wiring 502 is an example of the second power supply wiring, the power supply potential VPH is an example of the third power supply potential, and the power supply wiring 503 is an example of the third power supply wiring. This is an example. In the first embodiment, the control circuit 30 is an example of a first circuit and a logic circuit, and the data signal output circuit 50 is an example of a drive circuit.

[0097] Next, a second embodiment will be described. In the first embodiment described above, the power supply potentials supplied to one ends of the capacitive elements C0 to C9 are arranged to be equal to the power supply potential VL during the reset period, but during the output period, the normal rotation signal output from the corresponding level shifter Ls The configuration is such that the power supply potentials are aligned when is at H level.

[0098] FIG. 13 is a diagram showing the relationship between the power supply potential generated by the power supply circuit 15b and the power supply potential supplied from the outside of the electro-optical device 10 in the electro-optical device 10 according to the second embodiment. As shown in this figure, the electro-optical device 10 is similar to the first embodiment in that power supply potentials AVSS, AVDD, VSS and VDD are supplied from the outside, but the power supply circuit 15b is supplied with power supply potentials AVSS, AVDD, VSS and VDD from the outside. Power supply potentials VLL and VLH are generated using AVSS and AVDD. Note that in the electro-optical device 10, the power supply potential AVDD is supplied to the power supply wiring 504, the power supply potential VLL is supplied to the power supply wiring 505, and the power supply potential VLH is supplied to the power supply wiring 503. These power supply potentials AVDD, VLL, and VLH are used for the DA conversion circuit 500. Further, in the second embodiment, the power supply potential AVDD is, for example, 6.0 volts, the power supply potential VLL is, for example, 4.8 volts, and the power supply potential VLH is, for example, 3.1 volts.

[0099] In the second embodiment, power supply potentials VDD and VSS are only supplied from outside and are not generated by power supply circuit 15b. Note that in the second embodiment, the power supply potential VDD is supplied to the control circuit 30 and the like via the power supply wiring 508, and the power supply potential VSS is supplied to the control circuit 30 and the like via the power supply wiring 509. Therefore, in the second embodiment, the power supply wirings 504, 505, and 506 are separated from the power supply wirings 508, 509, so that the power supply potentials AVDD, VLL, and VPH used in the DA conversion circuit 500 are The configuration is such that it is not easily affected by power supply potentials VDD and VSS used for logic signals.

[0100] FIG. 14 is a circuit diagram showing the DA conversion circuit 500 in the electro-optical device 10 according to the second embodiment. As shown in this figure, in the second embodiment, the power supply potential AVDD is supplied to one end of the capacitive elements C0 to C9 when the normal rotation signal output from the level shifter Ls of the corresponding bit is at H level. be done. Furthermore, when the normal rotation signal output from the level shifter Ls of the corresponding bit is at L level, the power supply potential VLL is supplied to one end of the capacitive elements C0 to C4 corresponding to the lower 5 bits, and the upper 5 bits are supplied with the power supply potential VLL. When the normal rotation signal output from the level shifter Ls of the corresponding bit is at L level, the power supply potential VLH is supplied to one end of the corresponding capacitive element C5 to C9.

[0101] In the second embodiment, although the power supply of the level shifter Ls is not particularly illustrated, the high level is the power supply potential AVDD, and the low level is the power supply potential VLH (or VSS). Therefore, in the second embodiment, in the normal rotation signal or the inversion signal output from the level shifter Ls, the H level is the power supply potential AVDD, and the L level is the power supply potential VLH (or VSS).

[0102] In the second embodiment, the voltage change from the reset period to the output period at one end of the lower capacitive elements C0 to C4 is (AVDD-VLL) if the corresponding bit is "1", and the voltage change at one end of the lower capacitive elements C0 to C4 is (AVDD-VLL). The voltage change from the reset period to the output period at one end of ~C9 is (AVDD-VLH) if the corresponding bit is “1”. Note that the voltage change from the reset period to the output period at one end of the capacitive elements C0 to C9 is zero if the corresponding bit is "0".

[0103] As described above, in the second embodiment, the power supply potential AVDD is 6.0 volts, the power supply potential VLL is 4.8 volts, and the power supply potential VLH is 3.1 volts. Therefore, in the second embodiment, the voltage change (AVDD-VLL) when the corresponding bit is "1" at one end of the lower capacitive elements C0 to C4 is the voltage change (VPL-VLL) in the first embodiment. It becomes 1.2 volts, the same as VL). Furthermore, in the second embodiment, the voltage change (AVDD-VLH) when the corresponding bit is "1" at one end of the upper capacitive elements C5 to C9 is the voltage change (VPH-VLH) in the first embodiment. ), which is the same as 2.9 volts. Therefore, although the power supply potential supplied to one end of the capacitive elements C0 to C9 is different from that in the first embodiment, the DA conversion circuit 500 in the second embodiment operates similarly to the first embodiment because the voltage changes are the same. become.

[0104] FIG. 15 is a schematic plan view showing the relationship between various circuits and power supply wiring in the electro-optical device 10 according to the second embodiment. In the second embodiment, the power supply potential AVDD supplied from the outside is supplied to the DA conversion circuit 500, so the number of output lines of the power supply circuit 15b is reduced from three in the power supply circuit 15a to two. In addition, in the second embodiment, the power supply potential VLH used for DA conversion and the power supply potential VDD used for logic signals are separated, so as in the first embodiment, the power supply potential VL used for DA conversion and the power supply potential VDD used for logic signals There is no need to connect it to the power supply potential VDD.

[0105] In the second embodiment, the power supply potential AVDD used for DA conversion is supplied from the outside like the power supply potential AVDD in the first embodiment, so a separate terminal is not required. Therefore, in the second embodiment as well, it is possible to suppress an increase in the area of ​​the semiconductor substrate. Furthermore, in the second embodiment, the power supply potentials AVDD, VLL, and VLH used for DA conversion are separated from the power supply potential VDD used as the H level of the logic signal and the power supply potential VSS used as the L level of the logic signal. ing. Therefore, even if the load fluctuations in the power supply potentials VDD and VSS used as logic signals are large, the power supply potentials AVDD, VLL, and VLH used in DA conversion are not easily affected by the load fluctuations. Therefore, in the second embodiment as well, the output characteristics of the DA conversion circuit 500 are good, and deterioration in display quality due to crosstalk can be suppressed.

[0106] Note that in the second embodiment, the power supply potential AVDD is an example of the first power supply potential, and the power supply wiring 504 is an example of the first power supply wiring. Further, the power supply potential VLL is an example of the second power supply potential, the power supply wiring 505 is an example of the second power supply wiring, the power supply potential VLH is an example of the third power supply potential, and the power supply wiring 506 is an example of the third power supply wiring. This is an example. In the second embodiment, for example, the level shifter Ls is an example of the first circuit, the control circuit 30 is an example of a logic circuit, and the data signal output circuit 50 is an example of a drive circuit.

[0107] The first and second embodiments (hereinafter referred to as "embodiments, etc.") described above can be modified or applied in various ways as described below.

[0108] The DA conversion circuit 500 according to the various embodiments described above divides the 10 bits into upper bits D5 to D9 and lower bits D0 to D4. The configuration is such that bits D0 to D4 are converted and output directly to the data line 14, and the lower DA conversion circuit Lwb converts and outputs them to the data line 14 via the capacitive element Cser. The number of bits may be 2 or more.

[0109] Although the embodiments have been described using the OLED 130 as an example of a light emitting element, other light emitting elements may be used. For example, an LED, mini LED, micro LED, etc. may be used as the light emitting element. Furthermore, a liquid crystal element may be used as a display element instead of a light emitting element. Even when using a liquid crystal element, it is necessary to supply a data signal with a voltage corresponding to the brightness, so the above-described DA conversion circuit 500 is applied to the electro-optical device 10 according to the embodiments. That is, the light emitting element or the liquid crystal element may be an electro-optical element that has an optical (brightness) state that corresponds to the voltage of the data signal output from the DA conversion circuit 500.

[0110] The channel types of the transistors 66 and 121 to 125 are not limited to the embodiments. Further, these transistors 66, 121 to 125 may be replaced with transmission gates as appropriate. Conversely, transmission gates Tg0 to Tg2 may be replaced with transistors of one channel type.

[0111] Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for use in high-definition display with small pixels. Therefore, a head-mounted display will be described as an example of an electronic device.

[0112] FIG. 16 is a diagram showing the appearance of the head-mounted display, and FIG. 17 is a diagram showing its optical configuration. First, as shown in FIG. 16, the head-mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R, similar to general eyeglasses. In addition, as shown in FIG. 17, the head-mounted display 300 has an electro-optical device 10L for the left eye and an electro-optical device 10L for the right eye near the bridge 320 and behind the lenses 301L and 301R (bottom side in the figure). An electro-optical device 10R is provided. The image display surface of the electro-optical device 10L is arranged to be on the left in FIG. As a result, the image displayed by the electro-optical device 10L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is arranged to be on the right side opposite to that of the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

[0113] In this configuration, the person wearing the head-mounted display 300 can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state superimposed on the outside appearance. In addition, in this head-mounted display 300, when the electro-optical device 10L displays the left-eye image and the right-eye image is displayed by the electro-optical device 10R among the binocular images with parallax, the wearer can see The image can be perceived as if it had depth and three-dimensionality.

[0114] In addition to the head-mounted display 300, electronic devices including the electro-optical device 10 include electronic viewfinders in video cameras and digital cameras with interchangeable lenses, personal digital assistants, wristwatch displays, and projection projectors. It can also be applied to light valves, etc.

[0115] From the above description, preferred aspects of the present disclosure can be understood, for example, as follows. Note that in order to facilitate understanding of each aspect, the reference numerals in the drawings will be conveniently written in parentheses below, but this is not intended to limit the present invention to the illustrated aspects.

[0116] An electro-optical device (10) according to one aspect 1 includes a drive circuit (500) including a DA conversion circuit, a plurality of terminals (80), and a first terminal from at least one terminal among the plurality of terminals (80). The power supply potential (VL / AVDD) is supplied via the first circuit (30 / Ls) via the first power supply wiring (501 / 504) and two or more terminals among the plurality of terminals (80). A power supply circuit (15a) that generates a second power supply potential (VPL / VLL) different from the first power supply potential (VL / AVDD) according to the potential applied to the power supply and supplies it to the second power supply wiring (502 / 505). / 15b), and the DA conversion circuit (50) includes a plurality of capacitive elements (C0 to C9), and some of the plurality of capacitive elements (C0 to C9) (C0 to C4) include a first The power supply wiring (501 / 504) or the second power supply wiring (502 / 505) is selectively connected. According to the first embodiment, it is possible to maintain good output characteristics of the DA conversion circuit without increasing the area of ​​the semiconductor substrate.

[0117] In the electro-optical device (10) according to specific aspect 2 of aspect 1, the first circuit is a logic circuit (30) that supplies a control signal to the drive circuit (50), and the first power supply potential (VL) is , corresponds to a higher level in the logic circuit (30). According to the second aspect, even if load fluctuation occurs in the H level of the logic signal output from the logic circuit (30), the influence on the output characteristics of the DA conversion circuit is reduced.

[0118] In the electro-optical device (10) according to specific aspect 3 of aspect 2, the power supply circuit generates a first power supply potential (VL) and supplies it to the first power supply wiring (501). A third power supply potential (VPH) different from VL) and the second power supply potential (VPL) is generated and supplied to the third power supply wiring (503), and some of the plurality of capacitive elements (C0 to C9) are generated. The first power supply wiring (501) or the third power supply wiring (503) is selectively connected to the other parts (C5 to C9) except for the first power supply wiring (501) and the third power supply wiring (503).

[0119] In the electro-optical device (10) according to specific aspect 4 of aspect 3, the DA conversion circuit (500) includes a lower DA conversion circuit section (Lwb) and an upper DA conversion circuit section (Upb). The capacitive element included in the circuit section (Lwb) is a part of the plural capacitive elements (C0 to C4), and the capacitive element included in the upper DA conversion circuit section (Upb) is a part of the plural capacitive elements (C0 to C4). C5~C9).

[0120] In the electro-optical device (10) according to a specific example 5 of Aspect 1, the power supply circuit (15b) has a third power supply potential (VLL) different from the first power supply potential (AVDD) and the second power supply potential (VLL). VLH) is generated and supplied to the third power supply wiring (506), and among the plurality of capacitive elements (C0 to C9), except for some (C0 to C4), the other parts (C5 to C9) are The first power supply wiring (504) or the third power supply wiring (506) is selectively connected.

[0121] In the electro-optical device (10) according to specific aspect 6 of aspect 5, the DA conversion circuit (500) includes a lower DA conversion circuit section (Lwb) and an upper DA conversion circuit section (Upb), The capacitive element included in the circuit section (Lwb) is a part of the plural capacitive elements (C0 to C4), and the capacitive element included in the upper DA conversion circuit section (Upb) is a part of the plural capacitive elements (C0 to C4). C5~C9).

[0122] In the electro-optical device (10) according to specific aspect 7 of aspect 6, the first circuit is a logic circuit (30) that supplies a control signal to the drive circuit (50), and the first circuit is a logic circuit (30) that supplies a control signal to the drive circuit (50). The power supply wiring is electrically separated from the first power supply wiring (504), the second power supply wiring (505), and the third power supply wiring (506).

[0123] An electro-optical device (10) according to a specific embodiment 8 of any one of embodiments 1 to 7 includes a pixel circuit (110) including a light emitting element (130), and the pixel circuit (110) includes a DA conversion circuit ( A current corresponding to the voltage output from the light emitting element (130) is supplied to the light emitting element (130).

[0124] An electronic device (300) according to the ninth embodiment includes the electro-optical device (10) according to the eighth embodiment. [Explanation of symbols]

[0125] 10...Electro-optical device, 12...Scanning line, 14...Data line, 14b...Relay line, 100...Display area, 110...Pixel circuit, 121~125...Transistor, 130...OLED, 140...Capacitive element, 300...Head mount Display, 500...DA conversion circuit, 501, 504...Power wiring (1st power wiring), 502, 505...Power wiring (2nd power wiring), 503, 506...Power wiring (3rd power wiring), 508, 509 ...power supply wiring, Upb...upper DA conversion circuit section, Lwb...lower DA conversion circuit section, C0~C9...capacitive element, Cser...capacitive element.

Claims

1. a drive circuit including a DA conversion circuit; A plurality of terminals; a first circuit to which a first power supply potential is supplied from at least one of the plurality of terminals via a first power supply wiring; a power supply circuit that generates a second power supply potential different from the first power supply potential in response to a potential supplied via two or more terminals among the plurality of terminals, and supplies the second power supply potential to a second power supply wiring; Equipped with the DA conversion circuit includes a plurality of capacitance elements, Some of the plurality of capacitive elements include the first power supply wiring or the second power supply wiring is selectively connected; Electro-optical device characterized by:

2. the first circuit is a logic circuit that supplies a control signal to the drive circuit; The first power supply potential corresponds to a high level in the logic circuit.

2. The electro-optical device according to claim 1.

3. The power supply circuit includes: generating the first power supply potential and supplying it to the first power supply wiring; generating a third power supply potential different from the first power supply potential and the second power supply potential, and supplying the third power supply potential to a third power supply wiring; Among the plurality of capacitive elements, the remaining part excluding the part is the first power supply wiring or the third power supply wiring is selectively connected; 3. The electro-optical device according to claim 2.

4. The DA conversion circuit a lower order DA conversion circuit unit and an upper order DA conversion circuit unit, a capacitance element included in the lower-order DA conversion circuit unit is a part of the plurality of capacitance elements, the capacitive element included in the upper DA conversion circuit unit is another part of the plurality of capacitive elements; 4. The electro-optical device according to claim 3.

5. The power supply circuit includes: generating a third power supply potential different from the first power supply potential and the second power supply potential, and supplying the third power supply potential to a third power supply wiring; Among the plurality of capacitive elements, the remaining part excluding the part is the first power supply wiring or the third power supply wiring is selectively connected; 2. The electro-optical device according to claim 1.

6. The DA conversion circuit a lower order DA conversion circuit unit and an upper order DA conversion circuit unit, a capacitance element included in the lower-order DA conversion circuit unit is a part of the plurality of capacitance elements, the capacitive element included in the upper DA conversion circuit unit is another part of the plurality of capacitive elements; 6. The electro-optical device according to claim 5.

7. a logic circuit for supplying a control signal to the drive circuit; A power supply wiring for supplying power to the logic circuit is electrically separated from the first power supply wiring, the second power supply wiring, and the third power supply wiring.

7. The electro-optical device according to claim 5, wherein the first and second electrodes are electrically connected to each other.

8. a pixel circuit including a light-emitting element; In the pixel circuit, a current corresponding to the voltage output from the DA conversion circuit is supplied to the light emitting element.

8. The electro-optical device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

9. An electronic device comprising the electro-optical device according to claim 8.

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