Electro-optical device and image display device

Abstract

To reduce crosstalk and flicker of an image due to miniaturization of an organic EL panel.SOLUTION: An electro-optical device of the present invention comprises: a light emitting device that includes a first electrode, a luminous layer, and a second electrode; a drive transistor that is provided corresponding to the light emitting device; a relay electrode that is electrically connected with a gate electrode of the drive transistor, and is provided on a layer between the gate electrode and the first electrode of the light emitting device; power supply wiring that is provided on the same layer as the relay electrode, extends in a first direction in plan view, and is electrically connected with the first electrode of the light emitting device; and a conductive member that is provided between the relay electrode and the power supply wiring in plan view, and is supplied with a constant potential.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an image display device.

Background Art

[0002] In recent years, an organic EL (Electro-Luminescence) panel (electro-optical device) that displays an image using an organic light emitting diode (Organic Light Emitting Diode; OLED) has been developed, and the application of the organic EL panel to an image display device including a head-mounted display and a projector has been studied. The organic EL panel has an image generation region, and in the image generation region, a plurality of pixel circuits corresponding to a plurality of pixels for generating an image are provided in a matrix. In addition, a plurality of scan lines for driving the plurality of pixel circuits and a plurality of data lines orthogonal to these scan lines are provided in the image generation region, and a pixel circuit is configured in an intersection region of the scan line and the data line.

[0003] For example, Patent Document 1 discloses an electro-optical device including a relay node (relay electrode) electrically connected to a gate electrode of a driving transistor of a pixel circuit and a power supply line (power supply wiring) provided in a circuit on the anode side of an OLED (light emitting element).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the electro-optical device disclosed in Patent Document 1 mentioned above, as the miniaturization of the panel progresses, the distance between the relay node, which is electrically connected to the gate electrode of the transistor in the pixel circuit, and the feed line on the anode side of the OLED becomes narrower, causing parasitic capacitance to occur between the relay node and the feed line. In this situation, when the potential to the gate of the transistor, i.e., the potential of the relay node, changes due to the switching of the level of the control signal supplied to the pixel circuit, the current value flowing through the electrical wiring changes due to the effect of parasitic capacitance between the relay node and the feed line, which becomes a cause of crosstalk. As a result, there was a risk that flickering would be noticeable in the image output from the electro-optical device. [Means for solving the problem]

[0006] To solve the above problems, an electro-optical apparatus according to one aspect of the present invention comprises a light-emitting element including a first electrode, a light-emitting layer, and a second electrode; a drive transistor provided corresponding to the light-emitting element; a relay electrode electrically connected to the gate electrode of the drive transistor and provided in the layer between the gate electrode and the first electrode of the light-emitting element; power supply wiring provided in the same layer as the relay electrode, extending in a first direction in a plan view, and electrically connected to the first electrode of the light-emitting element; and a conductive member provided between the relay electrode and the power supply wiring in a plan view and supplied with a constant potential. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view showing the configuration of the electro-optical device according to the first embodiment. [Figure 2] Figure 1 is a schematic diagram showing the configuration of the electro-optical apparatus. [Figure 3] Figure 1 shows the equivalent circuit diagram of the pixel circuit of each pixel in the electro-optical device. [Figure 4] Figure 1 is a cross-sectional view showing the basic configuration of the pixel circuit of an electro-optical device. [Figure 5] Figure 1 is a plan view of the pixel circuit of an electro-optical device. [Figure 6] Figure 5 is a plan view of the pixel circuit. [Figure 7] Figure 5 is a cross-sectional view of the pixel circuit. [Figure 8] Figure 1 is a schematic diagram showing the configuration of an optical device equipped with an electro-optical apparatus. [Figure 9] Figure 1 is a schematic diagram showing the configuration of an image display device equipped with an electro-optical device. [Figure 10] Figure 9 is a perspective view showing the configuration of the optical system of the image display device shown. [Figure 11] Figure 10 is an optical path diagram of the optical system. [Figure 12] This is a schematic diagram illustrating the layout of the pixel circuit of the electro-optical apparatus according to the second embodiment. [Figure 13] This is a schematic diagram illustrating the layout of the pixel circuit of the electro-optical apparatus according to the third embodiment. [Figure 14] Figure 13 is a schematic diagram illustrating the layout of the pixel circuit in the electro-optical device. [Figure 15] Figure 13 is a schematic diagram illustrating the layout of the pixel circuit in the electro-optical device. [Figure 16] Figure 13 is a cross-sectional view of the pixel circuit of an electro-optical device. [Figure 17] This is a schematic diagram illustrating the layout of the pixel circuit of an electro-optical device in a modified example of the third embodiment. [Figure 18] Figure 17 is a schematic diagram illustrating the layout of the pixel circuit in the electro-optical apparatus. [Figure 19] Figure 17 is a cross-sectional view of the pixel circuit of an electro-optical device. [Figure 20] Figure 17 is a cross-sectional view of the pixel circuit of an electro-optical device. [Figure 21] Figure 1 is a schematic diagram showing the configuration of another image display device equipped with an electro-optical device. [Modes for carrying out the invention]

[0008] [First Embodiment] Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 11. In the following drawings, in order to make each component easy to see, the scale of the dimensions may be changed depending on the component.

[0009] (Electro-optical device) FIG. 1 is a perspective view showing the configuration of the electro-optical device 10G according to the first embodiment. The electro-optical device 10G is a device in which, for example, an OLED is used as the light-emitting element 54G described later. As shown in FIG. 1, the electro-optical device 10G includes a substrate 14, a pixel generation unit 19G, and a plurality of mounting terminals 39. The pixel generation unit 19G and the plurality of mounting terminals 39 are provided on the surface 14a of the substrate 14. The plurality of mounting terminals 39 are arranged at intervals along one side of the rectangular region occupied by the pixel generation unit 19G. One connector portion of the flexible flat cable 70G is connected to the plurality of mounting terminals 39. The other connector portion of the flexible flat cable 70G is connected to a control board (not shown).

[0010] The flexible flat cable 70G is provided with a plurality of wirings 2, 4 and a control circuit 3. One end of each of the plurality of wirings 2 is connected to the plurality of mounting terminals 39. The other end of each of the plurality of wirings 2 is connected to the control circuit 3. The control circuit 3 generates an image signal indicating a potential corresponding to the luminance of the light-emitting element 54G as described later, and supplies it to the mounting terminals 39 via the plurality of wirings 2. One end of each of the plurality of wirings 4 is connected to the control circuit 3. The other end of each of the plurality of wirings 4 is connected to a higher-level circuit (not shown).

[0011] FIG. 2 is a plan view showing the configuration of the electro-optical device 10G. In FIG. 2, the horizontal direction of the surface 14a of the substrate 14 of the electro-optical device 10G is taken as the X direction, and the vertical direction perpendicular to the X direction of the surface 14a is taken as the Y direction. As shown in FIG. 2, a pixel generation unit 19G is provided on the surface 14a of the substrate 14. The surface 14a includes a pixel region 12G and a non-pixel region 13G. In the pixel region 12G, a plurality of pixels 11G are arranged in a matrix along the X direction and the Y direction, and are rectangular regions when viewed from a direction perpendicular to the X direction and the Y direction. In the pixel region 12G, a plurality of scanning lines 31 extending parallel to the X direction and a plurality of data lines 33 extending parallel to the Y direction are provided. The pixel 11G is configured corresponding to each region where the plurality of scanning lines 31 and the plurality of data lines 33 intersect. The pixel circuit included in the pixel 11G will be described later.

[0012] The non-pixel region 13G includes a peripheral region 15 and a mounting region 16. The peripheral region 15 is a rectangular frame-shaped region surrounding the pixel region 12G when viewed from a direction perpendicular to the X direction and the Y direction. In the peripheral region 15, a drive circuit 35 for driving a plurality of pixels 11G is provided. The drive circuit 35 includes scanning line drive circuits 36A and 36B and a data line drive circuit 37. In the electro-optical device 10G, since the drive circuit 35 is formed on the surface 14a of the substrate 14 as described above, the electro-optical device 10G is a circuit-integrated device composed of active elements including transistors.

[0013] The mounting region 16 is a region provided on the opposite side of the pixel region 12G in the Y direction with respect to the data line drive circuit 37 provided in the peripheral region 15, that is, a region provided outside the peripheral region 15. In the mounting region 16, a plurality of mounting terminals 39 are provided. At least a video signal and a power supply voltage necessary for driving a plurality of pixels 11G of the electro-optical device 10G are input to the mounting terminals 39.

[0014] Figure 3 is an equivalent circuit diagram of the pixel circuit of pixel 11G. Since the configuration of the pixel circuits of multiple pixels 11G are common to each other, the pixel circuit of pixel 11G in the i-th row and j-th column will be used as an example for explanation. i represents the row number where pixel 11G is located, and is an integer between 1 and m. j represents the column number where pixel 11G is located, and is an integer between 1 and n. The pixel circuit of pixel 11G includes a selection transistor 51G, a drive transistor 52G, a light-emitting element 54G, and a holding capacitor 55G. The selection transistor 51G and the drive transistor 52G are, for example, P-channel type metal-oxide-semiconductor field-effect transistors (MOS-FETs).

[0015] The gate electrode of the selection transistor 51G is electrically connected to the scan line 31 in row i. One of the source / drain regions of the selection transistor 51G is electrically connected to the data line 33 in column j. The other of the source / drain regions of the selection transistor 51G is electrically connected to the gate electrode of the drive transistor 52G and one electrode of the retaining capacitor 55G. The back gate of the selection transistor 51G is electrically connected to the power supply wiring 61G to which the power supply potential is applied.

[0016] The gate electrode of the drive transistor 52G is electrically connected to the other region of the source / drain region of the selection transistor 51G, and to one electrode of the retaining capacitor 55G. One region of the source / drain region of the drive transistor 52G is electrically connected to a power supply line 63, which is separate from the power supply line 61G. The other region of the source / drain region of the drive transistor 52G is electrically connected to one electrode of the light-emitting element 54G, i.e., the anode AN. The back gate of the drive transistor 52G is electrically connected to the power supply line 61G.

[0017] The light-emitting element 54G is a light-emitting element that emits green light. The light-emitting layer EM of the light-emitting element 54G is sandwiched between the anode and the other electrode of the light-emitting element 54G, i.e., the cathode CT, and is, for example, an OLED or a micro-LED (μLED). One electrode of the light-emitting element 54G is electrically connected to the other region of the source / drain region of the drive transistor 52G. The other electrode of the light-emitting element 54G is electrically connected to the power supply wiring 62G to which the power supply potential is applied.

[0018] The retaining capacitor 55G is a capacitor for maintaining the voltage between the gate electrode of the drive transistor 52G and the aforementioned one of the source / drain regions of the drive transistor 52G. One electrode of the retaining capacitor 55G is electrically connected to the aforementioned other region of the source / drain region of the selection transistor 51G and the gate electrode of the drive transistor 52G. The other electrode of the retaining capacitor 55G is electrically connected to a power supply wiring (not shown) separate from the power supply wiring 61G. Note that the retaining capacitor 55G may be a capacitance parasitic to the gate electrode of the drive transistor 52G, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a Si substrate may be used.

[0019] In the pixel circuit of pixel 11G configured as described above, when the scan signal GWR(i) supplied to the i-th row scan line 31 is at a high (High:H) level, the selection transistor 51G is in the OFF state. On the other hand, when the scan signal GWR(i) is at a low (L) level, the selection transistor 51G is in the ON state. When the selection transistor 51G is in the ON state, current flows through the retaining capacitor 55G according to the potential difference Vd1 between the potential of the data line 33 and the potential of the other electrode of the retaining capacitor 55G, and the retaining capacitor 55G is charged until the voltage between the electrodes of the retaining capacitor 55G becomes the potential difference Vd1.

[0020] When the gate potential of the drive transistor 52G exceeds the threshold voltage of the drive transistor 52G, a drive current flows from the power supply wiring 63 to the power supply wiring 62G via the drive transistor 52G and the light-emitting element 54G. The value of the drive current is controlled by the gate potential of the drive transistor 52G. The voltage between the gate electrode of the drive transistor 52G and one of the aforementioned source / drain regions of the drive transistor 52G, which is electrically connected to the power supply wiring 63, is equal to the voltage held by the retaining capacitor 55G, i.e., the voltage between the electrodes of the retaining capacitor 55G. Therefore, the drive current has a current value corresponding to the voltage held by the retaining capacitor 55G. Furthermore, when the drive current flows to the light-emitting element 54G, the light-emitting element 54G emits green light with an intensity corresponding to the drive current.

[0021] Figure 4 is a cross-sectional view showing the basic configuration of the bottom of the pixel circuit shown in Figure 3. In each drawing from Figure 4 onward, the Z direction is defined as the direction perpendicular to the X and Y directions, parallel to the thickness direction of the pixel circuit, and opposite to the vertical direction. In the explanation referring to Figure 4, and in the claims described later, the plan view means observing along the direction perpendicular to the X and Y directions, i.e., the Z direction, and observing the surface 150a of the semiconductor substrate 150 from above the semiconductor substrate 150 along the direction perpendicular to the surface 150a of the semiconductor substrate 150. Hereinafter, the front surface of each component in the Z direction will be referred to as the surface, and the rear surface of each component in the Z direction will be referred to as the bottom surface.

[0022] As shown in Figure 4, each component of the pixel circuit of pixel 11G is formed on a P-type semiconductor substrate 150 made of Si substrate, that is, in front of the surface 150a of the semiconductor substrate 150 in the Z direction. In the upper region of the semiconductor substrate 150 including the surface 150a, that is, the front region of the semiconductor substrate 150 in the Z direction, an N-type well 160 is formed over the entire surface 150a. An N-type impurity dopant is injected into the N-type well 160 at an appropriate concentration. An appropriate concentration of each type of impurity dopant means a concentration that, considering the characteristics of the semiconductor substrate 150, can stably maintain the electrical characteristics and desired effects of the region containing the impurity dopant on the semiconductor substrate 150.

[0023] In the N-type well 160, in the upper region including the surface 150a of the semiconductor substrate 150, multiple P-type diffusion regions Pj and one or more N-type diffusion regions Nk are formed for each pixel circuit of one pixel 11G. Each of j and k is an arbitrary natural number. For the pixel circuit of pixel 11G, in the basic structure illustrated in Figure 4, for example, six P-type diffusion regions P1 to P6 and one N-type diffusion region N1 are formed in the N-type well 160. The P-type diffusion regions Pj are formed by injecting a P-type impurity dopant at an appropriate concentration into the surface 150a of a predetermined region of the N-type well 160. That is, the P-type diffusion regions Pj contain a P-type impurity dopant. The N-type diffusion regions Nk are formed by injecting an N-type impurity dopant at an appropriate concentration into the surface 150a of a predetermined region of the N-type well 160 that is different from the region where the P-type diffusion regions Pj are formed in a plan view. In other words, the N-type diffusion region Nk contains more N-type impurity dopants than the surrounding N-type well 160.

[0024] The P-type diffusion region Pj acts as the source or drain region of transistor 56, which includes the selection transistor 51G and the drive transistor 52G. In the N-type well 160, a frame-shaped STI (Shallow Trench Isolation) 171 is provided surrounding the P-type diffusion regions PA and PB used for one transistor 56 in a plan view. The provision of the STI 171 reduces leakage current between adjacent transistors 56 in a plan view, ensuring withstand voltage.

[0025] Transistor 56 is a P-channel MOS-FET having at least a gate electrode layer G and P-type diffusion regions PA and PB. The P-type diffusion region PA acts as one of the source / drain regions of transistor 56. The P-type diffusion region PB acts as the other of the source / drain regions of transistor 56.

[0026] Of the transistors 56, the driving transistor 52G has a gate electrode layer G1, P-type diffusion regions P1 and P2, and an N-type diffusion region N1. The P-type diffusion region P1 acts as one of the source / drain regions of the driving transistor 52G. The P-type diffusion region P2 acts as the other of the source / drain regions of the driving transistor 52G. The N-type diffusion region N1 acts as the body power supply of the transistor 56.

[0027] In the N-type well 160, an STI 172 is provided in a frame shape that surrounds the N-type diffusion region N1 used for the drive transistor 52G in a plan view. Figure 4 shows the STI 171 that surrounds the P-type diffusion regions PA and PB in a plan view, with the STI 171 positioned on either side of the P-type diffusion regions PA and PB in the X direction, and the STI 172 that surrounds the N-type diffusion region N1 in a plan view, with the STI 172 positioned on either side of the N-type diffusion region N1 in the X direction. A portion of the STI 172 is shared with the STI 171 that surrounds the P-type diffusion regions P1 and P2.

[0028] The potential of the N-type diffusion region N1 of the drive transistor 52G is set and supplied to be equivalent to the high potential applied to the source region.

[0029] A gate insulating layer L0 is formed on the surface of the N-type well 160, the P-type diffusion region Pj, and the N-type diffusion region Nk, i.e., the surface 150a of the semiconductor substrate 150. The gate insulating layer L0 is made of, for example, silicon oxide (SiO2). In a plan view, the gate electrode layer G of the transistor 56, or the gate electrode layer G1 of the driving transistor, is formed on the surface of the gate insulating layer L0 between the P-type diffusion regions PA, P1 and the P-type diffusion regions PB, P2, for example by patterning. The gate electrode layers G, G1 are made of, for example, polycrystalline silicon (Poly-Si). An interlayer insulating layer L1 is provided to cover the gate electrode layers G, G1 and the gate insulating layer L0.

[0030] In a plan view, contact holes are formed in at least a portion of the regions where each of the P-type diffusion regions Pj is formed, penetrating from the surface of the interlayer insulating layer L1 through the interlayer insulating layer L1 and the gate insulating layer L0 in the Z direction to reach each of the P-type diffusion regions Pj. In addition, in a plan view, contact holes are formed in at least a portion of the regions where the gate electrode layers G and G1 are formed, penetrating from the surface of the interlayer insulating layer L1 through the interlayer insulating layer L1 in the Z direction to reach the gate electrode layers G and G1. Furthermore, in a plan view, contact holes are formed in at least a portion of the regions where each of the N-type diffusion regions Nk is formed, penetrating from the surface of the interlayer insulating layer L1 through the interlayer insulating layer L1 and the gate insulating layer L0 in the Z direction to reach each of the N-type diffusion regions Nk.

[0031] Contact plugs C1 to C4 are formed by filling each contact hole with a conductive material. The aforementioned conductive material is, for example, tungsten (W). However, the aforementioned conductive material may be the same as the conductive material constituting the scan lines 31, data lines 33, power wiring 61G, or each electrode layer, and the contact holes may be filled with the conductive material constituting the scan lines 31, data lines 33, or power wiring 61G during the transistor 56 formation process. One end of contact plug C1, i.e., the rear end in the Z direction, is electrically connected to the P-type diffusion regions PA, P1. One end of contact plug C2 is electrically connected to the P-type diffusion regions PB, P2. One end of contact plug C3 is electrically connected to the gate electrode layers G, G1. One end of contact plug C4 of the drive transistor 52G is electrically connected to the N-type diffusion region N1. The other end faces of each of the contact plugs C1 to C4 are flush with the surface of the interlayer insulating layer L1.

[0032] An electrode layer A3 is formed, for example, by patterning, in a predetermined area of ​​the surface of the interlayer insulating layer L1 including the other end face of the contact plug C1. Electrode layer A3 is a component that forms part of the electrode layer constituting one of the regions in the source / drain region of transistor 56 where the P-type diffusion regions PA and P1 act, or a component that is electrically connected to the electrode layer constituting the aforementioned one region. An electrode layer A4 is formed, for example, by patterning, in a predetermined area of ​​the surface of the interlayer insulating layer L1 including the other end face of the contact plug C2. Electrode layer A4 is a component that forms part of the electrode layer constituting the other region in the source / drain region of transistor 56 where the P-type diffusion regions PB and P2 act, or a component that is electrically connected to the electrode layer constituting the aforementioned other region.

[0033] A relay layer T1 is formed, for example, by patterning, in a predetermined area of ​​the surface of the interlayer insulating layer L1 including the other end face of the contact plug C3. The relay layer T1 is a relay member (relay electrode) electrically connected to the gate electrode layer G of each transistor 56. An electrode layer A6 is formed, for example, by patterning, in a predetermined area of ​​the surface of the interlayer insulating layer L1 including the other end face of the contact plug C4 of the drive transistor 52G. The electrode layer A6 is a member electrically connected to the power supply wiring 61G of the transistor 56.

[0034] For example, in the image circuit shown in Figure 3, it is assumed that the source region of the selection transistor 51G is electrically connected to the data line 33 in column j, and the drain region of the selection transistor 51G is electrically connected to the gate electrode of the drive transistor 52G and one electrode of the retaining capacitor 55G. It is also assumed that the drain region of the drive transistor 52G is electrically connected to the anode AN of the light-emitting element 54G, and the source region of the drive transistor 52G is electrically connected to the power supply wiring 63.

[0035] In the above assumption, it is assumed that the P-type diffusion region P1 of the basic configuration of the selection transistor 51G in the image circuit shown in Figure 4 acts as the source region, and the P-type diffusion region P2 acts as the drain region. In this case, the electrode layers A3 and A13 electrically connected to the selection transistor 51G are either part of the conductive layer constituting the data line 33, or electrically connected to the conductive layer constituting the data line 33. For example, the electrode layers A3 and A13 are electrically connected to the conductive layer constituting the data line 33 by a conductive member (not shown) extending along a plane parallel to the X and Y directions, or by a contact plug (not shown) extending along the Z direction. The electrode layers A4 and A14 are electrically connected to the relay layers T1 and T11 as shown by the dashed lines. For example, the electrode layers A4 and A14 may be electrically connected to the relay layers T1 and T11 by a conductive member (not shown) extending along a plane parallel to the X and Y directions, or by a contact plug (not shown) extending along the Z direction. The electrode layer A50, which is made of conductive material between electrode layers A4 and A14 and relay layers T1 and T11, and the contact plug (not shown), are electrically connected to the conductive layer that constitutes one of the electrodes with a holding capacity of 55G.

[0036] The relay layers T1 and T11 are either part of the conductive layers that make up the scan line 31, or are electrically connected to the conductive layers that make up the scan line 31.

[0037] Furthermore, assuming that the P-type diffusion region P1 of the basic configuration of the drive transistor 52G in the image circuit shown in Figure 4 acts as the drain region and the P-type diffusion region P2 acts as the source region, the electrode layers A3 and A13 are either part of the conductive layer constituting the power supply wiring 63 or are electrically connected to the conductive layer constituting the power supply wiring 63. The electrode layers A4 and A14 are electrically connected to one electrode of the light-emitting element 54G, i.e., the electrode constituting the anode AN, and specifically are electrically connected to the electrode layer A100, which will be described later.

[0038] As described above, the relay layers T1 and T11 are electrically connected to the electrode layers A4 and A14. The electrode layers A6 and A16 are either part of the conductive layer constituting the power wiring 63, or are electrically connected to the conductive layer constituting the power wiring 63.

[0039] In the basic structure of the pixel circuit of pixel 11G shown in Figure 4, an interlayer insulating layer L2 is provided that covers electrode layers A3, A4, A6, a relay layer T1, and an interlayer insulating layer L1. On the surface of the interlayer insulating layer L2, there is an electrode layer A13 electrically connected to electrode layer A3, an electrode layer A14 electrically connected to electrode layer A4, an electrode layer A16 electrically connected to electrode layer A6, and a relay layer T11 electrically connected to relay layer T1. For example, electrode layers A3 and A13 are connected by a contact plug C11. The contact plug C11 can be formed by filling a conductive material into a contact hole formed in the interlayer insulating layer L2 that penetrates between electrode layers A3 and A13. Similarly, electrode layers A4 and A14 are connected by a contact plug C12. The contact plug C12 can be formed by filling a conductive material into a contact hole formed in the interlayer insulating layer L2 that penetrates between electrode layers A4 and A14. The relay layers T1 and T11 are connected by a contact plug C13. The contact plug C13 can be formed by filling a conductive material into a contact hole formed in the interlayer insulating layer L2 that penetrates between the relay layers T1 and T11. The electrode layers A6 and A16 of the drive transistor 52G are connected by a contact plug C14. The contact plug C14 can be formed by filling a conductive material into a contact hole formed in the interlayer insulating layer L2 that penetrates between the electrode layers A6 and A16.

[0040] In the basic structure of the pixel circuit of pixel 11G shown in Figure 4, electrode layers A13, A14, A16, a relay layer T11, and an interlayer insulating layer L3 covering the interlayer insulating layer L2 are provided. An electrode layer A100 electrically connected to electrode layer A14 is provided on the surface of the interlayer insulating layer L3. The size of electrode layer A100 in plan view corresponds to one pixel 11G. For example, electrode layers A14 and A100 are connected by a contact plug C21. Electrode layer A100 is an electrode layer that constitutes one electrode, i.e., anode AN, of the light-emitting element 54G, or an electrode layer electrically connected to anode AN of the light-emitting element 54G.

[0041] Each of the electrode layers A3, A4, A6, A13, A14, A16, and the intermediate layers T1, T11 is formed of a metal, for example, copper (Cu). Each of the interlayer insulating layers L1 to L3 is formed of, for example, SiO2.

[0042] In the pixel circuit of pixel 11G shown in Figure 4, the electrode layer A100 is the outermost layer component. However, interlayer insulating layers, insulating layers, semiconductor layers, and conductive layers (not shown) may be provided above the electrode layer A100, i.e., in front of the electrode layer A100 in the Z direction. The layered structure of the pixel circuit of pixel 11G is designed appropriately based on the optical and electrical performance required of the electro-optical device 10G. For example, at least one of the electrode layers A13, A16, relay layer T11, and contact plugs C11, C13, C14 may be omitted as appropriate.

[0043] In the pixel circuit of pixel 11G of the electro-optical device 10G of the first embodiment, when the P-type diffusion regions PB and P2 act as the source region of the drive transistor 52G, the electrode layer A6 extends between the electrode layer A4 and the relay layer T1 in a plan view of the surface of the interlayer insulating layer L1. The plan view layout of each component in the pixel circuit of pixel 11G is designed appropriately, taking into account the optical and electrical performance required of the electro-optical device 10G, as well as constraints on the shape and size of the electro-optical device 10G.

[0044] Figure 5 is a schematic diagram showing a plan view of the layout of the pixel circuit of the pixel 11G of the first embodiment, as appropriately designed, on the surface of the interlayer insulating layer L1. Figure 6 is a schematic diagram showing a plan view of the layout of the pixel circuit of the pixel 11G of the first embodiment, as appropriately designed, on the surface of the gate insulating layer L0. Figure 7 is a diagram showing the configuration of the pixel circuit formed with the layouts shown in Figures 5 and 6, and is a cross-sectional view taken along the line X1-X2 shown in Figure 5. Note that in Figure 7, the configuration above the electrode layers A4, A6 and the relay layer T1, i.e., the configuration in front of the electrode layers A4, A6 and the relay layer T1 in the Z direction, is omitted.

[0045] The relay layer T1 shown in Figure 5 is a conductive layer electrically connected to the gate electrode layer G1 of the drive transistor 52G in the equivalent circuit diagram shown in Figure 3. G1(51G) in Figure 6 represents the gate electrode layer G1 of the selection transistor 51G, and G1(52G) in the same figure represents the gate electrode layer G1 of the drive transistor 52G. The contact plug C1 shown in Figure 6 is formed in front of the relay layer T1 in the Y direction and is electrically connected to an anode AN (not shown). The contact plug C2 shown in Figure 6 is electrically connected to electrode layer A4, which is formed behind the relay layer T1 in the Y direction as shown in Figure 5. The contact plug C3 shown in Figure 6 is electrically connected to the relay layer T1 shown in Figure 5. The contact plug C4 shown in Figure 6 is electrically connected to electrode layer A6C, which is part of electrode layer A6 shown in Figure 5. Electrode layer A6C is formed behind electrode layer A6A and relay layer T1 in the Y direction, connects electrode layer A6B which extends along the X direction, and extends along the Y direction.

[0046] As shown in Figures 5 and 7, in the pixel circuit of the pixel 11G of the electro-optical device 10G of the first embodiment, electrode layer A6B is arranged between electrode layer A4 of the drive transistor 52G and relay layer T1 in the Y direction on the surface of the gate insulating layer L0 in plan view and cross view. In this case, electrode layer A4 is electrically connected to the P-type diffusion regions P2,PB which act as source regions, specifically via contact plug C2. Relay layer T1 is electrically connected to gate electrode layers G1,G, specifically via contact plug C3. In the pixel circuit of the pixel 11G of the electro-optical device 10G of the first embodiment, electrode layers A6C and A6B are newly formed extending from electrode layer A6A, which is at least required for the drive transistor 52G, i.e., electrode layer A6 which is electrically connected to the N-type diffusion region N1 via contact plug C4, thereby providing electrode layer A6B between electrode layer A4 and relay layer T1 in the Y direction.

[0047] Since each of the electrode layers A6A, A6B, and A6C constituting electrode layer A6 is electrically connected to the N-type diffusion regions N1 and Nk formed on the semiconductor substrate 150, the resistance of each electrode layer A6A, A6B, and A6C is lower than that of the power supply wiring 61G, and the potential of each electrode layer A6A, A6B, and A6C is more stable than that of the power supply wiring 61G. As described above, since electrode layer A6B is provided on the same layer as the interlayer insulating layer L1 on the surface between electrode layer A4 and relay layer T1, the gate electrode layers G1 and G of the drive transistor 52G and the power supply wiring 61G are stably shielded.

[0048] Next, a brief explanation will be given of the manufacturing method for the basic structure of the pixel circuit of the electro-optical device 10G of the first embodiment illustrated in Figures 4 to 7. Although not shown, an N-type impurity dopant is injected, for example, from the front in the Z direction, over the entire surface 150a of the semiconductor substrate 150, including the surface of the P-type Si substrate constituting the semiconductor substrate 150, to form an N-type well 160. Subsequently, an ionized P-type impurity dopant is injected, for example, from the front in the Z direction, into small regions that are different from each other in the region of the N-type well 160 in a plan view and will be designated as the source region or drain region of the transistor 56, to form a P-type diffusion region Pj. Subsequently, an ionized N-type impurity dopant is injected, for example, from the front in the Z direction, into small regions that are different from the P-type diffusion region Pj in a plan view within the region of the N-type well 160 and will be designated as the power supply wiring 61G of the transistor 56, to form an N-type diffusion region Nk. Next, the N-type well 160 is removed in a frame-like manner to surround the P-type diffusion regions Pj that constitute the source and drain regions within the N-type well 160 in a plan view, thereby forming a groove surrounding the P-type diffusion regions Pj that constitute the source and drain regions. The insulating material constituting the STI 171 is formed by filling this groove and extending forward in the Z direction beyond the surface 150a of the semiconductor substrate 150, for example, by a method such as plasma chemical vapor deposition (CVD). After that, the upper part of the deposited layer made of insulating material is removed using, for example, a CMP (Chemical Mechanical Polisher) apparatus until the surface 150a of the semiconductor substrate 150, i.e., the surface of the N-type well 160, is exposed. For example, SiO2 can be used as the insulating material.

[0049] Next, a gate insulating layer L0 made of SiO2 is formed on the surface 150a of the semiconductor substrate 150 by a film deposition method, for example, a thermal oxidation method or a sputtering apparatus. Subsequently, an insulating material constituting an interlayer insulating layer L1 is deposited on the surface of the gate insulating layer L0 to the same thickness as the gate electrode layer G, for example, by a CVD method. If necessary, the surface of the insulating layer made of insulating material is planarized. Next, the insulating layer in a small region that will become the gate electrode layer G in a planar view is removed to form a hole. Poly-Si, for example, is grown inside the hole as the material constituting the gate electrode layer G, and the gate electrode layer G is formed in the hole. If necessary, the surface of the gate electrode layer G may be planarized so that it is flush with the surface of the surrounding insulating layer.

[0050] Next, an insulating material is formed on the gate electrode layer G and the surface of the surrounding insulating layer in a plan view, for example by atomic layer deposition (ALD), to form an interlayer insulating layer L1. Then, in the interlayer insulating layer L1, in the regions that overlap with the P-type diffusion region Pj and the N-type diffusion region Nk in a plan view, contact holes are formed that penetrate the interlayer insulating layer L1 and the gate insulating layer L0 to the surface of the P-type diffusion region Pj and the N-type diffusion region Nk, respectively, by patterning and reactive ion etching (RIE). In addition, in the interlayer insulating layer L1, in the region that overlaps with the gate electrode layer G in a plan view, contact holes are formed that penetrate the interlayer insulating layer L1 to the surface of the gate electrode layer G, for example by patterning and reactive ion etching (RIE). Subsequently, conductive material is embedded inside each contact hole to form contact plugs C1 to C4. If necessary, the surfaces of contact plugs C1 to C4 may be flattened so that they are flush with the surface of the interlayer insulating layer L1.

[0051] Next, conductive materials constituting electrode layers A3, A4, A6 and relay layer T1 are formed on the surfaces of contact plugs C1 to C4 and the interlayer insulating layer L1. Then, using patterning and RIE methods, conductive layers made of conductive material are removed from the conductive layers, leaving the areas that will be designated as electrode layers A3, A4, A6 and relay layer T1 in a plan view, thereby forming electrode layers A3, A4, A6 and relay layer T1 on the surface of the interlayer insulating layer L1. In the mask patterns of electrode layers A3, A4, A6 and relay layer T1 used in this process, the area of ​​electrode layer A6 is positioned between the area of ​​electrode layer A4 and the area of ​​relay layer T1 in a plan view, i.e., in a predetermined direction parallel to the surface of the mask substrate. The predetermined direction represents the direction in which the electrode layer A4, which is electrically connected to the P-type diffusion region Pj acting as the source region of transistor 56, and the relay layer T1, which is electrically connected to the gate electrode layer G of transistor 56, are arranged with a distance between them, as illustrated in Figures 4 and 7. That is, when forming electrode layers A3, A4, A6 and relay layer T1 on the surface of the interlayer insulating layer L1, a mask having a pattern that matches the layout shown in Figure 5 in plan view is used.

[0052] Next, an interlayer insulating layer L2 made of insulating material is formed, for example, using the ALD method, so as to cover each of the interlayer insulating layer L1, electrode layers A3, A4, A6, and intermediate layer T1. Contact holes are formed in the interlayer insulating layer L2 in the regions that overlap with each of the electrode layers A3, A4, A6, and intermediate layer T1 in a plan view, for example, by patterning and reactive ion etching (RIE) to penetrate the interlayer insulating layer L2 to the surface of each of the electrode layers A3, A4, A6, and intermediate layer T1. Subsequently, conductive material is embedded inside each contact hole to form contact plugs C11 to C14. If necessary, the surfaces of the contact plugs C11 to C14 may be flattened so that they are flush with the surface of the interlayer insulating layer L2.

[0053] Next, conductive materials constituting electrode layers A13, A14, A16 and intermediate layer T11 are formed on the surfaces of contact plugs C11 to C14 and the interlayer insulating layer L2. Then, using patterning and RIE methods, conductive layers made of conductive material are removed from the conductive layers in the regions that will be designated as electrode layers A13, A14, A16 and intermediate layer T11 in a plan view, thereby forming electrode layers A13, A14, A16 and intermediate layer T11 on the surface of the interlayer insulating layer L2.

[0054] Next, an interlayer insulating layer L3 made of insulating material is formed, for example, using the ALD method, so as to cover the interlayer insulating layer L2, electrode layers A13, A14, A16, and relay layer T11. In the interlayer insulating layer L3, in the region that overlaps with the electrode layer A16 of the drive transistor 52G in a plan view, a contact hole is formed that penetrates the interlayer insulating layer L3 to the surface of the electrode layer A16, for example, by patterning and the RIE method. Next, a conductive material is embedded inside the contact hole to form a contact plug C21. If necessary, the surface of the contact plug C21 may be flattened so that it is flush with the surface of the interlayer insulating layer L3. Next, the conductive material constituting the electrode layer A100 is formed on the surface of the contact plug C21 and the surface of the interlayer insulating layer L3.

[0055] The pixel circuit of the electro-optical device 10G of the first embodiment can be manufactured through the process described above. If necessary, the interlayer insulating layer L2, contact plugs C11 to C14, and the components may be laminated in the Z direction on the surface of the electrode layer A100 through the same process as for the electrode layers A13, A14, A16 and the relay layer T11.

[0056] (Image display device) Next, an image display device equipped with the electro-optical device 10G of the first embodiment will be described. Figure 8 is a schematic diagram showing the configuration of the optical device 1 equipped with the electro-optical device 10G of the first embodiment. As shown in Figure 8, the optical device 1 comprises electro-optical devices 10G, 10B, and 10R, and a dichroic prism 20. The electro-optical device 10G is a self-emissive electro-optical device that emits green image light LG into the dichroic prism 20. The electro-optical device 10B has the same configuration as the electro-optical device 10G described above, and is a self-emissive electro-optical device that emits blue image light LB into the dichroic prism 20. The electro-optical device 10R has the same configuration as the electro-optical device 10G, and is a self-emissive electro-optical device that emits red image light LR into the dichroic prism 20. Each of the electro-optical devices 10G, 10B, and 10R is an organic EL panel.

[0057] The green wavelength range of the image light LG includes, for example, the wavelength range from 495 nm to 570 nm. Multiple pixels 11G of the electro-optical device 10G emit green light. The image light LG emitted from the electro-optical device 10G is composed of the green light emitted from each of the multiple pixels 11G.

[0058] The surface 14a of the substrate 14 of the electro-optical device 10G faces the incident surface 22 of the green light from the dichroic prism 20 and is bonded to the incident surface 22 via a translucent adhesive layer 40G. In other words, the electro-optical device 10G is positioned so that the image light LG is incident perpendicularly to the incident surface 22.

[0059] The electro-optical device 10B is a device that uses an OLED or μLED as a light-emitting element and comprises a pixel region 12B including a plurality of pixels 11B and a non-pixel region 13B. The blue wavelength range of the image light LB includes, for example, a wavelength range from 450 nm to 490 nm. The plurality of pixels 11B of the electro-optical device 10B emit blue light. The image light LB emitted from the electro-optical device 10B is composed of the blue light emitted from each of the plurality of pixels 11B.

[0060] The surface 14a of the substrate 14 of the electro-optical device 10B faces the incident surface 21 of the blue light from the dichroic prism 20 and is bonded to the incident surface 21 via a light-transmitting adhesive layer 40B. In other words, the electro-optical device 10B is positioned so that the image light LB is incident perpendicularly to the incident surface 21.

[0061] The electro-optical device 10R is a device that uses an OLED or μLED as a light-emitting element and comprises a pixel region 12R including a plurality of pixels 11R and a non-pixel region 13R. The red wavelength range of the image light LR includes, for example, a wavelength range from 610 nm to 680 nm. The plurality of pixels 11R of the electro-optical device 10R emit red light. The image light LR emitted from the electro-optical device 10R is composed of the red light emitted from each of the plurality of pixels 11R.

[0062] The surface 14a of the substrate 14 of the electro-optical device 10R faces the incident surface 23 of the red light from the dichroic prism 20 and is bonded to the incident surface 23 via a translucent adhesive layer 40R. In other words, the electro-optical device 10R is positioned so that the image light LR is incident perpendicularly to the incident surface 23.

[0063] Each of the image lights LG, LB, and LR is unpolarized light that does not possess polarization characteristics and does not have a specific direction of vibration. Note that unpolarized light, i.e., light without polarization characteristics, is not completely unpolarized; it contains some degree of polarization, but it has a degree of polarization that is considered not to significantly affect the optical performance of optical components, such as dichroic mirrors.

[0064] The dichroic prism 20 is composed of a translucent member having a rectangular prism shape. The rectangular prism translucent member is composed of four triangular prism translucent members combined together. The dichroic prism 20 has an incident surface 21, 22, 23 and an exit surface 24. The dichroic prism 20 further has a first dichroic mirror 25 that does not have polarization separation characteristics and a second dichroic mirror 26 that does not have polarization separation characteristics. The first dichroic mirror 25 and the second dichroic mirror 26 intersect each other at a 90° angle. The first dichroic mirror 25 reflects the image light LB incident on the incident surface 21 toward the exit surface 24 and transmits the image light LG incident on the incident surface 22 toward the exit surface 24. The second dichroic mirror 26 reflects the image light LR incident via the incident surface 23 toward the emission surface 24, and transmits the image light LG incident via the incident surface 22 toward the emission surface 24. Due to the properties of the first dichroic mirror 25 and the second dichroic mirror 26, the image light LG, LB, and LR are combined to produce a composite image light LW which is emitted from the emission surface 24.

[0065] Figure 9 is a schematic diagram showing the configuration of a head-mounted display (image display device) 1000, which is an image display device of the first embodiment. The head-mounted display 1000 is configured as a see-through type eyeglass display and has a frame 1110 with temples 1111 and 1112 on the left and right sides. The virtual image display unit 1010 is supported by the frame 1110 and causes the user (not shown) to perceive the image projected from the virtual image display unit 1010 as a virtual image.

[0066] The head-mounted display 1000 comprises a virtual image display unit 1010, which includes a left-eye display unit 1101 and a right-eye display unit 1102. The left-eye display unit 1101 and the right-eye display unit 1102 have the same configuration and are arranged symmetrically. Figure 10 is a perspective view showing the configuration of the optical system of the virtual image display unit 1010. Figure 11 is a schematic diagram showing the optical path of the optical system shown in Figure 10, and is a view taken from a direction perpendicular to the surface of the light guide unit 1050. As shown in Figures 10 and 11, the left-eye display unit 1101 comprises an optical device 1 and a light guide system 1030 that guides the composite image light LW emitted from the optical device 1 to the emission unit 1058. A projection lens system 1070 is arranged between the optical device 1 and the light guide system 1030. The composite image light LW emitted from the optical device 1 is incident on the light guide system 1030 via the projection lens system 1070. The projection lens system 1070 consists of a single collimating lens with positive power.

[0067] The light guide system 1030 comprises a translucent incident section 1040 into which the composite image light LW is incident, and a translucent light guide section 1050, one end 1051 of which is connected to the incident section 1040. The incident section 1040 and the light guide section 1050 are composed of a single, integrated translucent member.

[0068] Although no reflective film is formed on the incident surface 1041, the incident surface 1041 possesses light transmittance and light reflectivity, and totally reflects light incident at an incident angle greater than the critical angle. The reflective surface 1042 faces the incident surface 1041. One end 1422 of the reflective surface 1042 is spaced further from the incident surface 1041 than the other end 1421 of the reflective surface 1042. That is, the incident portion 1040 has a roughly triangular shape. The reflective surface 1042 consists of a plane, an aspherical surface, or a free-form surface, etc. The reflective surface 1042 has a structure in which a reflective metal layer mainly composed of aluminum, silver, magnesium, chromium, etc. is formed.

[0069] The light guide section 1050 comprises a first surface 1056 extending from one end 1051 to the other end 1052, a second surface 1057 extending from end 1051 to end 1052 parallel to and opposite to the first surface 1056, and an ejection section 1058 provided on the portion of the second surface 1057 spaced apart from the incident section 1040. The first surface 1056 and the reflective surface 1042 of the incident section 1040 are continuous via an inclined surface 1043. The distance between the first surface 1056 and the second surface 1057 is less than the thickness of the incident section 1040. The first surface 1056 and the second surface 1057 totally reflect light incident at an incident angle greater than or equal to a critical angle, based on the refractive index difference between the light guide section 1050 and the surrounding air. Therefore, no reflective film is formed on the first surface 1056 and the second surface 1057.

[0070] The ejection section 1058 is located on a part of the second surface 1057 side in the thickness direction of the light guide section 1050. In the ejection section 1058, a plurality of partial reflective surfaces 1055 are arranged parallel to each other and are inclined with respect to a direction perpendicular to the second surface 1057. The ejection section 1058 is the portion of the second surface 1057 that overlaps with the plurality of partial reflective surfaces 1055, and has a predetermined width in the extending direction of the light guide section 1050. Each of the plurality of partial reflective surfaces 1055 is made of a dielectric multilayer film. In addition, at least one of the plurality of partial reflective surfaces 1055 may be a composite layer of a dielectric multilayer film and a reflective metal layer mainly composed of one or more of aluminum, silver, magnesium, and chromium. When the partial reflective surface 1055 includes a metal layer, it is possible to increase the reflectivity of the partial reflective surface 1055, or to optimize the incident angle dependence and polarization dependence of the transmittance and reflectivity of the partial reflective surface 1055. Furthermore, the ejection section 1058 may be provided with optical elements including diffraction gratings or holograms.

[0071] In the head-mounted display 1000 having the above configuration, the composite image light LW, which consists of parallel light incident from the incident section 1040, is refracted at the incident surface 1041 and propagates toward the reflection surface 1042. The composite image light LW is reflected by the reflection surface 1042 and propagates toward the incident surface 1041 again. At this time, since the composite image light LW is incident on the incident surface 1041 at an incident angle greater than or equal to the critical angle, the composite image light LW is reflected toward the light guide section 1050 at the incident surface 1041 and propagates toward the light guide section 1050. In addition, in the incident section 1040, the incident surface 1041 and the reflection surface 1042 may be composed of free-form surfaces, and the non-parallel composite image light LW may be converted to parallel light while being reflected between the reflection surface 1042 and the incident surface 1041 after being incident on the incident surface 1041.

[0072] In the light guide unit 1050, the composite image light LW is reflected and propagates between the first surface 1056 and the second surface 1057. A portion of the composite image light LW incident on the partial reflection surface 1055 is reflected by the partial reflection surface 1055 and emitted from the emission unit 1058 toward the observer's eye E. At least the remaining portion of the composite image light LW incident on the partial reflection surface 1055 passes through the partial reflection surface 1055 and is incident on the next adjacent partial reflection surface 1055. Therefore, the composite image light LW reflected at each of the multiple partial reflection surfaces 1055 is emitted from the emission unit 1058 toward the observer's eye E. As a result, the observer can perceive a virtual image. At that time, light incident on the light guide unit 1050 from the outside world passes through the partial reflection surface 1055 after entering the light guide unit 1050 and reaches the observer's eye E. Therefore, the observer can view the color image emitted from the optical device 1 and see the outside world through it, in a so-called see-through manner.

[0073] The electro-optic apparatus 10G of the first embodiment described above comprises a light-emitting element 54G, a drive transistor 52G, a relay layer (relay electrode) T1, an electrode layer A4, and an electrode layer (conductive member) A6. The light-emitting element 54G includes an anode (first electrode) AN, a light-emitting layer EM, and a cathode (second electrode). The drive transistor 52G is provided in correspondence with the light-emitting element 54G. The relay layer T1 is electrically connected to the gate electrode layers (gate electrodes) G, G1 of the drive transistor 52G. The relay layer T1 is provided in the interlayer insulating layer (layer) L1 between the gate electrode layers G, G1 and the anode AN of the light-emitting element 54G in the Z direction parallel to the thickness direction of the semiconductor substrate 150. Electrode layer A4 is provided in the same layer as the relay layer T1 and in the interlayer insulating layer L1, that is, in the same layer as the relay layer T1, and extends, for example, in the X direction (first direction) in a plan view of the electro-optical device 10G, and is electrically connected to the electrode layer (first electrode side) A100 on the anode AN side of the light-emitting element 54G. Electrode layer A6 is provided between the relay layer T1 and electrode layer A4 in a plan view. A constant potential is supplied to electrode layer A6.

[0074] In the configuration of the electro-optical device 10G of the first embodiment, if electrode layer A6, i.e., electrode layer A6B, is not interposed between the relay layer T1 and electrode layer A4 on the surface of the interlayer insulating layer L1, parasitic capacitance, shown by the dashed line, will occur between the input to the gate of the drive transistor 52G from the region electrically connected to the retaining capacitance 55G in the source / drain region of the selection transistor 51G illustrated in Figure 3, and the output from the region of the drive transistor 52G that is electrically connected to the power supply wiring 63 in the source / drain region. Voltage changes in electrode layer A4 are transmitted to the relay layer T1, which is electrically connected to the gate electrodes G, G1 of the drive transistor 52G, via the aforementioned parasitic capacitance, causing crosstalk and image flickering. In the electro-optical device 10G of the first embodiment, the resistance of each electrode layer A6 is lower than that of the power supply wiring 63, and the potential of each electrode layer A6 is more stable than that of the power supply wiring 63. According to the electro-optical device 10G of the first embodiment, since an electrode layer A6 is provided between the relay layer T1 and the electrode layer A4 in a plan view, the space between the relay layer T1 and the electrode layer A4, which are electrically connected to the gate electrode layer G1 of the drive transistor 52G, is well shielded, and the generation of parasitic capacitance that occurred between the relay layer T1 and the electrode layer A4 in conventional electro-optical devices can be prevented. Therefore, crosstalk in the electro-optical device 10G of the first embodiment can be reduced and image flicker can be suppressed.

[0075] Furthermore, the electro-optical apparatus 10G of the first embodiment includes a P-type diffusion region (diffusion region) Pj containing a P-type impurity dopant and an N-type diffusion region (diffusion region) Nk containing an N-type impurity dopant in the N-type well 160 of the semiconductor substrate 150. That is, the semiconductor substrate 150 is provided with a plurality of diffusion regions consisting of P-type diffusion regions Pj and N-type diffusion regions Nk. The electrode layer (conductive member) A6 is electrically connected to the N-type diffusion region N1 among the plurality of diffusion regions, and is electrically connected to the N-type diffusion region N1 by, for example, a contact plug C4. According to the electro-optical apparatus 10G of the first embodiment, since the electrode layer A6 is electrically connected to the N-type diffusion region N1 which has stronger conductivity than the semiconductor substrate 150, the potential of the electrode layer A6 can be stabilized and the shielding effect between the relay layer T1 and the electrode layer A4 can be enhanced. Therefore, crosstalk in the electro-optical apparatus 10G of the first embodiment can be reduced and image flicker can be further suppressed.

[0076] Furthermore, in the electro-optical device 10G of the first embodiment, since the light-emitting element 54G is, for example, an OLED (organic light-emitting diode), the electrode layer A6 can be used as a terminal electrically connected to the body power supply.

[0077] Furthermore, the head-mounted display 1000 of the first embodiment includes the electro-optical device 10G described above, electro-optical devices 10B and 10R having the same configuration as the electro-optical device 10G, and an optical device (optical system) 1, a projection lens system (optical system) 1070, and a light guide system (optical system) 1030 for displaying image light LG, LB, and LR emitted from each of the electro-optical devices 10G, 10B, and 10R. According to the head-mounted display 1000 of the first embodiment, crosstalk and flicker of the image of the object being observed, displayed by the optical system that displays the image light LG, LB, and LR, can be suppressed.

[0078] [Second Embodiment] Next, a second embodiment of the present invention will be described with reference to Figure 12. In each embodiment from the second embodiment onward, components common to a higher embodiment are denoted by the same reference numerals, and their descriptions are omitted. In each embodiment from the second embodiment onward, the descriptions will mainly focus on components and contents that differ from those of the higher embodiment. Furthermore, the optical devices and image display devices equipped with electro-optical devices in each embodiment from the second embodiment onward are obtained by replacing the electro-optical devices 10G, 10B, and 10R in the optical device 1 and head-mounted display 1000 described in the first embodiment with the electro-optical devices of the respective embodiments.

[0079] The pixel circuit of pixel 11G of the electro-optical device 10G in the second embodiment has the same configuration as the pixel circuit of pixel 11G in the first embodiment. Figure 12 is a schematic diagram showing the plan view layout of the pixel circuit of pixel 11G of the second embodiment on the surface of the interlayer insulating layer L1. The plan view layout of the pixel circuit of pixel 11G of the second embodiment on the surface of the gate insulating layer L0, and the cross-section when viewed along the line X1-X2 shown in Figure 5, are the same as in the first embodiment.

[0080] As shown in Figure 12, in the pixel circuit of pixel 11G of the electro-optical device 10G of the second embodiment, electrode layer A6 includes electrode layer A6D in addition to electrode layers A6A, A6B, and A6C. Electrode layer A6D connects electrode layer A6A to electrode layer A6A at the opposite end from the end electrically connected to electrode layer A6C in electrode layer A6B in a plan view, and extends along the V direction. That is, the relay layer T1 is located in the region surrounded by electrode layer A6, which consists of electrode layers A6A to A6D. Also, in the pixel circuit of pixel 11G of the electro-optical device 10G of the second embodiment, similar to the first embodiment, electrode layer A4 is provided on the surface of the interlayer insulating layer L1, just like relay layer T1, and is located in the same layer as relay layer T1.

[0081] The method for manufacturing the electro-optical device 10G of the second embodiment is the same as the method for manufacturing the electro-optical device 10G of the first embodiment. However, when forming the electrode layers A3, A4, A6 and the relay layer T1 on the surface of the interlayer insulating layer L1, a mask having a pattern that matches the layout shown in Figure 12 in plan view is used.

[0082] The electro-optical device 10G of the second embodiment described above has the same configuration as the electro-optical device 10G of the first embodiment, and therefore provides the same effects and advantages as the electro-optical device 10G of the first embodiment. In addition, in the electro-optical device 10G of the second embodiment, the relay layer (relay electrode) T1 is surrounded by the electrode layer (conductive member) A6 in a plan view. In a plan view, the relay layer (relay electrode) T1 is adjacent to the electrode layer (conductive member) A6 via the interlayer insulating layer (insulating layer) L2 and is arranged surrounded by the electrode layer A6 via the interlayer insulating layer L2. According to the electro-optical device 10G of the second embodiment, the occurrence of unexpected parasitic capacitance in all directions around the relay layer T1 in a plan view can be prevented, and the shielding effect on the relay layer T1 can be enhanced without being limited to the space between the relay layer T1 and the electrode layer A4. Therefore, crosstalk in the electro-optical device 10G of the first embodiment can be reduced, and image flicker can be further suppressed.

[0083] [Third Embodiment] Next, a third embodiment of the present invention will be described with reference to Figures 13 to 20.

[0084] The pixel circuit of pixel 11G of the electro-optical device 10G in the third embodiment has the same configuration as the pixel circuit of pixel 11G in the first embodiment. Figure 13 is a schematic diagram showing the plan view layout of the pixel circuit of pixel 11G of the third embodiment on the surface of the interlayer insulating layer L1. Figure 14 is a schematic diagram showing the plan view layout of the pixel circuit of pixel 11G of the third embodiment on the surface of the gate insulating layer L0. Figure 15 is a schematic diagram showing the plan view layout of the pixel circuit of pixel 11G of the third embodiment on the surface of the interlayer insulating layer L2. Figure 16 is a diagram showing the configuration of the pixel circuit formed in the layout shown in Figures 13 to 15, and is a cross-sectional view taken along the line X1-X2 shown in Figures 13 and 15. In Figure 16, the configuration of the layers above electrode layer A14, i.e., the forward direction in the Z direction, is omitted, but electrode layer A14 is electrically connected to electrode layer A100 of anode AN of light-emitting element 54G.

[0085] As shown in Figures 13 to 16, in the pixel circuit of the pixel 11G of the electro-optical device 10G of the third embodiment, in the configuration and arrangement described in the second embodiment, the uppermost electrode layer A14 is provided on the surface of, for example, the interlayer insulating layer L2, and is provided on a different layer from the relay layer T1. Also, in the pixel circuit of the pixel 11G of the electro-optical device 10G of the third embodiment, at least a portion of the electrode layer A6 of the drive transistor 52G overlaps with the gate electrode layer G1 in a plan view. Specifically, on the surface of the gate insulating layer L0, the end of the gate electrode layer G1 closer to the electrode layer A4 extends in a direction closer to the electrode layer A4 than the relay layer T1 in a plan view.

[0086] The manufacturing method of the electro-optical device 10G of the third embodiment is generally the same as the manufacturing method of the electro-optical device 10G of the first embodiment. However, when forming electrode layers A3, A6 and relay layer T1 on the surface of the interlayer insulating layer L1, a mask having a pattern that matches the layout shown in Figure 13 in plan view is used. The pattern of electrode layer A6 in the mask used in the step of forming electrode layers A3, A6 and relay layer T1 on the surface of the interlayer insulating layer L1 overlaps, in plan view, with at least a portion of the area in the interlayer insulating layer L1 where holes for forming the gate electrode layer G1 are formed.

[0087] The electro-optical device 10G of the third embodiment described above has the same configuration as the electro-optical device 10G of the second embodiment, and therefore provides the same effects and advantages as the electro-optical device 10G of the second embodiment. As illustrated in Figure 16, even if the electrode layer A14 and the relay layer T1 are not provided in the same layer, the shielding effect between the electrode layer A14 and the relay layer T1 is achieved by providing the electrode layer A6 between the electrode layer A14 and the relay layer T1 in a plan view. Furthermore, in the electro-optical device 10G of the third embodiment, at least a portion of the electrode layer (conductive member) A6 overlaps with the gate electrode layer (gate electrode) G1 in a plan view. According to the electro-optical device 10G of the third embodiment, as shown in Figure 16, a retaining capacitance D10 can be configured between the region where the electrode layer A6 and the gate electrode layer G1 overlap in a plan view, and the retaining capacitance D10 can be used as a pixel capacitance.

[0088] Figures 17 to 20 are schematic diagrams showing modified configurations of the pixel circuit of pixel 11G of the electro-optical device 10G according to the third embodiment. Figure 17 is a schematic diagram showing a plan view layout on the surface of the interlayer insulating layer L1 in the pixel circuit of pixel 11G of the modified embodiment. The plan view layout on the surface of the gate insulating layer L0 in the pixel circuit of pixel 11G of the modified embodiment is the same as in the third embodiment. Figure 18 is a schematic diagram showing a plan view layout on the surface of the interlayer insulating layer L2 in the pixel circuit of pixel 11G of the modified embodiment. Figure 19 is a diagram showing the configuration of the pixel circuit formed with the layouts shown in Figures 14, 17, and 18, and is a cross-sectional view taken along the X1-X2 line shown in Figures 17 and 18. Figure 20 is a diagram showing the configuration of the pixel circuit formed with the layouts shown in Figures 14, 17, and 18, and is a cross-sectional view taken along the X3-X4 line shown in Figure 17. In Figures 19 and 20, the configuration above electrode layer A14, i.e., the forward configuration in the Z direction, is omitted, but electrode layer A14 is electrically connected to electrode layer A100 of the anode AN of the light-emitting element 54G.

[0089] In the pixel circuit of pixel 11G of the electro-optical device 10G of the modified embodiment of the third embodiment, as shown in Figures 17 to 19, electrode layers A6 and A16 are provided between the relay layer T1 and electrode layers A4 and A14 in a plan view, for example. As mentioned above, each of the relay layer T1 and electrode layers A4 and A6 is provided on the surface of the interlayer insulating layer L1. Also, each of the electrode layers A14 and A16 is provided on the surface of the interlayer insulating layer L2. Furthermore, the gate electrode layer G1 overlaps with the relay layer T1 and electrode layers A6 and A16 in a plan view. With this layout, a retaining capacitance D10 is formed between electrode layer A6 and gate electrode layer G1. Also, a retaining capacitance D12 is formed between electrode layer A16 and gate electrode layer G1.

[0090] As shown in Figures 17, 18, and 20, for example, an electrode layer A16 is provided between the relay layer T11 and the electrode layer A14 in a plan view. In this extraction region, in addition to the gate electrode layer G1 on the surface of the interlayer insulating layer L1, the relay layer T1 on the surface of the interlayer insulating layer L2 extends to a position where it overlaps with the electrode layer A16 in a plan view. In such a layout, a retaining capacitance D14 is formed between the electrode layer A16 and the relay layer T1 which is electrically equivalent to the gate electrode layer G1.

[0091] According to the electro-optical device 10G, a modified version of the third embodiment described above, similar to the electro-optical device 10G of the third embodiment, retaining capacitances D10, D12, and D14 are configured between regions where the electrode layers A6 and A16 and the gate electrode layer G1 overlap each other in a plan view, and these retaining capacitances D10, D12, and D14 can be used as pixel capacitances.

[0092] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the invention as described in the claims. Furthermore, the components of multiple embodiments can be combined as appropriate. While noteworthy effects have been described for each of the embodiments described above, the effects of other embodiments to which the configuration of the light source device applies can be obtained even without detailed explanation.

[0093] For example, the relative layout of the electrode layer, relay layer, and gate electrode layer described with reference to the drawings for the pixel circuits of the electro-optical apparatus of the first to third embodiments is one example included in the present invention. The layout can be modified as appropriate within the scope of the claims described later, and the relative layout of the electrode layer, relay layer, and gate electrode layer can be freely designed by combining the positions in the Z direction where each of the electrode layer, relay layer, and gate electrode layer is formed, i.e., the selection of the insulating layer that forms each of the electrode layer, relay layer, and gate electrode layer, and the shapes of each of the electrode layer, relay layer, and gate electrode layer in a plan view, as described in the modified example of the third embodiment, and the types and number of layouts are not particularly limited.

[0094] Furthermore, while a head-mounted display has been described as an image display device equipped with an electro-optical device according to the present invention, the image display device according to the present invention is not limited to a head-mounted display, and may be, for example, a projector, an electronic viewfinder (EVF), a portable information terminal, a tablet device, or a wristwatch.

[0095] Figure 21 is a schematic diagram showing the configuration of a projector 2000 equipped with the electro-optical devices 10G, 10B, and 10R described above. For example, as shown in Figure 21, the projector 2000 comprises the optical device 1 described above and a projection optical system (optical system) 2100 that magnifies and projects the composite image light LW emitted from the optical device 1 onto the screen 2200. With the projector 2000, the white balance of the composite image light LW projected onto the screen 2200 can be optimized, and the power consumption of each of the electro-optical devices 10G and 10B can be reduced compared to the electro-optical device 10R.

[0096] An electro-optical apparatus according to an embodiment of the present invention may have the following configuration. [1] An electro-optic apparatus according to one aspect of the present invention comprises a light-emitting element including a first electrode, a light-emitting layer, and a second electrode; a drive transistor provided corresponding to the light-emitting element; a relay electrode electrically connected to the gate electrode of the drive transistor and provided in the layer between the gate electrode and the first electrode of the light-emitting element; a power supply wiring provided in the same layer as the relay electrode, extending in a first direction in a plan view, and electrically connected to the first electrode of the light-emitting element; and a conductive member provided between the relay electrode and the power supply wiring in a plan view and supplied with a constant potential.

[0097] [2] In the electro-optic apparatus described in [1] above, the semiconductor substrate may include a diffusion region containing impurities, and the conductive member may be electrically connected to the diffusion region.

[0098] [3] In the electro-optic apparatus described in [2] above, the relay electrode may be surrounded by a conductive member in a plan view.

[0099] [4] In the electro-optical apparatus described in [3] above, the conductive member may be provided adjacent to the conductive member in a plan view, separated by an insulating layer.

[0100] [5] In the electro-optical apparatus described in [1] or [2] above, at least a portion of the conductive member may overlap with the gate electrode in a plan view.

[0101] [6] In the electro-optical apparatus described in any of [1] to [5] above, the light-emitting element may be an organic light-emitting diode.

[0102] [7] An image display device according to one embodiment of the present invention comprises an electro-optical device described in any of [1] to [6] above, and an optical system for displaying image light emitted from the electro-optical device. [Explanation of Symbols]

[0103] 54G…Light-emitting element, 150…Semiconductor substrate, 1000…Head-mounted display (image display device), 2000…Projector (image display device), A4…Electrode layer (power wiring), A6…Electrode layer (conductive material), AN…Anode (first electrode), CT…Cathode (second electrode), EM…Light-emitting layer, G, G1…Gate electrode layer (gate electrode), L0…Gate insulating layer (first layer), L1…Interlayer insulating layer (third layer), L3…Interlayer insulating layer (second layer), N1, Nk…N-type diffusion region (diffusion region), P1~P6, Pj…P-type diffusion region (diffusion region), T1, T11…Relay layer (relay electrode)

Claims

1. a light-emitting element including a first electrode, a light-emitting layer, and a second electrode; a driving transistor provided corresponding to the light-emitting element; a relay electrode electrically connected to the gate electrode of the driving transistor and provided in a layer between the gate electrode and the first electrode of the light-emitting element; a power supply wiring provided in the same layer as the relay electrode, extending in a first direction in a plan view, and electrically connected to the first electrode of the light emitting element; a conductive member provided between the relay electrode and the power supply wiring in a plan view and supplied with a constant potential; Equipped with Electro-optical device.

2. a diffusion region containing impurities in a semiconductor substrate; the conductive member is electrically connected to the diffusion region; The electro-optical device according to claim 1 .

3. the relay electrode is surrounded by the conductive member in a plan view; The electro-optical device according to claim 2 .

4. the relay electrode is provided adjacent to the conductive member via an insulating layer in plan view; The electro-optical device according to claim 3 .

5. At least a portion of the conductive member overlaps with the gate electrode in a plan view.

3. The electro-optical device according to claim 1.

6. The light-emitting element is an organic light-emitting diode. The electro-optical device according to claim 1 .

7. The electro-optical device according to claim 1 ; an optical system that displays image light emitted from the electro-optical device; Equipped with Image display device.

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