Piezoelectric element, liquid discharge head, and image recording device

Abstract

To provide a piezoelectric element that can sufficiently obtain a displacement amount and is excellent in durability, and a liquid discharge head and an image recording device having the piezoelectric element.SOLUTION: A piezoelectric element has a lower electrode, a piezoelectric film, and an upper electrode in this order on a substrate, and a film of aluminum oxide containing at least one element selected from the group III element, the group IV element, and the group V element is provided between the lower electrode and the piezoelectric film and / or between the piezoelectric film and the upper electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a piezoelectric element, a liquid ejection head, and an image recording apparatus.

Background Art

[0002] Piezoelectric materials that change their shape when an electric field is applied are applied to various industrial products as means for moving or vibrating an object minutely and accurately. For example, they are used in small speakers, hard disk drives, printers (image recording apparatuses), and the like. Among these, in printers, there are some that employ a piezoelectric film for a liquid ejection head that ejects droplets. In such a liquid ejection head, the piezoelectric film is driven by applying an electric field with electrodes (upper electrode, lower electrode) formed so as to sandwich the piezoelectric film from above and below, and droplets are ejected.

[0003] In recent years, printers have been required to have higher image quality and higher speed. The ejection structure of the liquid ejection head has been miniaturized, and efforts have been made to greatly displace the piezoelectric film by applying a high voltage. On the other hand, when a high voltage is applied, a large load is generated on the piezoelectric film. This is because although the piezoelectric film is a kind of insulator, its specific resistance (electrical resistivity) is small compared to that of silicon oxide or the like, and when a high voltage is applied, a current can flow through the film slightly. The occurrence of dielectric breakdown due to this current affects the durability of the piezoelectric film.

[0004] Therefore, studies have been made to improve the durability of the piezoelectric film. For example, Patent Document 1 describes a technique for suppressing the current flowing through the piezoelectric film and improving the durability by forming an insulating film between the piezoelectric film and the electrode.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] However, the technology disclosed in Patent Document 1, while improving the durability of the piezoelectric film, presented a technical challenge: insufficient displacement of the piezoelectric film could be obtained. This is thought to be due to the distribution of the voltage applied by the electrodes between the insulating film and the piezoelectric film, which reduced the magnitude of the electric field applied to the piezoelectric film. One approach to address this is to increase the voltage applied to the electrodes in anticipation of the reduction in the electric field applied to the piezoelectric film, but this could lead to deterioration of other parts such as wiring. Another approach considered was to reduce the thickness of the insulating film to increase the voltage distribution rate to the piezoelectric film, but a large electric field was still applied to the insulating film.

[0007] The present invention has been made in view of the above problems, and aims to provide a piezoelectric element that can obtain sufficient displacement of the piezoelectric film while also improving the durability of the piezoelectric film. [Means for solving the problem]

[0008] To achieve the above objective, the piezoelectric element in the present invention has a lower electrode, a piezoelectric film, and an upper electrode on a substrate in this order, and is characterized in that a film of aluminum oxide containing at least one element selected from group III, group IV, and group V elements is provided between the lower electrode and the piezoelectric film, and between the piezoelectric film and the upper electrode. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a piezoelectric element that is highly durable while obtaining sufficient displacement, a liquid discharge head having the piezoelectric element, and an image recording device. [Brief explanation of the drawing]

[0010] [Figure 1] A schematic cross-sectional view of a piezoelectric element of the present invention, in which an insulating film is provided between the piezoelectric film and the lower electrode. [Figure 2] A schematic cross-sectional view of a piezoelectric element of the present invention, in which an insulating film is provided between the piezoelectric film and the upper electrode. [Figure 3] A schematic cross-sectional view of a piezoelectric element of the present invention, in which an insulating film is provided both between the piezoelectric film and the lower electrode, and between the upper electrode. [Figure 4] A cross-sectional view illustrating the lower electrode having an adhesion layer. [Figure 5] A graph showing the results of high-temperature, high-humidity operation tests. [Figure 6] A cross-sectional view illustrating a crystal orientation-oriented film with an adhesion layer. [Figure 7] This is a cross-sectional view showing the film configuration of the piezoelectric element of the present invention, in which an insulating film is provided between the piezoelectric film and the lower electrode. [Figure 8] This diagram illustrates the processing process for the piezoelectric element of the present invention, and shows a cross-sectional view of a state in which a resist mask pattern for processing the piezoelectric material has been formed. [Figure 9] A cross-sectional view illustrating the etching process of the film of the piezoelectric element of the present invention. [Figure 10] This is a cross-sectional view showing the film configuration of the piezoelectric element of the present invention, in which an insulating film is provided between the piezoelectric film and the upper electrode. [Figure 11] This diagram illustrates the manufacturing process of the piezoelectric element of the present invention, and shows a schematic cross-sectional view of the protective film formed on the element. [Figure 12] This diagram illustrates the manufacturing process of the piezoelectric element of the present invention, and shows a cross-sectional view of a resist mask pattern for forming an opening on the lower electrode surface. [Figure 13] This diagram illustrates the manufacturing process of the piezoelectric element of the present invention, and shows a cross-sectional view of the lower electrode surface with an opening formed therein. [Figure 14] This diagram illustrates the manufacturing process of the piezoelectric element of the present invention, and shows a cross-sectional view of a resist mask pattern for forming an opening on the surface of the upper electrode. [Figure 15] This diagram illustrates the manufacturing process of the piezoelectric element of the present invention, and shows a cross-sectional view of the upper electrode surface with an opening formed therein. [Figure 16] This is a cross-sectional view showing a conductive film formed to form wiring, which explains the processing process of the piezoelectric element of the present invention. [Figure 17] This is a cross-sectional view showing a resist mask pattern formed to process a conductor film into a desired shape to form wiring, which explains the processing process of the piezoelectric element of the present invention. [Figure 18] This is a cross-sectional view showing the formed wiring, which explains the processing process of the piezoelectric element of the present invention. [Figure 19] This is a cross-sectional view showing a resist mask pattern for forming a recess on the back surface of a wafer, which explains the processing process of the piezoelectric element of the present invention. [Figure 20] A cross-sectional view for explaining the structure of an SOI wafer.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, as an embodiment of the piezoelectric element of the present invention, a piezoelectric element as a micro-structure manufactured using a semiconductor process will be described in detail with reference to the accompanying drawings. Note that the components described in the following embodiments are merely examples, and are not intended to limit the scope of the present invention only to them.

[0012] The piezoelectric element of the present invention has a lower electrode 210, a piezoelectric film 240, and an upper electrode 250 in this order on a substrate 100, and has an insulating film 220 between at least one of the lower electrode and the piezoelectric film and between the piezoelectric film and the upper electrode. As shown in FIG. 1, an insulating film 220 may be provided between the piezoelectric film 240 and the lower electrode 210. In this case, as described above, the presence of the insulating film 220 suppresses the current flowing in the piezoelectric film. Also, as shown in FIG. 2, an insulating film 220 may be provided between the piezoelectric film 240 and the upper electrode 250. Furthermore, as shown in FIG. 3, it is more preferable that the insulating film 220 is provided between both the lower electrode 210 and the piezoelectric film 240 and between the piezoelectric film 240 and the upper electrode 250.

[0013] When the piezoelectric element of the present invention is a microstructure, it is particularly preferable to form it on a flat substrate 100. The substrate 100 can be appropriately selected depending on its intended use, and wafers with high flatness made of materials such as silicon, silicon carbide, quartz, gallium nitride, gallium arsenide, indium phosphide, and sapphire are preferably used. Furthermore, SOI (Silicon On Insulator) wafers may be used to easily form a membrane structure.

[0014] The following explanation will use a piezoelectric element having an insulating film 220 between the piezoelectric film 240 and the lower electrode 210 shown in Figure 1.

[0015] The lower electrode 210 of the piezoelectric film 240 may be exposed to high temperatures of several hundred degrees Celsius in subsequent processes, and in such cases, it is preferable to use a material with a high melting point. Examples of such materials include copper, platinum, gold, chromium, cobalt, titanium, and their alloys. Furthermore, when the piezoelectric film 240 is formed in contact with the upper surface of the lower electrode 210, the lower electrode 210 may also serve as a film that controls the crystal orientation of the piezoelectric film. In that case, a material with an appropriate crystal structure is appropriately selected. In addition, to obtain adhesion between the lower electrode 210 and the film below it, a thin film of titanium, chromium, etc. may be placed as an adhesion layer 211, and the lower electrode 210 may be a laminated film with a conductive layer 212 made of the aforementioned materials or materials commonly used for wiring. As described above, when the piezoelectric film 240 is formed in contact with the conductive layer 212, a material with an appropriate crystal structure is appropriately selected (see Figure 4). If the substrate 100 is conductive, it is preferable to place an insulating film 110 between the lower electrode 210 and the substrate 100. For the insulating film 110, common insulating materials such as silicon oxide, silicon nitride, oxynitride, and alumina can be used.

[0016] An insulating film 220 is formed on the lower electrode 210 or on the piezoelectric film 240 to suppress the current flowing in the piezoelectric film (see Figures 1 to 3). In the present invention, the insulating film must be a film of aluminum oxide (aluminum oxide) containing at least one element selected from Group III, Group IV, and Group V elements. Examples of at least one element selected from Group III, Group IV, and Group V elements include titanium, lanthanum, yttrium, and hafnium. More specifically, it is preferable that the aluminum oxide is at least one selected from aluminate titanate, yttrium aluminate, hafnium aluminate, and lanthanum aluminate. Furthermore, the insulating film may also contain nitrogen atoms, such as hafnium nitride aluminate.

[0017] Piezoelectric elements were fabricated using an aluminum oxide (aluminum oxide) insulating film containing at least one element selected from Group III, Group IV, and Group V elements, as per the present invention, and an insulating film made of materials used in the prior art. High-temperature, high-humidity driving tests were then conducted. The test conditions were as follows: The piezoelectric elements were kept in a chamber set to a temperature of 85°C and a relative humidity of 85%RH, and a constant voltage was continuously applied for 1000 hours.

[0018] The results of the high-temperature, high-humidity driving test are shown in Table 1 and Figure 5. Table 1 lists the insulating film material used in the test, the relative permittivity and dielectric breakdown strength of each film, and the product of the relative permittivity and dielectric breakdown strength. Figure 5 is a graph of the product of the relative permittivity and dielectric breakdown strength. In Table 1, piezoelectric elements that showed high durability are marked with a "○". From the test results, it was found that materials with a larger product of relative permittivity and dielectric breakdown strength had higher durability of the piezoelectric elements. In particular, it was found that durability was higher when the product of relative permittivity and dielectric breakdown field strength was greater than 134 MV / cm. This is especially clear when comparing the case using alumina, which has the above product of 134 MV / cm, with the case using hafnium aluminate, which has a product of slightly more than 134 MV / cm.

[0019] [Table 1]

[0020] Furthermore, the film thickness of these insulating films is adjusted to a thickness that yields the desired displacement at a power supply voltage of 50V. Among these, the materials that could be made the thickest were aluminate titanate and aluminate lanthanum, both of which had a film thickness of 13nm. In other words, it is preferable that the film thickness of the insulating film be 13nm or less.

[0021] Depending on the material, the insulating film 220 may preferably be a thin film of a few nanometers. In such cases, it is preferable to deposit the film on a flatter surface and to form it before the piezoelectric film 240. Hafnium aluminate is an example of such a material. However, if the deposition conditions can be appropriately adjusted to cover the piezoelectric film 240, it may be formed on top of the piezoelectric film 240. Alternatively, the insulating film 221 and insulating film 222 may be formed separately on both the top and bottom of the piezoelectric film. In that case, the total thickness of both films should be 13 nm or less.

[0022] When an insulating film 220 is formed between the lower electrode 210 and the piezoelectric film 240, a crystal orientation control film 230 is formed between the insulating film 220 and the piezoelectric film 240 to control the crystal orientation of the piezoelectric film. The material of the crystal orientation control film 230 depends on the crystal orientation of the piezoelectric film 240 and is appropriately selected depending on the material of the piezoelectric film 240. For example, if the material of the piezoelectric film 240 is lead zirconate titanate, it is preferable to use platinum for the crystal orientation control film 230. General deposition methods such as magnetron sputtering can be used to deposit platinum, but the film thickness is adjusted as appropriate to obtain the desired orientation. In addition, to improve the adhesion between platinum and the insulating film 220, the crystal orientation control film 230 may be a laminated film of an adhesion layer 231 made of titanium or chromium and a crystal orientation control layer 232 (see Figure 6).

[0023] A piezoelectric film 240 is formed on the crystal orientation control film 230. Lead zirconate titanate is mainly used for the piezoelectric film because it is easy to obtain a large displacement, but other piezoelectric materials such as barium titanate, lead titanate, lead metaniobate, bismuth titanate, zinc oxide, aluminum nitride, and potassium sodium niobate can also be used.

[0024] The piezoelectric film 240 can be deposited using general deposition methods such as magnetron sputtering or spin coating. A film thickness of approximately 2 μm is preferred, and when formed by coating, it is deposited in several layers. Furthermore, crystal orientation is achieved by firing after coating. The firing temperature is appropriately selected depending on the material, but in the case of lead zirconate titanate, it can be within the range of 600°C to 900°C.

[0025] When forming an insulating film 220 between the piezoelectric film 240 and the upper electrode 250 to suppress the current flowing within the piezoelectric film 240, the insulating film 220 is formed in contact with the upper surface of the piezoelectric film 240. The materials used and the formation method are the same as when forming it between the lower electrode 210 and the piezoelectric film 240, as described above. However, when the thickness of the insulating film 220 is thinned to a few nanometers, the coverage may be insufficient due to the unevenness of the upper surface of the piezoelectric film 240. In such cases, it is preferable to form the insulating film 220 between the lower electrode 210 and the piezoelectric film 240.

[0026] If the insulating film 220 is not formed between the upper electrode 250 and the piezoelectric film 240, the upper electrode 250 is formed in contact with the upper surface of the piezoelectric film 240. The upper electrode 250 can be made of any material that exhibits conductivity, and materials commonly used as electrode materials can be used. However, if the internal stress of the crystal orientation-oriented film 230 or other material is large and the piezoelectric film 240 is bent, the upper electrode 250 can be given an opposite internal stress to counteract the stress of the entire element.

[0027] The multilayer film fabricated in the manner described above (see Figure 7) is processed to form a fine piezoelectric element.

[0028] A resist pattern 301 of the desired shape is formed on the surface of the multilayer film (see Figure 8). A general method can be used to form the resist pattern. Specifically, the resist is applied by spin coating, pre-baked, then irradiated with ultraviolet light through a mask on which the desired pattern has been formed, and then developed to remove unwanted resist areas. After that, post-baking is performed to ensure the stability of the formed resist pattern and to suppress gas release during etching.

[0029] Etching is performed using the fabricated resist pattern 301 as a mask. Common etching methods such as dry etching and wet etching can be used. As shown in Figure 9, etching is performed up to the upper surface of the insulating film 220. If the insulating film 220 is not provided below the piezoelectric film 240, as in the film configuration shown in Figure 10, etching is performed up to the upper surface of the lower electrode 210. After etching, the resist pattern 301 is removed by commonly used methods such as ashing.

[0030] To prevent corrosion of the piezoelectric element, which is a microstructure obtained by etching, a protective film 401 is formed on the entire surface of the structure. While a general insulating material can be used for the protective film 401, it is more preferable to use the same material as the insulating film 220 to prevent dielectric breakdown of the protective film 401 at the edges of the insulating film 220. To deposit the protective film 401 on the entire surface of the structure, it is preferable to use atomic layer stacking or chemical vapor deposition. It is also preferable to deposit another protective film 402 made of a different material on the surface of the protective film 401 to further improve the protective performance (see Figure 11).

[0031] A portion of the protective film is removed to form an opening 501 that allows the wiring 601, which electrically connects the external power supply and the element, to make contact with the lower electrode 210. A resist pattern 302 with holes is formed at the location of the opening (see Figure 12). Then, the protective film 401, or both the protective film 401 and 402 covering the lower electrode 210, is etched and removed. After that, the resist pattern 302 is removed (see Figure 13).

[0032] Next, an opening 502 is formed to bring the wiring 602 that electrically connects the external power supply and the element into contact with the upper electrode 250. A resist pattern 303 with holes is formed at the location of the opening (see Figure 14). After that, the protective film 401, or protective film 401 and protective film 402 covering the upper electrode 250, is etched and removed. Then, the resist pattern 303 is removed (see Figure 15).

[0033] To form wiring 601 and wiring 602, a conductive film 600 is deposited using a conductive material (see Figure 16). Common wiring materials can be used as the material. Such materials include, for example, aluminum, copper, gold, platinum, and their alloys. To process the conductive film 600 into the desired shape, a resist pattern 304 is formed on it (see Figure 17). Wiring 601 and wiring 602 are then fabricated by etching (see Figure 18).

[0034] Finally, the back surface of the wafer is thinned so that the piezoelectric element can be deformed by the application of voltage. The area to be thinned is the back surface of the wafer in the area where the previously fabricated piezoelectric element was formed. In other words, the thick substrate beneath the piezoelectric element is deeply etched. This process can be done by machining or by general semiconductor processes such as wet etching or dry etching, but since the area beneath the piezoelectric element is thinned, care must be taken to avoid vibration and other factors to prevent damage to the membrane. When processing by wet etching or dry etching, a resist pattern 305 as shown in Figure 19 is formed. Using this as a mask, etching is performed to form a recess 701 on the back surface of the wafer. The depth of the recess is controlled by the processing time, but if an SOI wafer is used, this processing depth can be performed with good reproducibility. Figure 20 shows the structure of an SOI wafer. An SOI wafer has a silicon oxide layer (BOX layer) formed on a silicon substrate, and a silicon layer on top of that. The BOX layer can be formed between tens of nanometers and hundreds of micrometers, and the thickness of the silicon layer on top of it can also be selected relatively freely. By appropriately combining these film thicknesses and performing selective etching with the BOX layer as the etching stop layer, only silicon can be removed. The bottom of the recess obtained by such etching is the surface of the BOX layer, making it possible to obtain an extremely flat bottom.

[0035] The durability of a liquid discharge head largely depends on the part that provides energy to the liquid for discharge. By using the piezoelectric element described above in the liquid discharge head, it is possible to obtain a liquid discharge head with high durability. Furthermore, by using an image recording device equipped with a liquid discharge head that discharges liquid by driving the piezoelectric element of the present invention, it is possible to achieve both fine image quality and high speed. [Examples]

[0036] Using a thermal oxidation furnace, an SOI wafer is heated in an oxygen atmosphere to form a thermal oxide film on the silicon layer surface. The thickness of the formed silicon oxide film is 250 nm. This thermal oxide film blocks the conductivity between the electrical circuit formed on the wafer surface and the silicon film.

[0037] Titanium and platinum are continuously deposited on the surface of a thermal oxide film by magnetron sputtering. The titanium layer has a thickness of 10 nm, and the platinum layer has a thickness of 20 nm. This conductive multilayer film will serve as the lower electrode of the piezoelectric film.

[0038] An aluminate titanate insulating layer was formed on the lower electrode film surface by atomic layer deposition using trimethylaluminum and tetrakisdimethylaminotitanium as raw materials. The wafer temperature at this time was 190°C, and the titanium to aluminum element composition was 2:3. The film thickness was 8 nm, the relative permittivity was 18, and the dielectric breakdown field strength was 10 MV / cm. In other words, the product of the relative permittivity and the dielectric breakdown field strength was 180 MV / cm. Because this insulating film has a relatively thin film thickness, it is preferable to form it on the surface of a flat film, and therefore it was formed between the piezoelectric film and the lower electrode.

[0039] A film for controlling the crystal orientation of the piezoelectric film is formed on the surface of the aluminate titanate insulating film. This layer is first formed by continuously depositing a titanium film as an adhesion layer and a platinum film as a crystal orientation control layer. The thickness of the titanium film was set to 10 nm, and the thickness of the platinum film to 100 nm. Furthermore, a lead titanate solution was spin-coated on top of this to form a seed layer.

[0040] A lead zirconate titanate sol gel solution was applied using a spin coater to form a piezoelectric film. A thin film with a thickness of approximately 200 nm could be formed in a single coating step. This process was repeated 10 times to achieve a total film thickness of approximately 2 μm. The piezoelectric film was then formed at a firing temperature of 700°C.

[0041] After the wafer is slowly cooled, a 100 nm thick titanium-tungsten alloy film is deposited. This multilayer film will serve as the upper electrode of the piezoelectric film.

[0042] A resist pattern measuring 600 μm × 100 μm is formed on the surface of the laminated film created as described above, and dry etching is performed to a depth of the aluminate titanate insulating film surface to form a fine piezoelectric element. Furthermore, a resist pattern is formed to cover an area slightly wider than the etched piezoelectric film, and the area away from the piezoelectric element is dry-etched down to below the lower electrode to form a lower electrode that slightly protrudes from the piezoelectric element.

[0043] A piezoelectric element fabricated using atomic layer deposition with trimethylaluminum as the raw material is covered entirely with aluminum oxide. Furthermore, a 250 nm silicon nitride film is deposited as a protective layer to prevent corrosion. To form a contact area for connecting the upper electrode of the piezoelectric film to the wiring, the silicon nitride film and aluminum oxide film on the upper electrode are partially removed by dry etching. Subsequently, to form a contact area for connecting the lower electrode to the wiring, the silicon nitride film, aluminum oxide film, and aluminum titanate insulating film are partially removed.

[0044] Wiring is formed to connect the external power supply circuit and the upper and lower electrodes of the piezoelectric element. Titanium and aluminum-copper alloy films are continuously deposited using a magnetron sputtering apparatus. The titanium film thickness was 10 nm, and the aluminum-copper alloy film thickness was 30 nm. Subsequently, a resist pattern in the shape of the wiring is formed, and the wiring is formed by dry etching. Furthermore, the surface is covered with a silicon nitride film with a thickness of 200 nm to serve as a protective film for the wiring surface.

[0045] The silicon nitride film on the surface of the pad area where the external power supply is connected is removed by dry etching to expose the pad surface. A resist pattern is formed on the back side of the SOI wafer, that is, the side opposite to the side on which the piezoelectric element is formed. The size of this pattern is 850 μm × 120 μm, slightly larger than the piezoelectric element, and fabricated so that there is a recess directly beneath the piezoelectric element. Subsequently, the silicon is removed down to the silicon oxide film, which is the BOX layer (embedded oxide layer), using the Bosch process, and the film above the BOX layer becomes the membrane.

[0046] As described above, the desired piezoelectric element was obtained. [Examples]

[0047] Similar to Example 1, a thermal silicon oxide film is formed on the surface of the SOI wafer to block electrical conductivity between the electrical circuit and the silicon film.

[0048] In this embodiment, in order to form an insulating film between the piezoelectric film and the upper electrode to reduce the current passing through the piezoelectric film, the platinum film for controlling the crystal orientation is shared with the lower electrode. Therefore, 10 nm titanium and 100 nm platinum films are continuously deposited on the surface of the thermal silicon oxide film by magnetron sputtering.

[0049] A lead titanate solution was spin-coated onto the platinum surface in the same manner as in Example 1 to form a seed layer. Furthermore, a lead zirconate titanate sol-gel solution was applied using a spin coater and annealed to form a piezoelectric film.

[0050] An insulating film made of 12 nm lanthanum aluminate was deposited on the surface of a piezoelectric film by magnetron sputtering. The relative permittivity of the obtained insulating film was 18, and the dielectric breakdown field strength was 16.7 MV / cm. Therefore, the product of the relative permittivity and the dielectric breakdown field strength is 300.6 MV / cm.

[0051] Furthermore, the upper electrode was fabricated in the same manner as in Example 1.

[0052] To form the piezoelectric element, dry etching was performed up to the upper surface of the lower electrode. The subsequent steps were carried out in the same manner as in Example 1 to obtain the piezoelectric element.

[0053] (Comparative Example 1) In Example 1, an insulating film with a thickness of 7 nm was fabricated from alumina to reduce the current passing through the piezoelectric film. The deposition method was atomic layer deposition, using trimethylaluminum as the raw material. The relative permittivity of alumina was 10, and the dielectric breakdown field strength was 13.4 MV / cm. Therefore, the product of the relative permittivity and the dielectric breakdown field strength is 134 MV / cm.

[0054] (Comparative Example 2) In Example 1, an insulating film to reduce the current passing through the piezoelectric film was fabricated from a silicon nitride film with a thickness of 8 nm. The film deposition method was plasma CVD. The relative permittivity of the silicon nitride film was 12, and the dielectric breakdown field strength was 8.8 MV / cm. Therefore, the product of the relative permittivity and the dielectric breakdown field strength is 105.6 MV / cm.

[0055] The piezoelectric elements shown in the above examples and comparative examples were subjected to a continuous application of a 50V DC voltage and kept in a constant temperature chamber at 85°C and 85% RH for 1000 hours to investigate their durability. As a result, none of the piezoelectric elements in the examples showed any failure and demonstrated high durability, while the piezoelectric elements in the comparative examples did not achieve the desired durability. [Explanation of Symbols]

[0056] 100 circuit boards 101 Silicon substrate 102 Silicon oxide layer (BOX layer) 103 Silicon layer 110 Insulating Film 210 Lower electrode 211 Contact layer of the lower electrode 212 Conductor layer of the lower electrode 220, 221, 222 The insulating film of the present invention 230 Crystal orientation controlled film 231 Adhesion layer of crystal orientation controlled film 232 Crystal orientation control layer 240 Piezoelectric film 250 Upper electrode 301, 302, 303, 304 Resist Patterns 401, 402 Protective film 501, 502 Opening 600 Conductive film for forming wiring 601 Wiring connected to the lower electrode 602 Wiring connected to the upper electrode 701 recess

Claims

1. A piezoelectric element having a lower electrode, a piezoelectric film, and an upper electrode on a substrate in this order, A piezoelectric element, characterized in that an insulating film made of aluminum oxide containing at least one element selected from the group consisting of group III elements, group IV elements, and group V elements is provided between the lower electrode and the piezoelectric film.

2. 2. The piezoelectric element according to claim 1, wherein the product of the relative dielectric constant and the dielectric breakdown field strength of the insulating film is greater than 134 MV / cm.

3. 2. The piezoelectric element according to claim 1, wherein the at least one element selected from the group consisting of group III elements, group IV elements, and group V elements is at least one element selected from the group consisting of titanium, yttrium, hafnium, and lanthanum.

4. 2. The piezoelectric element according to claim 1, wherein the aluminum oxide is at least one selected from the group consisting of aluminate titanate, yttrium aluminate, hafnium aluminate, and lanthanum aluminate.

5. A piezoelectric element having a lower electrode, a piezoelectric film, and an upper electrode on a substrate, in this order, A piezoelectric element, comprising an insulating film made of aluminum oxide containing aluminate titanate or lanthanum aluminate between the lower electrode and the piezoelectric film.

6. 2. The piezoelectric element according to claim 1, wherein the insulating film has a thickness of 13 nm or less.

7. A piezoelectric element as described in claim 1, wherein a second insulating film made of aluminum oxide containing at least one element selected from group III elements, group IV elements, and group V elements is provided between the piezoelectric film and the upper electrode.

8. 7. The piezoelectric element according to claim 6, wherein the sum of the thicknesses of the insulating film provided between the lower electrode and the piezoelectric film and the second insulating film provided between the piezoelectric film and the upper electrode is 13 nm or less.

9. A piezoelectric element as described in claim 1, having a crystal orientation control film between the insulating film and the piezoelectric film for controlling the crystal orientation of the piezoelectric film.

10. 9. A liquid ejection head comprising the piezoelectric element according to claim 1, the liquid ejection head ejecting liquid by driving the piezoelectric element.

11. A liquid ejection head as described in claim 9, which ejects ink as the liquid.

12. 10. A liquid ejection apparatus comprising: a liquid ejection head having the piezoelectric element according to claim 1, the liquid ejection head driving the piezoelectric element to eject liquid.

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