Semiconductor Device

Abstract

To provide a semiconductor device using an unipolar transistor capable of keeping power consumption low and preventing an amplitude of an output potential from being low.SOLUTION: A semiconductor device has: first wiring having a first potential; second wiring having a second potential; third wiring having a third potential; a first transistor and a second transistor having the same polarity; and a plurality of third transistors that select whether to give the first potential or the third potential to gates of the first and second transistors, and select whether or not to give the first potential to drain terminals of the first and second transistors. A source terminal of the first transistor is connected with the second wiring, and a source terminal of the second transistor is connected with the third wiring.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit using transistors of the same conductivity type, a semiconductor display device using the circuit, etc. , relates to semiconductor devices. [Background technology]

[0002] Semiconductor display devices such as liquid crystal display devices and EL display devices are made of a backplane (circuit board). To reduce costs, it is preferable for the device to be made of unipolar semiconductors rather than CMOS. In the following Patent Documents 1 and 2, an inverter circuit used in a driving circuit of a semiconductor display device is described. A technology to configure various circuits such as clocks and shift registers with unipolar transistors It has been disclosed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-325798 A [Patent Document 2] JP 2010-277652 A Summary of the Invention [Problem to be solved by the invention]

[0004] By the way, a semiconductor display including a transistor having amorphous silicon or an oxide semiconductor The equipment is capable of handling glass substrates of 5th generation or higher (1200mm wide x 1300mm long). Therefore, it has the advantage of high productivity and low cost. However, A transistor having a semiconductor is generally unipolar and normally on. In a circuit that consists of transistors of the same conductivity type, If the starter is normally on, power consumption increases or the amplitude of the output potential becomes small. This can cause problems such as

[0005] For example, in the circuit shown in FIG. 10 of Patent Document 2, the transistor Q2 is The source terminal is fixed to the low potential VSS. The transistor Q2 is normally off. In other words, when a low potential VSS is applied to the gate of the transistor Q2, the transistor Q2 is in a non-conducting state (off state). However, if the transistor Q2 is normally on, the transistor Q2 will Even if a low potential VSS is applied to the gate, the gate and source terminals are The gate voltage, the voltage across the gate terminals, remains higher than the threshold voltage of transistor Q2. As a result, transistor Q2 does not turn off and remains conductive (on).

[0006] If transistor Q2 is turned on when it should be off, unwanted current will flow into the circuit. Furthermore, the unnecessary current causes a potential (for example, For example, in the case of FIG. 10 of Patent Document 2, the low-level potential VSS or the clock signal CLKA The current flows through the wiring for supplying the high-level potential VDD and the low-level potential VSS. The current flowing through the wiring increases due to the resistance of the wiring. The potential of the line to which the potential VSS is supplied increases. As a result, The amplitude of the potential that is applied is greater than the ideal potential difference between the potential VDD and the potential VSS. It becomes smaller.

[0007] In particular, in the pixel portion of a semiconductor display device, a bus line connected to a plurality of pixels is When supplying a potential output from a circuit to a wiring, such as a scanning line or a signal line, A transistor that controls the output of the potential of the The transistor Q2) is required to have a large current supply capability. The channel width W of the transistor in the circuit must be designed to be larger than the channel width W of the other transistors in the circuit. However, the drain current of a transistor is proportional to the channel width W. If the channel width W of a transistor that is normally on is increased, the transistor will be turned off when it should be. The current flowing through the transistor is larger than that of the other transistors. This increases the unnecessary current flowing through the resistor, which increases the power consumption or reduces the amplitude of the output potential. The above-mentioned phenomenon, such as the above-mentioned phenomenon, is significantly more likely to occur.

[0008] In light of the above-mentioned technical background, the present invention provides a semiconductor device that can reduce power consumption. Alternatively, the present invention provides a method for reducing the amplitude of an output potential. It is an object of the present invention to provide a semiconductor device capable of preventing the above-mentioned problems. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment of the present invention includes a plurality of transistors. By turning on or off the two switches, the high potential or the low potential can be selected. In one embodiment of the present invention, the plurality of transistors are The wiring that applies a potential to the source terminal of the output transistor and the wiring that applies a potential to the source terminal of the other transistor The wiring for supplying a potential to the transistor terminal is different from the wiring for supplying a potential to the transistor terminal. A potential is supplied from the wiring that supplies the potential to the source terminal to the output transistor via the other transistor. When a voltage is applied to the gate of the output transistor, the output transistor is turned off. It shall have the following.

[0010] With the above configuration, the gate and source terminals of the output transistor are electrically separated. Therefore, if the output transistor is normally on, Even if the potential of the wiring for supplying a potential to the source terminal of the transistor fluctuates, The potential of the wiring for supplying potential to the gate of the transistor is independent of the above fluctuations. Therefore, the drain current of the output transistor causes the source When the potential of the terminal changes, the gate voltage of the transistor approaches the threshold voltage. In other words, a negative feedback circuit can be used. Even with a mullion, the transistor can be turned off when it should be turned off. . Effect of the Invention

[0011] In one embodiment of the present invention, a semiconductor device using transistors with the same conductivity type, which consumes less power, is Alternatively, in one aspect of the present invention, an apparatus can be provided in which the amplitude of the potential to be output is It is possible to provide a semiconductor device that can prevent the size from becoming smaller. [Brief description of the drawings]

[0012] [Figure 1] 1 illustrates a structure of a semiconductor device. [Diagram 2] FIG. 2 is a diagram showing the configuration of a pulse generating circuit. [Diagram 3] 4 is a timing chart of a pulse generating circuit. [Figure 4]FIG. 2 is a diagram showing a configuration of a shift register. [Diagram 5] 1 is a timing chart of a shift register. [Figure 6] FIG. 2 is a diagram showing a schematic diagram of a j-th pulse generating circuit 200_j. [Figure 7] 4A and 4B are diagrams for explaining the configuration of a pulse generating circuit of a comparative example and the waveform of a potential GROUT. [Figure 8] FIG. 2 is a diagram showing the configuration of a pulse generating circuit. [Figure 9] FIG. 2 is a diagram showing the configuration of a pulse generating circuit. [Figure 10] FIG. 2 is a diagram showing the configuration of a pulse generating circuit. [Figure 11] FIG. 2 is a diagram showing the configuration of an inverter. [Figure 12] FIG. 2 is a cross-sectional view of a driver circuit and a pixel. [Figure 13] FIG. 1 is a cross-sectional view of a transistor. [Figure 14] FIG. 2 is a diagram showing the configuration of a panel. [Figure 15] Electronic devices illustration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0014] The present invention also relates to a microprocessor, an image processing circuit, a DSP (Digital Sign al Processor), microcontrollers and other integrated circuits, RF tags, semiconductor The present invention can be used to manufacture various semiconductor devices, such as semiconductor display devices. The LCD has a liquid crystal display device, an organic light-emitting device (OLED) and other light-emitting devices in each pixel. EL display devices, electronic paper, DMD (Digital Micromirror Display) vice), PDP(Plasma Display Panel), FED(Fiel d Emission Display) and other circuit elements using semiconductor films as driving circuits. Other semiconductor display devices having the same structure are included in the category.

[0015] In this specification, the term "semiconductor display device" refers to a display device in which display elements such as liquid crystal elements and light emitting elements are used for each screen. A panel formed as a base and a model in which ICs including a controller are mounted on the panel This category includes modules.

[0016] (Embodiment 1) FIG. 1A illustrates an example of a circuit configuration of a semiconductor device of one embodiment of the present invention. The semiconductor device 100 shown in FIG. 1 includes a circuit 101 including a plurality of transistors. The semiconductor device 100 shown in FIG. In this case, at least the transistor 102 and the transistor 103 have the same polarity. In (A), the transistor 102 and the transistor 103 are both n-channel types. The case is illustrated.

[0017] The circuit 101 is supplied with a high-level potential VDD or A low-level potential VSS is applied to the wiring 104. A potential DD is applied to the circuit 101, and a potential VSS is applied to the circuit 101 through a wiring 105. In addition, the circuit 101 is connected to a signal potential Vin is given.

[0018] The gate and drain terminals of the transistor 102 are connected to the circuit 101. 01 selects either the potential VDD or the potential VSS according to the potential Vin, and The potential VSS of the wiring 105 is applied to the gate or drain terminal of the transistor 102. The input voltage Vcc is applied to the source terminal of resistor 102.

[0019] The source terminal of a transistor refers to a source region that is a part of the active layer, or Similarly, the drain terminal of a transistor refers to the connected source electrode of the active layer. The term "drain electrode" refers to a drain region that is a part of the active layer, or a drain electrode that is connected to the active layer.

[0020] In addition, the gate and drain terminals of the transistor 103 are connected to the circuit 101 . The circuit 101 selects either the potential VDD or the potential VSS according to the potential Vin, The gate or drain terminal of the transistor 103. The source of the transistor 103 A potential VEE is applied to the terminal via a wiring 106. The potential VEE is higher than the potential VDD. The potential VEE is a low level potential. The potential VEE is the same potential as the potential VSS, or A higher potential is desirable.

[0021] The source terminal and the drain terminal of the transistor are connected to each other. The name changes depending on the potential applied to the electrodes. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source terminal, and the electrode to which a high potential is applied is called the The electrode that is connected to the drain terminal is called the drain terminal. The electrode to which the high potential is applied is called the drain terminal, and the electrode to which the high potential is applied is called the source terminal. For convenience, it is assumed in this specification that the source and drain terminals are fixed. In some cases, the connection relationship of the transistors is explained based on the above potential relationships. The names of the source and drain terminals are interchangeable.

[0022] In this specification, the term "connection" means electrical connection, and the current, voltage, or potential is This corresponds to a state where the signal can be supplied or transmitted. Therefore, the connected state is a direct connection. does not necessarily refer to the state in which a current, voltage or potential is available or transferable. To make it possible to transmit signals, the devices must be wired, conductive, resistors, diodes, transistors, etc. This also includes situations where the connection is indirectly made via another means.

[0023] In addition, even if components that are independent on the circuit diagram are connected, For example, when a part of a wiring functions as an electrode, one conductive film is a In this specification, the term "connection" refers to such a single conductive film. However, cases where the functions of multiple components are combined are also included in this category.

[0024] In addition, the potential applied from the circuit 101 to the gate of the transistor 102 and the potential The potential applied to the gate of the transistor 103 is the same as that of the transistor 104. In A), the gate of transistor 102 and the gate of transistor 103 are connected. This example illustrates a case where

[0025] In the semiconductor device 100 shown in FIG. 1A, the potential Vin of the signal is The transistors 102 and 103 are turned on. By turning it off or on, you can select either the potential VDD or the potential VEE, and the potential Vo ut to the wiring 108. When the transistor 8 is connected, the potential of the wiring 104 is output as a potential Vout. When the wiring 106 and the wiring 108 are connected by the resistor 103, the potential of the wiring 106 becomes It is output as Vout.

[0026] The wiring called bus lines connected to multiple pixels, such as scanning lines and signal lines, When supplying a potential Vout output from the body device 100, the output of the potential Vout is controlled. The transistor 103 that controls the output is required to have a large current supply capability. The channel width W of the transistor 103 is the same as that of the transistor in the circuit 101 or the transistor 1 It is desirable to design it to a value larger than the channel width W of .02.

[0027] If the transistor 102 is an n-channel type, the transistor 102 is When a potential VDD is applied to the transistor 102 from the circuit 101, the transistor 102 is turned on. When the potential VSS is applied to the gate from the circuit 101, the gate voltage Vgs becomes 0V. Therefore, the transistor 102 is normally off, that is, the threshold voltage Vth is higher than 0V. If the transistor 102 is not normally on, the transistor 102 is turned off. That is, if the threshold voltage Vth is equal to or lower than 0 V, the transistor 102 is turned on and not turned off. become.

[0028] The transistor 103 operates in the same manner as the transistor 102. When the transistor 103 is an n-channel type, the transistor 103 has a gate connected to the When a potential VDD is applied from the transistor 103, the transistor 103 is turned on. When a potential VSS is applied from the line 101, the gate voltage Vgs=VSS-VEE. Therefore, the gate voltage Vgs is 0 V or less. Therefore, the transistor 103 is normally off. That is, if the threshold voltage Vth is higher than 0V, the transistor 103 is turned off. If the transistor 103 is normally on, that is, if the threshold voltage Vth is 0 V or less, the transistor There are also cases where the transistor 103 is turned on rather than turned off.

[0029] Hereinafter, when the transistor 102 and the transistor 103 are normally on, The operation of the semiconductor device 100 shown in FIG. 1A will be described in detail.

[0030] When VSS-VEE>Vth, the potential VSS is applied to the gate of the transistor 103. Then, the gate voltage Vgs of the transistor 103 is Vgs=VSS-VEE>Vth. Therefore, the transistor 103 is turned on. When the potential VSS is applied to the gate of the transistor 102, the transistor 102 is turned on regardless of the value of the potential VEE. do.

[0031] Then, the transistors 102 and 103 are turned on instead of being turned off. Then, the drain terminals of the transistors 102 and 103 are connected to the circuit 101. When a potential VDD is applied from the A current flows through the wiring 106 via the transistor 103. The potential of the wiring 106 also rises from the potential VSS to the potential VSS+Vα. The potential rises from VEE to VEE+Vβ.

[0032] As described above, the channel width W of the transistor 103 is If the width W of the transistor 102 is larger than the width W of the transistor 102, the gate voltage Vgs is the same. A current flows to a wiring 106 through a transistor 103 from a current flowing to a wiring 105 through the transistor 103. Therefore, the channel width W of the transistor 103 is larger than that of the transistor 102. When the channel width W of the wiring 106 is larger than the channel width W of the wiring 105, the increase in the potential of the wiring 106 is larger than the increase in the potential of the wiring 105. Eventually, the potential VSS+Vα=the potential VEE+Vβ+Vth. Thus, transistor 103 is driven low until its gate voltage Vgs reaches the threshold voltage Vth. Therefore, even if the transistor 103 is normally on, Therefore, when the transistor 103 should be off, it can be brought to a state close to off.

[0033] On the other hand, when VSS-VEE≦Vth, the potential VSS is applied to the gate of the transistor 103. When the gate voltage Vgs is given, VSS-VEE≦Vth. Therefore, in this case, Transistor 103 can be turned off even if it is normally on.

[0034] When a potential VSS is applied to the gate of the transistor 102, the value of the potential VEE Therefore, the potential of the wiring 105 is changed from the potential VSS to the potential VSS+Vα The potential of the wiring 105 is applied to the gate of the transistor 103 by the circuit 101. Therefore, the potential of the wiring 105 is increased, and a voltage is applied to the gate of the transistor 103. The potential at the node Vcc also rises from the potential VSS to the potential VSS+Vα.

[0035] Even if the potential applied to the gate of the transistor 103 increases, the gate voltage Vgs=VSS If +Vα-VEE≦Vth, the transistor 103 remains off. Gate voltage If Vgs=VSS+Vα-VEE>Vth, the transistor 103 will be turned on. However, in this case, a current flows through the wiring 106 via the transistor 103. The potential of the line 106 rises, and finally the potential VSS+Vα=the potential VEE+Vγ+Vth. Therefore, the transistor 103 does not turn on until the gate voltage Vgs reaches the threshold voltage Vth. Since the output voltage is low at

[0036] In this manner, in the semiconductor device 100 according to one aspect of the present invention, the transistor located on the output side A wiring 106 for applying a potential to the source terminal of the transistor 103 and a transistor other than the transistor 103 A wiring 105 for supplying a potential to a source terminal of a transistor (for example, a transistor 102) is connected to the By adopting this configuration, when the drain current of the transistor 103 is large, the drain current of the transistor 1 Negative feedback can be applied so that the gate voltage of transistor 03 approaches the threshold voltage. Even if the transistor 103 is normally on, it is possible to turn off the transistor 103. Therefore, the potential of the wiring 104 drops due to the resistance of each wiring, and the potential of the wiring 105 Even if the temperature rises, the power consumption of the semiconductor device 100 can be kept low. This makes it possible to prevent the amplitude of the potential Vout output from the device 100 from becoming small.

[0037] In FIG. 1A, the transistor 102 and the transistor 103 are both n-channel transistors. In the illustrated example, the transistor 102 and the transistor 103 are of a common type. However, in this case, the source terminal of the transistor 102 may be a p-channel type. A wiring 105 connected to the source terminal of the transistor 103 and a wiring 106 connected to the source terminal of the transistor 103 A higher potential than that of the wiring 104 is applied to the wiring 105 .

[0038] In addition, in the semiconductor device illustrated in FIG. 1A, an output The case where the output transistor 103 is normally on has been described. In this embodiment, a transistor on the output side that controls the output of the potential of the wiring 104 is normally Even if it is on, the transistor can be turned off when it should be turned off. The present invention focuses on a transistor on the output side that controls the output of the potential of the wiring 104. The operation of a semiconductor device according to one embodiment will be described.

[0039] FIG. 1B illustrates another example of a circuit configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device 100 shown in FIG. 1B is a circuit 101 including a plurality of transistors. The semiconductor device includes a resistor 102, a transistor 103, a transistor 109, and a capacitor 110. In the semiconductor device 100, at least a transistor 102 and a transistor 103 , and the transistor 109 have the same polarity. 1, the transistor 103 and the transistor 109 are both n-channel transistors. is doing.

[0040] In the semiconductor device 100 shown in FIG. 1B, unlike the case of FIG. 1A, The gate of transistor 103 is connected to circuit 101, and the drain terminal of transistor 103 is , is connected to the source terminal of the transistor 109 and the wiring 108. The gate of the transistor 109 is connected to the circuit 101. The circuit 101 is connected to the potential Vin as follows: Either the potential VDD or the potential VSS is applied to the gate of the transistor 103, and the other is applied to the gate of the transistor 104. The source terminal of the transistor 103 is connected to the wiring 106. A potential VEE is applied to the drain terminal of the transistor 109 via the wiring 104. A potential VDD is applied via

[0041] The capacitor 110 has a function of holding the gate voltage of the transistor 109. When the parasitic capacitance of the gate of the transistor 109 is large, a capacitor 110 is provided. If the gate voltage can be maintained without the need for a capacitor 110, the capacitor 110 is not necessarily required. .

[0042] Then, the transistor 102, the transistor 103, and the transistor 109 are normally The operation of the semiconductor device 100 when it is on will now be described in detail.

[0043] When VSS-VEE>Vth, the gates of the transistors 102 and 103 When a potential VDD is applied to the transistor 102, the transistor 103 is turned on. On the other hand, a potential VDD is applied to the gates of the transistors 102 and 103. When the transistor 109 is turned on, the gate of the transistor 109 is supplied with the potential VSS. The gate voltage Vgs of the transistor 109 is Vgs=VSS-VEE>Vth, so The transistor 109 and the transistor 110 are turned on, whereas they should be turned off. A current flows between the wiring 106 and the wiring 104 via the transistor 103, and the potential of the wiring 104 becomes The potential of the wiring 105 decreases, and the potential of the wiring 105 increases.

[0044] However, in one embodiment of the present invention, the potential of the wiring 106 is changed from the potential VEE to the potential VEE+Va. By increasing the gate voltage Vgs of the transistor 109, the gate voltage Vgs of the transistor 109 reaches the threshold voltage Vth. The potential Vs becomes lower, and finally the transistor 109 becomes close to OFF. When S=potential VEE+Vα+Vth, the transistor 109 is turned off. Even if the transistor 109 is normally on, the transistor 109 should be turned off. When the power is turned on, the power can be turned off.

[0045] On the other hand, when VSS-VEE≦Vth, the potential VSS is applied to the gate of the transistor 109. When the gate voltage Vgs is given, VSS-VEE≦Vth. Therefore, in this case, Transistor 109 can be turned off even if it is normally on.

[0046] In this manner, in the semiconductor device 100 according to one aspect of the present invention, the transistor located on the output side A wiring 106 for applying a potential to the source terminal of the transistor 103 and a transistor other than the transistor 103 A wiring 105 for supplying a potential to a source terminal of a transistor (for example, a transistor 102) is connected to the By configuring the transistor 109 so that the drain current of the transistor 109 is large, Negative feedback can be applied so that the gate voltage of transistor 09 approaches the threshold voltage. Even if the transistor 109 is normally on, it is possible to turn off the transistor 109. Therefore, the potential of the wiring 104 drops due to the resistance of each wiring, and the potential of the wiring 105 Even if the temperature rises, the power consumption of the semiconductor device 100 can be kept low. This makes it possible to prevent the amplitude of the potential Vout output from the device 100 from becoming small.

[0047] In FIG. 1B, the transistor 102, the transistor 103, and the transistor 1 In the example shown, both the transistor 102 and the transistor 09 are n-channel type. The transistor 103 and the transistor 109 may both be p-channel types. In this case, the wiring 105 connected to the source terminal of the transistor 102 and the A higher potential than that of the wiring 104 is applied to the wiring 106 connected to the source terminal of the third transistor. The composition is as follows.

[0048] Next, a pulse generating circuit, which is one of the semiconductor devices according to one embodiment of the present invention, will be described. 2 shows an example of a pulse generating circuit according to one embodiment of the present invention.

[0049] The pulse generating circuit 200 shown in FIG. 2 includes a circuit 201 and transistors 202 to The circuit 201 corresponds to the circuit 101 shown in FIG. The transistor 202 and the transistor 203 are the same as the transistor 102 shown in FIG. The transistor 204 corresponds to the transistor 103 shown in FIG. In addition, various potentials are applied to the pulse generating circuit 200 from wirings 205 to 212. A potential is output to the wiring 213 and the wiring 214 .

[0050] A shift register can be configured by connecting the above pulse generating circuit 200 in multiple stages. can.

[0051] In the case where the transistor 202 and the transistor 203 are n-channel type, specifically, A potential VDD is applied to the wiring 205, a potential VSS is applied to the wiring 206, and a potential A potential VEE is applied to the wiring 208, and a potential LIN is applied to the wiring 209. The potential LIN and the potential RIN are applied to the semiconductor device shown in FIG. This corresponds to the potential Vin at 100.

[0052] The wirings 210 to 212 are connected to the clock signals CL1 to CL4. That is, the potentials of any three clock signals are respectively applied. The potential of the clock signal CL1 is applied to the wiring 210, the potential of the clock signal CL2 is applied to the wiring 211, 2 is supplied with the potential of clock signal CL3.

[0053] The gate of the transistor 202 is connected to the gates of the transistors 203 and 204. The source terminal is connected to the wiring 206, and the drain terminal is connected to the circuit 201. The source terminal of the transistor 203 is connected to the wiring 206. The drain terminal of the transistor 204 is connected to the circuit 201. The drain terminal of the transistor is connected to the wiring 207, and the drain terminal of the transistor is connected to the circuit 201 and the wiring 213. do.

[0054] The circuit 201 includes transistors 215 to 223, a capacitor 224, and a Specifically, the transistor 215 has a gate connected to the wiring. 208, the source terminal of which is connected to the drain terminal of transistor 202, The drain terminal of the transistor 216 is connected to the wiring 205. line 211, the source terminal of which is connected to the drain terminal of transistor 218; The drain terminal is connected to the wiring 205. The gate of the transistor 217 is The source terminal of the transistor 202, the transistor 203, and the and the gate of the transistor 204, the drain terminal of which is connected to the wiring 205. The transistor 218 has a gate connected to the wiring 212 and a source terminal connected to the transistor 218. A transistor 202, a transistor 203, and a transistor 204 are connected to the gates of the transistors 202, 203, and 204. The transistor 219 has a gate connected to the wiring 208 and a source terminal connected to the wiring 209. line 206, the drain terminal of which is connected to transistors 202, 203, and and the gate of transistor 204. Transistor 220 has a gate One of the source terminal and the drain terminal of the transistor 215 is connected to the wiring 205. The other terminal is connected to the source terminal and the drain terminal of the transistor 202. The source terminal of the transistor 221 is connected to the gate of the wiring 214. and its drain terminal is connected to the wiring 210. The transistor 222 is The gate is connected to the wiring 205, and one of the source terminal and the drain terminal is a transistor. the source terminal of the transistor 215 and the drain terminal of the transistor 202, The transistor 223 is connected to the gate of the transistor 223. The transistor 223 is connected to its source terminal is connected to the wiring 213, and its drain terminal is connected to the wiring 210. 24 has one electrode connected to the gate of transistor 221 and the other electrode One electrode of the capacitor 225 is connected to the line 214 of the transistor 223. The other electrode is connected to the gate, and the other electrode is connected to the wiring 213.

[0055] The operation of the pulse generating circuit 200 shown in FIG. 2 will be described with reference to the timing chart shown in FIG. I will use this to explain.

[0056] As shown in FIG. 3, during a period t1, the voltage of the clock signal CL1 applied to the wiring 210 The potential of the clock signal CL2 applied to the wiring 211 is at a low level, the potential of the clock signal CL2 applied to the wiring 212 is at a high level, The potential of the clock signal CL3 applied to the wiring 212 is at a high level, and the potential of the clock signal CL3 applied to the wiring 208 is at a low level. The potential LIN is at a low level, and the potential RIN applied to the wiring 209 is at a low level.

[0057] Therefore, in the period t1, in the pulse generating circuit 200, the transistors 202 to transistor 204, transistor 216, transistor 218, transistor 220, Transistor 222 is turned on. Transistor 215, transistor 217, and transistor Therefore, the wiring The potential of the wiring 206 is outputted from the wiring 213 as a potential GOUT. The potential is output from the wiring 214 as a potential SROUT.

[0058] Next, as shown in FIG. 3, during a period t2, a clock signal C The potential of L1 is at a low level, and the potential of the clock signal CL2 applied to the wiring 211 is at a low level. The potential of the clock signal CL3 applied to the wiring 212 is at a high level, and the potential of the clock signal CL4 applied to the wiring 208 is at a low level. The potential LIN applied to the wiring 209 is at a high level, and the potential RIN applied to the wiring 209 is at a low level. .

[0059] Therefore, in the period t2, in the pulse generating circuit 200, the transistor 215 The transistors 218 to 223 are turned on. Transistor 204, transistor 216 and transistor 217 are turned off. The potential of the wiring 210 is outputted from the wiring 213 as a potential GOUT and is outputted from the wiring 213 as a potential SROUT. The signal is then output from a wiring 214.

[0060] Next, as shown in FIG. 3, during a period t3, a clock signal C The potential of L1 is high level, and the potential of the clock signal CL2 applied to the wiring 211 is low level. The potential of the clock signal CL3 applied to the wiring 212 is at a low level, and the potential of the clock signal CL4 applied to the wiring 208 is at a low level. The potential LIN applied to the wiring 209 is at a high level, and the potential RIN applied to the wiring 209 is at a low level. .

[0061] Therefore, in the period t3, in the pulse generating circuit 200, the transistor 215 The transistor 219, the transistor 221, and the transistor 223 are turned on. Transistors 202 to 204, transistors 216 to 218, Therefore, the potential of the wiring 210 is The potential GOUT is output from the wiring 213, and the potential SROUT is output from the wiring 214. can be.

[0062] Next, as shown in FIG. 3, during a period t4, a clock signal C The potential of L1 is at a high level, and the potential of the clock signal CL2 applied to the wiring 211 is at a high level. The potential of the clock signal CL3 applied to the wiring 212 is at a low level, and the potential of the clock signal CL4 applied to the wiring 208 is at a low level. The potential LIN applied to the wiring 209 is at a low level, and the potential RIN applied to the wiring 209 is at a low level. .

[0063] Therefore, in the period t4, in the pulse generating circuit 200, the transistor 216 The transistors 202 to 203 are turned on. transistor 204, transistor 215, transistor 217 to transistor 220, Therefore, the potential of the wiring 210 is changed to the potential GOUT. The potential is output from the wiring 213 and output from the wiring 214 as a potential SROUT.

[0064] Next, as shown in FIG. 3, during a period t5, a clock signal C The potential of L1 is low level, and the potential of the clock signal CL2 applied to the wiring 211 is high level. The potential of the clock signal CL3 applied to the wiring 212 is at a high level, and the potential of the clock signal CL4 applied to the wiring 208 is at a low level. The potential LIN applied to the wiring 209 is at a low level, and the potential RIN applied to the wiring 209 is at a high level. .

[0065] Therefore, in the period t5, in the pulse generating circuit 200, the transistors 202 to 204, transistors 216 to 218, transistor 220, Transistor 222 is turned on. Transistor 215, transistor 219, and transistor Therefore, the potential of the wiring 207 is The potential of the wiring 206 is output as a potential GOUT from the wiring 213. T is output from the wiring 214.

[0066] In the above operation, the transistor 204 is turned off from the period t2 to the period t4. In particular, during periods t3 and t4, the clock signal CL1 applied to the wiring 210 When the transistor 204 is on because the potential is at a high level, the transistor 204 A current flows between the wiring 210 and the wiring 207 through the transistor 223. In one embodiment of the present invention, the gate and source terminals of the transistor 204 are electrically separated. Specifically, when the transistor 204 is turned off, the gate of the transistor 204 The potential of the wiring 206 is applied to the transistor 204, and the potential of the wiring 207 is applied to the source terminal of the transistor 204. Therefore, even if a current flows between the wiring 210 and the wiring 207, The electric potential of the wiring 207 increases due to the current, and the gate voltage Vgs of the transistor 204 exceeds the threshold As the voltage Vth approaches, transistor 204 can eventually be turned off.

[0067] FIG. 4 shows a shift register constructed by connecting the above-mentioned pulse generating circuit 200 in multiple stages. is shown as an example.

[0068] The shift register shown in FIG. 4 includes pulse generating circuits 200_1 to 200_y. The pulse generating circuits 200_1 to 200_y each have the same configuration as shown in FIG. 2. However, the wiring 210 shown in FIG. The wiring 212 is connected to any three of the clock signals CL1 to CL4. The potentials are given as follows:

[0069] Specifically, in the pulse generating circuit 200_4m+1, a clock signal CL1 is applied to the wiring 210, A clock signal CL2 is applied to the line 211, and a clock signal CL3 is applied to the wiring 212. Pulse In the generating circuit 200_4m+2, the wiring 210 is connected to the clock signal CL2, the wiring 211 is connected to the clock signal CL3, A clock signal CL3 is applied to the wiring 211, and a clock signal CL4 is applied to the wiring 212. In 4m+3, the clock signal CL3 is applied to the wiring 210, the clock signal CL4 is applied to the wiring 211, and A clock signal CL1 is applied to a line 212. In the pulse generating circuit 200_4m+4, A clock signal CL4 is applied to a line 210, a clock signal CL1 is applied to a line 211, and a clock signal CL2 is applied to a line 212. Here, m is the total number of the pulse generating circuits 200, and y is the sum of the m and y. Let be any integer that satisfies.

[0070] In the shift register shown in FIG. 4, a pulse generating circuit 200_j (j is y or less) 4 and 5, the positions of the wirings 208 to 214 included in the semiconductor device 100 (natural numbers) are shown in FIG. As can be seen from FIG. 6, the wiring 208 of the pulse generating circuit 200_j is connected to the The potential SROUTj-1 output from the wiring 214 of the circuit 200_j-1 is set as the potential LIN. However, the wiring 208 of the first stage pulse generating circuit 200_1 is provided with a start The potential of the pulse signal SP is applied.

[0071] In addition, the wiring 209 of the pulse generating circuit 200_j is connected to the pulse generating circuit 200_ The potential SROUTj+2 output from the j+2th wiring 214 is given as the potential RIN. However, the wiring 208 of the pulse generating circuit 200_y-1 in the y-1th stage is connected to a potential RIN _y-1 is applied to the wiring 208 of the y-th stage pulse generating circuit 200_y, and a potential RIN The potential RIN_y-1 is given by the pulse generating circuit 200_y+1. Assuming that the pulse generator circuit 200_y+1 exists, The potential RIN_y is assumed to be a potential SROUTy+1. Assuming that a pulse generator circuit 200_y+2 exists, the pulse generator circuit 200_y+2 outputs The potential SROUTy+2 that would be reached is assumed.

[0072] A potential GOUTj is output from the wiring 213 of the pulse generating circuit 200_j.

[0073] FIG. 5 shows the potentials of the clock signals CL1 to CL4 and the start pulse signal SP 1 shows a timing chart of the potentials GOUT1 to GOUT3. The potential rise timing of the clock signals CL1 to CL4 is a quarter period. The shift register shown in FIG. 4 shifts the waveform backward according to the above signal. The pulse width is half the period of the clock signal. A potential GO having a waveform in which the pulses are shifted backward by a quarter period of the clock signal. UT1 outputs a potential GOUTy.

[0074] For example, the shift register shown in FIG. 4 can be used to When potentials GOUT1 to GOUTy are supplied to wiring, for example, scanning lines and signal lines, , the output side transistors of the pulse generating circuits 200_1 to 200_y The transistor 204 is required to have a large current supply capability. The channel width W of the transistor 204 is larger than the channel width W of the transistors other than the transistor 204. Therefore, if the transistor 204 is normally on, The power consumption of the shift register increases, or the output potentials GOUT1 to GO However, as one aspect of the present invention, In the embodiment, the output of each of the pulse generating circuits 200_1 to 200_y is Even if the transistor 204 on the output side is normally on, the transistor 204 is turned off. You can turn it off when you want to.

[0075] Therefore, a shift register according to one embodiment of the present invention using the above shift register has low power consumption. The force is suppressed to be small, and the amplitude of the output potentials GOUT1 to GOUTy is reduced. Furthermore, the semiconductor device according to one embodiment of the present invention using the above shift register can be prevented from being damaged. The display device has low power consumption and the amplitude of the signal applied to the bus line is small. It is possible to prevent display defects caused by the above.

[0076] As a comparative example, in the pulse generating circuit 200 shown in FIG. Consider the case where the two are electrically connected. The circuit includes a transistor 204, a transistor 222, a transistor 223, and a capacitance element 2 25, the connection relationship between the wiring 205, the wiring 207, and the wiring 210. In this example, the wiring 207 is connected to the wiring 206 (not shown) and is supplied with the potential VSS. It is assumed that the above information is correct.

[0077] In addition, in FIG. 7A, the wiring resistance of the wiring 207 is illustrated as a resistor 230. The wiring resistance of the wiring 210 is illustrated as a resistor 231.

[0078] As mentioned above, transistors using amorphous silicon or oxide semiconductors For example, if the channel length L of a transistor is 6 μm, When the width W is 10 μm, the current flowing when the gate voltage Vgs is 0 V is 0.5 μm. In order to increase the current supply capacity of the transistor, the channel width W is increased to 1 It is not uncommon to make the thickness of the transistor about 1000 μm, but the thickness of the transistor having the above current-voltage characteristics is about 1000 μm. If the channel width is increased from 10 μm to 1000 μm, when the gate voltage Vgs is 0 V, The current flowing through the resistor will be 100 times that, or 0.05 mA.

[0079] Assuming that each pulse generator consumes 0.05mA of current, the shift register If the number of stages of the pulse generation circuit in the shift register is 960, the total number of stages of the shift register is about 50. A current of mA will flow.

[0080] Assume that resistor 230 is 100 Ω and resistor 231 is 100 Ω. The transistor 204 is normally on, and as described above, when the gate voltage Vgs is 0 V, Assume that a current of .05 mA flows between the drain terminal of transistor 223 and wiring 210. The connection point is node A, and the connection point between the source terminal of the transistor 204 and the wiring 207 is node When the transistor 204 is turned on, a current flows through the transistor 204, and the potential of the node A falls. The potential of the wiring 207 increases due to the transistor 20 It corresponds to the product of the current flowing through resistor 4, the resistance value of resistor 230, and the number of stages of the shift register. The amount of potential drop in the wiring 210 is determined by the current flowing through the transistor 204 and the resistance of the resistor 231. The amount of potential drop and the amount of potential rise are , each with a maximum of 5V.

[0081] In FIG. 7B, an ideal waveform of the potential GOUT output from the wiring 213 is shown by a solid line 232. The ideal potential GOUT is a pulse whose potential difference corresponds to the difference between the potentials VSS and VDD. In addition, in FIG. 7B, the potential of the wiring 207 increases and the potential of the wiring 210 decreases. The waveform of the potential GOUT output from the wiring 213 when the potential is lowered is shown by a solid line 233. The potential GOUT shown by the solid line 233 is the potential difference between the pulse potential VSS+ΔV1 and the It corresponds to the difference between VDD and ΔV2. In the above example, ΔV1 and ΔV2 are about 5V. It can be seen that the amplitude is significantly reduced compared to the previous one.

[0082] However, in one embodiment of the present invention, if the transistor 204 on the output side is normally on, Therefore, the output potential GOUT This prevents the amplitude of the input signal from becoming small, thereby reducing power consumption.

[0083] (Embodiment 2) A configuration example of a pulse generating circuit according to one embodiment of the present invention will be described.

[0084] The pulse generating circuit 300 shown in FIG. 8A includes a circuit 301 and transistors 302 to The circuit 301 corresponds to the circuit 101 shown in FIG. The transistor 302 and the transistor 303 are the same as the transistor 1 shown in FIG. The transistor 304 corresponds to the transistor 103 shown in FIG. Correct.

[0085] A shift register can be configured by connecting the above pulse generating circuit 300 in multiple stages. can.

[0086] The gate of the transistor 302 is connected to the gates of the transistors 303 and 304. The source terminal is connected to the wiring 306, and the drain terminal is connected to the circuit 301. The source terminal of the transistor 303 is connected to the wiring 306. The drain terminal of the transistor 304 is connected to the circuit 301 and the wiring 314. The source terminal is connected to the wiring 307, and the drain terminal is connected to the circuit 301 and the wiring 313. is connected to

[0087] The circuit 301 also includes transistors 315 to 320. The transistor 315 has a gate connected to the wiring 308 and a source terminal connected to the transistor The drain terminal of the transistor 302 is connected to the wiring 305. The transistor 316 has a gate connected to the wiring 309 and a source terminal connected to the transistor 316. connected to the gates of transistors 302, 303, and 304; The drain terminal is connected to the wiring 305. The gate of the transistor 317 is The source terminal of the transistor 302, the transistor 303, and the and the gate of the transistor 304, the drain terminal of which is connected to the wiring 305. The transistor 318 has a gate connected to the wiring 308 and a source terminal connected to the wiring 309. line 306, the drain terminal of which is connected to transistors 302, 303, and and the gate of transistor 304. Transistor 319 has a gate A source terminal of the transistor 315 and a drain terminal of the transistor 302 are connected to the The source terminal of the transistor is connected to the wiring 314, and the drain terminal of the transistor is connected to the wiring 311. Transistor 320 has its gate connected to the source terminal of transistor 315 and the transistor The drain terminal of the capacitor 302 is connected to the source terminal of the capacitor 302, and the drain terminal of the capacitor 302 is connected to the wiring 313. The IN terminal is connected to the wiring 312 .

[0088] When the transistors 302 to 304 are n-channel transistors, specifically, A potential VDD is applied to the wiring 305, a potential VSS is applied to the wiring 306, and a potential A potential VEE is applied to the wirings 308 to 312. In addition to the potential Vin in the semiconductor device 100, various signal potentials such as a clock signal are applied. A potential GOUT is output from the wiring 313, and a potential SROUT is output from the wiring 314. will be done.

[0089] The pulse generating circuit 300 shown in FIG. 8A has the above-mentioned configuration, and the transistor 30 on the output side The gate and source terminals of the transistor 3 can be electrically separated. 304 is normally on, so that the source terminal of the transistor 304 Even if the potential of the wiring 307 for supplying a potential rises, the transistor 304 is turned off. You can turn it off when you need it.

[0090] The pulse generating circuit 330 shown in FIG. 8B includes a circuit 331 and transistors 332 to The circuit 331 corresponds to the circuit 101 shown in FIG. The transistor 332 and the transistor 333 are the same as the transistor 1 shown in FIG. The transistor 334 corresponds to the transistor 103 shown in FIG. Correct.

[0091] A shift register can be configured by connecting the above pulse generating circuit 330 in multiple stages. can.

[0092] The gate of the transistor 332 is connected to the gates of the transistors 333 and 334. The source terminal is connected to the wiring 336, and the drain terminal is connected to the circuit 331. The source terminal of the transistor 333 is connected to the wiring 336. The drain terminal of the transistor 334 is connected to the circuit 331 and the wiring 345. The source terminal is connected to the wiring 337, and the drain terminal is connected to the circuit 331 and the wiring 344. is connected to

[0093] The circuit 331 also includes transistors 346 to 352. A transistor 346 has its gate connected to the line 338 and its source terminal connected to the transistor The drain terminal of the transistor 332 is connected to the wiring 335. The transistor 347 has a gate connected to the wiring 339 and a source terminal connected to the transistor 347. connected to the gates of transistors 332, 333, and 334; The drain terminal is connected to the line 335. The gate of the transistor 348 is The source terminal of the transistor 332, the transistor 333, and the and the gate of a transistor 334, the drain terminal of which is connected to a wiring 335. The transistor 349 has its gate connected to the wiring 338 and its source terminal connected to the wiring 338. line 336, the drain terminal of which is connected to transistors 332, 333, and and the gate of transistor 334. Transistor 350 has a gate The source terminal of the transistor 332, the transistor 333, and the and the gate of a transistor 334, the drain terminal of which is connected to a wiring 335. Transistor 351 has its gate connected to the source terminal of transistor 346 and the The drain terminal of the resistor 332 is connected to the wiring 345, and the source terminal of the resistor 332 is connected to the wiring 345. The drain terminal is connected to the wiring 342. The transistor 352 has a gate The source terminal of the transistor 346 and the drain terminal of the transistor 332 are connected to the The source terminal is connected to wiring 344 and the drain terminal is connected to wiring 343 .

[0094] When the transistors 332 to 334 are n-channel transistors, specifically, A potential VDD is applied to the wiring 335, a potential VSS is applied to the wiring 336, and a potential VSS is applied to the wiring 337. A potential VEE is applied to the wirings 338 to 343. In addition to the potential Vin in the semiconductor device 100, various signal potentials such as a clock signal are applied. Then, the potential GOUT is output from the wiring 344, and the potential SROUT is output from the wiring 345. will be done.

[0095] With the above configuration, the pulse generating circuit 330 shown in FIG. The gate and source terminals of the transistor 3 can be electrically separated. Assuming that transistor 334 is normally on, then the source terminal of the transistor 334 Even if the potential of the wiring 337 for supplying a potential rises, the transistor 334 is turned off. You can turn it off when you need it.

[0096] The pulse generating circuit 360 shown in FIG. 9A includes a circuit 361 and transistors 362 to The circuit 361 corresponds to the circuit 101 shown in FIG. The transistor 362 and the transistor 363 are the same as the transistor 1 shown in FIG. The transistor 364 corresponds to the transistor 103 shown in FIG. Correct.

[0097] A shift register can be configured by connecting the above pulse generating circuit 360 in multiple stages. can.

[0098] The gate of the transistor 362 is connected to the gates of the transistors 363 and 364. The source terminal is connected to the wiring 366, and the drain terminal is connected to the circuit 361. The transistor 363 has its source terminal connected to the wiring 366. The drain terminal of the transistor 364 is connected to the circuit 361 and the wiring 375. The source terminal is connected to the wiring 367, and the drain terminal is connected to the circuit 361 and the wiring 374. is connected to

[0099] The circuit 361 also includes transistors 376 to 382. A transistor 376 has its gate connected to the line 368 and its source terminal connected to the transistor The drain terminal of the transistor 362 is connected to the wiring 365. The transistor 377 has a gate connected to the wiring 365 and a source terminal and One of the drain terminals is connected to the source terminal of transistor 376 and the drain terminal of transistor 362. The other end is connected to the gates of transistors 381 and 382. The transistor 378 has its gate connected to the wiring 369 and its source The terminal is connected to the gates of transistors 362, 363, and 364. The drain terminal of the transistor 379 is connected to the line 365. The gate is connected to the wiring 368, the source terminal is connected to the wiring 366, and the drain The terminal is connected to the gates of transistors 362, 363, and 364. The transistor 380 has its gate connected to the wiring 370 and its source The terminal is connected to the gates of transistors 362, 363, and 364. The drain terminal of the transistor 381 is connected to the line 365. The source terminal is connected to the wiring 375 and the drain terminal is connected to the wiring 371 . Transistor 382 has its source terminal connected to line 374 and its drain terminal connected to line It is connected to line 372.

[0100] In the case where the transistors 362 to 364 are n-channel transistors, specifically, A potential VDD is applied to the wiring 365, a potential VSS is applied to the wiring 366, and a potential A potential VEE is applied to the wirings 368 to 372. In addition to the potential Vin in the semiconductor device 100, various signal potentials such as a clock signal are applied. Then, the potential GOUT is output from the wiring 374, and the potential SROUT is output from the wiring 375. will be done.

[0101] With the above configuration, the pulse generating circuit 360 shown in FIG. The gate and source terminals of the transistor 3 can be electrically separated. Assuming that transistor 364 is normally on, then the source terminal of the transistor 364 Even if the potential of the wiring 367 for supplying a potential rises, the transistor 364 is turned off. You can turn it off when you need it.

[0102] The pulse generating circuit 400 shown in FIG. 9B includes a circuit 401 and transistors 402 to The circuit 401 corresponds to the circuit 101 shown in FIG. The transistor 402 and the transistor 403 are the same as the transistor 1 shown in FIG. The transistor 404 corresponds to the transistor 103 shown in FIG. Correct.

[0103] A shift register can be configured by connecting the above pulse generating circuit 400 in multiple stages. can.

[0104] The gate of the transistor 402 is connected to the gates of the transistors 403 and 404. The source terminal is connected to the wiring 406, and the drain terminal is connected to the circuit 401. The source terminal of the transistor 403 is connected to the wiring 406. A drain terminal of the transistor 404 is connected to the circuit 401 and a wiring 415. The source terminal is connected to the wiring 407, and the drain terminal is connected to the circuit 401 and the wiring 414. is connected to

[0105] The circuit 401 also includes transistors 416 to 423. A transistor 416 has its gate connected to the wiring 408 and its source terminal connected to the transistor The drain terminal of the transistor 402 is connected to the wiring 405. The transistor 417 has a gate connected to the wiring 405 and a source terminal and One of the drain terminals is connected to the source terminal of transistor 416 and the drain terminal of transistor 402. The other end is connected to the gate of transistor 421. The gate of the transistor 418 is connected to the wiring 409, and the source terminal of the transistor 40 2, connected to the gates of transistors 403 and 404, and The gate of the transistor 419 is connected to the wiring 408. The source terminal is connected to the wiring 406, and the drain terminal is connected to the transistor 40 2, connected to the gates of transistors 403 and 404. The gate of the transistor 420 is connected to the wiring 410, and the source terminal of the transistor 40 2, connected to the gates of transistors 403 and 404, and The source terminal of the transistor 421 is connected to the wiring 415. and its drain terminal is connected to the wiring 411. The transistor 422 is The gate is connected to the wiring 405, and one of the source terminal and the drain terminal is a transistor. The other end is connected to the gate of transistor 423. The transistor 423 has a source terminal connected to the wiring 414 and a drain terminal is connected to the wiring 412.

[0106] When the transistors 402 to 404 are n-channel transistors, specifically, A potential VDD is applied to the wiring 405, a potential VSS is applied to the wiring 406, and a potential A potential VEE is applied to the wirings 408 to 412. In addition to the potential Vin in the semiconductor device 100, various signal potentials such as a clock signal are applied. A potential GOUT is output from the wiring 414, and a potential SROUT is output from the wiring 415. will be done.

[0107] The pulse generating circuit 400 shown in FIG. 9B has the above-mentioned configuration, and the transistor 40 on the output side The gate and source terminals of transistor 4 can be electrically separated. 04 is normally on, so that the source terminal of the transistor 404 Even if the potential of the wiring 407 for supplying a potential rises, the transistor 404 is turned off. You can turn it off when you need it.

[0108] The pulse generating circuit 430 shown in FIG. 10 includes a circuit 431 and transistors 432 to The circuit 431 corresponds to the circuit 101 shown in FIG. The transistor 432 and the transistor 433 are the same as the transistor 102 shown in FIG. The transistor 434 corresponds to the transistor 103 shown in FIG. do.

[0109] A shift register can be configured by connecting the above pulse generating circuit 430 in multiple stages. can.

[0110] The gate of the transistor 432 is connected to the gates of the transistors 433 and 434. The source terminal is connected to the wiring 436, and the drain terminal is connected to the circuit 431. The transistor 433 has a source terminal connected to a wiring 436. A drain terminal of the transistor 434 is connected to the circuit 431 and the wiring 445. The source terminal is connected to the wiring 437, and the drain terminal is connected to the circuit 431 and the wiring 444. is connected to

[0111] The circuit 431 also includes transistors 446 to 453. A transistor 446 has its gate connected to the line 438 and its source terminal connected to the transistor The drain terminal of the transistor 432 is connected to the wiring 435. The transistor 447 has a gate connected to the wiring 439 and a source terminal connected to the transistor 447. connected to the gates of transistors 432, 433, and 434; The drain terminal is connected to the wiring 435. The transistor 448 has a gate The source terminal of the transistor 432, the transistor 433, and the and the gate of a transistor 434, the drain terminal of which is connected to a wiring 435. The transistor 449 has a gate connected to the wiring 438 and a source terminal connected to the wiring 438. line 436, the drain terminal of which is connected to transistors 432, 433, and and the gate of transistor 434. Transistor 450 has a gate One of the source terminal and the drain terminal of the transistor 446 is connected to the wiring 435. The other terminal is connected to the source terminal and the drain terminal of the transistor 432. The source terminal of the transistor 451 is connected to the gate of the wiring 445. and its drain terminal is connected to the wiring 441. The transistor 452 is The gate is connected to the wiring 435, and one of the source terminal and the drain terminal is a transistor. the source terminal of transistor 446 and the drain terminal of transistor 432, The transistor 453 is connected to the gate of the transistor 453. The transistor 453 is connected to its source terminal is connected to the wiring 444 and its drain terminal is connected to the wiring 442 .

[0112] When the transistors 432 to 434 are n-channel transistors, specifically, A potential VDD is applied to the wiring 435, a potential VSS is applied to the wiring 436, and a potential A potential VEE is applied to the wirings 438 to 442. In addition to the potential Vin in the semiconductor device 100, various signal potentials such as a clock signal are applied. A potential GOUT is output from the wiring 444, and a potential SROUT is output from the wiring 445. will be done.

[0113] The pulse generating circuit 430 shown in FIG. 10 has the above-mentioned configuration. The gate and source terminals of the transistor 434 can be electrically separated. is normally on, so that the source terminal of the transistor 434 has a potential Even if the potential of the wiring 437 for supplying power increases, the transistor 434 is turned off. You can turn it off when you need to.

[0114] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0115] (Embodiment 3) A configuration example of an inverter, which is one of the semiconductor devices of one embodiment of the present invention, will be described.

[0116] FIG. 11 shows an example of an inverter according to one embodiment of the present invention. The inverter 50 shown in FIG. Circuit 500 includes a circuit 501, a transistor 502, and a transistor 503. The transistor 502 corresponds to the circuit 101 shown in FIG. The transistor 503 corresponds to the transistor 102 shown in FIG. This corresponds to the transistor 103.

[0117] The transistor 502 has a gate connected to a wiring 509 and a source terminal connected to a wiring 50 5 and its drain terminal is connected to the circuit 501. The transistor 503 is , its gate is connected to the wiring 509, its source terminal is connected to the wiring 506, and its drain The drain terminal is connected to the circuit 501 and the wiring 508 .

[0118] The circuit 501 includes transistors 510 to 512 and a capacitor 513. Specifically, the transistor 510 has a gate connected to the wiring 507, The source terminal is connected to the drain terminal of transistor 502, and the drain terminal is The gate of the transistor 511 is connected to the wiring 504. , one of its source terminal and drain terminal is connected to the source terminal and drain terminal of transistor 510. The drain terminal of the transistor 502 is connected to the gate of the transistor 512. The transistor 512 has a source terminal connected to the drain terminal of the transistor 503. The capacitance element is connected to a drain terminal of the capacitance element and a wiring 508, and the drain terminal of the capacitance element is connected to a wiring 504. One electrode of the transistor 513 is connected to the gate of the transistor 512, and the other electrode is connected to wiring 508.

[0119] In the case where the transistor 502 and the transistor 503 are n-channel transistors, specifically, A potential VDD is applied to the wiring 504, a potential VSS is applied to the wiring 505, and a potential A potential VEE is applied to the wiring 507. A potential of a clock signal is applied to the wiring 508. The potential Vin in the semiconductor device 100 shown in FIG. In FIG. 1, the potential Vin is the potential output from the wiring 214 of the pulse generating circuit 200 shown in FIG. The example shows a case where the potential SROUT is a polarity of the potential SROUT. A potential SROUTb obtained by inverting the polarity of the potential SROUTb is output.

[0120] In the inverter 500 shown in FIG. 11, the gate of the transistor 503 on the output side is Therefore, the transistor 503 can be electrically separated from the source terminal. As a result, a potential is provided to the source terminal of the transistor 503. Even if the potential of the wiring 506 for supplying the current increases, the transistor 503 should be turned off. Sometimes you can turn it off.

[0121] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0122] (Embodiment 4) Taking an EL display device as an example, the following describes a configuration of a pixel and a driver circuit of a semiconductor display device according to one embodiment of the present invention. The cross-sectional structure will be described with reference to FIG. 12. In FIG. 12, a pixel 840 and a driving circuit 841 are shown. A cross-sectional view is shown as an example.

[0123] In FIG. 12, a pixel 840 includes a light emitting element 832 and a control circuit for controlling the supply of current to the light emitting element 832. The pixel 840 includes the light emitting element 832 and a transistor 831 for controlling the light emitting element. In addition to the transistor 831, a transistor that controls the input of an image signal to the pixel 840 and a The input / output terminal may include various semiconductor elements such as a capacitor element for holding the potential of the signal.

[0124] In addition, in FIG. 12, the driver circuit 841 includes a transistor 830 and a transistor and a capacitor 833 for holding the gate voltage of the transistor 830. The shift register corresponding to a part of the driver circuit 841 has an output transistor. The driver circuit 841 includes a transistor 830 and a capacitor 833. It may also include various semiconductor elements such as transistors and capacitors.

[0125] The transistor 831 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 816, the gate insulating film 802 on the conductive film 816, and the conductive film 816 at a position overlapping the gate insulating film 802. A semiconductor film 817 located on the gate insulating film 802 and a source terminal or a drain terminal The conductive film 815 and the conductive film 818 are located over the semiconductor film 817. The film 816 also functions as a scan line.

[0126] The transistor 830 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 812, the gate insulating film 802 on the conductive film 812, and the conductive film 812 at a position overlapping the gate insulating film 802 A semiconductor film 813 located on the gate insulating film 802 and a source terminal or a drain terminal The semiconductor film 813 includes a conductive film 814 and a conductive film 819 located over the semiconductor film 813 .

[0127] The capacitor 833 is formed by forming a conductive film 812 over a substrate 800 having an insulating surface. The gate insulating film 802 and the conductive film 812 are overlapped with each other. and a conductive film 819 disposed therebetween.

[0128] In addition, an insulating film 820 is formed over the conductive film 814, the conductive film 815, the conductive film 818, and the conductive film 819. and an insulating film 821 are provided in this order. A conductive film 822 that functions as an anode is provided on the insulating film 820. and is connected to the conductive film 818 via a contact hole 823 formed in the insulating film 821. It is being done.

[0129] In addition, an insulating film 824 having an opening through which a part of the conductive film 822 is exposed is formed on the insulating film 82 An EL layer 825 and an insulating film 824 are provided on a part of the conductive film 822 and the insulating film 824. A conductive film 826 serving as a cathode is provided in this order. The region where the light emitting element 832 is formed is an area where the EL layer 825 and the conductive film 826 overlap each other. do.

[0130] Note that in one embodiment of the present invention, the transistors 830 and 831 are amorphous and Semiconductors such as silicon or germanium, which may be crystalline, polycrystalline or single crystalline, are used for the semiconductor film. Alternatively, a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor film. It's fine if it is.

[0131] The semiconductor films of the transistors 830 and 831 may be amorphous, microcrystalline, polycrystalline, or When a semiconductor such as silicon or germanium, which is a single crystal, is used, it is necessary to give one conductivity. The semiconductor film is doped with an impurity element that functions as a source terminal or a drain terminal. For example, by adding phosphorus or arsenic to the semiconductor film, It is possible to form an impurity region having n-type conductivity. By adding this to a semiconductor film, an impurity region having p-type conductivity can be formed.

[0132] When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, In this case, a dopant is added to the semiconductor film to function as a source terminal or a drain terminal. The dopant can be added by ion implantation. Dopants include rare gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, Group 15 atoms such as arsenic and antimony can be used. For example, nitrogen can be used as a dopant. When used as a sintered body, the concentration of nitrogen atoms in the impurity region is 5×10 19 / cm 3 1x or more 10 22 / cm 3 It is desirable that the following:

[0133] Silicon semiconductors are grown by vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon produced by the laser annealing method, amorphous silicon Polycrystalline silicon that has been crystallized by implanting hydrogen ions into single crystal silicon wafers. For example, single crystal silicon from which a portion has been peeled off can be used.

[0134] The oxide semiconductor contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of the transistors In addition, it is preferable to have gallium (Ga). Also, tin (S n) as a stabilizer. It is preferable that the stabilizer is aluminum (Al). It is nice.

[0135] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may contain one or more of the elements tetraethium (Lu).

[0136] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. The oxide semiconductor may contain silicon.

[0137] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, Since it is possible to sufficiently reduce the current and the mobility is high, it is suitable for use in semiconductor devices. It is suitable as a semiconductor material.

[0138] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The oxides of In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having a molecular ratio or an oxide having a composition close to that.

[0139] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0140] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid The reduced electron vacancies result in a highly purified oxide semiconductor. A de semiconductor is an i-type (intrinsic semiconductor) or is very close to an i-type. Therefore, the off-state current of a transistor including the oxide semiconductor is extremely low. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. More preferably, the concentration of impurities such as moisture or hydrogen is sufficiently reduced. In addition, an oxide semiconductor film that has been highly purified by reducing oxygen vacancies is used. This allows the off-state current of the transistor to be reduced.

[0141] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor for a semiconductor film is low. For example, when the channel width is 1×10 6 μm Even with a device with a channel length of 10 μm, the voltage between the source and drain terminals (drain voltage When the applied voltage is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-state current normalized by the channel width of the transistor was found to be 100 zA / μm or less. In addition, the capacitance element and the transistor are connected to each other, so that current can flow into or out of the capacitance element. The off-state current was measured using a circuit that controls the outflow of charge using the transistor. In the measurement, a highly purified oxide semiconductor film was placed in a channel formation region of the transistor. The off-state current of the transistor is measured based on the change in the amount of charge per unit time of the capacitor. As a result, when the voltage between the source and drain terminals of the transistor is 3V, several It was found that an even lower off-current of 10 yA / μm could be obtained. In a transistor in which an oxide semiconductor film having a crystalline structure is used for a channel formation region, the off-state current is This is significantly lower than that of a silicon-based transistor having a low thermal conductivity.

[0142] Unless otherwise specified, in this specification, the off-state current is In this case, the drain terminal is set to a higher potential than the source terminal and gate. When the potential of the gate is 0 V or less with respect to the potential of the transistor, In this specification, the off-state current refers to the current that flows between the p-channel and p-channel terminals. In a diode-type transistor, the drain terminal is at a lower potential than the source terminal and gate. In this state, when the potential of the gate is 0V or higher with respect to the potential of the source terminal as the reference In other words, it refers to the current that flows between the source terminal and the drain terminal.

[0143] For example, the oxide semiconductor film may be formed using In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing In-Ga- When the Zn-based oxide semiconductor film is formed by a sputtering method, the atomic ratio is preferably In :Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or A target of In-Ga-Zn oxide with the atomic ratio of 3:1:4 is used. The oxide semiconductor film is formed by using an In-Ga-Zn oxide target having the above structure. Polycrystals or CAAC-OS, which will be described later, are easily formed. The filling rate of the target containing Zn is 90% or more and 100% or less, preferably 95% or more and 100% or less. The oxide semiconductor film formed by using a target with a high filling rate is less than 0%. forms a dense film.

[0144] When an In-Zn oxide material is used as the oxide semiconductor, The atomic ratio composition of the metal elements is In:Zn=50:1 to 1:2 (molar ratio). This translates to In 2 O 3 In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 ~1:1 (molar ratio of In 2 O 3 ZnO=10:1 to 1:2), more preferably Or In:Zn=1.5:1 to 15:1 (in terms of molar ratio, In 2 O 3 :ZnO= For example, in the formation of an oxide semiconductor film that is an In-Zn oxide, The target used has an atomic ratio of In:Zn:O=X:Y:Z, where Z>1.5X+Y By keeping the ratio of Zn within the above range, it is possible to improve the mobility.

[0145] Specifically, the oxide semiconductor film is formed by holding the substrate in a treatment chamber that is kept in a reduced pressure state. The residual moisture in the treatment chamber is removed while introducing a sputtering gas from which hydrogen and moisture have been removed. During the film formation, the substrate temperature is preferably set to 100° C. or higher and 600° C. or lower. Preferably, the temperature may be 200° C. or higher and 400° C. or lower. In this way, the impurity concentration in the formed oxide semiconductor film can be reduced. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a blimpation pump. Also, a turbo pump is used as the exhaust means. A cold trap may be added to the vacuum chamber. The processing chamber is evacuated using a cryopump. Then, for example, hydrogen atom, water (H 2 Compounds containing hydrogen atoms such as 1,2-dihydrogen (preferably carbon-1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, Since the exhaust gas contains fluorine atoms, the oxide semiconductor film formed in the treatment chamber is This can reduce the concentration of impurities contained in the material.

[0146] Note that moisture or hydrogen ( Water or hydrogen can form donor levels and Therefore, in one embodiment of the present invention, To reduce impurities such as moisture or hydrogen in semiconductor films (dehydration or dehydrogenation) For the oxide semiconductor film, a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an oxygen atmosphere is used. Under nitrogen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. The heat treatment is performed in an atmosphere of air, preferably 1 ppm or less, preferably 10 ppb or less. Carry out.

[0147] By performing heat treatment on the oxide semiconductor film, moisture or hydrogen is released from the oxide semiconductor film. Specifically, the substrate temperature is 250° C. or higher and 750° C. or lower, preferably 400° C. or higher. For example, the heat treatment may be performed at 500° C. for 3 to 6 minutes. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be carried out in a short time. Therefore, processing can be performed at temperatures exceeding the distortion point of the glass substrate.

[0148] Note that the heat treatment causes oxygen to be released from the oxide semiconductor film and the oxygen to be left in the oxide semiconductor film. Therefore, in one embodiment of the present invention, a vacancy may be formed in the gate electrode in contact with the oxide semiconductor film. An insulating film containing oxygen is used as an insulating film such as a gate insulating film. After the insulating film is formed, heat treatment is performed, whereby oxygen is supplied from the insulating film to the oxide semiconductor film. With the above structure, oxygen vacancies serving as donors are reduced, and oxygen atoms contained in the oxide semiconductor film are The stoichiometric composition of the oxide semiconductor to be formed can be satisfied. As a result, the oxide semiconductor film is made to have a nearly i-type This reduces the variation in the electrical characteristics of transistors caused by oxygen vacancies, and It is possible to realize improved mechanical properties.

[0149] Note that the heat treatment for supplying oxygen to the oxide semiconductor film is performed using nitrogen, ultra-dry air, or rare earth metal. In a gas (argon, helium, etc.) atmosphere, preferably at 200°C to 400°C The gas has a water content of 20 ppm or less. It is desirable that the concentration is not more than 1 ppm, and more preferably not more than 10 ppb.

[0150] The oxide semiconductor may be amorphous or crystalline. In the latter case, it may be a single crystal, a polycrystal, or a structure partially having crystallinity. It may be composed of an amorphous structure, a structure containing a crystalline portion in an amorphous structure, or a non-amorphous structure. An example of a structure having a portion with crystallinity is a structure having a c-axis orientation and an ab-plane. It has a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the surface or interface, and has a perpendicular c-axis. When viewed from the perpendicular direction, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers, In the b-plane, the crystals have different a-axis or b-axis orientations (rotated around the c-axis). Things(CAAC-OS:C Axis Aligned Crystalline Oxi de Semiconductor.) may also be used.

[0151] In a broad sense, CAAC-OS is a non-single crystal that has three crystals perpendicular to the ab plane. The atomic arrangement is a square, hexagonal, equilateral triangle, or equilateral hexagon, and the direction is perpendicular to the c-axis. From the viewpoint of the structure, oxides that contain a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers, are called say.

[0152] CAAC-OS is not a single crystal, but it is not composed only of amorphous matter. CAAC-OS contains crystalline parts, but the boundary between one crystalline part and another crystalline part cannot be clearly determined. Sometimes it’s impossible to tell.

[0153] A part of oxygen constituting CAAC-OS may be replaced by nitrogen. The c-axes of the individual crystal parts constituting the CAAC-OS are aligned in a certain direction (for example, The CAAC-OS surface may be aligned in a direction perpendicular to the plate surface. The normal of the ab plane of each crystal part constituting the -OS is in a certain direction (for example, CAAC-OS The direction may be perpendicular to the substrate surface on which the CAAC-OS is formed, or perpendicular to the surface of the CAAC-OS.

[0154] Depending on the composition, CAAC-OS may or may not be transparent to visible light. It may not be there.

[0155] An example of such a CAAC-OS is a film-like structure having a structure perpendicular to the film surface or the supporting substrate surface. When observed from a certain direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, This reveals a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms). Crystals may also be mentioned.

[0156] Next, an example of a specific structure of a transistor included in the semiconductor device of the present invention will be described. do.

[0157] The transistor shown in FIG. 13A is a bottom-gate type transistor with a channel-etched structure.

[0158] The transistor shown in FIG. 13A has a gate electrode (Gate 1602, a gate insulating film 1603 on the gate electrode 1602, and a gate insulating film 160 3, a semiconductor film 1604 overlapping the gate electrode 1602, and a semiconductor film 1604 The transistor further includes a conductive film 1605 and a conductive film 1606 formed thereon. An insulating film 1607 formed on the semiconductor film 1604, the conductive film 1605, and the conductive film 1606 is , may be included in its components.

[0159] Note that the transistor shown in FIG. 13A has an insulating layer at a position overlapping with the semiconductor film 1604. A back gate electrode formed on the insulating film 1607 may also be included.

[0160] The transistor shown in FIG. 13B is a bottom-gate transistor with a channel protection structure.

[0161] The transistor shown in FIG. 13B has a gate electrode 161 formed on an insulating surface. 2, a gate insulating film 1613 on the gate electrode 1612, and A semiconductor film 1614 overlapping the gate electrode 1612 and a gate electrode 1613 formed on the semiconductor film 1614. A channel protective film 1618 formed on the semiconductor film 1614, a conductive film 1615 formed on the semiconductor film 1614, and a conductive The transistor further includes a channel protection film 1618 and a conductive film 1616. 15 and an insulating film 1617 formed on the conductive film 1616 may be included as a component. .

[0162] Note that the transistor shown in FIG. 13B has an insulating layer at a position overlapping with the semiconductor film 1614. A back gate electrode formed on the insulating film 1617 may also be included.

[0163] By providing a channel protective film 1618, the channel forming region of the semiconductor film 1614 and In the later process, the film is formed by plasma or etching agent during etching on the part that will be This prevents damage such as wear and tear, thus improving the reliability of the transistor. can be done.

[0164] The transistor shown in FIG. 13C is a bottom-gate type transistor having a bottom-contact structure.

[0165] The transistor shown in FIG. 13C has a gate electrode 162 formed on an insulating surface. 2, a gate insulating film 1623 on the gate electrode 1622, and a conductive film on the gate insulating film 1623. A gate electrode 1622 is formed on the gate insulating film 1623. The semiconductor film 162 overlaps the conductive film 1625 and the conductive film 1626. The transistor further includes a conductive film 1625, a conductive film 1626, and a semiconductor An insulating film 1627 formed on the film 1624 may be included as a component thereof.

[0166] Note that the transistor shown in FIG. 13C has an insulating layer at a position overlapping with the semiconductor film 1624. A back gate electrode formed on the insulating film 1627 may also be included.

[0167] The transistor shown in FIG. 13D is a top-gate type with a bottom-contact structure.

[0168] The transistor shown in FIG. 13D includes a conductive film 1645 formed on an insulating surface, A conductive film 1646, a semiconductor film 1644 over the conductive film 1645 and the conductive film 1646, and a semiconductor A gate insulating film 1643 is formed on the film 1644, and a semiconductor device is formed on the gate insulating film 1643. The transistor further comprises a gate electrode 1642 overlapping the conductive film 1644. An insulating film 1647 formed on the gate electrode 1642 may be included as a component thereof.

[0169] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0170] (Embodiment 5) FIG. 14 illustrates an example of a panel, which is one embodiment of a semiconductor display device. The panel shown in FIG. 1 includes a substrate 700, a pixel portion 701 on the substrate 700, a signal line driver circuit 702, The display device includes a scanning line driver circuit 703 and a terminal 704 .

[0171] The pixel portion 701 has a plurality of pixels, and each pixel has a display element and a control circuit for controlling the operation of the display element. The scanning line driver circuit 703 is provided with one or more transistors for each pixel. The pixel portion 701 is provided with a pixel selector 702, and a pixel selector 703 is provided to select the pixel by controlling the supply of a potential to a scanning line connected to the pixel. The signal line driver circuit 702 outputs an image to the pixel selected by the scanning line driver circuit 703. Controls the signal supply.

[0172] In the panel shown in FIG. 14, the scanning line driver circuit 703 is provided with a shift register according to one embodiment of the present invention. In FIG. 14, a potential V This shows an example in which EE, potential VSS, and potential VDD are applied.

[0173] Since the scanning lines are connected to multiple pixels, they require a large current supply capacity. A potential is supplied to the scanning line by using a shift register according to one embodiment of the present invention. Therefore, the amplitude of the potential applied to the scanning line can be prevented from becoming small. The display defect in the pixel portion 701 caused by the small amplitude of the signal is reduced, and high image quality is achieved. It is possible to display images of.

[0174] In this embodiment, the scan line driver circuit 703 is provided with a shift register according to one embodiment of the present invention. However, the case where a transistor according to one embodiment of the present invention is used for the signal line driver circuit 702 is described. A soft register may also be used.

[0175] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0176] (Embodiment 6) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras, digital cameras, etc. Cameras such as TasStill cameras, goggle-type displays (head-mounted displays) ), navigation systems, audio playback devices (car audio, digital audio players) Years, etc.), copiers, facsimiles, printers, printer-combination machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0177] FIG. 15A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The semiconductor according to one embodiment of the present invention is used in a driver circuit of a portable game machine. By using this device, it is possible to provide a portable game machine with low power consumption and stable operation. The semiconductor device according to one embodiment of the present invention is used for the display portion 5003 or the display portion 5004. By doing so, it is possible to provide a portable game machine with high image quality. The portable game machine has two display units 5003 and 5004. The number of display units that the game machine has is not limited to this.

[0178] FIG. 15B shows a display device, which includes a housing 5201, a display portion 5202, a support stand 5203, and the like. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a display device, power consumption can be reduced. It is possible to provide a display device with low resistance and stable operation. By using the semiconductor display device according to one embodiment, a display device with high image quality can be provided. Display devices include those for personal computers, those for receiving TV broadcasts, and those for displaying advertisements. All display devices for displaying information are included.

[0179] FIG. 15C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. 5403, a pointing device 5404, etc. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a mobile computer, power consumption can be reduced. It is possible to provide a notebook type personal computer that requires less force and operates stably. By using a semiconductor display device according to one embodiment of the present invention for the display portion 5402, a notebook type A personal computer may be provided.

[0180] FIG. 15D shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 5602. 5605, and the angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 5605. It may also be configured to switch according to the angle between the first housing 5601 and the second housing 5602. In addition, at least one of the first display section 5603 and the second display section 5604 may be provided with a position input. A semiconductor display device with additional functions as a device may be used. The function of the input device can be added by providing a touch panel to the semiconductor display device. Alternatively, the function as a position input device can be realized by using a photoelectric conversion element also called a photosensor. The signal can also be added by providing it in a pixel portion of a semiconductor display device. By using a semiconductor device according to one embodiment of the present invention in a circuit, power consumption is low and operation is stable. A portable information terminal having the first display unit 5603 or the second display unit 5604 can be provided. By using a semiconductor display device according to one embodiment of the present invention, a portable information terminal with high image quality can be provided. It can be provided.

[0181] FIG. 15E shows a mobile phone. The mobile phone includes a housing 5801, a display unit 5802, an audio input unit 5803, The device has a voice output unit 5804, an operation key 5805, a light receiving unit 5806, etc. By converting the light received in the mobile phone into an electrical signal, it is possible to capture an image from the outside. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a mobile phone, power consumption can be reduced. In this way, a mobile phone with stable operation can be provided. By using such a semiconductor display device, a mobile phone with high image quality can be provided.

[0182] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0183] 100 Semiconductor device 101 Circuit 102 Transistor 103 Transistor 104 Wiring 105 Wiring 106 Wiring 107 Wiring 108 Wiring 109 Transistor 110 Capacitive element 200 Pulse Generator Circuit 200_1 to 200_y Pulse generating circuit 201 Circuit 202 Transistor 203 Transistor 204 Transistor 205 Wiring 206 Wiring 207 Wiring 208 Wiring 209 Wiring 210 Wiring 211 Wiring 212 Wiring 213 Wiring 214 Wiring 215 Transistor 216 Transistor 217 Transistor 218 Transistor 219 Transistor 220 Transistor 221 Transistor 222 Transistor 223 Transistor 224 Capacitive element 225 Capacitive element 230 Resistance 231 Resistance 232 Solid line 233 Solid Line 300 Pulse Generator Circuit 301 Circuit 302 Transistor 303 Transistor 304 Transistor 305 Wiring 306 Wiring 307 Wiring 308 Wiring 309 Wiring 310 Wiring 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Transistor 316 Transistor 317 Transistor 318 Transistor 319 Transistor 320 Transistor 330 Pulse Generator Circuit 331 Circuit 332 Transistor 333 Transistor 334 Transistor 335 Wiring 336 Wiring 337 Wiring 338 Wiring 339 Wiring 340 Wiring 341 Wiring 342 Wiring 343 Wiring 344 Wiring 345 Wiring 346 Transistor 347 Transistor 348 Transistor 349 Transistor 350 Transistors 351 Transistor 352 Transistor 360 Pulse Generator Circuit 361 circuits 362 Transistor 363 Transistor 364 Transistor 365 Wiring 366 Wiring 367 Wiring 368 Wiring 369 Wiring 370 Wiring 371 Wiring 372 Wiring 374 Wiring 375 Wiring 376 Transistors 377 Transistors 378 Transistors 379 Transistor 380 Transistors 381 Transistor 382 Transistor 400 Pulse Generator Circuit 401 Circuit 402 Transistor 403 Transistor 404 Transistor 405 Wiring 406 Wiring 407 Wiring 408 Wiring 409 Wiring 410 Wiring 411 Wiring 412 Wiring 414 Wiring 415 Wiring 416 Transistor 417 Transistor 418 Transistor 419 Transistor 420 Transistor 421 Transistor 422 Transistor 423 Transistor 430 Pulse Generator Circuit 431 Circuit 432 Transistor 433 Transistor 434 Transistor 435 Wiring 436 Wiring 437 Wiring 438 Wiring 439 Wiring 440 Wiring 441 Wiring 442 Wiring 444 Wiring 445 Wiring 446 Transistor 447 Transistor 448 Transistor 449 Transistor 450 Transistors 451 Transistor 452 Transistor 453 Transistor 500 Inverter 501 Circuit 502 Transistor 503 Transistor 504 Wiring 505 Wiring 506 Wiring 507 Wiring 508 Wiring 509 Wiring 510 Transistor 511 Transistor 512 Transistor 513 Capacitive element 700 Substrates 701 Pixel section 702 Signal line driver circuit 703 Scanning line driver circuit 704 Terminal 800 boards 802 Gate insulating film 812 Conductive film 813 Semiconductor Film 814 Conductive film 815 Conductive Film 816 Conductive Film 817 Semiconductor Film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 823 Contact Hole 824 Insulating film 825 EL layer 826 Conductive Film 830 Transistor 831 Transistor 832 Light emitting element 833 Capacitive element 840 pixels 841 Drive circuit 1602 Gate electrode 1603 Gate insulating film 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Gate electrode 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protection film 1622 Gate electrode 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Gate electrode 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Support stand 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 1st unit 5602 2nd unit 5603 1st display section 5604 2nd display section 5605 Connection 5606 Operation key 5801 Case 5802 Display section 5803 Audio input unit 5804 Audio output unit 5805 Operation key 5806 Light receiving section

Claims

1. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; A second potential is supplied to the other of the source and the drain of the ninth transistor. Semiconductor device.

2. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; Semiconductor device.

3. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; a second potential is supplied to the other of the source and the drain of the ninth transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

4. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

5. In any one of claims 1 to 4, The first transistor to the ninth transistor have the same polarity. Semiconductor device.

6. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; a second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; Semiconductor device.

7. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; Semiconductor device.

8. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; a second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

9. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

10. In any one of claims 6 to 9, The first transistor to the eleventh transistor have the same polarity. Semiconductor device.

11. In any one of claims 6 to 10, A gate of the tenth transistor and a gate of the eleventh transistor are input with mutually different signals. Semiconductor device.

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