Authentication device and image forming apparatus

Abstract

To provide an authentication system that enhances resistance to an information analysis type of attack while preventing an increase in cost.SOLUTION: An authentication target device stores in advance first allowance data used for determination as to whether or not to allow responding to an authentication request. An authentication device comprises: a measurement unit that measures a time during which the authentication device is energized; a storage unit that stores restriction data that becomes readable after the measured time reaches a reference time; a communication unit that transmits, to the authentication target device, second allowance data that is verified by the authentication target device with the use of the first allowance data, and is based on the restriction data read from the storage unit; and an authentication unit that, when the verification of the second allowance data using the first allowance data is successful in the authentication target device, authenticates the authentication target device on the basis of an authentication response received from the authentication target device.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to an authentication device and an image forming device. [Background technology]

[0002] Conventionally, many electronic devices are known that are used with replaceable parts connected. For example, an image forming apparatus can operate with various replaceable parts, such as a cartridge containing toner or ink, a process cartridge, a conveying roller, or a fixing unit. If a replaceable part that is not assumed in the design of an electronic device is connected to the electronic device, problems such as a breakdown of the electronic device, a malfunction, or a decrease in output quality may occur. For this reason, some electronic devices have a mechanism for authenticating whether a replaceable part connected to the main body is a genuine part.

[0003] Patent Document 1 discloses an example of an authentication method for a printer (authentication device) to authenticate a replaceable consumable (authenticated device) such as a toner cartridge. In the authentication method disclosed in Patent Document 1, password authentication is performed using a different password for each authentication device, and a challenge-response type main authentication session is started only when the password authentication is successful. This reduces the risk that the authentication key used for the main authentication will be read by a malicious third party. In addition, since a password derivative value derived from a master password is used for password authentication, the master password is not exposed outside the device. Since a legitimate authenticated device stores all candidate values ​​of secret information for deriving a derivative value for verification in a non-volatile memory, it operates effectively no matter which authentication device it is connected to. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-167671 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the authentication method of Patent Document 1, in order to improve resistance to information analysis attacks such as microprobing, it is necessary to increase the variation of secret information installed in a product. When M types of secret information are used in a certain product group, the number of products required to know M values ​​can be calculated according to the idea of ​​the so-called coupon collector problem. For example, when M=10, statistically, there is a high possibility that all 10 types of secret information can be known by obtaining 30 products. On the other hand, increasing the variation of secret information leads to an increase in the size of the non-volatile memory built into the device, increasing costs.

[0006] In view of the above, the present invention provides an authentication method that improves resistance to information analysis attacks while suppressing increases in costs. [Means for solving the problem]

[0007] According to one aspect, there is provided an authentication device for authenticating an authenticated device, the authenticated device pre-stores first permission data used to determine whether or not to permit a response to an authentication request received from the authentication device, the authentication device including: a measurement unit that measures a time during which the authentication device is powered on, a storage unit that stores restriction data that becomes readable after the time measured by the measurement unit reaches a preset reference time, a communication unit that transmits to the authenticated device second permission data to be verified by the authenticated device using the first permission data, the second permission data being based on the restriction data read from the storage unit, and an authentication unit that authenticates the authenticated device based on an authentication response received from the authenticated device when the verification of the second permission data using the first permission data in the authenticated device is successful. An image forming apparatus including the authentication device is also provided. Effect of the Invention

[0008] According to the present invention, it is possible to provide an authentication method that improves resistance to information analysis attacks while suppressing increases in costs. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram showing a state in which a process cartridge is connected to an image forming apparatus in an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of an authentication chip according to the first embodiment. [Diagram 3] FIG. 2 is a block diagram showing an example of the configuration of an authenticated chip according to the first embodiment. [Figure 4] 6 is a flowchart showing an example of the flow of a data generation process for generating data to be stored in the memories of the authenticating chip and the authenticated chip according to the first embodiment. [Diagram 5] 4 is a flowchart showing an example of an overall processing flow in the authentication system according to the first embodiment. [Figure 6] FIG. 4 is a sequence diagram showing an example of a detailed flow of authentication processing according to the first embodiment. [Figure 7] FIG. 11 is a block diagram showing an example of the configuration of an authentication chip according to a second embodiment. [Figure 8] FIG. 11 is a block diagram showing an example of the configuration of an authenticated chip according to a second embodiment. [Figure 9] 10 is a flowchart showing an example of the flow of a data generation process for generating data to be stored in the memories of an authenticating chip and an authenticated chip according to the second embodiment. [Figure 10] FIG. 11 is a sequence diagram showing an example of a detailed flow of authentication processing according to the second embodiment. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of an authentication chip according to a third embodiment. [Figure 12] FIG. 11 is a block diagram showing an example of the configuration of an authenticated chip according to a third embodiment. [Figure 13] 13 is a flowchart showing an example of the flow of a data generation process for generating data to be stored in the memories of an authenticating chip and an authenticated chip according to the third embodiment. [Figure 14] 13 is a flowchart showing an example of an overall processing flow in an authentication system according to a third embodiment. [Figure 15] FIG. 13 is a sequence diagram showing an example of a detailed flow of authentication processing according to the third embodiment. [Figure 16] FIG. 13 is a block diagram showing an example of the configuration of an authentication chip according to a fourth embodiment. [Figure 17] FIG. 13 is a sequence diagram showing an example of a detailed flow of authentication processing according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] <1. Basic configuration> In the embodiment described below, the authentication chip mounted on the image forming apparatus authenticates the process cartridge connected to the image forming apparatus. Therefore, the image forming apparatus may be referred to as the authentication device, the process cartridge as the authenticated device, and the two collectively as the authentication system. The process cartridge is an example of a replaceable part for the image forming apparatus. However, the technology disclosed herein is not limited to the combination of the image forming apparatus and the process cartridge, and can be applied to combinations of various electronic devices and replaceable parts.

[0012] FIG. 1 shows a state in which a process cartridge 200 is connected to an image forming apparatus 100. The image forming apparatus 100 may be, for example, a printer, a copier, or a multifunction machine, and forms an image on a sheet according to an electrophotographic process. The process cartridge 200 is a replaceable part involved in the electrophotographic process. For example, a user can open a cover (not shown) arranged on a housing of the image forming apparatus 100 and attach / detach the process cartridge 200 to / from the image forming apparatus 100. The process cartridge 200 includes, for example, a photoconductor and one or more members for forming a toner image on the surface of the photoconductor. The image forming apparatus 100 includes an engine controller 101. The engine controller 101 controls the overall operation of an image forming unit (not shown) of the image forming apparatus 100 for forming an image on a sheet, such as, for example, conveying a sheet, forming a toner image, transferring the toner image to the sheet, and fixing the toner image on the sheet.

[0013] If an unauthorized process cartridge is connected to the image forming apparatus 100, problems such as device failure, malfunction, or deterioration of print quality may occur. Therefore, the image forming apparatus 100 has a mechanism for authenticating whether a process cartridge attached to the apparatus is an authorized product. As components related to this authentication mechanism, the engine controller 101 has a connection interface (I / F) 103, a sensor 105, a control unit 107, and an authentication chip 110. The process cartridge 200 has an authenticated chip 210. Typically, the authentication chip 110 and the authenticated chip 210 are tamper-resistant.

[0014] The connection I / F 103 is communicatively connected to the authenticated chip 210. The connection between the connection I / F 103 and the authenticated chip 210 may be a wired connection via an electrical contact, or may be a wireless connection via an antenna. The sensor 105 is a detection unit for detecting whether or not a process cartridge is attached to the image forming apparatus 100. The control unit 107 is a controller for overall control of the operation of the image forming apparatus 100. The authentication chip 110 is an integrated circuit (IC) chip having a function of authenticating whether the process cartridge 200 is genuine based on authentication data received from the authenticated chip 210 via the connection I / F 103. The authenticated chip 210 is an IC chip with a built-in memory that prestores authentication data of the process cartridge 200.

[0015] In this embodiment, the authenticated chip 210 stores in advance first permission data used to determine whether or not to permit a response to an authentication request received from the authentication chip 110. Meanwhile, the authentication chip 110 stores in advance restriction data that is the basis for deriving second permission data verified by the authenticated chip 210 using the first permission data. Reading of the restriction data from the memory in the authenticated chip 210 is enabled after the time during which the authentication chip 110 is energized reaches a preset reference time. When the sensor 105 detects that the process cartridge 200 is mounted in the image forming apparatus 100, the control unit 107 starts an authentication process. In the authentication process, the authentication chip 110 reads the restriction data from the memory and transmits the second permission data to the authenticated chip 210 only when the time during which the authentication chip 110 is energized has already reached the reference time. Then, when the authentication chip 110 successfully verifies the second permission data using the first permission data, the authentication chip 110 authenticates the authenticated chip 210 according to a challenge-response authentication method.

[0016] In this way, by not transmitting the second authorization data to the authenticated chip 210 until the power-on time of the authentication chip 110 reaches the reference time (also called the time threshold), the time required for an attacker to analyze the product increases. Before the power-on time reaches the reference time, the image forming apparatus 100 may be permitted to use the process cartridge 200 without authentication, or the use may be restricted in some way. In the next section, some examples of such authentication methods will be described in detail.

[0017] <2. First Example> <2-1. Example of authentication chip configuration> Fig. 2 is a block diagram showing an example of the configuration of the authentication chip 110 according to the first embodiment. Referring to Fig. 2, the authentication chip 110 includes an internal bus 111, an input / output circuit 112, a control circuit 113, a volatile memory 114, a non-volatile memory 115, a cryptographic processing circuit 121, a random number generation circuit 122, a timer circuit 123, and a key access unit 124.

[0018] The internal bus 111 is a signal line that interconnects the control circuit 113, the volatile memory 114, the non-volatile memory 115, the encryption processing circuit 121, the random number generating circuit 122, the timer circuit 123, and the key access device 124. The input / output circuit 112 is a communication unit that relays data between the control unit 107 and the control circuit 113 of the authentication chip 110. The control circuit 113 controls communication with the device to be authenticated. The control circuit 113 may be, for example, a central processing unit (CPU), a microcontroller, or a microprocessor, and performs various processes according to commands input from the control unit 107. The volatile memory 114 may be, for example, a random access memory (RAM), and provides the control circuit 113 with a temporary storage area for calculations. The non-volatile memory 115 is a storage unit that may include, for example, a semiconductor memory or a hard disk.

[0019] In this embodiment, the non-volatile memory 115 stores one or more computer programs 116 executed by the control circuit 113, a password key (K PO ) 117, Authentication source key (K AO ) 118, and a timer counter (CT 2, the password source key 117 and the authentication source key 118 are stored in the non-volatile memory 115. The password source key 117 is an example of the restricted data described above. A password, which will be described later, is derived based on the password source key 117. The authentication source key 118 is a key that is a basis for deriving an authentication key used in challenge-response authentication. The authentication chip 110 stores the authentication source key 118, while the authenticated chip 210 stores a corresponding authentication key 218, as will be described later. As indicated by the dashed line in FIG. 2, the password source key 117 and the authentication source key 118 are stored in the restricted storage area 115a of the non-volatile memory 115. Access to the restricted storage area 115a (e.g., reading of data) is only possible via the key accessor 124.

[0020] The timer counter 119 is a counter value for monitoring the passage of time while the authentication chip 110 is energized. For example, the timer counter 119 has a value equal to the above-mentioned reference time as an initial value, and the value may be counted down while the authentication chip 110 is energized. In this case, when the value of the timer counter 119 becomes zero, it is determined that the reference time has elapsed.

[0021] The encryption processing circuit 121 is a calculation unit that executes encryption-related processing that may include hash function calculation or encryption using a common key cryptosystem. The random number generation circuit 122 is a generation unit that generates random numbers according to a command input from the control circuit 113. The random number generation circuit 122 is used, for example, to generate challenge data for challenge-response authentication. The timer circuit 123 is a measurement unit that measures the time during which the authentication chip 110 is energized. Although not shown in FIG. 2, the authentication chip 110 may further include a power supply circuit. The power supply circuit supplies power to each unit of the authentication chip 110 from an external power source (e.g., a commercial power source or a battery). The non-volatile memory 115 can maintain the above-mentioned programs and data even while the authentication chip 110 is not energized. The key access unit 124 is a device that restricts access to the restricted storage area 115a. Before the power-on time of the authentication chip 110 reaches a reference time, the key access unit 124 blocks access to the restricted storage area 115a. When the power-on time of the authentication chip 110 reaches a reference time, the key accessor 124 enables the authentication unit 131, which will be described later, to read data from the restricted storage area 115a.

[0022] In this embodiment, the control circuit 113 cooperates with the encryption processing circuit 121, the random number generating circuit 122, and the timer circuit 123 to function as an authentication unit 131 that performs authentication processing for authenticating the authenticated chip 210. The flow of the authentication processing will be described in detail later.

[0023] <2-2. Example of the configuration of the authenticated chip> Fig. 3 is a block diagram showing an example of the configuration of the authenticated chip 210 according to the first embodiment. Referring to Fig. 3, the authenticated chip 210 includes an internal bus 211, a connection I / F 212, a control circuit 213, a volatile memory 214, a non-volatile memory 215, a cryptographic processing circuit 221, and a key access unit 224.

[0024] The internal bus 211 is a signal line that interconnects the control circuit 213, the volatile memory 214, the non-volatile memory 215, the cryptographic processing circuit 221, and the key accessor 224. The connection I / F 212 is a communication unit that is communicatively connected to the authentication device. The control circuit 213 controls communication with the authentication device via the connection I / F 212. The control circuit 213 may be, for example, a CPU, a microcontroller, or a microprocessor. The volatile memory 214 may be, for example, a RAM, and provides the control circuit 213 with a temporary storage area for calculations. The non-volatile memory 215 is a storage unit that includes, for example, a semiconductor memory.

[0025] In this embodiment, the non-volatile memory 215 stores one or more computer programs 216 executed by the control circuit 213, a password hash value (P H ')217, Authentication key (K A ') 218, and the chip identifier (C ID ) 219. The password hash value 217 is an example of the above-mentioned first permission data. As will be described later, the password hash value 217 is used to determine whether or not to permit a response to an authentication request received from the authentication chip 110. The authentication key 218 is a key (first authentication key) used to generate response data in challenge-response authentication. The authentication key 218 forms a pair of common keys in a common key cryptosystem together with a key (second authentication key) derived in the authentication chip 110 based on the authentication source key 118. As shown by a dashed line in FIG. 3, the authentication key 218 is stored in a limited storage area 215a of the nonvolatile memory 215. Access to the limited storage area 215a (e.g., reading of data) is permitted only via the key access unit 224. The chip identifier 219 is an identifier unique to the authenticated chip 210. The chip identifier 219 may be, for example, a serial number that uniquely identifies an individual product of the process cartridge 200. The chip identifier 219 is used in pre-deriving the authentication key 218, and is additionally transmitted to the authentication chip 110 in order to cause the authentication chip 110 to derive a second authentication key during the authentication process.

[0026] Although not shown in FIG. 3, the non-volatile memory 215 may further store one or more control parameters indicating operating conditions suitable for the process cartridge 200. The operating conditions here may be image forming conditions that may include, for example, one or more of a process speed, a photoconductor charging voltage, a toner transfer voltage, and a fixing temperature. When access to the memory of the authenticated chip 210 is permitted, such control parameters may be read by the control unit 107 from the non-volatile memory 215 via the connection I / F 103 and used to control the operation of the image forming apparatus.

[0027] The cryptographic processing circuit 221 is a calculation unit that executes cryptographic processing that may include hash function calculations or encryption using a common key cryptosystem. The key access unit 224 is a device that restricts access to the restricted storage area 215a. The key access unit 224 allows data to be read from the restricted storage area 215a only when password verification by the verification unit 231, which will be described later, is successful.

[0028] In this embodiment, the control circuit 213 functions as a verification unit 231 and a response unit 232. The verification unit 231 verifies the password (second permission data) received from the authentication chip 110 via the connection I / F 212, by using the password hash value 217 read from the non-volatile memory 215. The response unit 232 responds to the control command received from the authentication chip 110 for challenge-response type authentication. The processes executed by the verification unit 231 and the response unit 232 will be described in detail later.

[0029] Each of the circuits (e.g., the random number generation circuit and the encryption processing circuit) shown separately from the control circuit in FIG. 2 and FIG. 3 may be implemented as a software module executed by the control circuit instead of being implemented as an independent circuit. Also, each of the modules (e.g., the authentication unit, the verification unit, and the response unit) described as the functions of the control circuit may be implemented as an independent circuit separate from the control circuit. Also, although one non-volatile memory is shown in each of FIG. 2 and FIG. 3, each of the memories shown in the figures may actually be a collection of multiple memory circuits. For example, the limited storage area 115a of the authentication chip 110 may be implemented using a storage device separate from the non-volatile memory 115, and the limited storage area 215a of the authenticated chip 210 may be implemented using a storage device separate from the non-volatile memory 215.

[0030] <2-3. Generating authentication data and storing it in memory> The manufacturers of the image forming apparatus 100 and the process cartridge 200 generate the above-mentioned data used for authenticating the process cartridge 200 at the manufacturing stage, and store it in the memory of the authentication chip 110 and the authenticated chip 210. In this section, the processing at the manufacturing stage will be described.

[0031] Fig. 4 is a flowchart showing an example of the flow of a data generation process for generating data to be stored in the non-volatile memory 115 of the authentication chip 110 and the non-volatile memory 215 of the authenticated chip 210. The data generation process of Fig. 4 may be executed, for example, in a factory, using a device (for example, a general-purpose computer) different from the image forming apparatus 100 and the process cartridge 200. In the following explanation, processing steps are abbreviated as 'S'.

[0032] Referring to FIG. 4, first, in S10, an authentication source key K AO Then, in S12, the password original key K PO The authentication source key K is generated. AO and password original key K POand may both be random numbers having a predetermined length. Then, in S14, an initial value of the countdown timer, i.e., a reference time, is determined. The reference time may be any value suitable for delaying the information analysis, such as a few seconds, a few minutes, or a few hours. Then, in S16, the authentication source key K AO and password original key K PO Next, in S18, the value C of the timer counter 119 of the authentication chip 110 is stored. T is set to the initial value determined in S14.

[0033] Next, in S20, an identifier (chip identifier) ​​C unique to the authenticated chip 210 is ID is generated. Chip identifier C ID may be a random value having a predetermined length. Then, in S22, the chip identifier C ID and the authentication key K AO Based on this, the authentication key K A For example, the authentication key K A ' is a chip identifier C as shown in the following formula (1). ID and the authentication key K AO and the input data (also called the payload) generated by concatenating K A ' = MSB L (h1(C ID ||K AO )) (1) Here, the operator || represents an operation of concatenating the values ​​before and after the operator. The function h1 is a one-way cryptographic hash function. As an example of a cryptographic hash function, SHA256 defined as FIPS PUB 180-4 by NIST (National Institute of Standards and Technology) can be used. The function MSB L is a function that cuts out the most significant L bits (discards the remaining bits), and may be, for example, L=128. When formula (1) is used, the chip identifier CID and the authentication key K AO Deterministically, we obtain the authentication key K A ', while the authentication key K A ' to the authentication source key K AO It is difficult to guess.

[0034] Alternatively, the authentication key K A ' is expressed as the authentication source key K AO as a common key to identify the chip ID may be generated by encrypting: K A ' = Enc X (K AO ,C ID ||c)) (2) Here, Enc X is a function that represents an encryption process in a common key cryptosystem X. For example, the common key cryptosystem X may be AES (Advanced Encryption Standard), which is a type of block cipher defined by NIST as FIPS PUB 197, and the block length may be, for example, 128 bits. X The first argument of is the common key, and the second argument is the object of encryption (also called plaintext). In the example of formula (2), the function Enc X To match the size of the second argument to the block length, the chip identifier C ID A predetermined bit string c is concatenated to the chip identifier C. ID and the authentication key K AO Deterministically, we obtain the authentication key K A ' can be derived, while the authentication key K A ' to the authentication source key K AO It is difficult to guess.

[0035] Next, in S24, the password hash value P H In this embodiment, the password hash value P H ' is generated by using the password key K PODerive the password PW from the password PW, and further derive the hash value P H The password PW can be obtained by deriving the authentication source key K AO The password key K PO may be derived according to the following formula (3) with PW = MSB L (h1(C ID ||K PO )) (3)

[0036] Alternatively, the password PW may be calculated by multiplying the authentication key K AO The password key K PO may be derived according to the following equation (4) with PW = Enc X (K PO ,C ID ||c)) (4)

[0037] Password hash value P H ' may also be derived, for example, using a one-way cryptographic hash function according to the following formula (5), or using a symmetric cryptosystem X according to the following formula (6): P H ' = MSB L (h1(PW)) (5) P H ' = Enc X (PW,c')) (6) In addition, the function Enc X The second argument c' of may be a predetermined fixed bit string having a length equal to the block length.

[0038] Next, in S26, the password hash value P H ', authentication key K A ' and chip identifier C ID The authentication key K is stored. A' is stored in restricted storage area 215a.

[0039] In addition, when a plurality of process cartridges are manufactured, S20 to S26 are repeated a plurality of times. ID differs for each individual manufactured. In addition, when a plurality of image forming apparatuses are manufactured, S10 to S26 may be repeated a plurality of times. Then, the data generation process of FIG. 4 ends.

[0040] <2-4. Cartridge authentication> FIG. 5 is a flowchart showing an example of the overall process flow in the authentication system according to the present embodiment.

[0041] 5 may be started by the control unit 107 transmitting a control command to the authentication chip 110 to instruct the start of authentication, triggered, for example, by the sensor 105 detecting the mounting of the process cartridge 200 in the image forming apparatus 100. Note that the trigger for starting authentication may not be the detection of the mounting of the process cartridge 200, but may be, for example, the detection of a user operation to request the start of authentication via a user interface of the image forming apparatus 100.

[0042] 5, first, in S101, the authentication unit 131 of the authentication chip 110 waits until a predetermined monitoring period has elapsed, using the timer circuit 123. After one monitoring period has elapsed, in S103, the authentication unit 131 counts up the timer counter value C T Then, in S105, the authentication unit 131 subtracts the length of the monitoring period from the timer counter value C T becomes zero or less, that is, the power-on time of the authentication chip 110 becomes (C T It is determined whether the power-on time of the authentication chip 110 has reached the reference time (represented by the initial value of ). If the power-on time of the authentication chip 110 has reached the reference time, the authentication process of S110 is executed. On the other hand, if the power-on time of the authentication chip 110 has not reached the reference time, the authentication process of S110 is skipped.

[0043] Fig. 6 is a sequence diagram showing an example of a detailed flow of the authentication process executed in S110 of Fig. 5. The authentication process mainly involves the authentication chip 110 of the image forming apparatus 100 and the authenticated chip 210 of the process cartridge 200. The connection I / F 103 of the engine controller 101 is interposed in the communication path between the authentication chip 110 and the authenticated chip 210, but the connection I / F 103 is omitted in Fig. 6.

[0044] First, in S111, the authentication unit 131 transmits an authentication start instruction to the authenticated chip 210. The authentication start instruction is transmitted to the chip identifier C ID Alternatively, the request may include a request to read the chip identifier C. ID In S113, the response unit 232 of the authenticated chip 210 reads the chip identifier C from the non-volatile memory 215 in response to the request from the authentication unit 131. ID The input / output circuit 112 of the authentication chip 110 reads out the chip identifier C transmitted from the authenticated chip 210 and transmits it to the authentication chip 110. ID Receive.

[0045] Next, in S115, the authentication unit 131 reads the password original key K from the limited storage area 115a of the non-volatile memory 115 via the key access unit 124. PO If the power-on time has reached the reference time, the key access unit 124 permits access to the restricted storage area 115a. Next, in S117, the authentication unit 131 reads out the password original key K PO and the received chip identifier C ID The password PW may be derived, for example, by the encryption processing circuit 121 according to the above-mentioned formula (3) or formula (4). Next, in S119, the authentication unit 131 transmits a random number value D CH Generate:

[0046] Next, in S121, the authentication unit 131 receives the password PW derived in S117 and the challenge data D generated in S119. CH The authentication request including the password PW is transmitted to the authenticated chip 210 via the input / output circuit 112. The password PW transmitted here is the password original key K PO The connection I / F 212 of the authenticated chip 210 receives the authentication request transmitted from the authentication chip 110.

[0047] The verification unit 231 of the authenticated chip 210 determines whether or not to permit a response to the authentication request received from the authentication chip 110 by verifying the validity of the password PW. Specifically, in S123, the verification unit 231 derives a verification hash value P H The verification hash value P H is the password hash value P H Similarly to the verification hash value P′, it can be derived according to the above-mentioned formula (5) or formula (6). Next, in S125, the verification unit 231 calculates the derived verification hash value P H The password hash value P H The validity of the password PW is verified by comparing it with the password hash value P H ' serves as the first authorization data used to verify the second authorization data. If the two hash values ​​match each other, the password verification is determined to be successful and access to the restricted storage area 215a is permitted via the key accessor 224. If the two hash values ​​do not match in S125, the password verification is determined to be unsuccessful and access to the restricted storage area 215a is not permitted.

[0048] If the password verification is successful, in S127, the responder 232 of the authenticated chip 210 retrieves the authentication key K from the restricted storage area 215a via the key accessor 224. A Next, in S129, the response unit 232 transmits the challenge data D received from the authentication chip 110 to the encryption processing circuit 221.CH and authentication key K A ' and based on the response data D RS For example, response data D RS is expressed as the following equation (7): A ' and Challenge Data D CH and D RS = MSB L (h1(K A '||D CH )) (7) As mentioned above, function h1 may be a one-way cryptographic hash function, and the function MSB L may be a function that cuts out the most significant L bits of the argument. Alternatively, the response data D RS is expressed as the following equation (8): A ' as a common key to generate challenge data D CH may be generated by encrypting: D RS = Enc X (K A ',D CH ) (8) As mentioned above, Enc X is a function representing an encryption process in a common key cryptosystem X. For example, AES (NIST FIPS PUB 197) with a block length of 128 bits may be used as the common key cryptosystem X. Alternatively, the response data D RS is expressed as the following equation (9): A ' as a common key to generate challenge data D CH may be generated by deriving a Message Authentication Code (MAC) for: D RS = MAC Y (K A ',D CH ) (9) Here, MAC Yis a function representing an encryption process for generating a message authentication code. For example, the hash-based MAC (HMAC) defined in the NIST FIPS PUB 198-1 standard or the cipher-based MAC (CMAC) defined in NIST SP 800-38B may be used as the message authentication code generation method Y.

[0049] Then, in S137, the response unit 232 generates response data D RS to the authentication chip 110. If the password verification in S125 fails, the response unit 232 returns the authentication key K A 6, the authentication chip 110 returns an error response without reading the authentication key K A The processing path in which the reading of ' is skipped is shown by a dashed line.

[0050] On the other hand, the authentication unit 131 of the authentication chip 110 that sent the authentication request in S121 retrieves the authentication source key K from the restricted storage area 115a via the key access unit 124 in S131. AO Next, in S133, the authentication unit 131 transmits the chip identifier C received from the authenticated chip 210 to the cryptographic processing circuit 121. ID and the read authentication source key K AO Based on the authentication key K A The authentication key K A is the authentication key K A Similarly, the authentication key K′ can be derived according to the above-mentioned formula (1) or formula (2). When formula (1) is used, the authentication key K A ' (first authentication key) and authentication key K A (Second authentication key) is a common authentication source key K AO and chip identifier C ID When formula (2) is used, the authentication key K is derived by inputting the input data based on A ' (first authentication key) and authentication key K A (Second authentication key) is a common authentication source key K AO as the encryption key to obtain the chip identifier C IDNext, in S135, the authentication unit 131 encrypts the challenge data D CH and the authentication key K generated in S133 A Based on this, the validation data D VF Generate the verification data D VF is the response data D RS Similarly, it can be generated according to equation (7), (8) or (9) above.

[0051] In S137, the input / output circuit 112 of the authentication chip 110 receives the authentication response transmitted from the authenticated chip 210. If the password verification is successful in the authenticated chip 210, the authentication response is response data D RS If the password verification fails in the authenticated chip 210, the authentication response is an error response. The authenticating unit 131 authenticates the authenticated chip 210 based on this authentication response.

[0052] Specifically, in S139, the authentication unit 131 receives response data D RS The verification data D generated in S135 VF By checking whether it matches the response data D RS Verify the validity of the response data D RS The verification data D VF If the response data D matches the authentication data D, the authentication unit 131 determines that the authentication of the process cartridge 200 has been successful. RS The verification data D VF If they do not match, or if the authentication response is an error response, the authentication unit 131 determines that the authentication of the process cartridge 200 has failed. The authentication unit 131 reports the result of the authentication determined in S139 to the control unit 107.

[0053] Returning to FIG. 5, the subsequent processing branches depending on whether authentication of the process cartridge 200 (authenticated chip 210) was successful or failed in S151. If authentication was successful, access to the memory of the process cartridge 200 is permitted. In this case, in S153, the control unit 107 executes access to the memory of the process cartridge 200. For example, the control unit 107 may read out control parameters indicating the above-mentioned operating conditions from the non-volatile memory 215 and control the operation of the image forming unit in accordance with the read out control parameters. Even if it is determined in S105 that the power-on time of the authentication chip 110 has not yet reached the reference time, access to the memory of the process cartridge 200 is permitted.

[0054] If authentication of the process cartridge 200 (authenticated chip 210) fails, access to the memory of the process cartridge 200 (for example, reading of control parameters indicating the above-mentioned operating conditions) is prohibited. In this case, in S155, the control unit 107 may warn the user that the process cartridge 200 is not genuine. The warning here may be given by any method, such as displaying a warning message on the display of the image forming apparatus 100, turning on a warning light, or outputting an alarm sound.

[0055] Throughout the description, the processing steps shown in the flowcharts and sequence diagrams may be performed in an order different from that shown in the drawings. For example, in the authentication process of FIG. 6, the authentication chip 110 verifies the verification data D VF may be generated at any timing, such as before transmitting an authentication request to the authenticated chip 210 or after receiving an authentication response from the authenticated chip 210.

[0056] <2-5. Summary of the first embodiment> In the above-mentioned first embodiment, the authenticated device (authenticated chip) stores in advance the first permission data (password hash value) used to determine whether or not to permit a response to an authentication request received from the authenticating device (authentication chip). The authenticated device does not access the authentication data (authentication key) used for the main authentication stored in the internal memory until it receives the legitimate second permission data (password) from the authenticating device. Meanwhile, the authenticating device stores in advance in the memory the restricted data (password original key) that is the basis for deriving the second permission data, but reading of the restricted data from the memory is possible after the time during which the authenticating device is energized reaches a preset reference time. Therefore, even if an attacker attempts to perform semiconductor operation analysis such as microprobing while operating the authenticated device, the permission data and authentication data cannot be detected until the reference time has passed. In this way, by delaying the timing at which significant information is exposed against an information analysis type attack, the probability of the attack succeeding within a realistic time constraint can be reduced and resistance to the attack can be increased. In addition, since such a delay does not depend on the variation of the secret information, it is possible to avoid an increase in cost due to an increase in the scale of the non-volatile memory.

[0057] In the first embodiment described above, the authenticated device stores an identifier (chip identifier) ​​unique to the device in advance. The authentication unit of the authentication device derives the second permission data based on the restriction data read from the memory after a reference time has elapsed and the identifier received from the authenticated device. Therefore, the second permission data transmitted from the authentication device to the authenticated device differs for each authenticated device, so that it is possible to prevent fraud such as reusing the second permission data obtained using a certain authenticated device for another authenticated device. In addition, since the second permission data is derived using a one-way cryptographic hash function, it is impossible to guess the restriction data based on a change in the second permission data.

[0058] In the above-mentioned first embodiment, the authenticated device stores a first authentication key used to generate response data from challenge data received from the authenticating device together with an authentication request, the first authentication key being derived in advance based on the identifier of the authenticated device. The authenticating unit of the authenticating device derives a second authentication key based on the identifier of the authenticated device, and authenticates the authenticated device by verifying response data from the authenticated device using the derived second authentication key. In this way, by using different first and second authentication keys, which form a common key pair, for each authenticated device in the challenge-response authentication, even if one of the authentication keys is leaked, it becomes meaningless to reuse the authentication key in another device.

[0059] In the first embodiment described above, before the power-on time of the authentication device reaches the reference time, the authenticated device is not authenticated and access to the memory of the authenticated device (for example, reading of control parameters) is permitted. Therefore, even if the timing of authentication is delayed, the user can use the genuine replaceable part equipped with the authenticated device normally from the time the part was first obtained.

[0060] In this specification, the expressions "based on" a first element and "based on" a second element are used, but these expressions do not exclude an embodiment in which the first element is equal to the second element. For example, the expression "transmitting second authorization data based on the restriction data" is intended to include an embodiment in which the restriction data is transmitted as the second authorization data.

[0061] <3. Second Example> <3-1. Example of authentication chip configuration> The first embodiment described in the previous section can be implemented using challenge-response authentication based on a symmetric key cryptography method, whereas the second embodiment described in this section can be implemented using challenge-response authentication based on a public key cryptography method.

[0062] Fig. 7 is a block diagram showing an example of the configuration of an authentication chip 110 according to the second embodiment. Referring to Fig. 7, the authentication chip 110 includes an internal bus 111, an input / output circuit 112, a control circuit 313, a volatile memory 114, a non-volatile memory 315, a cryptographic processing circuit 321, a random number generation circuit 122, a timer circuit 123, and a key access unit 124.

[0063] The control circuit 313 controls communication with the authenticated device. The control circuit 313 may be, for example, a CPU, a microcontroller, or a microprocessor, and performs various processes according to commands input from the control unit 107. The non-volatile memory 315 is a storage unit that may include, for example, a semiconductor memory or a hard disk.

[0064] In this embodiment, the non-volatile memory 315 stores one or more computer programs 316, a password key (K PO ) 117, Certificate Verification Key (K CV ) 318, and a timer counter (C T The certificate verification key 318 is stored as a chip verification key K 119, which will be described later, received from the authenticated chip 210. V 7, the password original key 117 and the certificate verification key 318 are stored in a limited storage area 315a of the non-volatile memory 315. Access to the limited storage area 315a (e.g., reading of data) is permitted only via the key accessor 124. Before the power-on time of the authentication chip 110 reaches a reference time, the key accessor 124 blocks access to the limited storage area 315a. When the power-on time of the authentication chip 110 reaches the reference time, the key accessor 124 permits reading of data from the limited storage area 315a by the authentication unit 331, which will be described later.

[0065] The cryptographic processing circuit 321 is a calculation unit that executes cryptographic-related processes that may include hash function calculations, encryption using a common key cryptosystem, digital signature verification, and certificate verification. Although not shown in FIG. 7, the authentication chip 110 may further include a power supply circuit. The power supply circuit supplies power from an external power source to each unit of the authentication chip 110. The non-volatile memory 315 can maintain the above-mentioned programs and data even while the authentication chip 110 is not powered.

[0066] In this embodiment, the control circuit 313 cooperates with the encryption processing circuit 321, the random number generation circuit 122, and the timer circuit 123 to function as an authentication unit 331 that performs authentication processing for authenticating the authenticated chip 210. The flow of the authentication processing will be described in detail later.

[0067] <3-2. Example of the configuration of the authenticated chip> Fig. 8 is a block diagram showing an example of the configuration of the authenticated chip 210 according to the second embodiment. Referring to Fig. 8, the authenticated chip 210 includes an internal bus 211, a connection I / F 212, a control circuit 413, a volatile memory 214, a non-volatile memory 415, a cryptographic processing circuit 421, and a key access unit 224.

[0068] The control circuit 413 controls communication with the authentication device via the connection I / F 212. The control circuit 413 may be, for example, a CPU, a microcontroller, or a microprocessor. The non-volatile memory 415 is, for example, a storage unit including a semiconductor memory.

[0069] In this embodiment, the non-volatile memory 415 stores one or more computer programs 416, a password hash value (P H ')217, Chip Identifier (C ID )219, signing key (K S ) 417, chip verification key (K V ) 418, and chip certificate (C V8, the chip 415 stores the signature key 417 and the chip certificate 419. The signature key 417 is a private key of a public key cryptosystem used to generate a digital signature of challenge data received from the authentication chip 110 together with an authentication request. The chip verification key 418 is a public key corresponding to the signature key 417. The chip certificate 419 is an electronic certificate that certifies the authenticity of the chip verification key 418. As indicated by a dashed line in FIG. 8, the signature key 417 is stored in a limited storage area 415a of the non-volatile memory 415. Access to the limited storage area 415a (e.g., reading of data) is permitted only via the key accessor 224. The key accessor 224 permits reading of data from the limited storage area 415a only when password verification by a verification unit 231, which will be described later, is successful.

[0070] The cryptographic processing circuit 421 is a computing unit that performs cryptographic related processes that may include hash function calculations, encryption using a common key cryptosystem, and generation of digital signatures.

[0071] In this embodiment, the control circuit 413 functions as a verification unit 231 and a response unit 432. The response unit 432 responds to a control command received from the authentication chip 110 for challenge-response type authentication. The process executed by the response unit 432 will be described in detail later.

[0072] Each of the circuits shown in Figures 7 and 8 separately from the control circuit may be implemented as a software module executed by the control circuit instead of being implemented as an independent circuit. Also, each of the modules described as the functions of the control circuit may be implemented as an independent circuit separate from the control circuit. Also, although Figures 7 and 8 each show one non-volatile memory, each of the memories shown may actually be a collection of multiple memory circuits.

[0073] <3-3. Generating authentication data and storing it in memory> 9 is a flowchart showing an example of the flow of a data generation process for generating data to be stored in the non-volatile memory 315 of the authentication chip 110 and the non-volatile memory 415 of the authenticated chip 210. The data generation process of FIG. 9 may be executed by using a device different from the image forming apparatus 100 and the process cartridge 200, for example, in a factory.

[0074] Referring to FIG. 9, first, in S30, a chip verification key K V and the corresponding signing key K S Then, in S31, a certificate verification key K CV and the corresponding certificate signing key K CS Then, in S32, the password source key K PO Next, in S34, the initial value of the countdown timer, i.e., the reference time, is determined. Next, in S36, the password original key K PO and the certificate verification key K CV Next, in S38, the value C of the timer counter 119 of the authentication chip 110 is stored. T is set to the initial value determined in S34.

[0075] Next, in S40, an identifier (chip identifier) ​​C unique to the authenticated chip 210 is ID Then, in S42, the certificate signing key K CS Using the chip identifier C ID and the chip verification key K V A chip certificate C that proves the authenticity of the input data concatenated with V is generated. Chip Certificate C V The digital signature value σ CV may be generated, for example, according to the following equation (10): σ CV =Sign(K CS ,C ID ||K V ) (10) The function Sign in formula (10) represents a digital signature algorithm. The digital signature algorithm used here may be, for example, an algorithm defined by NIST as FIPS PUB 186-4. The first argument of the function Sign is the certificate signing key K CS and the second argument is the chip identifier C ID and the chip verification key K V It is a concatenation of.

[0076] Next, in S44, similar to S24 in the first embodiment, the password original key K PO Based on the password hash value P H Next, in S46, the password hash value P H ', chip identifier C ID , chip verification key K V , Chip Certificate C V , and the signing key K S The signing key K S is stored in restricted storage area 415a.

[0077] In addition, when a plurality of process cartridges are manufactured, S40 to S46 are repeated a plurality of times. ID differs for each individual manufactured. In addition, when a plurality of image forming apparatuses are manufactured, S30 to S46 may be repeated a plurality of times. Then, the data generation process of FIG. 9 ends.

[0078] <3-4. Cartridge authentication> The overall process flow in the authentication system according to this embodiment may be similar to the process flow in the first embodiment described with reference to Fig. 5. Fig. 10 is a sequence diagram showing an example of a detailed flow of the authentication process executed in S110 of Fig. 5. The authentication process mainly involves the authentication chip 110 of the image forming apparatus 100 and the authenticated chip 210 of the process cartridge 200. The connection I / F 103 of the engine controller 101 is interposed in the communication path between the authentication chip 110 and the authenticated chip 210, but the connection I / F 103 is omitted in Fig. 10.

[0079] First, in S311, the authentication unit 331 of the authentication chip 110 transmits an authentication start instruction to the authenticated chip 210. The authentication start instruction is transmitted to the chip identifier C ID Alternatively, the request may include a request to read the chip identifier C. ID In S313, the response unit 432 of the authenticated chip 210 reads the chip identifier C from the non-volatile memory 415 in response to the request from the authentication unit 331. ID , chip verification key K V and Chip Certificate C V and transmits the read data to the authentication chip 110. The input / output circuit 112 of the authentication chip 110 receives the data transmitted from the authenticated chip 210.

[0080] Next, in S314, the authentication unit 331 reads the certificate verification key K from the restricted storage area 315a of the non-volatile memory 315 via the key access unit 124. CV Next, in S315, the authentication unit 331 reads out the chip certificate C received from the authenticated chip 210. V Based on this, the chip verification key K V (and chip identifier C ID For example, the authenticity verification here can be expressed as the following equation (11): res = Verify(K CV ,C ID ||K V ,C V ) (11) The function Verify in formula (11) represents a digital signature verification algorithm corresponding to the digital signature algorithm used in formula (10). The first argument of the function Verify is the certificate signing key K CS The certificate verification key K CV , the second argument is the chip identifier C ID and the chip verification key K V The third argument is the chip certificate C V The output res of the function Verify indicates the signature verification result, i.e., whether the verification was successful or unsuccessful, as a logical value ("true" or "false"). V If the authenticity of is confirmed, the chip verification key K V The chip verification key K is used to verify the digital signature included in the authentication response during the subsequent authentication. V and chip identifier C ID If the authenticity of the password is not confirmed, the subsequent password authentication and main authentication are skipped, as indicated by the dashed line in the figure.

[0081] Here, the chip verification key K V and chip identifier C ID In S316, the authentication unit 331 reads the password original key K from the limited storage area 315a of the non-volatile memory 315 via the key access unit 124. PO If the power-on time has reached the reference time, the key access unit 124 permits access to the restricted storage area 315a. Next, in S317, the authentication unit 331 reads out the password original key K PO and chip identifier C ID The password PW may be derived, for example, by the encryption processing circuit 321 according to the above-mentioned formula (3) or formula (4). Next, in S319, the authentication unit 331 transmits a random number value D CH Generate:

[0082] Next, in S321, the authentication unit 331 receives the password PW derived in S317 and the challenge data D generated in S319. CH The authentication chip 110 transmits an authentication request including the above to the authenticated chip 210 via the input / output circuit 112. The connection I / F 212 of the authenticated chip 210 receives the authentication request transmitted from the authentication chip 110.

[0083] In S323 and S325, the verification unit 231 of the authenticated chip 210 verifies the validity of the password PW to determine whether or not to permit a response to the authentication request received from the authenticating chip 110. Since S323 and S325 may be the same processing steps as S123 and S125 in Fig. 6, a description thereof will be omitted here.

[0084] If the password verification is successful, in S327, the responder 432 of the authenticated chip 210 retrieves the signature key K from the restricted storage area 415a via the key accessor 224. S Next, in S329, the response unit 432 transmits the challenge data D received from the authentication chip 110 to the encryption processing circuit 421. CH and the signing key K S For example, the response data σ may be a digital signature value generated according to the following equation (12): σ = Sign(K S ,D CH ) (12) The function Sign in formula (12) represents the same digital signature algorithm as formula (10). However, a digital signature algorithm different from formula (10) may be used here. The first argument of the function Sign is the signature key K S and the second argument is the challenge data D CH It is.

[0085] Then, in S337, the response unit 432 returns the response data σ to the authentication chip 110 as a response to the authentication request. Note that if the password verification in S325 fails, the response unit 432 returns the signature key KS 10, the signature key K S A processing path in which the reading of is skipped is shown by a dashed line.

[0086] The input / output circuit 112 of the authentication chip 110 receives the authentication response transmitted from the authenticated chip 210. If the password verification is successful in the authenticated chip 210, the authentication response includes response data (digital signature value) σ. If the password verification is unsuccessful in the authenticated chip 210, the authentication response is an error response. The authentication unit 331 authenticates the authenticated chip 210 based on this authentication response.

[0087] Specifically, in S339, the authentication unit 331 converts the signature value σ included in the authentication response into the chip verification key K V and Challenge Data D CH The authenticated chip 210 is authenticated by verifying the signature value σ using the following formula (13): res = Verify(K V ,D CH ,σ) (13) The function Verify in formula (13) represents a digital signature verification algorithm corresponding to the digital signature algorithm used in formula (12). The first argument of the function Verify is the signature key K S The public key corresponding to the chip verification key K V , the second argument is the challenge data D CH The first argument is the signature value σ to be verified, and the third argument is the signature value σ to be verified. The output res of the function Verify indicates the signature verification result, i.e., whether the verification was successful or unsuccessful, as a logical value ("true" or "false"). If the digital signature value σ received together with the authentication response is valid, the signature verification result res indicates "true" according to the mechanism of public key cryptography. If the digital signature value σ is invalid, the signature verification result res indicates "false".

[0088] If the signature verification result res indicates "true", the authentication unit 331 determines that the authentication of the process cartridge 200 has been successful. If the signature verification result res indicates "false" or if the authentication response is an error response, the authentication unit 331 determines that the authentication of the process cartridge 200 has failed. The authentication unit 331 reports the result of the authentication determined in S339 to the control unit 107.

[0089] Note that the message input (second argument) in the signature function Sign in formula (12) and the signature verification function Verify in formula (13) is not necessarily the challenge data D CH The message input may also include other data known to both the authenticator and the prover (e.g., a chip identifier C ID ) and Challenge Data D CH Alternatively, the chip identifier C ID may be input as challenge data to the signature function Sign and the signature verification function Verify. In this case, although the response data transmitted from the same authenticated chip 210 always has the same value, the effect of improving security by delaying the timing at which the permission data and authentication data are exposed can still be achieved.

[0090] <3-5. Summary of the second embodiment> In the second embodiment described above, the authenticated device (authenticated chip) also stores in advance the first permission data (password hash value) used to determine whether or not to permit a response to an authentication request received from the authenticating device (authentication chip). The authenticated device does not access the authentication data (signature key) used for the main authentication stored in the internal memory until it receives the legitimate second permission data (password) from the authenticating device. Meanwhile, the authenticating device stores in advance in the memory the restricted data (password original key) that is the basis for deriving the second permission data, but reading of the restricted data from the memory is possible after the time during which the authenticating device is energized reaches a preset reference time. Therefore, even if an attacker attempts to perform semiconductor operation analysis such as microprobing while operating the authenticated device, the permission data and authentication data cannot be detected until the reference time has elapsed. In this way, by delaying the timing at which significant information is exposed against an information analysis type attack, the probability of the attack succeeding within a realistic time constraint can be reduced and resistance to the attack can be increased. In addition, since such a delay does not depend on the variation of the secret information, it is possible to avoid an increase in cost due to an increase in the scale of the non-volatile memory.

[0091] In the second embodiment described above, the device to be authenticated prestores a private key (signature key) of the public key cryptosystem used to generate a digital signature of the challenge data received from the authentication device. The authentication unit of the authentication device authenticates the device to be authenticated by verifying the digital signature received from the device to be authenticated as response data in response to an authentication request, using a public key (chip verification key) corresponding to the private key and the challenge data. Therefore, the device to be authenticated can be authenticated through verification of the digital signature using a secure public key cryptosystem algorithm. Even if the public key is leaked, the device to be authenticated prepared by an attacker cannot masquerade as a legitimate device to be authenticated as long as the private key is not leaked.

[0092] In addition, in the above-mentioned second embodiment, the authentication unit of the authentication device verifies the above-mentioned digital signature included in the authentication response only when the authenticity of the above-mentioned public key is confirmed based on the electronic certificate (chip certificate) received from the device to be authenticated. Therefore, even if the device to be authenticated prepared by an attacker provides the authentication device with its own public key for fraudulent authentication, the authentication device can be prevented from misusing the public key.

[0093] In this specification, the term "public key" simply means a key that forms a pair with a private key in a public key cryptosystem, and does not mean that the key is made public in a form accessible to any third party. In other words, the public key may actually be kept secret, and access to the public key may be restricted in various ways.

[0094] <4. Third Example> <4-1. Example of authentication chip configuration> In the above-mentioned first embodiment, only one type of original key that is a basis for deriving a common key or a password can be prepared for one pair of an authenticator and an authenticated device, whereas in the third embodiment described in this section, multiple types of original keys are prepared in advance, and the original key used for authentication can be switched over time.

[0095] Fig. 11 is a block diagram showing an example of the configuration of an authentication chip 110 according to the third embodiment. Referring to Fig. 11, the authentication chip 110 includes an internal bus 111, an input / output circuit 112, a control circuit 513, a volatile memory 114, a non-volatile memory 515, a cryptographic processing circuit 121, a random number generation circuit 122, a timer circuit 123, and a key access unit 524.

[0096] The control circuit 513 controls communication with the authenticated device. The control circuit 513 may be, for example, a CPU, a microcontroller, or a microprocessor, and performs various processes according to commands input from the control unit 107. The non-volatile memory 515 is a storage unit that may include, for example, a semiconductor memory or a hard disk.

[0097] In this embodiment, the non-volatile memory 515 stores one or more computer programs 516, a password original key table 517, an authentication original key table 518, and a timer counter table 519. The password original key table 517 stores N (N is an integer equal to or greater than 2) different password original keys K as an example of the above-mentioned limiting data. PO_k (k=1,...,N) PO_k is N password hash values ​​P H_k The authentication source key table 518 has N different authentication source keys K′, each of which is used to derive an authentication key for challenge-response authentication. AO_k (k=1,...,N) for each authentication key K AO_k are N authentication keys K A_k 11, password original key table 517 and authentication original key table 518 are stored in restricted storage area 515a of non-volatile memory 515. Access to restricted storage area 515a (e.g., reading of data) is only possible via key accessor 524.

[0098] The timer counter table 519 holds N counter values ​​for monitoring the passage of time while the authentication chip 110 is energized. That is, in this embodiment, N different reference times are preset as initial values ​​of N timer counters. These counter values ​​are counted down simultaneously while the authentication chip 110 is energized, and reach zero at different times.

[0099] Although not shown in FIG. 11 , the authentication chip 110 may further include a power supply circuit. The power supply circuit supplies power from an external power source to each part of the authentication chip 110. The non-volatile memory 515 is capable of maintaining the above-mentioned programs and data even while the authentication chip 110 is not powered. The key accessor 524 is a device that restricts access to the restricted storage area 515a. When the power-on time of the authentication chip 110 reaches the reference time of the i-th timer counter (i is an integer greater than or equal to 1 and less than or equal to N), the key accessor 524 reads the i-th password original key K from the restricted storage area 515a. PO_i and the authentication key K AO_i This enables reading of the

[0100] In this embodiment, the control circuit 513 cooperates with the encryption processing circuit 121, the random number generation circuit 122, and the timer circuit 123 to function as an authentication unit 531 that performs authentication processing for authenticating the authenticated chip 210. The flow of the authentication processing will be described in detail later.

[0101] <4-2. Example of the configuration of the authenticated chip> Fig. 12 is a block diagram showing an example of a configuration of an authenticated chip 210 according to Example 3. Referring to Fig. 12, the authenticated chip 210 includes an internal bus 211, a connection I / F 212, a control circuit 613, a volatile memory 214, a non-volatile memory 615, a cryptographic processing circuit 221, and a key access unit 224.

[0102] The control circuit 613 may be, for example, a CPU, a microcontroller, or a microprocessor. The non-volatile memory 615 is, for example, a storage unit including a semiconductor memory.

[0103] In this embodiment, the non-volatile memory 615 stores one or more computer programs 616, a password hash table 617, an authentication key table 618, and a chip identifier (C ID ) 219. The password hash table 617 stores N different password hash values ​​P H_k'(k=1,...,N) for each password hash value P H_k The authentication key table 618 stores N different authentication keys K A_k '(k=1,...,N) for each authentication key K A_k The authentication key table 618 is stored in a restricted storage area 615a of the non-volatile memory 615 as indicated by a dashed line in FIG. 12. Access to the restricted storage area 615a (e.g., reading of data) is permitted only via the key accessor 224. The key accessor 224 receives the i-th password PW by a verification unit 631 (to be described later). _k If the verification of the i-th authentication key K A_k ' to enable reading.

[0104] In this embodiment, the control circuit 613 functions as a verification unit 631 and a response unit 632. The verification unit 631 verifies the i-th password PW received from the authentication chip 110 via the connection I / F 212. _i is the i-th password hash value P H_i The response unit 632 responds to the control command received from the authentication chip 110 for challenge-response type authentication. The processing executed by the verification unit 631 and the response unit 632 will be described in detail later.

[0105] Each of the circuits shown in Figures 11 and 12 separately from the control circuit may be implemented as a software module executed by the control circuit instead of being implemented as an independent circuit. Also, each of the modules described as the functions of the control circuit may be implemented as an independent circuit separate from the control circuit. Also, although Figures 11 and 12 each show one non-volatile memory, each of the memories shown may actually be a collection of multiple memory circuits.

[0106] <4-3. Generating authentication data and storing it in memory> 13 is a flowchart showing an example of the flow of a data generation process for generating data to be stored in the non-volatile memory 515 of the authentication chip 110 and the non-volatile memory 615 of the authenticated chip 210. The data generation process of FIG. 13 may be executed by using a device different from the image forming apparatus 100 and the process cartridge 200, for example, in a factory.

[0107] Referring to FIG. 13, first, in S50, N authentication source keys K AO_1 ,...,K AO_N Next, in S52, N password original keys K PO_1 ,...,K PO_N Next, in S54, N different initial values ​​of the countdown timer, i.e., N reference times, are determined. Next, in S56, the authentication source key table 518 of the authentication chip 110 stores the N authentication source keys K AO_1 ,...,K AO_N Next, in S57, the password original key table 517 of the authentication chip 110 stores N password original keys K PO_1 ,...,K PO_N Next, in S58, the N counter values ​​C T_1 ,...,C T_N are initialized to the initial values ​​determined in S54. Each entry in the table described in this embodiment may be configured by a pair of an index that identifies the entry and a value.

[0108] Next, in S60, an identifier (chip identifier) ​​C unique to the authenticated chip 210 is ID Then, in S62, the chip identifier C ID and N authentication keys K AO_1 ,...,K AO_N Based on this, N authentication keys K A_1 ',...,K A_N ' is derived. Each authentication key K A_k ' is the chip identifier C according to the above formula (1) or formula (2). ID and the corresponding authentication key K AO_k It can be generated based on:

[0109] Next, in S64, N password hash values ​​P H_1 ',...,P H_N ' is generated for each password hash value P H_k is the corresponding password key K PO_k From Password PW _k Derive the derived password PW _k Then, the hash value P H_k For example, the password PW _k The derivation of is performed according to the above formula (3) or formula (4), and the hash value P H_k The derivation of ' can be performed according to equation (5) or equation (6) above.

[0110] Next, in S65, the authentication key table 618 of the authenticated chip 210 stores N authentication keys K A_1 ',...,K A_N Next, in S66, the N password hash values ​​P H_1 ',...,P H_N Then, in S67, the chip identifier C' is stored in the non-volatile memory 615 of the authenticated chip 210. ID is stored.

[0111] In addition, when a plurality of process cartridges are manufactured, S60 to S67 are repeated a plurality of times. ID differs for each individual manufactured. In addition, when a plurality of image forming apparatuses are manufactured, S50 to S67 may be repeated a plurality of times. Then, the data generation process of FIG. 13 ends.

[0112] <4-4. Cartridge authentication> FIG. 14 is a flowchart showing an example of the overall process flow in the authentication system according to the present embodiment.

[0113] 14 may be started by, for example, the control unit 107 transmitting a control command to the authentication chip 110 to instruct the start of authentication, triggered by the sensor 105 detecting the mounting of the process cartridge 200 in the image forming apparatus 100. Note that the trigger for starting authentication may not be the detection of the mounting of the process cartridge 200, but may be, for example, the detection of a user operation to request the start of authentication via a user interface of the image forming apparatus 100.

[0114] 14, first, in S501, the authentication unit 131 of the authentication chip 110 waits until a predetermined monitoring period has elapsed, using the timer circuit 123. When one monitoring period has elapsed, in S503, the authentication unit 131 counts N counter values ​​C T_1 ,...,C T_N The authentication unit 131 subtracts the length of the monitoring cycle from the counter value (i.e., counts down). Next, in S505, the authentication unit 131 determines whether any of the counter values ​​has reached zero, that is, whether the power-on time of the authentication chip 110 has reached any of the reference times. If the power-on time of the authentication chip 110 has reached any of the reference times, the authentication process of S510 is executed. On the other hand, if the power-on time of the authentication chip 110 has not reached any of the reference times, the authentication process of S510 is skipped.

[0115] 15 is a sequence diagram showing an example of a detailed flow of the authentication process executed in S510 of FIG. 14. Here, the i-th counter value C T_i Since the count reaches zero, the authentication process of S510 is executed.

[0116] First, in S511, the authentication unit 531 transmits an authentication start instruction to the authenticated chip 210. In S513, in response to a request from the authentication unit 531, the response unit 632 of the authenticated chip 210 retrieves the chip identifier C from the non-volatile memory 615. ID The input / output circuit 112 of the authentication chip 110 reads out the chip identifier C transmitted from the authenticated chip 210 and transmits it to the authentication chip 110. ID Receive.

[0117] Next, in S515, the authentication unit 531 obtains the i-th password original key K from the password original key table 517 via the key access unit 524. PO_i Next, in S517, the authentication unit 531 reads out the password original key K PO_i and the received chip identifier C ID Based on the password PW _i Derive the password PW _i can be derived, for example, according to the above-mentioned formula (3) or formula (4) by using the cryptographic processing circuit 121. Next, in S519, the authentication unit 531 transmits a random value D CH Generate:

[0118] Next, in S521, the authentication unit 531 receives the password PW derived in S517. _i , Challenge data D generated in S519 CH , and the index i to the authenticated chip 210 via the input / output circuit 112. The connection I / F 212 of the authenticated chip 210 receives the authentication request transmitted from the authentication chip 110.

[0119] The verification unit 631 of the authenticated chip 210 determines whether or not to permit a response to an authentication request received from the authenticating chip 110 based on the password PW _i Specifically, in S523, the verification unit 631 verifies the validity of the password PW received together with the authentication request. _i Based on this, the verification hash value P H_i The verification hash value P H_i is the password hash value P H_i Similarly to the verification hash value P′, it can be derived according to the above-mentioned formula (5) or formula (6). Next, in S525, the verification unit 631 calculates the derived verification hash value P H_i The i-th password hash value P H_i ' to check the password PW _i If the two hash values ​​match each other, the password verification is determined to be successful, and the i-th authentication key K A_i ' can be read.

[0120] In S527, the responder 632 of the authenticated chip 210 receives the i-th authentication key K A_i Next, in S529, the response unit 632 transmits the challenge data D received from the authentication chip 110 to the encryption processing circuit 221. CH and authentication key K A_i ' and based on the response data D RS_i For example, response data D RS_i can be generated according to equation (7), (8) or (9) above.

[0121] Then, in S537, the response unit 632 generates response data D RS_i to the authentication chip 110. If the password verification in S525 fails, the response unit 632 returns the authentication key K A_i 15, the authentication chip 110 returns an error response without reading the authentication key K A_iThe processing path in which the reading of ' is skipped is shown by a dashed line.

[0122] On the other hand, the authentication unit 531 of the authentication chip 110 that sent the authentication request in S521 retrieves the i-th authentication source key K from the authentication source key table 518 via the key access unit 524 in S531. AO_i Next, in S533, the authentication unit 531 transmits the chip identifier C received from the authenticated chip 210 to the cryptographic processing circuit 121. ID and the read authentication source key K AO_i Based on the authentication key K A_i The authentication key K A_i is the authentication key K A_i Similarly to the above, the challenge data D′ can be derived according to the above-mentioned formula (1) or formula (2). Next, in S535, the authentication unit 531 transmits the challenge data D CH and the authentication key K generated in S533 A_i Based on this, the validation data D VF_i Generate the verification data D VF_i is the response data D RS_i Similarly, it can be generated according to equation (7), (8) or (9) above.

[0123] In S537, the input / output circuit 112 of the authentication chip 110 receives the authentication response transmitted from the authenticated chip 210. If the password verification is successful in the authenticated chip 210, the authentication response is response data D RS_i If the password verification fails in the authenticated chip 210, the authentication response is an error response. The authentication unit 531 uses the response data D RS_i The authenticated chip 210 is authenticated by verifying the above.

[0124] Specifically, in S539, the authentication unit 531 receives response data D RS_i Challenge Data D CH and authentication key K A_i The validation data D generated using VF_i By comparing with the response data D RS_iVerify the validity of the response data D RS_i The verification data D VF_i If the response data D matches the authentication data D, the authentication unit 531 determines that the authentication of the process cartridge 200 is successful. RS_i The verification data D VF_i If they do not match, or if the authentication response is an error response, the authentication unit 531 determines that the authentication of the process cartridge 200 has failed. The authentication unit 531 reports the result of the authentication determined in S539 to the control unit 107.

[0125] Returning to FIG. 14, the subsequent processing branches depending on whether authentication of the process cartridge 200 was successful or failed in S551. If authentication was successful, in S553 the control unit 107 executes access to the memory of the process cartridge 200. For example, the control unit 107 may read out control parameters (not shown in FIG. 12) related to the operating conditions stored in the memory of the process cartridge 200 and use them for subsequent control. Even if it is determined in S505 that the power-on time of the authentication chip 110 has not yet reached any of the reference times, access to the memory of the process cartridge 200 may be executed.

[0126] If the authentication fails, in S555, the control unit 107 may warn the user that the process cartridge 200 is not genuine. The warning here may be given by any method, such as displaying a warning message on the display of the image forming apparatus 100, turning on a warning light, or outputting an alarm sound.

[0127] <4-5. Modifications> When the power-on time of the authentication chip 110 reaches the i-th reference time, the i-th (last accessible) password original key K PO_i The i-th password PW is derived based on _iIn the above example, a single password verification is performed for each of the first to i-th password source keys K. However, the present embodiment is not limited to such an example. In a modified example, when the power-on time of the authentication device reaches the i-th reference time, the first to i-th password source keys K PO_1 ,...,K PO_i The i passwords derived based on the i passwords may be transmitted to the authenticated chip 210 for password verification. Note that the indexes are assigned in ascending order of the reference time. The verification unit 631 of the authenticated chip 210 verifies the i passwords PW _1 ,...,PW _i The validity of the corresponding password hash values ​​P H_1 ',...,P H_i Then, only when the verification of all the i passwords is successful, the verification unit 631 selects the i-th authentication key K A_i ' and uses it to respond to an authentication request from the authentication chip 110. With this configuration, the number of passwords verified in the password verification increases over time, making it possible to further strengthen resistance to information analysis attacks.

[0128] <4-6. Summary of the third embodiment> In the above-mentioned third embodiment, the authenticated device (authenticated chip) stores in advance in a memory N hash values ​​(password hash values) of the first permission data used to determine whether to permit a response to an authentication request received from the authenticating device (authentication chip). The authenticating device (authentication chip) stores in advance in a memory restriction data including N original values ​​(password original keys) corresponding to the N hash values ​​of the first permission data. In addition, N different reference times are set in advance in the authenticating device. Then, when the power-on time of the authenticating device reaches the i-th reference time, the i-th original value of the restriction data is read from the memory, and the i-th value of the second permission data (password) derived based on the i-th original value is transmitted to the authenticated device. After the i-th value of the second permission data is successfully verified using the corresponding i-th hash value of the first permission data, the authenticated device reads out the i-th first authentication key from the memory among the N first authentication keys stored in advance for this authentication. Therefore, in this embodiment as well, the timing at which significant information is exposed against an information analysis type attack is delayed, thereby reducing the probability of the attack succeeding within a realistic time constraint.

[0129] In the above-described third embodiment, password verification is repeated as time passes, and the password value changes with each repetition. Also, the authentication key used for challenge-response authentication changes with each repetition. This makes it more difficult to analyze information that may include passwords and authentication keys, and further enhances resistance to information analysis attacks. Also, an attacker will need a longer analysis time to learn all passwords or all authentication keys.

[0130] <5. Fourth Example> <5-1. Example of authentication chip configuration> In the above-mentioned first to third embodiments, when the same authenticated device is connected to the authentication device multiple times, the authenticated device is authenticated by the authentication device each time the device is connected. In contrast, in the fourth embodiment described in this section, a mechanism is adopted that omits re-authentication of an authenticated device that has already been authenticated in the past.

[0131] Fig. 16 is a block diagram showing an example of the configuration of an authentication chip 110 according to the fourth embodiment. Referring to Fig. 16, the authentication chip 110 includes an internal bus 111, an input / output circuit 112, a control circuit 713, a volatile memory 114, a non-volatile memory 715, a cryptographic processing circuit 121, a random number generation circuit 122, a timer circuit 123, and a key access unit 524.

[0132] The control circuit 713 controls communication with the authenticated device. The control circuit 713 may be, for example, a CPU, a microcontroller, or a microprocessor, and performs various processes according to commands input from the control unit 107. The non-volatile memory 715 is a storage unit that may include, for example, a semiconductor memory or a hard disk.

[0133] In this embodiment, the non-volatile memory 715 stores one or more computer programs 716 , a password source key table 517 , an authentication source key table 518 , a timer counter table 519 , and a history table 740 .

[0134] The history table 740 includes the chip identifiers C of the authenticated chips 210 that have been successfully authenticated based on the authentication responses. ID The history table 740 may store a list of chip identifiers of one or more authenticated chips that have been successfully authenticated in the past, or may store chip identifiers of one or more authenticated chips that have attempted authentication in the past in association with the respective authentication results (success or failure).

[0135] In this embodiment, the control circuit 713 cooperates with the encryption processing circuit 121, the random number generating circuit 122, and the timer circuit 123 to function as an authentication unit 731 that performs authentication processing for authenticating the authenticated chip 210. The authentication unit 731 receives a chip identifier C from the authenticated chip 210 connected to the authentication chip 110. ID When received, the chip identifier C ID The authentication unit 731 judges whether the chip identifier C exists in the history table 740 (whether it has been registered as history). IDexists in the history table 740, the connected authenticated chip 210 is determined to have been authenticated without transmitting an authentication request to the connected authenticated chip 210. If the authenticated chip 210 has been successfully authenticated in the past, further data (e.g., control parameters indicating optimal operating conditions) can be read from the memory of the authenticated chip 210. If the authenticated chip 210 has not been successfully authenticated in the past, connection to the authenticated chip 210 may be refused, or access to the memory of the authenticated chip 210 may be prohibited. The flow of such processing will be described in detail later.

[0136] The configuration of the authenticated chip 210 according to this embodiment may be similar to the configuration described with reference to Fig. 12 in relation to the third embodiment. Also, the process flow for storing data generated in advance in the manufacturing stage of the product in the memories of the authentication chip 110 and the authenticated chip 210 may be similar to the process flow described with reference to Fig. 13 in relation to the third embodiment. However, in this embodiment, a history table 740 (empty at the time of manufacturing) is additionally generated in the non-volatile memory 715 of the authentication chip 110.

[0137] <5-2. Cartridge authentication> The overall process flow in the authentication system according to this embodiment may be similar to the process flow in the third embodiment described with reference to Fig. 14. Fig. 17 is a sequence diagram showing an example of a detailed flow of the authentication process executed in S510 in Fig. 14. Here, the i-th counter value C T_i Since the count reaches zero, the authentication process of S510 is executed.

[0138] First, in S711, the authentication unit 731 transmits an authentication start instruction to the authenticated chip 210. In S712, in response to a request from the authentication unit 731, the response unit 632 of the authenticated chip 210 retrieves the chip identifier C from the non-volatile memory 615. ID The input / output circuit 112 of the authentication chip 110 reads out the chip identifier C transmitted from the authenticated chip 210 and transmits it to the authentication chip 110.ID Receive.

[0139] Next, in S713, the authentication unit 731 searches the history table 740 to find the chip identifier C received from the authenticated chip 210. ID In the subsequent process, in S714, the chip identifier C is added to the history table 740. ID The branch depends on whether the chip identifier C exists in the history table 740. ID If no password exists (S714-NO), password verification and challenge-response authentication are performed in S715 to S739. S715 to S739 may be the same processing steps as S515 to S539 described with reference to FIG. 15 in relation to the third embodiment. When the authentication of the authenticated chip 210 is completed in S739, the authentication unit 731 registers the authentication result in the history table 740 in S741 (for example, the chip identifier C of the authenticated chip 210 that has been successfully authenticated). ID (Add a record to history table 740 indicating the

[0140] The history table 740 includes the chip identifier C ID If present (S714-YES), password verification and challenge-response authentication are skipped. In this case, the authentication unit 731 reports the result of past authentication indicated by the history table 740 to the control unit 107. If authentication has already been successful in the past, the control unit 107 may immediately access the memory of the process cartridge 200.

[0141] <5-3. Summary of the Fourth Example> In the above-mentioned fourth embodiment, the authentication device (authentication chip) has a table (history table) that stores the identifiers of devices to be authenticated that have been successfully authenticated. When an identifier received from a newly connected device to be authenticated exists in the table, the authentication unit of the authentication device determines that the device to be authenticated has already been authenticated without sending an authentication request to the device to be authenticated. Therefore, data required for authentication of the same device to be authenticated does not flow repeatedly through the wiring on the chip and the communication lines between the chips, making it difficult to statistically analyze the data flowing through these lines. This further improves resistance to information analysis attacks such as microprobing. Even if an identifier registered in the table is leaked, the identifier is only valid for a specific device to be authenticated. Therefore, attacks on the history table are not useful for the fraudulent purpose of imitating a device to be authenticated.

[0142] It should be noted that the various embodiments and modifications described herein may be combined with each other in any manner. For example, the history table described in the fourth embodiment may be adopted in the first or second embodiment. In general, the effects described in relation to one embodiment may be achieved in other embodiments having common features.

[0143] <6. Other embodiments> The above-mentioned embodiment can also be realized in the form of a process in which a program for realizing one or more functions is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0144] The disclosure of this specification includes at least the following authentication device and image forming device. (Item 1) An authentication device for authenticating an authenticated device, the authenticated device stores in advance first permission data used to determine whether or not to permit a response to an authentication request received from the authenticating device, The authentication device includes: A measurement unit that measures a time during which the authentication device is energized; a storage unit that stores limiting data that can be read out after the time measured by the measuring unit reaches a preset reference time; a communication unit that transmits to the authenticated device second permission data that is verified by the authenticated device using the first permission data, the second permission data being based on the restriction data read from the storage unit; an authentication unit that authenticates the authenticated device based on an authentication response received from the authenticated device when the authentication target device has successfully verified the second authorization data using the first authorization data; An authentication device comprising: (Item 2) the authenticated device stores an identifier unique to the authenticated device in advance, The communication unit receives the identifier from the authenticated device, the authenticator derives the second authorization data based on the restriction data and the identifier received from the authenticated device. Item 1. The authentication device according to item 1. (Item 3) the authenticated device prestores a first authentication key used to generate response data from challenge data received from the authenticator together with the authentication request, the first authentication key being derived based on the identifier; The communication unit is transmitting the challenge data to the prover together with the authentication request; receiving the authentication response including the response data transmitted from the authenticated device in response to the authentication request; the authentication unit verifies the response data included in the authentication response by using a second authentication key derived based on the challenge data transmitted to the authenticated device and the identifier received from the authenticated device, thereby authenticating the authenticated device. Item 2. An authentication device according to item 2. (Item 4) 4. The authentication device according to item 3, wherein the first authentication key and the second authentication key are used as a common key in a common key cryptosystem. (Item 5) 5. The authentication device according to claim 4, wherein the first authentication key and the second authentication key are derived by inputting input data based on a common master key and the identifier into a cryptographic hash function. (Item 6) 5. The authentication device according to claim 4, wherein the first authentication key and the second authentication key are derived by encrypting the identifier using a common master key as an encryption key. (Item 7) the device to be authenticated stores in advance a private key of a public key cryptosystem used for generating a digital signature of challenge data received from the authenticator together with the authentication request; The communication unit is transmitting the challenge data to the prover together with the authentication request; receiving the authentication response including the digital signature transmitted from the authenticated device in response to the authentication request; the authentication unit verifies the digital signature included in the authentication response by using a public key corresponding to the private key and the challenge data transmitted to the authenticated device, thereby authenticating the authenticated device. Item 1. The authentication device according to item 1. (Item 8) the device to be authenticated stores in advance the public key corresponding to the private key and a digital certificate certifying authenticity of the public key; The communication unit receives the public key and the electronic certificate from the device to be authenticated, the authentication unit verifies the digital signature included in the authentication response by using the public key when authenticity of the public key is confirmed based on the electronic certificate received from the device to be authenticated. Item 7. An authentication device according to item 7. (Item 9) the storage unit includes a table for storing identifiers of devices that have been successfully authenticated; When an identifier received by the communication unit from the authenticated device connected to the authentication device exists in the table, the authentication unit determines that the authenticated device has been authenticated without transmitting an authentication request to the authenticated device. An authentication device according to any one of items 1 to 8. (Item 10) 10. The authentication device according to any one of items 1 to 9, wherein the storage unit stores a counter value for monitoring the passage of time while the authentication device is energized. (Item 11) Item 11. The authentication device according to item 10, wherein the storage unit is a non-volatile memory. (Item 12) the first permission data includes N hash values ​​(N is an integer equal to or greater than 2) used for determining whether or not to permit a response to the authentication request; the restriction data includes N original values ​​corresponding to the N hash values, N different reference times are preset, when the time measured by the measurement unit reaches an i-th reference time (i is an integer between 1 and N), the communication unit transmits the i-th value of the second permission data derived based on the i-th original value of the restriction data to the authenticated device for verification using the corresponding i-th hash value of the first permission data. The authentication device according to any one of items 1 to 11. (Item 13) The authentication device described in Item 12, wherein when the time measured by the measurement unit reaches the i-th reference time, the communication unit transmits i values ​​of the second permission data, each derived based on the first to i-th original values ​​of the restriction data, to the authenticated device for verification using the corresponding i hash values ​​of the first permission data. (Item 14) the authenticated device prestores N first authentication keys each used to generate response data from challenge data received from the authenticator together with the authentication request; The communication unit is transmitting the challenge data to the prover together with the authentication request; receiving an authentication response including the response data generated by using the i-th first authentication key, the response data being transmitted from the authenticated device in response to the authentication request; the authentication unit verifies the response data included in the authentication response by using the challenge data transmitted to the authenticated device and a second authentication key corresponding to the i-th first authentication key, thereby authenticating the authenticated device. Item 14. An authentication device according to item 12 or 13. (Item 15) An authentication device according to any one of items 1 to 14, an image forming unit that forms an image on a sheet; An image forming apparatus comprising: (Item 16) Item 16. The image forming apparatus according to item 15, wherein the authenticated device is a replaceable part that is attached to the image forming apparatus. (Item 17) the replaceable part stores control parameters indicative of suitable operating conditions for the replaceable part; The image forming apparatus includes: a control unit that prohibits reading of the control parameters from the replaceable part when the authentication unit fails to authenticate the replaceable part; Further equipped with the control unit permits reading of the control parameter of the replaceable part without causing the authentication unit to authenticate the replaceable part before the time measured by the measurement unit reaches the reference time. Item 17. The image forming apparatus according to item 16.

[0145] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0146] 100: Image forming apparatus, 101: Engine controller, 103: Connection I / F, 105: Sensor, 107: Control unit, 110: Authentication chip, 115, 315, 515, 715: Non-volatile memory, 117: Password original key (K PO ), 517: Password key table, 118: Authentication key (K AO ), 318: Certificate verification key (K CV ), 518: Authentication source key table, 119: Timer counter (C T ), 519: timer counter table, 123: timer circuit, 124, 524: key access device, 131, 331, 531, 731: authentication unit, 740: history table, 200: process cartridge, 210: authenticated chip, 215, 415, 615: non-volatile memory, 217: password hash value (P H '), 617: Password hash table, 218: Authentication key (K A '), 618: Authentication key table, 417: Signature key (K S ), 418: Chip verification key (K V ), 219: Chip identifier (C ID ), 419: Chip Certificate (C V ), 224: key accessor, 231, 631: verification unit, 232, 432, 632: response unit

Claims

1. An authentication device for authenticating an authenticated device, the authenticated device stores in advance first permission data used to determine whether or not to permit a response to an authentication request received from the authenticating device, The authentication device includes: A measurement unit that measures a time during which the authentication device is energized; a storage unit that stores limiting data that can be read out after the time measured by the measuring unit reaches a preset reference time; a communication unit that transmits to the authenticated device second permission data that is verified by the authenticated device using the first permission data, the second permission data being based on the restriction data read from the storage unit; an authentication unit that authenticates the authenticated device based on an authentication response received from the authenticated device when the authentication target device has successfully verified the second authorization data using the first authorization data; An authentication device comprising:

2. the authenticated device stores an identifier unique to the authenticated device in advance, The communication unit receives the identifier from the authenticated device, the authentication unit derives the second authorization data based on the restriction data and the identifier received from the authenticated device. The authentication device according to claim 1 .

3. the authenticated device prestores a first authentication key used to generate response data from challenge data received from the authenticator together with the authentication request, the first authentication key being derived based on the identifier; The communication unit is transmitting the challenge data to the prover together with the authentication request; receiving the authentication response including the response data transmitted from the authenticated device in response to the authentication request; the authentication unit verifies the response data included in the authentication response by using a second authentication key derived based on the challenge data transmitted to the authenticated device and the identifier received from the authenticated device, thereby authenticating the authenticated device. The authentication device according to claim 2 .

4. The authentication device according to claim 3 , wherein the first authentication key and the second authentication key are used as a common key in a common key cryptosystem.

5. The authentication device according to claim 4 , wherein the first authentication key and the second authentication key are derived by inputting input data based on a common master key and the identifier into a cryptographic hash function.

6. The authentication device according to claim 4 , wherein the first authentication key and the second authentication key are derived by encrypting the identifier using a common master key as an encryption key.

7. The device to be authenticated stores in advance a private key of a public key cryptosystem used for generating a digital signature of challenge data received from the authenticator together with the authentication request; The communication unit is transmitting the challenge data to the prover together with the authentication request; receiving the authentication response including the digital signature transmitted from the authenticated device in response to the authentication request; the authentication unit verifies the digital signature included in the authentication response by using a public key corresponding to the private key and the challenge data transmitted to the authenticated device, thereby authenticating the authenticated device. The authentication device according to claim 1 .

8. the device to be authenticated stores in advance the public key corresponding to the private key and a digital certificate certifying authenticity of the public key; The communication unit receives the public key and the electronic certificate from the device to be authenticated, the authentication unit verifies the digital signature included in the authentication response by using the public key when authenticity of the public key is confirmed based on the electronic certificate received from the device to be authenticated. The authentication device according to claim 7.

9. the storage unit includes a table for storing identifiers of devices that have been successfully authenticated; When an identifier received by the communication unit from the authenticated device connected to the authentication device exists in the table, the authentication unit determines that the authenticated device has been authenticated without transmitting an authentication request to the authenticated device. The authentication device according to claim 1 .

10. The authentication device according to claim 1 , wherein the storage unit stores a counter value for monitoring the passage of time while the authentication device is energized.

11. The authentication device according to claim 10 , wherein the storage unit is a non-volatile memory.

12. the first authorization data includes N hash values ​​(N is an integer equal to or greater than 2) used for determining whether or not to permit a response to the authentication request, the restriction data includes N original values ​​corresponding to the N hash values, N different reference times are preset; When the time measured by the measurement unit reaches an ith reference time (i is an integer greater than or equal to 1 and less than or equal to N), the communication unit transmits the ith value of the second permission data derived based on the ith original value of the restriction data to the authenticated device for verification using the ith hash value corresponding to the first permission data. The authentication device according to claim 1 .

13. The authentication device described in claim 12, wherein when the time measured by the measurement unit reaches the i-th reference time, the communication unit transmits i values ​​of the second permission data, each derived based on the first to i-th original values ​​of the restriction data, to the authenticated device for verification using the corresponding i hash values ​​of the first permission data.

14. the authenticated device prestores N first authentication keys each used to generate response data from challenge data received from the authenticator together with the authentication request; The communication unit is transmitting the challenge data to the prover together with the authentication request; receiving an authentication response including the response data generated by using the i-th first authentication key, the response data being transmitted from the authenticated device in response to the authentication request; the authentication unit verifies the response data included in the authentication response by using the challenge data transmitted to the authenticated device and a second authentication key corresponding to the i-th first authentication key, thereby authenticating the authenticated device.

13. The authentication device according to claim 12.

15. An authentication device according to any one of claims 1 to 14, an image forming unit that forms an image on a sheet; An image forming apparatus comprising:

16. The image forming apparatus according to claim 15 , wherein the authenticated device is a replaceable part that is attached to the image forming apparatus.

17. the replaceable part stores control parameters indicative of suitable operating conditions for the replaceable part; The image forming apparatus includes: a control unit that prohibits reading of the control parameters from the replaceable part when the authentication unit fails to authenticate the replaceable part; Further equipped with the control unit permits reading of the control parameter of the replaceable part without causing the authentication unit to authenticate the replaceable part before the time measured by the measurement unit reaches the reference time. The image forming apparatus according to claim 16.

Images