Method and apparatus for lossless compression of GPU data

Abstract

The present disclosure relates to methods and devices for data processing or graphics processing, including an apparatus, e.g., a GPU. The apparatus may receive at least one bitstream including a plurality of bits, each of the bits corresponding to a position in the at least one bitstream, and each of the bits associated with color data. The apparatus may also arrange an order of the plurality of bits of the at least one bitstream such that at least one of the bits corresponds to an updated position in the at least one bitstream. Furthermore, the apparatus may transform color data associated with each of the plurality of bits of the at least one bitstream upon arranging the order of the bits. The apparatus may also compress the plurality of bits of the at least one bitstream upon transforming the color data associated with each of the bits.

Description

Claiming priority

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. patent application Ser. No. 17 / 169,342, filed Feb. 5, 2021, entitled "METHODS AND APPARATUS FOR LOSSLESS COMPRESSION OF GPU DATA," the entire contents of which are expressly incorporated by reference into this specification. [Technical field]

[0002] The present disclosure relates generally to processing systems, and more particularly to one or more techniques for data or graphics processing. [Background technology]

[0003] Introduction

[0003] Computing devices often perform graphics processing and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that work together to execute graphics processing commands and output frames. The central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are generally capable of concurrently executing multiple applications, each of which may need to utilize the GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values ​​and may issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0004]

[0004] A GPU of a device may be configured to perform operations in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform the process of display processing. However, with the advent of wireless communications and smaller handheld devices, an increased need for improved graphics or display processing has arisen. Summary of the Invention

[0005]

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, nor is it intended to identify key or critical elements of all aspects or to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006]

[0006] In one aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a graphics processing unit (GPU) or any apparatus capable of performing data processing or graphics processing. The apparatus may receive at least one bitstream including a plurality of bits, each of the plurality of bits corresponding to a position in the at least one bitstream, and each of the plurality of bits associated with color data. The apparatus may also arrange an order of the plurality of bits of the at least one bitstream such that at least one of the plurality of bits corresponds to an updated position in the at least one bitstream. Furthermore, the apparatus may transform color data associated with each of the plurality of bits of the at least one bitstream upon arranging an order of the plurality of bits. The apparatus may also compress the plurality of bits of the at least one bitstream upon transforming the color data associated with each of the plurality of bits. The apparatus may also encode the plurality of bits of the at least one bitstream upon compressing the plurality of bits. The apparatus may also transmit the at least one bitstream including the compressed plurality of bits to a memory. The apparatus may also receive at least one bitstream including the compressed bits from the memory, decompress the compressed bits in the at least one bitstream, decompress the bits of the at least one bitstream, reconverting color data associated with each of the bits of the at least one bitstream, rearranging an order of the bits of the at least one bitstream, and transmit the at least one bitstream including the bits.

[0007]

[0007] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. [Brief description of the drawings]

[0008] [Figure 1]

[0008] A block diagram illustrating an example content generation system in accordance with one or more techniques of this disclosure. [Diagram 2]

[0009] 1 illustrates an example GPU, in accordance with one or more techniques of this disclosure. [Diagram 3]

[0010] 1 illustrates a data compression process for data processing or graphics processing in accordance with one or more techniques of this disclosure. [Figure 4]

[0011] 1 illustrates a data prediction process for data processing or graphics processing in accordance with one or more techniques of this disclosure. [Diagram 5]

[0012] 1 illustrates a bit rearrangement process for data or graphics processing in accordance with one or more techniques of this disclosure. [Figure 6]

[0013] 4 is a communication flow diagram illustrating example communications between a GPU pipeline, GPU components, and memory, in accordance with one or more techniques of this disclosure. [Figure 7]

[0014] 1 is a flowchart of an exemplary method of graphics processing in accordance with one or more techniques of this disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0015] There are several different types of compression techniques that may be utilized for data processing or graphics processing. For example, universal bandwidth compression (UBWC) techniques or universal bandwidth restoration techniques may be utilized for data processing or graphics processing. The R11G11B10 data format may be utilized for data processing or graphics processing, which corresponds to compressed floating-point data, i.e., compressed floating-point red (R) green (G) blue (B) (RGB) data. In some aspects, the floating-point texture or vertex data may correspond to high bandwidth consumption. For example, the floating-point texture or vertex data may be at a certain amount of bits per pixel (bpp), e.g., 96 bpp, for RGB data. Since the R11G11B10 data format utilizes 32 bpp, this may correspond to high bandwidth usage. In some cases, due to the non-uniform bit depth of the B channel of RGB data, these formats may not be easy to compress losslessly. For example, it may be difficult to decorrelate data of the R channel, the G channel, and the B channel. Aspects of the present disclosure may losslessly compress some types of data formats, e.g., the R11G11B10 data format. Aspects of the present disclosure may also losslessly compress some types of data formats, e.g., the R11G11B10 data format, for graphics processing or GPU applications. Moreover, aspects of the present disclosure may enable decorrelation of data of different color channels, e.g., the R channel, the G channel, and / or the B channel, for some types of data formats, e.g., the R11G11B10 data format. Aspects of the present disclosure may also reduce the amount of bandwidth consumed in the case of lossless compressed data formats. For example, aspects of the present disclosure may reduce the amount of bandwidth utilized by the R11G11B10 data format on a GPU.

[0010]

[0016] Various aspects of the system, device, computer program product, and method are described more fully below with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout the present disclosure. Rather, these aspects are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should appreciate that the scope of the present disclosure covers any aspect of the system, device, computer program product, and method disclosed herein, whether implemented independently of other aspects of the present disclosure or in combination with other aspects of the present disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of aspects described herein. Furthermore, the scope of the present disclosure is intended to cover such an apparatus or method practiced using other structures, functions, or structures and functions in addition to or other than the various aspects of the present disclosure described herein. Any aspect disclosed herein may be implemented by one or more elements of a claim.

[0011]

[0017] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some potential benefits and advantages of the aspects of the disclosure are described, the scope of the disclosure is not limited to any particular benefit, use, or purpose. Rather, the aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated in the figures and in the following description by way of example. The detailed description and drawings are merely illustrative rather than limiting of the disclosure, the scope of which is defined by the appended claims and their equivalents.

[0012]

[0018] Several aspects are presented with respect to various apparatus and methods that are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system.

[0013]

[0019] As an example, an element, or any portion of an element, or any combination of elements, may be implemented as a "processing system" including one or more processors (sometimes referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chips (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gate logic, discrete hardware circuits, and other suitable hardware configured to perform various functions described throughout this disclosure. One or more processors in a processing system may execute software. Software may be broadly construed to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, and the like, regardless of whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application may refer to software. As described herein, one or more techniques may refer to an application, i.e., software configured to perform one or more functions. In such an example, the application may be stored in a memory, e.g., an on-chip memory of a processor, a system memory, or any other memory. Hardware described herein, such as a processor, may be configured to execute the application. For example, an application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein.As an example, hardware may access code from memory and execute the code accessed from memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or subcomponents of a single component.

[0014]

[0020] Thus, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on a computer-readable medium or encoded as one or more instructions or codes on the computer-readable medium. Computer-readable media includes computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may comprise random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the above types of computer-readable media, or any other medium that can be used to store computer-executable code in the form of instructions or data structures that can be accessed by a computer.

[0015]

[0021] In general, this disclosure describes techniques for improving the rendering of graphical content and / or reducing the load on a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU, having a graphics processing pipeline in a single device or multiple devices. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0016]

[0022] Instances of the term “content” as used herein may refer to “graphical content,” “images,” and vice versa. This is true whether the term is used as an adjective, a noun, or other part of speech. In some examples, the term “graphical content” as used herein may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, the term “graphical content” as used herein may refer to content produced by a processing unit configured to perform graphics processing. In some examples, the term “graphical content” as used herein may refer to content produced by a graphics processing unit.

[0017]

[0023] In some examples, the term "display content" as used herein may refer to content generated by a processing unit configured to perform display processing. In some examples, the term "display content" as used herein may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (sometimes referred to as a frame buffer). The display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to generate the display content. For example, the display processing unit may be configured to perform compositing on one or more rendered layers to generate a frame. As another example, the display processing unit may be configured to composite, blend, or otherwise combine two or more layers together into a single frame. The display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on the frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form a frame, i.e., a frame includes two or more layers, and a frame including two or more layers may then be blended.

[0018]

[0024] FIG. 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several optional components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frames for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first and second displays may not receive frames for presentation thereon. Instead, the frames or the graphics processing results may be forwarded to another device. In some aspects, this may be referred to as split-rendering.

[0019]

[0025] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in the graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a display processor, such as a display processor 127, to perform one or more display processing techniques on one or more frames generated by the processing unit 120 prior to presentation by the one or more displays 131. The display processor 127 may be configured to perform the display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0020]

[0026] Memory external to the processing unit 120 and the content encoder / decoder 122, such as a system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to an external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other over a bus or a different connection.

[0021]

[0027] The content encoder / decoder 122 may be configured to receive graphical content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphical content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphical content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphical content.

[0022]

[0028] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memory or storage devices. In some examples, the internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic or optical data media, or any other type of memory.

[0023]

[0029] The internal memory 121 or the system memory 124 may be a non-transitory storage medium, according to some examples. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagating signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

[0024]

[0030] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In some examples, processing unit 120 may be on a graphics card installed in a port in the motherboard of device 104, or in some cases may be embedded within a peripheral device configured to interoperate with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium, such as the internal memory 121, and execute those instructions in hardware using one or more processors to implement the techniques of the present disclosure. Any of the above, including hardware, software, combinations of hardware and software, etc., may be considered to be one or more processors.

[0025]

[0031] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the motherboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. When the technique is implemented in part in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium, for example, the internal memory 123, and execute those instructions in hardware using one or more processors to perform the techniques of the present disclosure. Any of the above, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0026]

[0032] In some aspects, the content generation system 100 may include an optional communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device that may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such an example, the transceiver 132 may be configured to perform any receiving and / or transmitting functions described herein with respect to the device 104.

[0027]

[0033] Referring again to FIG. 1 , in some aspects, the processing unit 120 may include a determining component 198 configured to receive at least one bitstream including a plurality of bits, each of the plurality of bits corresponding to a position in the at least one bitstream, and each of the plurality of bits associated with color data. The determining component 198 may also be configured to arrange an order of the plurality of bits of the at least one bitstream such that at least one of the plurality of bits corresponds to an updated position in the at least one bitstream. The determining component 198 may also be configured to convert color data associated with each of the plurality of bits of the at least one bitstream upon arranging an order of the plurality of bits. The determining component 198 may also be configured to compress the plurality of bits of the at least one bitstream upon converting the color data associated with each of the plurality of bits. The determining component 198 may also be configured to encode the plurality of bits of the at least one bitstream upon compressing the plurality of bits. The determining component 198 may also be configured to transmit the at least one bitstream including the compressed plurality of bits to a memory. The determining component 198 may also be configured to receive at least one bitstream including the compressed bits from the memory, decode the compressed bits in the at least one bitstream, restore the bits of the at least one bitstream, reconvert color data associated with each of the bits of the at least one bitstream, rearrange the order of the bits of the at least one bitstream, and transmit the at least one bitstream including the bits. Although the following description may focus on data processing or graphics processing, the concepts described herein may be applicable to other similar processing techniques.

[0028]

[0034] As described herein, a device, such as device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer, e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smartphone, a server, a video game platform or console, a handheld device, e.g., a portable video game device or a personal digital assistant (PDA), a wearable computing device, e.g., a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Although the processes herein may be described as being performed by a particular component (e.g., a GPU), in further embodiments, they may be performed using other components (e.g., a CPU) in accordance with the disclosed embodiments.

[0029]

[0035] A GPU can process multiple types of data or data packets in a GPU pipeline. For example, in some aspects, a GPU can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a set of global state information, e.g., information about global registers, shading programs, or constant data, that can adjust how a graphics context is processed. For example, a context register packet can include information about a color format. In some aspects of a context register packet, there can be a bit that indicates which workload belongs to a context register. Also, there can be multiple functions or programming running simultaneously and / or in parallel. For example, a function or programming can describe a certain operation, e.g., a color mode or color format. Thus, a context register can define multiple states of a GPU.

[0030]

[0036] The context state may be utilized to determine how individual processing units, e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, function and / or in which mode the processing units function. To do so, the GPU may use context registers and programming data. In some aspects, the GPU may generate workloads, e.g., vertex or pixel workloads, in a pipeline based on the context register definition of a mode or state. Some processing units, e.g., a VFD, may use these states to determine some functions, e.g., how vertices are assembled. Because these modes or states may change, the GPU may need to change the corresponding context. Additionally, the workloads corresponding to the modes or states may follow the changing mode or state.

[0031]

[0037] FIG. 2 illustrates an example GPU 200 in accordance with one or more techniques of this disclosure. As illustrated in FIG. 2, GPU 200 includes a command processor (CP) 210, a draw call packet 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a render backend (RB) 236, a level 2 (L2) cache (UCHE) 238, and a system memory 240. Although FIG. 2 illustrates GPU 200 including processing units 220-238, GPU 200 may include several additional processing units. Additionally, processing units 220-238 are merely examples and any combination or order of processing units may be used by a GPU in accordance with this disclosure. GPU 200 also includes a command buffer 250, a context register packet 260, and a context state 261.

[0032]

[0038] As shown in FIG. 2, the GPU can utilize a CP, e.g., CP 210, or a hardware accelerator, to parse the command buffer into context register packets, e.g., context register packet 260, and / or draw call data packets, e.g., draw call packet 212. CP 210 can then send the context register packet 260 or draw call data packet 212 through separate paths to a processing unit or block in the GPU. Additionally, command buffer 250 can alternate between different states of context registers and draw calls. For example, the command buffer can be structured in the following manner: context register of context N, draw call(s) of context N, context register of context N+1, and draw call(s) of context N+1.

[0033]

[0039] Some aspects of data processing or graphics processing may utilize lossless compression, which is a type of data compression that corresponds to an exact reconstruction of the compressed data (i.e., data that is reconstructed without any data loss). In some cases, lossless compression may be associated with an increased data compression ratio, since the data can be largely correctly reconstructed. This high level of data reconstruction may correspond to a reduction in data size or a reduction in media size of the data. Lossless compression techniques may also include a number of different data compression algorithms that may allow data to be reconstructed without any data loss.

[0034]

[0040] There are several different types of compression techniques that may be utilized in data processing or graphics processing. For example, a universal bandwidth compression (UBWC) technique or a universal bandwidth restoration technique may be utilized in data processing or graphics processing. Furthermore, different data formats may be associated with the UBWC compression techniques utilized in data processing or graphics processing. For example, an R11G11B10 data format may be utilized in data processing or graphics processing, which corresponds to compressed floating-point data, i.e., compressed floating-point Red (R) Green (G) Blue (B) (RGB) data. The R11G11B10 data format may include 11 bits for the R channel, 11 bits for the G channel, and 10 bits for the B channel. In some aspects, the R11G11B10 data may be utilized as a format for texture files and / or rendering, e.g., for texture files and / or rendering during graphics processing in a GPU. The R11G11B10 data may enable some GPU components, such as double data rate (DDR) memory, to reduce the amount of data fetched or retrieved by the GPU. Additionally, the R11G11B10 data may correspond to a reduced amount of utilized memory bandwidth.

[0035]

[0041] In some aspects, floating-point texture or vertex data may correspond to high bandwidth consumption. For example, floating-point texture or vertex data may be at a certain amount of bits per pixel (bpp), for example 96 bpp, for RGB data. This RGB data may differ from RGBA data in that RGB data does not have alpha values. Some techniques for saving bandwidth may utilize half-float data formats, for example, half-float RGB161616 data format (corresponding to 48 bpp) or R11G11B10 data format (corresponding to 32 bpp). Since R11G11B10 data format utilizes 32 bpp, this may correspond to high bandwidth usage. In some cases, due to the non-uniform bit depth of the B channel of RGB data, these formats may not be easily compressed losslessly. For example, it may be difficult to decorrelate data of the R channel, the G channel, and the B channel.

[0036]

[0042] In accordance with the above, it may be beneficial to losslessly compress some types of data formats, for example, the R11G11B10 data format. It may also be beneficial to losslessly compress these data formats for graphics processing or GPU applications. Furthermore, in these types of data formats, it may be beneficial to enable de-correlation of data of different color channels, for example, the R channel, the G channel, and / or the B channel. It may also be beneficial to reduce the amount of bandwidth consumed in losslessly compressed data formats.

[0037]

[0043] Aspects of the present disclosure may losslessly compress some types of data formats, e.g., the R11G11B10 data format. Aspects of the present disclosure may also losslessly compress some types of data formats, e.g., the R11G11B10 data format, for graphics processing or GPU applications. Moreover, aspects of the present disclosure may enable decorrelation of data of different color channels, e.g., the R channel, the G channel, and / or the B channel, for some types of data formats, e.g., the R11G11B10 data format. Aspects of the present disclosure may also reduce the amount of bandwidth consumed in the case of lossless compressed data formats. For example, aspects of the present disclosure may reduce the amount of bandwidth utilized by the R11G11B10 data format on a GPU.

[0038]

[0044] Some aspects of the present disclosure may utilize lossless compression techniques for some types of data, e.g., R11G11B10 data or RGB111110 data, using a bit rearranging technique. For example, aspects of the present disclosure may utilize a lossless compression process for data, e.g., R11G11B10 data, using bit rearranging from a particular bit format, e.g., 11-11-10 bit format, to another bit format, e.g., 10-10-10-2 bit format. This bit rearrangement process may be followed by a decorrelation process, e.g., an RGB decorrelation process, which may use some type of transform, e.g., a luma (Y) chrominance orange (Co) chrominance green (Cg) (YCoCg) transform. Following the decorrelation process, aspects of the present disclosure may utilize lossless compression techniques that exploit spatial correlation, e.g., spatial correlation in the Y-Co-Cg color space.

[0039]

[0045] FIG. 3 is a diagram 300 illustrating a data compression process for data processing or graphics processing according to one or more techniques of the present disclosure. As shown in FIG. 3, the diagram 300 includes an encoder 310, an R11G11B10 data format 312, an R11G11B10X2 data format 314, and an Y10Co11Cg11X2 data format 316. The diagram 300 also includes a lossless compression process 320 including a Y channel 322, a Co channel 324, a Cg channel 326, and an X channel 328. The diagram 300 also includes a bitstream 330, a decoder 340, a Y10Co11Cg11X2 data format 342, an R11G11B10X2 data format 344, and an R11G11B10 data format 346. FIG. 3 illustrates a lossless compression process of R11G11B10 data. More specifically, Figure 3 displays a lossless compression process of R11G11B10 data using bit rearrangement from one bit format, e.g., 11-11-10 bit format, to another bit format, e.g., 10-10-10-2 bit format. Figure 3 also shows a decorrelation process, e.g., RGB decorrelation process, that may use a Y-Co-Cg transform. As shown in Figure 3, diagram 300 may also include lossless compression techniques that exploit spatial correlation in the Y-Co-Cg format.

[0040]

[0046] As shown in FIG. 3, the encoder 310, e.g., an engine of the encoder 310, may rearrange the color data to make it more suitable for compression. For example, the encoder 310 may rearrange bits of an RGB data format 312 into another color format, e.g., an R11G11B10X2 data format 314 associated with an RGBA format. During this process, the encoder 310 may separate bits in the R and G channels to create separate planar channels, e.g., an X channel. The encoder 310 may then convert the data bits into a color space by performing an RGB to YCoCgR conversion. This color space conversion may result in a data format that is more suitable for compression, e.g., an Y10Co11Cg11X2 data format 316, since it provides correlation across multiple channels.

[0041]

[0047] After this color space conversion, an embodiment of the present disclosure may perform a lossless compression process 320, for example in a UBWC engine. This lossless compression process 320 may utilize different channels, for example, Y channel 322, Co channel 324, Cg channel 326, and X channel 328. Also, after the lossless compression process 320, i.e., 2D compression, the data may be formed into a bitstream, for example, bitstream 330, for storage in a memory, for example, a DDR memory. Accordingly, the data is encoded before storing in the DDR memory.

[0042]

[0048] As shown in FIG. 3, after being stored in the DDR memory, the bitstream 330 may be decoded at the decoder 340. In some aspects, the bitstream 330 may include a header, metadata, and / or compression data. The header may include information for the decoder 340, such as information regarding which color space conversion or compression format to utilize. At the decoder 340, the bitstream 330 may be in a Y10Co11Cg11X2 data format, e.g., Y10Co11Cg11X2 data format 342. In this case, the decoder 340 may perform a YCoCgR to RGB conversion, resulting in an R11G11B10X2 data format 344. After this, the decoder 340 may perform a bit rearrangement resulting in an R11G11B10 data format 346. Accordingly, the decoder 340 may perform the inverse functions of each of the steps performed by the encoder 310. By doing so, the decoder 340 may obtain the original data received and processed by the encoder 310. In some aspects, the encoder 310 and the decoder 340 may be in the GPU between the GPU pipeline and the DDR memory, or the encoder 310 and the decoder 340 may be in a chipset in the GPU and coupled with the display.

[0043]

[0049] As described above, to apply color space conversion or correction to a data format, for example, the R11G11B10 format, embodiments of the present disclosure may apply a bit rearrangement process. For example, embodiments of the present disclosure may rearrange certain bits of data to allow color channels, for example, the R, G, and B channels, to have the same bit depth. By doing so, this may result in data that is more suitable for color space conversion. In some embodiments, the present disclosure may rearrange the R and G bits of an RGB data format to match the format of the B bits. For example, in the R11G11B10 format, both the R and G channels contain 11 bits, but the B channel contains 10 bits. Thus, embodiments of the present disclosure may rearrange the 11-bit format of the R and G channels of an RGB data format to match the 10-bit format of the B channel.

[0044]

[0050] Since there are many possible color mappings for color space conversion, embodiments of the present disclosure may minimize the bit depth of some channels, e.g., the X channel bit depth, and maximize the bit depth of other channels, e.g., channels that are suitable for color space conversion. In one embodiment, this process may be achieved by moving a number of bits, e.g., m bits, from the R and G channels to another channel, e.g., the X channel. This may result in the other channel, e.g., the X channel, having a bit depth, e.g., 2m bits. Also, the number of bits, e.g., m bits, may be selected based on results or experiments that maximize lossless compression ratio.

[0045]

[0051] In some aspects, after the bit rearrangement process, aspects of the present disclosure may apply a color space conversion. Some color spaces, e.g., Y-Co-Cg-R color space, may be more suitable for some types of data prediction, e.g., two-dimensional (2D) prediction. After the generation of the color channel, e.g., RGBX channel, some types of data, e.g., RGB data, may undergo a lossless color space conversion to a color space, e.g., Y-Co-Cg color space. Also, the RGBX channel may correspond to a color data format, e.g., RGBA format. For example, during this conversion, Y may occupy a certain amount of bits, e.g., n bits, and Co / Cg may occupy another amount of bits, e.g., n+1 bits, where n is the original bit depth of the R / G / B channels in the RGBX channel. As mentioned above, some channels, e.g., X channel, may be excluded from the conversion process. After this conversion process, the Y-Co-Cg-X data may be sent to a prediction engine, e.g., a spatial 2D prediction engine. In addition, all of the data in the above color space conversion may be interleaved, for example, RGB data, RGBX data, and YCoCgX data may be interleaved. Thus, the data in the color space conversion may correspond to a 2D plane conversion.

[0046]

[0052] 4 is a diagram 400 illustrating a data prediction process for data processing or graphics processing according to one or more techniques of the present disclosure. FIG. 4 illustrates a data prediction process that may be utilized in a prediction engine, for example, a spatial 2D prediction engine. As shown in FIG. 4, all four channels, for example, channels of pixels A, B, C, and X, may undergo a spatial compression process. For 2D prediction, aspects of the present disclosure may utilize a spatial neighborhood predictor or a parallelogram predictor, as shown in FIG. 400.

[0047]

[0053] The diagram 400 includes a predicted pixel, e.g., pixel X, and spatial neighboring pixels, e.g., pixel A, pixel B, and pixel C. As shown in FIG. 4, a predictor (e.g., X') of a predicted pixel, e.g., pixel X, may be generated using spatial neighboring pixels, e.g., pixels A, B, and C. The predictor (e.g., X') may be calculated by the following formula: X'=A+BC. In some aspects, the predicted residual may then be block fixed length coding (BFLC) encoded (i.e., lossless encoded) and placed in a bitstream with an appropriate header. Moreover, the decoding process may follow the inverse steps of each of the aforementioned steps to obtain the original data.

[0048]

[0054] FIG. 5 is a diagram 500 illustrating a bit rearrangement process for data processing or graphics processing according to one or more techniques of the present disclosure. FIG. 5 displays a bit rearrangement process including a bit arrangement 510 and several bits for bit rearrangements or mappings 520, 530, 540, 550, and 560. That is, the diagram 500 includes an initial bit arrangement, e.g., B10G11R11 format 510, and several different bit rearrangements (i.e., mappings), e.g., mappings 520, 530, 540, 550, and 560. Each of the bit rearrangements (i.e., mappings) may be suitable for several types of color space conversion or correction, e.g., RGB color space conversion or correction. As shown in FIG. 5, the bit arrangement 510 may include several bits in an R11G11B10 format, which may include exponent bits and floating point bits (i.e., mantissa bits) for each channel, e.g., for each R, G, and B channel. For example, in bit constellation 510 including the R11G11B10 format, the R and G channels include 11 bits (5 exponent bits and 6 mantissa bits) and the B channel includes 10 bits (5 exponent bits and 5 mantissa bits).

[0049]

[0055] As shown in FIG. 5, compared to the bit arrangement 510, each of the bit rearrangements or mappings 520, 530, 540, 550, and 560 includes a different number of exponent and mantissa bits for the R, G, and B channels. For example, the bit mapping 520 includes a B channel with 8 bits (e.g., 5 exponent and 3 mantissa bits), a G channel with 8 bits (e.g., 5 exponent and 3 mantissa bits), and an R channel with 8 bits (e.g., 5 exponent and 3 mantissa bits). The bit mapping 520 also includes an X channel with a combination of 8 RGB bits (e.g., 2 B mantissa bits, 3 G mantissa bits, and 3 R mantissa bits). As shown in FIG. 5, each of the mappings 520, 530, 540, 550, and 560 may include bit rearrangements depending on the bit position. In the bit mapping 530, the B channel includes 8 bits (e.g., 5 exponent bits and 3 mantissa bits), the G channel includes 8 bits (e.g., 5 exponent bits and 3 mantissa bits), and the R channel includes 8 bits (e.g., 5 exponent bits and 3 mantissa bits). The bit mapping 530 also includes an X channel with 8 RGB bits (e.g., 2 B mantissa bits, 3 G mantissa bits, and 3 R mantissa bits).

[0050]

[0056] Additionally, bit mapping 540 includes a B channel with 8 bits (e.g., 3 exponent bits and 5 mantissa bits), a G channel with 8 bits (e.g., 3 exponent bits and 5 mantissa bits), and an R channel with 8 bits (e.g., 3 exponent bits and 5 mantissa bits). Bit mapping 540 also includes an X channel with 8 RGB bits (e.g., 2 B exponent bits, 2 G exponent bits, 1 G mantissa bit, 2 R exponent bits, and 1 R mantissa bit). Bit mapping 550 includes an X channel with a combination of 8 RGB bits (e.g., 2 B exponent bits, 2 G exponent bits, 1 G mantissa bit, 2 R exponent bits, and 1 R mantissa bit). Finally, bit mapping 560 includes a B channel with 10 bits (e.g., 5 exponent bits and 5 mantissa bits), a G channel with 10 bits (e.g., 5 exponent bits and 5 mantissa bits), and an R channel with 10 bits (e.g., 5 exponent bits and 5 mantissa bits). Bit mapping 560 also includes an X channel with 2 RGB bits (1 G mantissa bit and 1 R mantissa bit). In bit mapping 560, each of the RGB channels includes a similar amount of bits, e.g., 8 bits including a similar amount of exponent bits (i.e., magnitude) and mantissa bits (i.e., floating point). As shown in FIG. 5, mapping 560 corresponds to a complete bit rearrangement.

[0051]

[0057] The embodiments of the present disclosure may include several benefits and advantages. For example, based on the compression process described above, for example the compression process shown in FIG. 3, and the bit rearrangement described above, for example the bit rearrangement shown in FIG. 5, the embodiments of the present disclosure may include several advantages. For example, in one embodiment, the average bandwidth saving for a dataset of various files, for example GPU-related files, may be an amount of lossless gain, for example 15.93% lossless gain. Thus, the embodiments of the present disclosure may reduce the time and / or amount of storage of the memory storage process (for example, a 15.93% reduction in the time and / or amount of storage). Furthermore, when the present disclosure is utilized with a spatial prediction process as shown in FIG. 4, an amount of lossless gain, for example 21.64% lossless gain, may be observed. This spatial prediction process may be used for some GPU files that exhibit strong horizontal correlation. To achieve these benefits and / or lossless gains, embodiments of the present disclosure may utilize a certain data format, for example, the R11G11B10 format, along with a certain prediction and encoding process, for example, a 2D prediction and BFLC coding process.

[0052]

[0058] 6 is a communication flow diagram 600 of data or graphics processing in accordance with one or more techniques of the present disclosure. As shown in FIG. 6, diagram 600 includes example communications between GPU components 602, e.g., a chipset of a GPU, a GPU pipeline 604, and memory 606, e.g., a DDR memory of a GPU, in accordance with one or more techniques of the present disclosure.

[0053]

[0059] At 610, the GPU component 602 may receive at least one bitstream including a plurality of bits, e.g., bitstream 612, from the GPU pipeline 604, each of the plurality of bits corresponding to a position in the at least one bitstream, each of the plurality of bits being associated with color data. The plurality of bits may correspond to a 32-bit high dynamic range (HDR) format or an R11G11B10 format.

[0054]

[0060] At 620, the GPU component 602 may arrange an order of bits of at least one bitstream, e.g., bitstream 612 / 662, such that at least one of the bits corresponds to an updated position in the at least one bitstream. The order of the bits may be arranged by moving one or more floating-point bits in the at least one bitstream. Also, the one or more floating-point bits may be moved to the beginning of the order of the bits or to the end of the order of the bits. The one or more floating-point bits may correspond to a red (R) floating-point bit, a green (G) floating-point bit, and a blue (B) floating-point bit.

[0055]

[0061] At 630, the GPU component 602, upon arranging the order of the bits, may transform color data associated with each of the bits of at least one bitstream, e.g., bitstream 612 / 662. The color data may be converted from Red (R) Green (G) Blue (B) (RGB) data to Luma (Y) Chrominance Orange (Co) Chrominance Green (Cg) (YCoCg) data. Furthermore, the color data associated with each of the bits may be transformed based on at least one of a color space transformation or a lossless transformation.

[0056]

[0062] At 640, the GPU component 602 may compress the plurality of bits in at least one bitstream, e.g., bitstream 612, upon transforming the color data associated with each of the plurality of bits. The plurality of bits may be compressed based on a predictive compression scheme. The predictive compression scheme may be based on spatially neighboring color data of the color data associated with each of the plurality of bits. Also, the predictive compression scheme may be associated with at least one of a spatial neighborhood predictor or a parallelogram predictor. In some aspects, the plurality of bits in at least one bitstream, e.g., bitstream 612 / 662, may be compressed into one or more data packets. The one or more data packets may be double data rate (DDR) packets. Moreover, the compression of the plurality of bits may be lossless compression.

[0057]

[0063] At 650, upon compressing the bits, the GPU component 602 may encode the bits in at least one bitstream, e.g., bitstream 612 / 662. The bits may be encoded based on a block fixed length coding (BFLC) process. The bits may also be encoded by appending at least one of a header or metadata to the bits.

[0058]

[0064] At 660, the GPU component 602 may send at least one bitstream including the compressed bits, e.g., bitstream 662, to a memory, e.g., memory 606. The memory may be a double data rate (DDR) memory within a graphics processing unit (GPU).

[0059]

[0065] At 670, the GPU component 602 may receive at least one bitstream, e.g., bitstream 672, including compressed bits from a memory, e.g., from memory 606, decode the compressed bits in the at least one bitstream, e.g., bitstream 672 / 674, restore the bits of the at least one bitstream, e.g., bitstream 672 / 674, reconvert color data associated with each of the bits of the at least one bitstream, e.g., bitstream 672 / 674, rearrange the order of the bits of the at least one bitstream, e.g., bitstream 672 / 674, and transmit the at least one bitstream, e.g., bitstream 674, including the compressed bits.

[0060]

[0066] 7 is a flowchart 700 of an example method of data or graphics processing in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus such as an apparatus for graphics processing, a GPU or other graphics processor, a chipset, a GPU pipeline, a wireless communication device, and / or any apparatus capable of performing data or graphics processing used in connection with the examples of FIGS. 1-6.

[0061]

[0067] At 702, the apparatus may receive at least one bitstream including a plurality of bits, each of the plurality of bits corresponding to a position in the at least one bitstream, and each of the plurality of bits associated with color data, as described in connection with the examples of FIGS. 1-6. For example, the GPU component 602 may receive at least one bitstream including a plurality of bits, each of the plurality of bits corresponding to a position in the at least one bitstream, and each of the plurality of bits associated with color data. Further, the processing unit 120 may perform 702. The plurality of bits may correspond to a 32-bit high dynamic range (HDR) format or an R11G11B10 format, as described in connection with the examples of FIGS. 1-6.

[0062]

[0068] At 704, the apparatus may arrange an order of the plurality of bits of the at least one bitstream such that at least one of the plurality of bits corresponds to an updated position in the at least one bitstream, as described in conjunction with the examples of FIGS. 1-6. For example, the GPU component 602 may arrange an order of the plurality of bits of the at least one bitstream such that at least one of the plurality of bits corresponds to an updated position in the at least one bitstream. Further, the processing unit 120 may perform 704. The order of the plurality of bits may be arranged by moving one or more floating-point bits in the at least one bitstream, as described in conjunction with the examples of FIGS. 1-6. Also, the one or more floating-point bits may be moved to the beginning of the order of the plurality of bits or to the end of the order of the plurality of bits, as described in conjunction with the examples of FIGS. 1-6. The one or more floating-point bits may correspond to a red (R) floating-point bit, a green (G) floating-point bit, and a blue (B) floating-point bit, as described in connection with the examples of Figures 1-6.

[0063]

[0069] At 706, the apparatus may transform color data associated with each of the plurality of bits of the at least one bitstream, as described in conjunction with the examples of FIGS. 1-6, upon arranging the order of the plurality of bits. For example, the GPU component 602 may transform color data associated with each of the plurality of bits of the at least one bitstream, as described in conjunction with the examples of FIGS. 1-6. Further, the processing unit 120 may perform 706. The color data may be transformed from Red (R) Green (G) Blue (B) (RGB) data to Luma (Y) Chrominance Orange (Co) Chrominance Green (Cg) (YCoCg) data, as described in conjunction with the examples of FIGS. 1-6. Further, the color data associated with each of the plurality of bits may be transformed based on at least one of a color space transformation or a lossless transformation, as described in conjunction with the examples of FIGS. 1-6.

[0064]

[0070] At 708, the apparatus may compress the plurality of bits of the at least one bitstream upon transforming the color data associated with each of the plurality of bits, as described in conjunction with the examples of FIGS. 1-6. For example, the GPU component 602 may compress the plurality of bits of the at least one bitstream upon transforming the color data associated with each of the plurality of bits. Additionally, the processing unit 120 may perform 708. The plurality of bits may be compressed based on a predictive compression scheme, as described in conjunction with the examples of FIGS. 1-6. The predictive compression scheme may be based on spatially neighboring color data of the color data associated with each of the plurality of bits, as described in conjunction with the examples of FIGS. 1-6. Also, the predictive compression scheme may be associated with at least one of a spatial neighborhood predictor or a parallelogram predictor, as described in conjunction with the examples of FIGS. 1-6. In some aspects, the plurality of bits of the at least one bitstream may be compressed into one or more data packets, as described in conjunction with the examples of FIGS. 1-6. The one or more data packets may be double data rate (DDR) packets. Moreover, the compression of multiple bits may be a lossless compression, as described in relation to the examples of FIGS.

[0065]

[0071] At 710, the apparatus may, upon compressing the plurality of bits, encode the plurality of bits of the at least one bitstream, as described in conjunction with the examples of FIGS. 1-6. For example, the GPU component 602 may, upon compressing the plurality of bits, encode the plurality of bits of the at least one bitstream. Further, the processing unit 120 may perform 710. The plurality of bits may be encoded based on a block fixed length coding (BFLC) process, as described in conjunction with the examples of FIGS. 1-6. The plurality of bits may also be encoded by appending at least one of a header or metadata to the plurality of bits, as described in conjunction with the examples of FIGS. 1-6.

[0066]

[0072] At 712, the apparatus may transmit at least one bitstream including the compressed plurality of bits to a memory, as described in connection with the examples of Figures 1-6. For example, the GPU component 602 may transmit at least one bitstream including the compressed plurality of bits to a memory. Further, the processing unit 120 may perform 712. The memory may be a double data rate (DDR) memory in a graphics processing unit (GPU), as described in connection with the examples of Figures 1-6.

[0067]

[0073] At 714, the apparatus may receive at least one bitstream including compressed bits from memory, decode the compressed bits in the at least one bitstream, decompress the bits of the at least one bitstream, reconvert color data associated with each of the bits of the at least one bitstream, rearrange the order of the bits of the at least one bitstream, and transmit at least one bitstream including the bits, as described in connection with the examples of FIGS. 1-6. For example, GPU component 602 may receive at least one bitstream including compressed bits from memory, decode the compressed bits in the at least one bitstream, decompress the bits of the at least one bitstream, reconvert color data associated with each of the bits of the at least one bitstream, rearrange the order of the bits of the at least one bitstream, and transmit at least one bitstream including the bits. Additionally, processing unit 120 may perform 714.

[0068]

[0074] In an arrangement, a method or apparatus for data processing or graphics processing is provided. The apparatus may be a GPU, a graphics processor, a data processor, or any other processor capable of performing data processing or graphics processing. In an aspect, the apparatus may be a processing unit 120 in the device 104, or some other hardware in the device 104 or another device. The apparatus may include means for receiving at least one bitstream including a plurality of bits, each of the plurality of bits corresponding to a position in the at least one bitstream, and each of the plurality of bits associated with color data. The apparatus may further include means for arranging an order of the plurality of bits of the at least one bitstream such that at least one of the plurality of bits corresponds to an updated position in the at least one bitstream. The apparatus may further include means for transforming color data associated with each of the plurality of bits of the at least one bitstream upon arranging an order of the plurality of bits. The apparatus may further include means for compressing the plurality of bits of the at least one bitstream upon transforming the color data associated with each of the plurality of bits. The apparatus may further include means for encoding the plurality of bits of the at least one bitstream upon compressing the plurality of bits. The apparatus may further include means for transmitting the at least one bitstream including the compressed plurality of bits to a memory. The apparatus may further include means for receiving the at least one bitstream including the compressed plurality of bits from a memory. The apparatus may further include means for decoding the compressed plurality of bits in the at least one bitstream. The apparatus may further include means for decompressing the plurality of bits of the at least one bitstream. The apparatus may further include means for reconverting color data associated with each of the plurality of bits of the at least one bitstream. The apparatus may further include means for rearranging an order of the plurality of bits of the at least one bitstream. The apparatus may further include means for transmitting the at least one bitstream including the plurality of bits.

[0069]

[0075] The subject matter described herein may be implemented to achieve one or more benefits or advantages. For example, the described data processing or graphics processing techniques may be used by a GPU, a graphics processor, a data processor, or any other processor capable of performing data or graphics processing to implement the lossless compression or color space conversion techniques described herein. This may also be achieved at a low cost compared to other data or graphics processing techniques. Moreover, the data or graphics processing techniques herein may improve or speed up data processing or execution. Furthermore, the data or graphics processing techniques herein may improve resource or data utilization and / or resource efficiency. Furthermore, aspects of the present disclosure may utilize lossless compression or color space conversion to improve memory bandwidth and / or reduce performance overhead in the GPU.

[0070]

[0076] It should be understood that the particular order or hierarchy of the blocks in the disclosed processes / flowcharts is intended to describe example approaches. Based on design preferences, it should be understood that the particular order or hierarchy of the blocks in the processes / flowcharts may be rearranged. Additionally, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in an example order, and are not limited to the particular order or hierarchy presented.

[0071]

[0077] The foregoing description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Thus, the claims are not limited to the aspects set forth herein but are to be accorded the full scope consistent with the language of the claims, and reference to an element in the singular does not mean "one and only one" unless specifically so stated, but rather means "one or more." As used herein, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0072]

[0078] Unless otherwise noted, the term "some" refers to one or more, and the term "or" may be interpreted as "and / or" unless the context dictates otherwise. Combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, and any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or later known to those skilled in the art are expressly incorporated herein by reference and are encompassed by the claims. Moreover, nothing disclosed herein is intended to be exclusive to the public, regardless of whether such disclosure is expressly recited in the claims. Words such as "module," "mechanism," "element," "apparatus," and the like cannot substitute for the word "means." Thus, a claim element is not to be construed as a means-plus-function unless the element is expressly recited using the phrase "means for."

[0073]

[0079] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

[0074]

[0080] According to the present disclosure, the term "or" may be interrupted as "and / or" unless the context dictates otherwise. Furthermore, phrases such as "one or more" or "at least one" may be used for some features disclosed herein and not for other features, but the feature for which such phraseology is not used may be construed as having such implied meaning unless the context dictates otherwise.

[0075]

[0081] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on or transmitted via a computer-readable medium as one or more instructions or code. A computer-readable medium may include a computer data storage medium or a communication medium, including any medium that enables the transfer of a computer program from one place to another. In this manner, a computer-readable medium may generally correspond to (1) a tangible computer-readable storage medium that is non-transitory, or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementation of the techniques described in this disclosure. By way of example and not limitation, such computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer readable media. A computer program product may include a computer readable medium.

[0076]

[0082] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, the term "processor" as used herein may refer to any of the above structures, or any other structure suitable for implementing the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.

[0077]

[0083] The techniques of the present disclosure may be implemented in a wide variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs) or sets of ICs, e.g., chipsets. In this disclosure, various components, modules or units have been described to highlight functional aspects of devices configured to implement the disclosed techniques, but those components, modules or units do not necessarily require realization by different hardware units. Rather, as described above, the various units may be combined in any hardware unit or provided by a collection of interoperable hardware units, including one or more processors described above, along with suitable software and / or firmware. Thus, the term "processor" as used herein may refer to any of the aforementioned structures, or any other structure suitable for implementing the techniques described herein. Also, the present techniques may be fully implemented in one or more circuits or logic elements.

[0078]

[0084] The following aspects are illustrative only and can be combined with other aspects or teachings described herein, without limitation.

[0079]

[0085] Aspect 1 is a method of data processing or graphics processing, the method including: receiving at least one bitstream including a plurality of bits, arranging an order of the plurality of bits of the at least one bitstream such that each of the plurality of bits corresponds to a position in the at least one bitstream, each of the plurality of bits being associated with color data, and at least one of the plurality of bits corresponds to an updated position in the at least one bitstream, transforming the color data associated with each of the plurality of bits of the at least one bitstream upon arranging the order of the plurality of bits, and compressing the plurality of bits of the at least one bitstream upon transforming the color data associated with each of the plurality of bits.

[0080]

[0086] Aspect 2 is the method of aspect 1, wherein an order of the plurality of bits is arranged by shifting one or more floating-point bits in at least one bitstream.

[0081]

[0087] Example 3 is the method of any of examples 1 and 2, wherein one or more floating-point bits are moved to the beginning of the sequence of the multiple bits or to the end of the sequence of the multiple bits.

[0082]

[0088] Example 4 is a method according to any of examples 1 to 3, wherein the one or more floating-point bits correspond to a red (R) floating-point bit, a green (G) floating-point bit, and a blue (B) floating-point bit.

[0083]

[0089] Example 5 is the method of any of examples 1 to 4, wherein the plurality of bits is compressed based on a predictive compression scheme.

[0084]

[0090] Example 6 is the method of any of examples 1 to 5, wherein the predictive compression scheme is based on spatially neighboring color data of the color data associated with each of the plurality of bits.

[0085]

[0091] Example 7 is the method of any of examples 1 to 6, wherein the predictive compression scheme is associated with at least one of a spatial neighboring predictor or a parallelogram predictor.

[0086]

[0092] Example 8 is a method according to any of examples 1 to 7, wherein the color data is converted from Red (R) Green (G) Blue (B) (RGB) data to Luma (Y) Chrominance Orange (Co) Chrominance Green (Cg) (YCoCg) data.

[0087]

[0093] Example 9 is the method of any of Examples 1 to 8, wherein the color data associated with each of the plurality of bits is transformed based on at least one of a color space transformation or a reversible transformation.

[0088]

[0094] Example 10 is the method of any of examples 1 to 9, wherein the plurality of bits corresponds to a 32-bit high dynamic range (HDR) format or an R11G11B10 format.

[0089]

[0095] Example 11 is the method of any of Examples 1 to 10, further comprising encoding the plurality of bits of the at least one bitstream upon compressing the plurality of bits.

[0090]

[0096] Example 12 is the method of any of examples 1 to 11, wherein the plurality of bits is encoded based on a block fixed length coding (BFLC) process.

[0091]

[0097] Example 13 is the method of any of Examples 1 to 12, wherein the plurality of bits is encoded by appending at least one of a header or metadata to the plurality of bits.

[0092]

[0098] Example 14 is the method of any of Examples 1 to 13, further comprising transmitting at least one bitstream comprising the compressed plurality of bits to a memory.

[0093]

[0099] Example 15 is a method of any of examples 1 to 14, further including receiving at least one bitstream from a memory comprising a plurality of compressed bits, decoding the compressed plurality of bits in the at least one bitstream, restoring the plurality of bits of the at least one bitstream, reconverting color data associated with each of the plurality of bits of the at least one bitstream, rearranging an order of the plurality of bits of the at least one bitstream, and transmitting the at least one bitstream comprising the plurality of bits.

[0094]

[0100] Example 16 is the method of any of examples 1 to 15, wherein the memory is a double data rate (DDR) memory in a graphics processing unit (GPU).

[0095]

[0101] Example 17 is the method of any of Examples 1 to 16, wherein a plurality of bits of at least one bitstream are compressed into one or more data packets.

[0096]

[0102] Example 18 is the method of any of examples 1 to 17, wherein the one or more data packets are double data rate (DDR) packets.

[0097]

[0103] Example 19 is the method of any of Examples 1 to 18, wherein the compression of the plurality of bits is a lossless compression.

[0098]

[0104] Aspect 20 is an apparatus for data processing or graphics processing including at least one processor coupled to a memory and configured to implement a method according to any of aspects 1-19.

[0099]

[0105] Aspect 21 is an apparatus for data processing or graphics processing, comprising means for implementing the method according to any of aspects 1 to 19.

[0100]

[0106] Aspect 22 is a computer-readable medium storing computer-executable code that, when executed by at least one processor, causes the at least one processor to implement a method according to any of aspects 1-19.

Claims

1. 1. A method of data processing, comprising: receiving at least one bitstream including a first plurality of bits associated with color data of a first color channel, a second plurality of bits associated with color data of a second color channel, and a third plurality of bits associated with color data of a third color channel, wherein a number of the first plurality of bits is different from a number of the second plurality of bits and / or a number of the third plurality of bits, and wherein each of the first, second, and third plurality of bits has a respective first position within the at least one bitstream; arranging an order of the plurality of bits of the at least one bitstream such that at least one bit of the first, second, or third plurality of bits corresponds to an updated position within the at least one bitstream relative to a respective first position; and the rearranged bitstream has an equal number of bits of the first, second, and third plurality of bits grouped together in a first portion of the rearranged bitstream and one or more remaining bits of the first, second, and / or third plurality of bits grouped in a second portion of the rearranged bitstream, wherein the number of bits of the first plurality of bits in the second portion is different from the number of bits of the second and / or third plurality of bits in the second portion. transforming the color data associated with the first portion of the rearranged bitstream to decorrelate the color data; compressing the transformed first portion of the rearranged bitstream and the second portion of the rearranged bitstream; A method comprising:

2. The method of claim 1 , wherein the order of the plurality of bits is arranged by shifting one or more floating-point bits of color data in the at least one bitstream.

3. 2. The method of claim 1, wherein the plurality of bits are compressed based on a predictive compression scheme, the predictive compression scheme preferably being either based on spatially neighboring color data of the color data associated with each of the plurality of bits or associated with at least one neighboring predictor.

4. 2. The method of claim 1, wherein the color data is converted from Red (R) Green (G) Blue (B) (RGB) data to Luma (Y) Chrominance Orange (Co) Chrominance Green (Cg) (YCoCg) data.

5. The method of claim 1 , wherein the color data associated with each of the plurality of bits is transformed based on at least one of a color space transformation or a reversible transformation.

6. The method of claim 1 , wherein the plurality of bits corresponds to a 32-bit high dynamic range (HDR) format or an R11G11B10 format.

7. The method of claim 1 , further comprising: encoding the plurality of bits of the at least one bitstream upon compressing the plurality of bits.

8. The method of claim 7 , wherein the plurality of bits are coded based on a block fixed length coding (BFLC) process.

9. The method of claim 7 , wherein the plurality of bits is encoded by appending at least one of a header or metadata to the plurality of bits.

10. The method of claim 1 , further comprising transmitting the at least one bitstream including the compressed plurality of bits to a memory.

11. receiving the at least one bitstream from the memory, the at least one bitstream including the compressed plurality of bits; decoding the compressed bits in the at least one bitstream; recovering the plurality of bits of the at least one bitstream; re-transforming the color data associated with each of the plurality of bits of the at least one bitstream; rearranging the order of the plurality of bits of the at least one bitstream; and transmitting said at least one bitstream comprising said plurality of bits; The method of claim 10 further comprising:

12. The method of claim 1 , wherein the plurality of bits of the at least one bitstream are compressed into one or more data packets.

13. The method of claim 1 , wherein the compression of the plurality of bits is lossless compression.

14. 1. An apparatus for data processing, comprising: means for receiving at least one bitstream including a first plurality of bits associated with color data of a first color channel, a second plurality of bits associated with color data of a second color channel, and a third plurality of bits associated with color data of a third color channel, wherein the number of the first plurality of bits is different from the number of the second plurality of bits and / or the number of the third plurality of bits, and each of the first, second, and third plurality of bits has a respective first position within the at least one bitstream; means for arranging an order of the plurality of bits of the at least one bitstream such that at least one bit of the first, second, or third plurality of bits corresponds to an updated position within the at least one bitstream relative to a respective first position; and the rearranged bitstream has an equal number of bits of the first, second, and third plurality of bits grouped together in a first portion of the rearranged bitstream and one or more remaining bits of the first, second, and / or third plurality of bits grouped in a second portion of the rearranged bitstream, wherein the number of bits of the first plurality of bits in the second portion is different from the number of bits of the second and / or third plurality of bits in the second portion. means for transforming the color data associated with the first portion of the rearranged bitstream to decorrelate the color data; means for compressing the transformed first portion of the rearranged bitstream and the second portion of the rearranged bitstream; An apparatus comprising:

15. 14. A computer readable medium storing computer executable code for processing data, said code, when executed by a processor, causing said processor to perform a method according to any one of claims 1 to 13.

Images