Multi-Carrier Transceiver and Multi-Frequency PLL Systems

Abstract

A multi-carrier transceiver simultaneously receives and transmits wireless communication signals on multiple carriers. A multi-frequency LO signal generation circuit includes a set of integer-N phase-locked loop (PLL) circuits to generate local oscillator (LO) signals for mixers operating at different frequencies. All PLL circuits receive the same reference frequency, but each output a different frequency LO signal at an integer multiple of the reference frequency. Thus, the LO signal frequencies are on an equidistant frequency grid with the granularity of the reference frequency. Spurs are also at multiples of the reference frequency and can be easily filtered. A fractional-N PLL circuit may generate the reference frequency and make the frequency grid adjustable. The multiple PLL circuits in the set output a phase error feedback signal to a phase error correction circuit and receive a phase error control signal that phase-locks the multiple PLL circuits together and mitigates phase noise deviations between them. The PLL circuits operating near the transmitter frequency are not in the phase-locked multiple, so not all PLL circuits are frequency-pulled. For carriers that are not aligned with the LO signal, a complex channel selection filter is used.

Description

[Technical field]

[0001] The present invention relates generally to wireless communication system circuitry, and more particularly to a multi-carrier transceiver and a system for generating local oscillator signals for the multi-carrier transceiver at different frequencies with low phase noise. [Background technology]

[0002] Wireless communication networks, including network nodes and wireless network devices such as mobile phones and smartphones, are prevalent in many parts of the world. These networks continue to grow in capacity and complexity. To accommodate both more users and a wider range of types of devices that can benefit from wireless communication, the technical standards governing the operation of wireless communication networks continue to evolve. The fourth generation of network standards has been deployed (4G, also known as Long Term Evolution or LTE), the fifth generation is in development (5G, also known as New Radio or NR), and the sixth generation (6G) is planned.

[0003] One important aspect of the development of wireless communication networks is the addition of new frequency bands to increase system capacity and data rates. For example, 6G is envisaged to include carrier frequencies in the range of 7-15 GHz. Network equipment therefore requires flexible solutions with a high degree of integration, capable of receiving and transmitting in multiple frequency bands. It would also be advantageous to have integrated circuits capable of receiving and transmitting several simultaneous carriers.

[0004] One way to handle multiple carriers is to process the entire frequency range, for example 7-15 GHz, in a single data converter. In the receiver, this requires a very wideband analog-to-digital converter (ADC), which is difficult to design. Achieving a high dynamic range in the track-and-hold circuit at such high frequencies is also a big challenge. Radio frequency (RF) filters are also required for the different carriers to avoid distortion due to off-carrier signals. It means that the signals are first filtered, amplified separately, and then combined before being processed by the ADC. Such wideband ADCs consume a significant amount of power. In the transmitter, there must be a corresponding wideband digital-to-analog converter (DAC), after which a separate power amplifier chain and filters can process the analog signal. The DAC must have high linearity, handling several carriers with low cross-modulation and intermodulation distortion, and its power consumption is also considerable.

[0005] One benefit of using a wideband converter to process all carriers is that a single clock frequency generated by one oscillator circuit can be used. Therefore, there is no problem of coupling between oscillators operating at different frequencies, which would cause spurious signals. By knowing the potential carrier frequencies, it is also possible to select the clock frequency such that frequency "pulling" problems between the transmitter and nearby (in frequency) oscillators are minimized. However, operating a wideband converter to process the full band incurs significant costs.

[0006] Designs employing narrower band converters are more efficient. In such designs, only the carrier signal is converted, nothing in between. In addition, the signal is converted to baseband so that the track-and-hold circuit can more easily achieve high dynamic range. However, this requires frequency conversion mixers with different local oscillator (LO) frequencies, which in turn requires multiple phase-locked loops (PLLs) with oscillators.

[0007] In addition to the desire to process multiple carriers together, other developments in modern wireless communication networks necessitate the widespread use of PLLs. One such development is the use of spatial diversity and / or spatial multiplexing. Spatial diversity refers to transmitting the same signal over different propagation paths (e.g., different transmit / receive antennas), which increases robustness against fading, co-channel interference, and other deleterious effects of RF signal transmission. Spatial multiplexing also refers to using multiple transmit and receive antennas to transmit different portions of data over different propagation paths using space-time coding to increase data rates. These techniques are collectively referred to as multiple input multiple output, or "MIMO." The key to all MIMO techniques is the deployment of multiple antennas on at least one side, and preferably both sides, of the air interface channel. 4G network standards contemplate two, four, or eight antennas per transceiver, while 5G networks envision up to 128 antennas per transceiver, and this number may be much higher in 6G networks. In highly parallel architectures, each antenna used to transmit or receive RF signals is associated with a dedicated transceiver. Each transceiver requires an LO signal to perform frequency conversion between the carrier frequency and baseband. Phase coherence of the multiple LO signals is important for efficient, low-power processing of received signals and for the transmission of coherent signals from multiple antennas.

[0008] Another advanced feature of modern wireless communication networks that imposes the requirement of multiple PLLs is beamforming, where the directivity of RF transmissions is enhanced and controlled to be "aimed" in a particular direction. This can be achieved by the use of phased array antennas with multiple antenna elements. The relative phase of the transmit signals sent to each antenna element is controlled to create constructive or destructive interference, thus amplifying the signal in some spatial directions and attenuating the signal in other spatial directions, thus controlling the direction in which the beam is transmitted. Similar phase manipulation of signals from antenna elements at the receiving antenna can also result in beamforming the sensitivity of the phased array antenna in receiving signals. In such beamforming systems, the LO signals at each antenna element transceiver must be phase aligned to allow precise control of the phase offset.

[0009] One challenge in multi-PLL design is how to mitigate spurs due to coupling between oscillators. Another significant challenge is how to mitigate pulling between oscillators that are close in frequency and the transmitter. A third challenge is how to achieve low phase noise in many PLLs, as well as scaling power consumption and chip area linearly with the number of PLLs without phase noise improvement. In particular, high frequency noise in the reference frequency signal input to the PLL can propagate to the LO signal that the PLL generates, introducing phase noise that limits performance in all of the applications described above.

[0010] The Background section of this specification is provided to aid those skilled in the art in placing embodiments of the present invention in a technical and operational context to aid in understanding the scope and usefulness thereof. Approaches described in the Background section may be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless expressly identified as such, statements herein are not admitted to be prior art merely by inclusion in the Background section. Summary of the Invention

[0011] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those skilled in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of embodiments of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[0012] The embodiments of the invention described and claimed herein provide an architecture for a transceiver chip with multiple channels for receiving or transmitting multiple carriers. Each channel features an antenna switch connected to an external RF filter, a receive chain, and a transmit chain. The receive chain features a low noise amplifier (LNA), a frequency down-conversion mixer, a filter, and an ADC. The transmit chain features a power amplifier, a frequency up-conversion mixer, a filter, and a DAC. The LO signals to the mixers in different channels are at different frequencies to receive and transmit carriers at different frequencies. Not all channels are necessarily active processing carriers, and some channels may process more than one carrier if they are close in frequency.

[0013] The LO signals are generated on an equidistant frequency grid. To generate these signals, several integer-N PLLs operate at the same reference frequency but with different (integer) division numbers in their feedback paths. To improve phase noise, the multiple PLLs provide phase deviation information to a PLL synchronization circuit and receive a common adjustment signal from the PLL synchronization circuit. PCT Application No. PCT / EP2019 / 086845, filed December 20, 2019, discloses a system and method of phase noise improvement for a system of interconnected PLLs, particularly suitable for digital PLL implementations. PCT Application No. PCT / EP2021 / 058001, filed March 26, 2021, discloses a different approach of phase noise improvement for a system of interconnected PLLs, particularly suitable for analog PLL implementations. Both of these references are assigned to the assignee of the present disclosure and both are incorporated herein by reference in their entirety. Both of these references describe systems of interconnected PLLs, all of which operate at the same oscillator frequency. In accordance with an embodiment of the present invention, similar integration is applied to multiple PLLs operating at different oscillator frequencies. However, because the PLLs operate based on the same reference frequency, the PLLs can still be phase locked together. This also reduces the risk of pull-in between the oscillators via harmonics / subharmonics, which may occur in some cases despite the different fundamental frequencies.

[0014] Spurs at multiples of the frequency grid distance are inevitable due to oscillator pulling. However, their effect on the transceiver system can be mitigated by RF filters that suppress signals outside the desired carrier on both receive and transmit. Coupling can also be reduced by using figure-eight inductors, as disclosed in European Patent Application No. 2,819,131, which is assigned to the assignee of the present disclosure and is incorporated herein by reference in its entirety.

[0015] Frequency pulling of an oscillator by transmitters operating closely in frequency is a well-known phenomenon that occurs as a result of coupling between inductors, through power lines, and through the substrate. Further information on oscillator frequency pulling is provided in Behzad Razavi, "A Study of Injection Locking and Pulling in Oscillators," IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004, pp. 1415-24, the entire disclosure of which is incorporated herein by reference. To reduce such pulling, the oscillator can be operated at multiple frequencies, for example, at twice the LO frequency, with its output divided by two. Even then, coupling from the power amplifier second harmonic may still be present. To mitigate such pulling, the PLL system can make the affected oscillator less susceptible. One remedy is to remove that PLL from the cooperative phase noise mitigation scheme of multiple PLLs. In that case, phase deviations in that oscillator do not affect the remaining phase of the PLL system, and the PLL system remains stable. The cost of this isolation is a slight reduction in phase noise mitigation in the interconnected PLLs due to the loss of energy in one participating oscillator. Another solution is to increase the bandwidth of the differential loop in the affected PLLs to further stabilize the oscillators and cancel the phase modulation.

[0016] In one embodiment, the filters in the receiver and transmitter are complex analog filters, so their passbands do not necessarily need to be centered around baseband DC. This means that even if the carrier is not centered around the LO frequency, it can still be filtered before the ADC or after the DAC.

[0017] In one embodiment, to further increase the flexibility of the system, the common reference frequency of the PLL is generated by a fractional-N PLL with high frequency resolution, which allows fine tuning of the reference frequency and makes the frequency grid adjustable, which can help to obtain the best compromise for all carriers being processed.

[0018] One embodiment relates to a multi-frequency LO signal generation circuit configured to receive a reference signal and generate and output a set of local oscillator (LO) signals. The multi-frequency LO signal generation circuit includes a set of phase-locked loop (PLL) circuits, each configured to receive a frequency input signal at a reference signal frequency and a common tuning signal, and output an LO signal. The LO signal frequency is an integer multiple of the frequency input signal. At least two PLL circuits are configured to output different frequency LO signals. A plurality of PLL circuits in the set of PLL circuits output a phase deviation signal. The multi-frequency LO signal generation circuit also includes a PLL synchronization circuit configured to receive the phase deviation signals from the plurality of PLL circuits and output the common tuning signal. The PLL synchronization circuit is configured to synchronize the operation of the plurality of PLL circuits such that they lock together over a wide bandwidth and mitigate the propagation of high frequency reference signal noise to the LO signal.

[0019] Another embodiment relates to a multi-carrier transceiver for a wireless communication network node or wireless device. The multi-carrier transceiver includes the LO signal generation circuit described above. The multi-carrier transceiver also includes a mixer configured to frequency convert wireless communication signals between baseband and a plurality of RF carrier frequencies. The multi-carrier transceiver further includes a filter configured to suppress signal energy outside of a frequency band around each carrier frequency.

[0020] Yet another embodiment relates to a multi-carrier transceiver integrated circuit (IC) for a wireless communication network node or wireless device. The multi-carrier transceiver IC includes a plurality of channels. Each channel includes an antenna switch connected to an external RF filter, a receive (Rx) chain of circuitry, and a transmit (Tx) chain of circuitry. The Rx chain includes a low noise amplifier, a frequency down-conversion mixer, a filter, and an analog-to-digital converter. The Tx chain includes a power amplifier, a frequency up-conversion mixer, a filter, and a digital-to-analog converter (DAC). The multi-carrier transceiver IC also includes the LO signal generation circuit described above. The LO signals provided to the mixers in the different channels have corresponding different frequencies, and the different channels are configured to process different carrier frequency signals.

[0021] Yet another embodiment relates to a method for generating a set of periodic signals at different frequencies. A set of integer-N PLL circuits is provided. Divider values ​​in at least two PLL circuits of the set are set to different integers to generate at least two LO signals having different frequencies. The frequency of each LO signal is an integer multiple of a reference frequency. A signal at the reference signal frequency and a common adjustment signal are applied to each PLL circuit in the set of PLL circuits. A phase deviation signal is received from each of the multiple PLL circuits in a PLL synchronization circuit. The PLL synchronization circuit outputs the common adjustment signal. The PLL synchronization circuit is configured to synchronize the operation of the multiple PLL circuits such that they lock together over a wide bandwidth and mitigate the propagation of high frequency reference signal noise to the LO signals.

[0022] Yet another embodiment relates to a user equipment (UE) operating in a wireless communication network, the UE including a multi-carrier transceiver as described above and a processing circuit operatively connected to the multi-carrier transceiver and configured to communicate with one or more nodes of the wireless communication network over a radio access network.

[0023] Yet another embodiment relates to a base station operating in a wireless communication network, the base station including a multi-carrier transceiver as described above and processing circuitry operatively connected to the multi-carrier transceiver and configured to communicate with a plurality of user equipments (UEs) over a wireless access network.

[0024] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. [Brief description of the drawings]

[0025] [Figure 1] 1 is a block diagram floor plan of a multi-carrier transceiver IC. [Diagram 2] FIG. 1 is a block diagram of one embodiment of a multi-frequency LO signal generation circuit optimized for digital implementation. [Diagram 3] FIG. 3 is a more detailed block diagram of the embodiment of FIG. 2. [Figure 4] FIG. 1 is a block diagram of one embodiment of a multi-frequency LO signal generation circuit optimized for analog implementation. [Diagram 5] FIG. 5 is a more detailed block diagram of the embodiment of FIG. [Figure 6] FIG. 2 is a block diagram of a transceiver chain. [Figure 7] 4 is a frequency domain graph illustrating an example of a PLL circuit output frequency, a corresponding LO frequency, and a carrier signal. [Figure 8] 1 is a flow diagram of a method for generating a set of periodic signals at different frequencies. [Figure 9] A is a diagram of multi-carrier transmission over the air interface of a wireless communication network, B is a hardware block diagram of a UE of A, and C is a hardware block diagram of a base station of A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] For purposes of brevity and exemplification, the present invention is described primarily by reference to its exemplary embodiments. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be readily apparent to those skilled in the art that the present invention may be practiced without being limited to these specific details. In this description, well-known methods and structures are not described in detail in order not to unnecessarily obscure the present invention.

[0027] An embodiment of the invention is described herein with reference to a base station for the new frequency range 7-15 GHz. The base station is designed to simultaneously process (i.e. transmit or receive signals at) up to four different carrier frequencies, each using digital beamforming. For each antenna signal, each carrier is filtered by a separate RF filter. For example, if there are 64 antenna elements, there are 256 RF filters.

[0028] FIG. 1 shows a representative floor plan of a multi-carrier transceiver IC 10 with multiple transceiver circuits 12 and multi-frequency local oscillator (LO) signal generation circuits 14 implemented on the same chip. Each RF filter is connected to a port of the transceiver circuit 12. If each multi-carrier transceiver IC 10 has 16 transceiver ports as shown, it can handle four antenna elements with four carriers. In the floor plan shown in FIG. 1, the multi-frequency LO signal generation circuit 14, including a phase-locked loop (PLL) circuit for generating the required LO signal, is located in the center of the IC. Those skilled in the art will readily recognize that the circuitry of the multi-carrier transceiver IC 10 can be organized in many different ways, for example, with a different number of transceivers and PLLs located on each multi-carrier transceiver IC 10, with the PLL circuitry of the multi-frequency LO signal generation circuit 14 being distributed among the transceiver circuits 12, etc.

[0029] The multi-frequency LO signal generation circuit 14 generates one or two dedicated LO frequency signals (depending on the frequency plan) for each column of transceivers. The transceivers each receive or transmit one of the carriers. As mentioned above, in another embodiment, the PLL circuits of the multi-frequency LO signal generation circuit can be more distributed. In the extreme case, a local PLL circuit is placed adjacent to each transceiver on the multi-carrier transceiver IC 10. Regardless of how the PLL circuits are distributed, nominally all the PLL circuits (with exceptions described herein) are connected to form a synchronous system.

[0030] The multi-frequency LO signal generating circuit 14 has a single reference frequency input and a set of LO signal outputs. The reference signal (or a different signal, but at the reference signal frequency) is distributed to all PLL circuits in the multi-frequency LO signal generating circuit 14 to synchronize them in frequency and phase. To enable reception and transmission of different carriers, the different LO signals are at different frequencies. However, the LO signal frequencies are on a frequency grid with the granularity of the reference frequency. That is, all PLL circuits in the multi-frequency LO signal generating circuit 14 generate signals at integer multiples of the reference frequency. That is, the PLL circuits all operate with integer N dividers.

[0031] The multi-frequency LO signal generation circuit 14 may be implemented in analog or digital technology. Advantages of a digital PLL circuit include the absence of large area capacitors in the analog loop filter and the possibility of supporting advanced digital algorithms, such as for implementing fast frequency hops. Advantages of an analog PLL circuit, on the other hand, include reduced design complexity and superior phase noise. As an example of a design trade-off, the simplicity of an analog PLL circuit makes it a good choice at very high frequencies or for very low power. However, this choice comes at the expense of the possibility that a digital algorithm may achieve improved performance. Embodiments of the present invention optimized for implementation in both analog and digital technologies are disclosed and claimed herein.

[0032] In either embodiment, the multi-frequency LO signal generation circuit 14 uses a signal at a reference frequency to phase-lock the multiple PLL circuits together. In that case, since the reference signal is at the same frequency, it is possible to compare the phase deviations of different PLL circuits even though the different PLL circuits generate LO signals at different frequencies. Thus, the phases of the different LO signals have a certain relationship when the frequency is divided down to (or sampled at) the reference frequency, when all the PLL circuits in the multiple PLL circuits are phase-locked and stable at various integer multiples of the reference frequency. In that case, phase drift between the PLL circuits can be detected and corrected, even though the PLL circuits are operating to generate different frequency LO signals.

[0033] According to an embodiment of the present invention, the oscillator energies of multiple PLL circuits are combined to obtain a phase noise lower than that of a single PLL circuit, even if the PLL circuits operate at different frequencies. This can be achieved in differential mode or up to the loop bandwidth of the local PLL loop. This represents a fundamental advance in the state of the art compared to multi-core PLL circuits, where the cores must operate at the same frequency to be combined so that low phase noise can be achieved. Thus, an embodiment of the present invention obtains both low phase noise and LO signals with different frequencies as required by multi-carrier transceivers.

[0034] Figures 2 and 4 show the basic structure of the multi-frequency LO signal generation circuit 14 in embodiments optimized for implementation with digital and analog circuits, respectively. The detailed operation of the coordinated phase locking operation for each embodiment is described in more detail below with reference to Figures 3 and 5. Both embodiments include a system that receives a single reference frequency input and outputs multiple LO signals. At least some of the LO signals are at different frequencies, which lie on a frequency grid with the granularity of the reference frequency input. That is, the PLL circuits all employ integer N dividers to generate LO signals that are (different) integer multiples of the reference frequency.

[0035] In both embodiments, multiple PLL circuits are phase-locked together through mutual operation enabled by a PLL synchronization circuit. A simple, high-level diagram of this operation is provided with reference to Figures 2 and 4, and a detailed description of each embodiment is provided with reference to Figures 3 and 5.

[0036] Each of the multiple phase-locked PLL circuits outputs a phase deviation signal to the PLL synchronization circuit. The phase deviation signals are each derived from a phase or phase frequency detector in the PLL circuit and are indicative of a local phase error. The PLL synchronization circuit processes or utilizes the phase deviation signal and outputs a common adjustment signal to all of the PLL circuits. The PLL synchronization circuit synchronizes the operation of the multiple PLL circuits so that they lock together over a wide bandwidth and mitigate the propagation of high frequency reference signal noise to the LO signal.

[0037] FIG. 2 shows an embodiment 20 of the multi-frequency LO signal generation circuit 14 optimized for implementation with a digital PLL circuit. It includes a PLL synchronization circuit 22 and a plurality of phase-locked PLL circuits 24-0, 24-1, ..., 24-n, and in some embodiments, a PLL circuit 26 that is not part of the plurality of PLL circuits 24 because it does not provide a phase deviation signal to the PLL synchronization circuits. In this embodiment 20, all PLL circuits 24, 26 receive a reference signal as a reference frequency input. As will be explained in more detail below, each of the PLL circuits 24, 26 includes two loop filters. Each of the plurality of PLL circuits 24 outputs a phase deviation signal, which in this embodiment 20 is a digital value of a local phase error. The PLL synchronization circuit 22 receives the phase deviation signals, processes them, and in this embodiment 20 averages them. The PLL synchronization circuit 22 outputs a common adjustment signal, which in this embodiment 20 is a digital value of the average phase error of the plurality of PLL circuits 24. Each PLL circuit 24, 26 generates oscillator control inputs from both a common mode loop and a differential mode loop. The common mode loop causes all PLL circuits in the multiple PLL circuits 24 to track the phase of a reference signal, and the differential mode loop minimizes the spread or variation in phase between the LO signal outputs of the PLL circuits 24, 26, which may be at different frequencies. The PLL circuit 26 operates at a frequency close to the transmitter and may be subject to frequency pulling. Therefore, the PLL circuit 26 does not output a phase deviation signal to the PLL synchronization circuit (22), so frequency pulling in the PLL circuit 26 does not propagate to the multiple PLL circuits 24.

[0038] 3 is a detailed diagram illustrating the structure and operation of two of the multiple PLL circuits 24-1, 24-2 in the embodiment 20 of the multi-frequency LO signal generation circuit optimized for implementation by a digital PLL circuit. The two PLL circuits 24-1, 24-2 each receive a reference signal A. The two PLL circuits 24 output their local phase errors as a phase deviation signal B to the PLL synchronization circuit 22. The PLL synchronization circuit 22 calculates the average phase error of the multiple PLL circuits 24 and returns the value to each PLL circuit 24 as a common adjustment signal C.

[0039] Each PLL circuit 24-1, 24-2 comprises a phase detector 28 (which in some PLL architectures may be a phase / frequency detector (PFD)), a common mode loop filter 30, a differential mode loop filter 32, a controlled oscillator (CO) 34, and an integer divider 36. Each PLL circuit 24-1, 24-2 operates conventionally except that it has two loop filters 30, 32, the outputs of which are combined to form the CO 34 control input.

[0040] The CO 34, which may comprise, for example, a digitally controlled oscillator (DCO), generates a periodic output signal LO in response to a CO control input G. n (labeled H in FIG. 3). The frequency of output signal H is divided by a divider circuit 36 ​​by an integer value, which may be a different integer value in the two PLL circuits 24-1, 24-2. Thus, while the output LO signals may have different frequencies, the divided output signal I is at the same frequency (that of reference signal A). Phase detector 28 compares divided output signal I with the reference signal and outputs a phase error signal B indicative of the phase error between the two. Common mode loop filter 30 and differential mode loop filter 32 operate as described further herein and each generate a CO control signal E, F. These CO control signals E, F are combined to generate a CO control input G that controls operation of CO 34 to lock it to a frequency that is an integer multiple of the reference signal A frequency, and is phase-locked to reference signal A.

[0041] In one embodiment, the reference signal A is at a higher frequency than the input to the normal PLL circuit, for example 100 MHz to 4 GHz, to allow for a high bandwidth in the differential mode loop 32. This provides excellent rejection of undesired interactions between the oscillators 34 due to coupling and suppresses uncorrelated noise between the oscillators 34 up to higher frequency offsets. At offset frequencies where the differential mode loop gain is high, the PLL circuits 24-1, 24-2 lock into common mode and then behave as a single PLL circuit (but outputting different frequency LO signals), and the phase noise is improved by 10·log(N) dB compared to a single PLL circuit, where N is the number of PLL circuits 24-1, 24-2 involved.

[0042] As described above, the phase detector 28 in each PLL circuit 24-1, 24-2 compares the divided output signal I of that PLL circuit with the reference signal A and outputs a local phase error as a phase deviation signal B. One comparison is performed at each reference signal period, so that if the reference signal A is, for example, 200 MHz, a data stream of 200 million samples per second is generated by each phase detector 28. If bit errors are avoided by representing the phase deviation signal B in a digital form, which is common in digital PLL circuits 24, data can be transported across the IC without signal degradation. For further signal integrity, the phase deviation signal B and the common adjustment signal C (average phase error) communicated to the PLL circuit 24 can be transmitted with a parity bit or other error detection / correction as known in the art, as long as the processing does not introduce significant delays. The phase deviation signal B from the phase detector 28 in each of the multiple PLL circuits 24-1, 24-2 is communicated to the PLL synchronization circuit 22, which calculates the average phase error and outputs it as the common adjustment signal C. This calculation is simple to implement and can be performed with low power. For example, the phase error signals B from all participating phase detectors 28 are summed and then the result is divided by the number (N) of participating PLL circuits 24-1, 24-2. N is equal to a power of 2, e.g., N=2. MIf , then the division is particularly simple and is performed by shifting M bit positions to the right.

[0043] The common adjustment signal C is used by both the common mode loop filter 30 and the differential mode loop filter 32 in each PLL circuit 24-1, 24-2. The common mode loop filter 30 operates using only the common adjustment signal C as an input. The common mode loop filter 30 includes an integrator to achieve high low frequency gain. The common mode loop filter 30 makes the average phase of all of the multiple PLL circuit 24 outputs closely track the phase of the reference signal A. If this is implemented as a digital filter, the integrator can be made ideal with a pole at DC. The common mode loop filter 30 also has more transmission poles and zeros to shape the response and ensure stability. In each of the multiple PLL circuits 24, the output E of the common mode loop filter 30 is input (by summing) to a digitally controlled oscillator (DCO) 34. The output of the DCO 34 is then fed back to the phase detector 28 through an integer N divider 36 to close the feedback loop. The bandwidth of this loop is chosen to be fairly low so that the reference noise contribution at the output is minimized. This occurs by setting the bandwidth equal to the offset frequency at which the equivalent reference noise at the output is equal to the phase noise of the synthesis oscillator 34, i.e., the noise of a single DCO 34 minus 10·log(N), where N is the number of DCOs 34 in the multiple PLL circuits 24. The common mode loop filter 30 ensures that the frequency accuracy of the reference signal A is achieved by all output signals H. However, the reference noise is not tracked to frequencies higher than necessary, and the common mode loop filter bandwidth is only wide enough for the DCOs 34 to provide sufficiently low common mode phase noise above the common mode loop bandwidth.

[0044] The differential mode loop filter 32 operates using the difference D between the average phase error C (common adjustment signal) and the local phase error B (phase deviation signal) of the PLL circuit. It pulls the phase of each PLL circuit to match the common phase of the multiple PLL circuits 24. The differential mode loop filter 32 is designed to have as wide a bandwidth as possible. A common practice for the PLL bandwidth is not to exceed about 1 / 10 of the reference frequency, which is a reasonable guideline. For example, if the reference frequency is 200 MHz, the bandwidth of the differential mode loop is about 20 MHz. Up to that frequency, the phase difference between the controlled oscillators 34 in the different PLL circuits 24-1, 24-2 is suppressed. In particular, their uncorrelated phase noise is suppressed.

[0045] Thus, the two loop filters 30, 32 work together to cause all of the multiple PLL circuits 24 to track the phase of a common reference signal A. The common mode loop filter 30 causes the multiple PLL circuits 24 to track the reference, but there is a spread or variation in phase between the outputs of the PLL circuits 24-1, 24-2. The differential mode loop filter 34 operates to minimize that spread, effectively causing all of the multiple PLL circuits 24 to operate as a single PLL circuit in terms of phase, but with different frequency LO signal outputs.

[0046] As described with respect to FIG. 2, the PLL circuit k26 may operate at a frequency close to the frequency of the transmitter. To prevent the frequency pulling of the PLL circuit k26 from affecting the entire system, the PLL circuit k26 does not provide its phase deviation signal to the PLL synchronization circuit (22). For example, the PLL circuit k26 may simply not output a phase deviation signal to the PLL synchronization circuit 22. Alternatively, the PLL synchronization circuit 22 excludes the phase deviation signal from the PLL circuit k26 when calculating the average phase deviation that is output as a common adjustment signal. Of course, when excluding one or more PLL circuits from this calculation, the PLL synchronization circuit 22 must adjust its divisor to the number of PLL circuits 24 for which the average is calculated. Other mitigation measures for the PLL circuit k26 may include increasing its loop bandwidth and / or operating the PLL circuit k26 at a different frequency (e.g., 2×) and dividing its output (e.g., by 2) to obtain the desired frequency LO signal.

[0047] 4 illustrates an embodiment 40 of the multi-frequency LO signal generation circuit 14 optimized for implementation with an analog PLL circuit. It includes a PLL synchronization circuit 42 and a plurality of secondary PLL circuits 48-0, 48-1, ..., 48-n, and in some embodiments, a PLL circuit 49 that is not part of the plurality 48 because it does not provide a phase deviation signal to the PLL synchronization circuit 42. In this embodiment 40, the PLL synchronization circuit 42 includes a primary PLL circuit 44 and a phase noise correction loop filter 46. Note that in this embodiment 40, the plurality of secondary PLL circuits 48 and the independent PLL circuit 49 do not receive a reference signal, but rather a frequency input signal generated by the primary PLL circuit 44 in the PLL synchronization circuit 42. This signal is a divided output signal of the primary PLL circuit 44, which is at the reference signal frequency.

[0048] As will be described in more detail below, each of the plurality of secondary PLL circuits 48 includes two charge pumps. One charge pump operates conventionally, converting signal pulses from the phase frequency detector into current pulses that are passed to a loop filter. The second charge pump operates similarly, but inverts the current polarity and outputs it as a phase deviation signal to the PLL synchronization circuit 42. In this embodiment 40, the phase deviation signals are summed in the PLL synchronization circuit 42 by connecting the individual phase deviation signals to a single node, thus summing their individual currents into a composite current signal. Those skilled in the art will readily recognize that the individual phase deviation signals may be connected to a composite phase deviation signal at the output of each secondary PLL circuit 48, with the composite phase deviation signal being routed to the PLL synchronization circuit 42. The composite current of the phase deviation signals is input to a phase noise correction loop filter 46, which generates a control input for a controlled oscillator in the primary PLL circuit 44. The PLL synchronization circuit 42 outputs a common adjustment signal to all of the PLL circuits 48, 49, which is the control input to their oscillators in this embodiment 40. The PLL circuit 49 operates at a frequency close to the transmitter and is subject to frequency pulling. Thus, frequency pulling in the PLL circuit 49 does not propagate to the multiple PLL circuits 48 because the PLL circuit 49 is not part of the multiple secondary PLL circuits 48 that output a phase deviation signal to the PLL synchronization circuit 42.

[0049] 5 is a detailed diagram illustrating the structure and operation of an embodiment of a multi-frequency LO signal generation circuit 40 optimized for analog implementation. FIG 5 shows a PLL synchronization circuit 42, multiple second-order PLL circuits 48, and a common-mode (CM) voltage control circuit. The PLL synchronization circuit 42 includes a first-order PLL circuit 44 and a phase noise cancellation loop filter (PNC-LF) 46.

[0050] Those skilled in the art will note at least two structural differences between the PLL circuit of FIG. 5 and conventional PLL circuits. First, the voltage controlled oscillator (VCO) has both a primary control input and an auxiliary control input. Second, the plurality of secondary PLL circuits 48 includes both a first charge pump (CP1) and a second charge pump (CP2). The structure and operation of both features are described herein.

[0051] The primary PLL circuit 44 operates in a generally conventional manner (other than the auxiliary control input to the VCO, described below). It receives a periodic reference signal (ref). The output of the VCO is divided by an integer divider circuit (DIV) to provide a divided periodic signal at the reference signal frequency. The phase and frequency of the divided output signal are compared to the phase and frequency of the reference signal in a phase / frequency detector (PFD), which alternatively outputs a charge-up or charge-down pulse in response to one of the inputs leading or lagging the other. A charge pump (CP) generates a positive or negative current in response to the CU / CD pulses. A loop filter (LF) converts the CP output current to a voltage signal, which is output as the primary VCO control input. In response to a change in the primary VCO control input, the VCO increases or decreases the frequency of its LO signal output so that it remains an integer multiple of the reference signal. Conventional analog charge pump PLL circuits are well known in the art and exhibit proven performance and robustness.

[0052] In this embodiment of the multi-frequency LO signal generating circuit 40, the primary PLL circuit 44 outputs its primary VCO control input. This signal is output by the PLL synchronization circuit 42 as a common adjustment signal to the multiple secondary PLL circuits 48. In each of the secondary PLL circuits 48-0, 48-1, 48-2, the common adjustment signal is the primary VCO control input. Thus, the multiple PLL circuits 48 track the phase of the primary PLL circuit 44. However, in a real implementation, there will inevitably be some mismatch between the oscillators, resulting in phase drift. This is compensated by the secondary PLL circuit 48 control loop, which causes each secondary PLL circuit 48 to lock the phase of the LO signal to the phase of the primary PLL circuit 44.

[0053] The bandwidth of the primary PLL circuit 44 is preferably set for best phase noise performance. A larger bandwidth causes an increase in output noise from the reference signal and in-band PLL noise sources, and a lower bandwidth causes an increase in output noise from the VCO. Thus, there is an optimum bandwidth for phase noise. This bandwidth is usually quite limited, and a multi-frequency LO generation circuit 40 in which all loops are limited to this bandwidth is not effective in suppressing detrimental interactions due to coupling between oscillators. To compensate, the control loops in the multiple secondary PLL circuits 48 can have a larger bandwidth than the primary PLL circuit 44, and to reduce the effect of reference signal noise in the increased bandwidth, they are configured to lock to the phase of the primary PLL circuit 44 rather than locking directly to the phase of the reference signal.

[0054] Each of the multiple secondary PLL circuits 48 includes a VCO configured to generate an LO signal at an integer multiple of its frequency input signal that matches the frequency of the reference signal. Each secondary PLL circuit 48 also includes an integer divider circuit configured to generate a local divided LO signal. The divider value may be different from the divider values ​​of the primary PLL circuit 44 and the other secondary PLL circuits 48. In the PFD, each secondary PLL circuit 48 compares its local divided LO signal to the divided output signal received from the primary PLL circuit 44. According to the well-known operation of analog PLL circuits, if one of these PFD inputs leads or lags the other in phase, the PFD alternatively outputs a charge-up (CU) or charge-down (CD) pulse whose length is proportional to the phase mismatch of the PFD input signals. The first charge pump (CP1) generates a positive or negative current in response to the CU / CD pulse, and the loop filter (LF) converts the CP current to a VCO control voltage. This control voltage is the auxiliary VCO control input.

[0055] Both the common adjustment signal received from the PLL synchronization circuit 42 and the control loop of each secondary PLL circuit 48 drive each secondary PLL circuit 48 to track the phase of the primary PLL circuit 44 .

[0056] The bandwidth of the phase control loop in the secondary PLL circuit 48 can be much higher than the bandwidth of the control loop of the primary PLL circuit 44 because there is no reference signal. Instead of a reference signal, the divided LO signal of the primary PLL circuit 44, the frequency input signal, is used, which has less high frequency phase noise than the reference signal due to the low pass filtering of the primary PLL circuit 44 loop.

[0057] The VCO of the primary PLL circuit 44 may introduce a phase deviation, referred to herein as phase noise. This is sensed by a secondary PLL circuit 48, which includes a second charge pump (CP2) for generating a phase deviation signal, which in this embodiment 40 is a current signal. Each secondary PLL circuit 48 that is locked to the primary PLL circuit 44 typically drives its VCO to track the primary PLL circuit 44, i.e., to propagate the phase noise and cancel the phase noise, so that the phase deviation current output by CP2 has the opposite polarity to the current output by CP1. The phase deviation current is also scaled down by a factor related to the number of secondary PLL circuits 48, in one embodiment. For example, if there are N secondary PLL circuits 48 in the multiple secondary PLL circuits 48, each may scale its phase deviation CP2 current by 1 / N (compared to the CP1 current) to provide an effective current to counter the deviation in the VCO of the primary PLL circuit 44, resulting in the same loop bandwidth as in the case of the secondary PLL circuit 48 VCO deviation (assuming that the loop filter in the secondary PLL circuit 48 has the same impedance as the PNC-LF 46 and the relative tuning sensitivity of the second control input is the same in the primary PLL circuit 44 VCO as in the case of the secondary PLL circuit 48 VCO).

[0058] The phase deviation currents are summed (e.g., by connecting all CP2 outputs) and the resulting composite phase deviation current is input to a phase noise correction loop filter (PNC-LF) 46. The PNC-LF 46 converts the composite phase deviation current to a voltage and outputs it to the primary PLL circuit 44 for use as an auxiliary VCO control input. In this way, the phase noise caused by the VCO of the primary PLL circuit 44 is detected and cancelled by the secondary PLL circuit 48.

[0059] As an alternative to each secondary PLL circuit 48 scaling its phase deviation current (e.g., by 1 / N), the PNC-LF 46 may be scaled in impedance by 1 / N. Preferably, the loop gain of the phase deviation loop is the same as the phase control loop of the secondary PLL circuit 48. If N paths operate in parallel, then either the CP2 current or the PNC-LF 46 impedance should be scaled by 1 / N compared to the CP1 current and secondary PLL circuit 48 LF impedance, respectively. Alternatively, both may be scaled by various combinations of values ​​resulting in an overall scaling of 1 / N. The appropriate scaling to achieve the desired loop gain and which circuits to scale are implementation details that may be derived by one of ordinary skill in the art for a given implementation without undue experimentation, given the teachings of this disclosure.

[0060] A common mode (CM) voltage control circuit monitors the auxiliary VCO control voltages, averages them, and compares the average to a CM target value or interval. This prevents the secondary PLL auxiliary VCO control input level from going out of range, which could cause the phase control loop to stop operating properly. Details of the CM voltage control circuit can be found in the above-incorporated PCT patent application PCT / EP2021 / 058001.

[0061] As mentioned above, if a PLL circuit is at risk of frequency pulling by a nearby transmitter circuit (in frequency), the PLL circuit may be removed from the multiple PLL circuits 48 that jointly participate in phase noise mitigation. In particular, in the embodiment 40 of FIG. 4, the PLL circuit k 49 does not output a correction current from CP2 to the PHC-LF 46. For example, the CP2 current is simply turned off. In that case, pulling in the affected PLL circuit k 49 does not affect the primary PLL circuit 44 phase, which prevents pulling of the entire system. It should be noted that the CP2 currents output by the remaining secondary PLL circuits 48 should be increased to maintain the same total CP2 current in order to keep the phase noise correction transfer function of the secondary PLL circuits 48 close to optimal. For example, if there are four secondary PLL circuits 48 and one CP2 output is turned off, the CP2 currents output by each remaining PLL circuit should be increased by a factor of 4 / 3.

[0062] Other mitigation measures for the PLL circuit k49 may include increasing its loop bandwidth and / or operating the PLL circuit k49 at a different frequency (e.g., 2×) and dividing its output (e.g., by 2) to obtain the desired frequency LO signal.

[0063] In one embodiment, to increase the flexibility of the system and allow a greater variety of frequency grid plans to match the LO signal frequency with the carriers desired to be processed, the reference frequency input is generated by a high-resolution fractional-N PLL circuit. The output of this PLL circuit can be tuned to a particular desired reference frequency, and all LO signals are generated as integer multiples of this reference frequency. In a system with 64 antenna elements and 4 carriers, as an example, there may be 16 multi-carrier transceiver ICs with 4 PLLs in each, i.e., a total of 64 integer-N PLLs in the system. Thus, the complexity and power consumption of a single fractional-N PLL does not significantly affect the complexity and power consumption of the complete system. However, the flexibility gained can be considerable, allowing a much better match of the LO signal to the carriers to be processed.

[0064] However, even with a programmable reference frequency, it is inevitable that some carriers will not be centered on the available LO frequencies. In that case, for more accurate analog channel filtering, a complex bandpass filter is used.

[0065] FIG. 6 shows an example of a transceiver chain using a single frequency conversion and complex mixer stage. Signals to and from antenna element 81 are externally RF filtered 82. An antenna switch 83 (e.g., a duplexer, a surface acoustic wave (SAW) filter, etc.) switches between the Tx and Rx functions. In both chains, a frequency conversion mixer 86 mixes the Rx or baseband signal, respectively, with a quadrature LO signal. Depending on the relationship between the carrier frequency and the LO signal, the circuit can be operated as a homodyne or low IF transceiver. In some cases where the offset frequency is very low, it becomes a floating boundary between the two. A complex channel selection filter 87 is realized using known techniques, such as using two coupled low pass filters. The channel can then be filtered accurately but not centered on the LO frequency. This reduces the requirements of the data converter. The DAC 88 and ADC 89 must be able to process at least the frequency range of the carrier signal, and in practice a wider range to handle aliasing, since the analog filters have limited suppression. To support transmitter predistortion, the channel filter at the Tx may have to use a wider bandwidth, covering adjacent channels as well, in which case the DAC also requires a higher bandwidth.

[0066] Although FIG. 6 shows a single conversion stage, embodiments of the present invention are not limited to this implementation. In one embodiment (not shown), a sliding IF technique is used, and the LO signal is derived from a single oscillator. In another embodiment (not shown), a switch is introduced, and the LO signals in different mixer stages are provided by different PLL circuits. Although this embodiment increases cost and complexity due to high frequency routing and switches, it provides more flexibility to cover more carrier frequencies with fewer PLL circuits.

[0067] In some embodiments, in FIG. nThe periodic signal output by the PLL circuit 24, 48, denoted as , is frequency multiplied or divided before being applied to the mixer. For example, the PLL circuit 24, 48 may generate, for example, twice the desired LO frequency and its output is divided by two.

[0068] Figure 7 is a frequency graph showing an example of such an embodiment. In this example, the reference frequency is 2 GHz, and the four PLL circuits have division numbers 8, 11, 12, and 14. These PLL circuits generate output signals at 16, 22, 24, and 28 GHz. These are divided by 2 to obtain the desired LO frequencies of 8, 11, 12, and 14 GHz. These are well matched to carriers centered at 7.7, 10.8, and 14.3 GHz.

[0069] 8 shows steps in a method 100 for generating a set of periodic LO signals at different frequencies. A set of integer-N PLL circuits 24, 26, 44, 48, 49 is provided (block 101). Divider values ​​in at least two PLL circuits 24, 26, 44, 48, 49 of the set are set to different integers to generate at least two LO signals with different frequencies (block 102). The frequency of each LO signal is an integer multiple of a reference frequency. A frequency signal at the reference signal frequency is applied to each of the PLL circuits 24, 26, 44, 48, 49 in the set of PLL circuits 24, 26, 44, 48, 49 (block 103). A phase deviation signal is received from each of the multiple PLL circuits 24, 48 in the PLL synchronization circuit 22, 42 (block 104). The PLL synchronization circuit 22, 42 outputs a common adjustment signal (block 105) to each PLL circuit 24, 26, 44, 48, 49. The operation of the multiple PLL circuits 24, 48 is synchronized (block 106) so that they lock together over a wide bandwidth and mitigate the propagation of high frequency reference signal noise to the LO signal.

[0070] 9A is a diagram of transmissions on multiple carriers 130a, 130b over the air interface of a wireless communication network. A user equipment (UE) 110, such as a smartphone, receives and transmits modulated radio frequency (RF) signals on two carriers 130a, 130b to and from a base station 20, such as an LTE eNB or NR gNB. The RF signals 130a, 130b may be, for example, in the frequency range 7-15 GHz. Although only two RF signals 130a, 130b are shown, in general, transmissions may occur on multiple carriers (and other UEs (not shown) may communicate on different carriers). In each of the UE 110 and the base station 120, a multi-carrier transceiver integrated circuit (IC) system receives and transmits the RF signals. These multi-carrier transceiver systems require multiple phase-locked local oscillator (LO) signals at different frequencies for accurate frequency conversion. In addition, one or both of the UE 110 and the base station 120 may implement beamforming, where the directivity of a Tx or Rx antenna beam is increased and controlled, such as by controlling the phase of multiple antenna elements in a phased array antenna. The UE 110 and the base station 120 may also implement MIMO techniques, such as spatial diversity and / or spatial multiplexing.

[0071] Figure 9B is a block diagram of the UE 110 of Figure 9A. The term UE as used herein may refer to a user-operated telephone terminal, a machine-to-machine (M2M) device, a machine-type communication (MTC) device, a narrowband Internet of Things (NB-IoT) device (especially a UE implementing the 3GPP standard for NB-IoT), and the like. The UE 10 may also be referred to as a wireless device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal, and unless the context dictates otherwise, use of any of these terms is intended to include device-to-device (D2D) UEs or devices, machine-type devices or devices capable of machine-to-machine communication, sensors with wireless network devices, wireless-enabled table computers, mobile terminals, smartphones, laptop embedded equipment (LEE), laptop mounted equipment (LME), USB dongles, wireless customer premises equipment (CPE), and the like.

[0072] The UE 110 transmits and receives RF signals on multiple carriers via at least one antenna 113, which may be internal or external, as indicated by the dashed line. The RF signals are generated and received by one or more multi-carrier transceiver circuits 112. The multi-carrier transceiver circuit 112 includes multi-frequency LO signal generation circuits 14, 20, 40 according to an embodiment of the present invention configured to generate multiple phase-locked LO signals at different frequencies. The multi-carrier transceiver circuit 112, as well as other components of the UE 110, are controlled by a processing circuit 114. A memory 116 operatively connected to the processing circuit 114 stores software in the form of computer instructions that operate to cause the processing circuit 114 to perform various procedures. The user interface 118 may include output devices, such as a display and speaker (and / or a wired or wireless connection to an audio device such as an earphone), and / or input devices, such as buttons, a keypad, a touch screen, etc. As indicated by the dashed line, the user interface 118 may not be present in all UEs 110; for example, a UE 110 designed for machine type communication (MTC), such as an Internet of Things (IoT) device, may perform dedicated functions such as sensing / measurement, monitoring, meter reading, etc., and may not have user interface 118 features.

[0073] Figure 9C is a block diagram of the base station 120 of Figure 9A. The base station 120, known in various network generations as a Radio Base Station (RBS), base transceiver station (BTS), Node B (NB), enhanced Node B (eNB), next generation Node B (gNB), etc., is a node of a wireless communication network that implements a Radio Access Network (RAN) in a defined geographic area called a cell by providing radio transceivers for communicating wirelessly with multiple UEs 110.

[0074] The base station 120 transmits and receives RF signals on multiple carriers via multiple antennas 123. As shown by the dashed lines, the antennas 123 may be located remotely from the base station 120, such as on a tower or building. The RF signals are generated and received by one or more multi-carrier transceiver circuits 122. The multi-carrier transceiver circuit 122 includes a multi-frequency LO signal generation circuit according to an embodiment of the present invention configured to generate multiple phase-locked LO signals at different frequencies. The multi-carrier transceiver circuit 122, as well as other components of the base station 120, are controlled by a processing circuit 124. A memory 126 operably connected to the processing circuit 124 stores instructions that operate to cause the processing circuit 124 to perform various procedures. Although the memory 126 is shown as being separate from the processing circuit 124, those skilled in the art will understand that the processing circuit 124 includes internal memory, such as a cache memory or a register file. Those skilled in the art will further appreciate that virtualization techniques enable some functions nominally performed by processing circuitry 124 to actually be performed by other hardware, possibly located remotely (e.g., in a data center in the so-called "cloud"). Communications circuitry 128 provides one or more communications links to one or more other network nodes to carry communications to and from UE 110, other network nodes, or other networks, such as a telephone network or the Internet.

[0075] In all embodiments, the processing circuitry 114, 124 may include any sequential state machine that operates to execute machine instructions stored in memory 116, 126 as a machine-readable computer program, such as one or more hardware-implemented state machines (e.g., in discrete logic, an FPGA, an ASIC, etc.), programmable logic together with appropriate firmware, one or more built-in, general-purpose processors, such as a microprocessor or digital signal processor (DSP) together with appropriate software, or any combination of the above.

[0076] In all embodiments, memory 116, 126 may include any non-transitory machine-readable medium known in the art or that may be developed, including, but not limited to, magnetic media (e.g., floppy disks, hard disk drives, etc.), optical media (e.g., CD-ROMs, DVD-ROMs, etc.), solid-state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, flash memory, solid-state disks, etc.), and the like.

[0077] In all embodiments, the multi-carrier transceiver circuitry 112, 122 operates to communicate with one or more other transceivers over a radio access network (RAN) according to one or more communication protocols known or to be developed in the art, such as IEEE802.xx, CDMA, WCDMA, GSM, LTE, UTRAN, WiMax, NB-IoT, etc. The multi-carrier transceiver circuitry 112, 122 implements transmitter and receiver functions (e.g., frequency allocation, etc.) appropriate for the RAN link. The transmitter and receiver functions may share circuit components and / or software or, alternatively, may be implemented separately.

[0078] In all embodiments, communications circuitry 128 may include receiver and transmitter interfaces used to communicate with one or more other nodes over a communications network according to one or more communications protocols known in the art or that may be developed, such as Ethernet, TCP / IP, SONET, ATM, IMS, SIP, etc. Communications circuitry 28 implements receiver and transmitter functions appropriate for a communications network link (e.g., optical, electrical, etc.). The transmitter and receiver functions may share circuit components and / or software or, alternatively, may be implemented separately.

[0079] Those skilled in the art will recognize that the embodiments herein further include corresponding computer programs.

[0080] The computer program comprises instructions which, when executed on at least one processor of the apparatus, cause the apparatus to perform any of the respective operations described above. The computer program may in this regard comprise one or more code modules corresponding to the means or units described above.

[0081] Embodiments further include a carrier containing such a computer program, which may comprise one of an electronic signal, an optical signal, a radio signal, or a computer readable storage medium.

[0082] In this regard, embodiments herein also include a computer program product comprising instructions stored on a non-transitory computer-readable (storage or recording) medium and which, when executed by a processor of the device, causes the device to perform as described above.

[0083] Embodiments further include a computer program product comprising program code portions for performing any of the steps of the embodiments herein when the computer program product is executed by a computing device, the computer program product may be stored on a computer readable recording medium.

[0084] The embodiments of the present invention offer many advantages over prior art PLL circuits and transceivers. By restricting the LO signal frequency to a grid with the granularity of the reference frequency, the baseband operation of all PLL circuits is compatible and multiple PLL circuit oscillators can share energy to cooperatively mitigate phase noise. In some embodiments, the frequency grid is programmable through the use of a fractional-N PLL circuit to generate the reference frequency signal. Spurs in the LO signal occur at well-known large frequency offsets (integer numbers of the reference frequency) and therefore their effects can be mitigated by RF filters in the transceiver. PLL instability due to oscillator coupling is suppressed. Oscillators at risk of frequency pulling by the transmitter can be isolated from the multiple PLL circuits involved in phase noise mitigation, so that pulling does not affect the entire system. These PLL circuits can be further made immune to pulling by increasing their loop bandwidth and / or operating them at multiples of the desired frequency combined with a divider at their output. The embodiments of the present invention allow the ADC and DAC to operate at lower signal frequencies compared to solutions that are narrowband and cover the full frequency range without frequency conversion, and these blocks are crucial for transceiver power consumption and dynamic range. To provide flexibility in carrier frequency, the carrier is offset from the LO frequency grid by digital up / down conversion of the signal to and from the data converter. In that case, in the analog part, a complex channel selection filter is used. The multi-frequency LO signal generation system supports different frequency plans with both single and double frequency conversion in the transceiver. In some embodiments, the frequency plan also employs a frequency multiplier or divider after the PLL circuit to generate the LO signal applied to the mixer.

[0085] In general, all terms used herein should be interpreted according to the ordinary meaning of the term in the relevant technical field, unless a different meaning is clearly given and / or implied from the context in which the term is used. All references to a / an / the element, apparatus, component, means, step, etc. should be openly interpreted as referring to at least one instance of the element, apparatus, component, means, step, etc., unless otherwise specified. The steps of the methods disclosed herein need not be performed in the strict order disclosed, unless a step is explicitly described as following or preceding another step, and / or it is implicit that a step must follow or precede another step. Any feature of the embodiments disclosed herein may be applied to any other embodiment, whenever appropriate. Similarly, the advantages of any of the embodiments may apply to any other embodiment, and vice versa. Other objects, features, and advantages of the enclosed embodiments will become apparent from the description thereof.

[0086] The term unit may have its conventional meaning in the field of electronics, electrical devices, and / or electronic devices, and may include, for example, electrical and / or electronic circuits, devices, modules, processors, memories, logical solid state and / or discrete devices, computer programs or instructions, etc., for performing a respective task, procedure, computation, output, and / or display function, such as those described herein. As used herein, the term "configured to" means set up, organized, adapted, or configured to operate in a particular manner, and this term is synonymous with "designed to." As used herein, the term "substantially" means nearly or essentially, but not necessarily completely, and this term encompasses and takes into account mechanical or component value tolerances, measurement errors, random variations, and similar sources of inaccuracy.

[0087] Some of the embodiments contemplated herein are more fully described with reference to the accompanying drawings. However, other embodiments are included within the scope of the subject matter disclosed herein. The subject matter disclosed should not be construed as being limited to only the embodiments described herein, but rather, these embodiments are provided as examples to convey the scope of the subject matter to those skilled in the art.

Claims

1. A multi-frequency local oscillator (LO) signal generation circuit (14, 20) configured to receive a periodic reference signal and generate and output a set of LO signals, a set of phase-locked loop (PLL) circuits (24, 26) including a plurality of PLL circuits (24), each PLL circuit in the set of PLL circuits configured to receive the reference signal and a common adjustment signal and output an LO signal, the common adjustment signal indicative of an average phase error of the plurality of PLL circuits (24), the average phase error being an average of local phase errors at each PLL circuit of the plurality of PLL circuits (24), the local phase error being a phase error between the LO signal and the reference signal at each PLL circuit of the plurality of PLL circuits (24), a frequency of the LO signal being an integer multiple of the frequency of the reference signal, at least two PLL circuits (24, 26) of the set of PLL circuits configured to output LO signals of different frequencies, each PLL circuit of the plurality of PLL circuits (24) outputting a phase deviation signal, the phase deviation signal being indicative of the local phase error; a set of phase-locked loop (PLL) circuits (24, 26); a PLL synchronization circuit (22) configured to receive the phase deviation signals from the plurality of PLL circuits (24) and to output the common adjustment signal to each PLL circuit in the set of PLL circuits to synchronize operation of the plurality of PLL circuits (24); A multi-frequency LO signal generation circuit (14, 20) comprising:

2. one or more integer multipliers or integer dividers connected to the PLL circuits in the set of PLL circuits and configured to multiply or divide the frequency of the LO signal by an integer value; The LO signal generation circuit (14, 20) of claim 1 further comprising:

3. 3. The LO signal generating circuit (14, 20) of claim 1 or 2, wherein a PLL circuit (26) in the set of PLL circuits (24, 26) is not in the plurality of PLL circuits (24) and does not output a phase deviation signal to the PLL synchronization circuit (22).

4. The PLL synchronization circuit (22) receiving the phase deviation signals from the plurality of PLL circuits (24); calculating the average phase error of the plurality of PLL circuits (24); outputting the average phase error of the plurality of PLL circuits (24) as the common adjustment signal to each of the PLL circuits (24, 26) in the set of PLL circuits; a phase error averaging circuit configured to perform the following, and each PLL circuit (24) among the plurality of PLL circuits (24) a common mode loop filter configured to generate a common mode oscillator control signal based on the average phase error of the plurality of PLL circuits (24); a differential mode loop filter configured to generate a differential mode oscillator control signal based on a difference between a local phase error signal of the PLL circuit (24) and the average phase error of the plurality of PLL circuits (24); a summing circuit configured to output the sum of the common mode oscillator control signal and the differential mode oscillator control signal to a controlled oscillator; The LO signal generating circuit (20) of any one of claims 1 to 3, comprising:

5. 5. The LO signal generation circuit (20) of claim 4, wherein the common adjustment signal output from the PLL synchronization circuit (22) is digital, and for each PLL circuit (24) in the plurality of PLL circuits (24), the phase deviation signal, the common mode oscillator control signal, and the differential mode oscillator control signal are digital.

6. A multi-frequency local oscillator (LO) signal generation circuit (40) configured to receive a periodic reference signal and generate and output a set of LO signals, the multi-frequency LO signal generation circuit (40) comprising: a set of phase-locked loop (PLL) circuits (44, 48, 49) including a plurality of PLL circuits (48), wherein a frequency of the LO signal is an integer multiple of a frequency of the reference signal, and at least two PLL circuits (44, 48, 49) of the set of PLL circuits are configured to output LO signals of different frequencies, and each PLL circuit of the plurality of PLL circuits (48) outputs a phase deviation signal, the phase deviation signal being indicative of a local phase error; a PLL synchronization circuit (42) configured to receive the phase deviation signal from the plurality of PLL circuits (48) and to synchronize operation of the plurality of PLL circuits (48); Equipped with the set of PLL circuits further comprising a primary PLL circuit (44) that is not in the plurality of PLL circuits (48); each PLL circuit (48) in the plurality of PLL circuits is a second-order PLL circuit (48); a frequency input signal to the primary PLL circuit (44) is the reference signal; a frequency input signal to each of the secondary PLL circuits (48) being a divided LO signal of the primary PLL circuit (44) at the frequency of the reference signal; the PLL synchronization circuit (42) comprises the first-order PLL circuit (44) and a phase noise correction loop filter (46); the phase noise correction loop filter receives a sum of the phase deviation signals from the plurality of PLL circuits (48), each phase deviation signal including a correction current based on a comparison of the phase of a divided output signal of a secondary PLL circuit (48) with the divided LO signal of the primary PLL circuit (44); the primary PLL circuit comprises a controlled oscillator adapted to receive a primary control input signal based on a comparison of the phase of the divided LO signal of the primary PLL circuit (44) with the reference signal and an auxiliary control input signal from the phase noise correction loop filter, the primary PLL circuit being configured to output the primary control input signal as a common adjustment signal; each secondary PLL circuit (48) comprising a controlled oscillator adapted to receive an auxiliary control input signal based on a phase comparison of the divided LO signal of that PLL circuit (48) with the divided LO signal of the primary PLL circuit (44), and a primary control input signal which is the common adjustment signal; LO signal generation circuit (40).

7. 7. The LO signal generation circuit (40) of claim 6, wherein the correction current output by each secondary PLL circuit (48) as a phase deviation signal has a polarity opposite to that of a current output by a charge pump used to generate the primary control input signal of the controlled oscillator of the PLL circuit (48).

8. 7. The LO signal generation circuit (40) of claim 6, wherein the correction current output by each second-order PLL circuit (48) as a phase deviation signal is scaled based on the number of second-order PLL circuits (48).

9. 9. The LO signal generating circuit (40) of claim 8, wherein the number of second-order PLL circuits (48) is N, and each second-order PLL circuit (48) is set to scale its correction current by 1 / N.

10. 10. The LO signal generation circuit (40) of claim 6, wherein the phase noise correction loop filter (46) has an impedance related to the number of second-order PLL circuits (48).

11. A multi-carrier transceiver (10, 112, 122) for a wireless communication network node or wireless device, comprising: An LO signal generating circuit (14, 20, 40) according to any one of claims 1 to 10; a mixer (86) configured to frequency translate wireless communication signals between baseband and a plurality of RF carrier frequencies; a filter (87) configured to suppress signal energy outside a frequency band around each RF carrier frequency among the plurality of RF carrier frequencies; A multi-carrier transceiver (10, 112, 122) comprising:

12. 12. The multi-carrier transceiver (10, 112, 122) of claim 11, wherein one or more LO signals, or integer multiples or quotients of LO signals, coincide in frequency with corresponding RF carrier frequencies within a predetermined tolerance.

13. A multi-carrier transceiver integrated circuit (IC) system (10, 112, 122) for a wireless communication network node or wireless device, comprising: A plurality of channels (80), each channel (80) comprising: an antenna switch (83) connected to an external RF filter (82); a receive chain of circuits including a low noise amplifier (84), a frequency down-conversion mixer (86), a filter (87), and an analog-to-digital converter (89); A transmit chain of a circuit including a power amplifier (85), a frequency up-conversion mixer (86), a filter (87), and a digital-to-analog converter (88). a plurality of channels (80) comprising:

11. The multi-frequency LO signal generation circuit (14, 20, 40) of claim 1, wherein LO signals provided to the frequency down-conversion mixer (86) and the frequency up-conversion mixer (86) in different channels have different frequencies corresponding to the different channels, whereby the different channels are configured to process different carrier frequency signals; A multi-carrier transceiver integrated circuit (IC) system (10, 112, 122) comprising:

14. A user equipment (UE) (110) operating in a wireless communication network, the UE (110) comprising: The multi-carrier transceiver integrated circuit (IC) system (112) of claim 13; a processing circuit (114) operatively connected to the multi-carrier transceiver integrated circuit (IC) system (112) and configured to communicate in a radio access network with one or more nodes of a wireless communication network; A user equipment (UE) (110) comprising:

15. A base station (120) operating in a wireless communication network, said base station (20) comprising: The multi-carrier transceiver integrated circuit (IC) system (122) of claim 13; a processing circuit (124) operatively connected to the multi-carrier transceiver integrated circuit (IC) system (122) and configured to communicate with a plurality of user equipments (UEs) (110) in a wireless access network; A base station (120) comprising:

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