Inductor coil, voltage-controlled oscillator and method for improving gate voltage swing

Abstract

The application discloses an inductor coil, a voltage-controlled oscillator and a method for improving gate voltage swing, and relates to the technical field of inductor coils. The inductor coil comprises a P-side inductor coil branch and an N-side inductor coil branch, and the P-side inductor coil branch is connected with the N-side inductor coil branch. The P-side inductor coil branch comprises a first P-side inductor and a second P-side inductor connected in series, and the connection point of the first P-side inductor and the second P-side inductor is a first tapping point, which is used for increasing P-side passive gain. The N-side inductor coil branch comprises a first N-side inductor and a second N-side inductor connected in series, and the connection point of the first N-side inductor and the second N-side inductor is a second tapping point, which is used for increasing N-side passive gain. The first P-side inductor is connected with the first N-side inductor. When the inductor coil is applied to a resonant cavity of a voltage-controlled oscillator, passive gain can be used to improve gate voltage swing, reduce saturation time and realize current noise suppression.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to an inductor coil, a voltage-controlled oscillator, and a method for increasing the gate voltage swing. Background Technology

[0002] With the development of wireless communication technology, the improvement in communication quality has placed higher demands on the low-noise design of Phase Lock Loops (PLLs). As a key module in PLLs, the voltage-controlled oscillator (VCO) plays a crucial role in high-performance PLL design, particularly in suppressing the phase noise of the inductor-capacitor resonant VCO (LC-VCO). In LC-VCO design, there is a trade-off between power consumption and noise. Conventional low-noise designs suppress noise by increasing power consumption or by using multi-core designs, placing greater pressure on chip power consumption and area.

[0003] For single-core LC-VCOs, the following methods are mostly used to achieve noise optimization:

[0004] 1) Increasing the size of the cross-coupled transistors can improve the voltage swing of the MOSFETs, thereby reducing the saturation time of the transistors and suppressing their current noise. However, increasing the size of the transistors also introduces more transistor noise, resulting in limited actual noise optimization and increased power consumption. 2) Using a cross-coupled P / NMOS pair stack (CMOS type), the P / NMOS transistors on the same side will not turn on simultaneously, thus reducing the saturation time of the pair. See [link to documentation]. Figure 1 As shown, in this structure, DP is connected to GN and DN is connected to GP. Its gate voltage swing is the same as its drain voltage swing, while the drain voltage swing is limited by the power supply voltage of the voltage-controlled oscillator. In low-voltage circuits, it is difficult to continue to increase the swing to suppress noise.

[0005] Therefore, in existing voltage-controlled oscillators (VCOs), noise optimization is mostly achieved by increasing the gate voltage swing to reduce saturation time. However, noise suppression will lead to increased power consumption and chip area, and the noise suppression effect is limited by the power supply voltage. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, the present invention aims to provide a method for improving the gate voltage swing of an inductor coil, a voltage-controlled oscillator, and a method that effectively improves the passive gain of the inductor coil itself without requiring additional power consumption or chip area. When the inductor coil is applied to the resonant cavity of the voltage-controlled oscillator, the enhanced passive gain can be used to improve the gate voltage swing, reduce its saturation time, and achieve more effective suppression of current noise.

[0007] This invention is implemented according to the following scheme: An inductor is provided, comprising: a P-side inductor branch and an N-side inductor branch, wherein the P-side inductor branch is connected to the N-side inductor branch; The P-side inductor branch includes a first P-side inductor and a second P-side inductor connected in series. The connection point between the first P-side inductor and the second P-side inductor is a first tap, which is used to increase the passive gain on the P-side. The N-side inductor branch includes a first N-side inductor and a second N-side inductor connected in series. The connection point between the first N-side inductor and the second N-side inductor is a second tap, which is used to increase the passive gain on the N-side. The first P-side inductor is connected to the first N-side inductor.

[0008] A voltage-controlled oscillator is also provided, comprising: a cross-coupled pair of transistors and a resonant cavity, wherein the resonant cavity includes an inductor coil and a capacitor unit as described above, the inductor coil being connected to the capacitor unit, and the cross-coupled pair of transistors being connected to the inductor coil and the capacitor unit.

[0009] Optionally, the cross-coupled transistor includes a first conducting unit and a second conducting unit, wherein the first conducting unit is connected to the second conducting unit, the inductor coil, and the capacitor unit, and the second conducting unit is connected to the inductor coil and the capacitor unit.

[0010] Optionally, the first conducting unit includes a first PMOS transistor and a first NMOS transistor; The source of the first PMOS transistor is connected to the power supply voltage and the second conduction unit; the drain of the first PMOS transistor is connected to the first tap and the second conduction unit; and the gate of the first PMOS transistor is connected to the second N-side inductor, the capacitor unit, and the second conduction unit. The source of the first NMOS transistor shares a common ground with the second conduction unit, the drain of the first NMOS transistor is connected to the second tap and the second conduction unit, and the gate of the first NMOS transistor is connected to the second P-side inductor, the capacitor unit, and the second conduction unit.

[0011] Optionally, the second conduction unit includes a second PMOS transistor and a second NMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage and the first conduction unit; the drain of the second PMOS transistor is connected to the second tap and the first conduction unit; and the gate of the second PMOS transistor is connected to the second P-side inductor, the capacitor unit, and the first conduction unit. The source of the second NMOS transistor shares a common ground with the first conducting unit, the drain of the second NMOS transistor is connected to the first tap and the first conducting unit, and the gate of the second NMOS transistor is connected to the second N-side inductor, the capacitor unit, and the first conducting unit.

[0012] Optionally, the second conduction unit includes a second PMOS transistor and a second NMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage and the source of the first PMOS transistor. The drain of the second PMOS transistor is connected to the second tap and the drain of the first NMOS transistor. The gate of the second PMOS transistor is connected to the second P-side inductor, the capacitor unit, and the gate of the first NMOS transistor. The source of the second NMOS transistor shares a common ground with the source of the first NMOS transistor. The drain of the second NMOS transistor is connected to the first tap and the drain of the first PMOS transistor. The gate of the second NMOS transistor is connected to the second N-side inductor, the capacitor unit, and the gate of the first PMOS transistor.

[0013] Optionally, the capacitor unit includes a capacitor array and a varactor tube, the capacitor array is connected to the varactor tube, the cross-coupled tube is connected to the capacitor array and the varactor tube, and the inductor coil is connected to the capacitor array and the varactor tube.

[0014] A method for increasing the gate voltage swing is also provided, applied to the aforementioned voltage-controlled oscillator, comprising: Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor, the P-side ratio between the inductance value of the first P-side inductor and the total inductance value of the P-side inductor coil branch is determined. Based on the P-side ratio, the position of the first tap in the P-side inductor coil branch is determined. By adjusting the position of the first tap in the P-side inductor coil branch, the gate voltage swing of the first PMOS transistor or the gate voltage swing of the second PMOS transistor in the cross-coupled transistor is increased to the maximum gate-source voltage. Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor, the N-side ratio between the inductance value of the first N-side inductor and the total inductance value of the N-side inductor coil branch is determined. Based on the N-side ratio, the position of the second tap in the N-side inductor coil branch is determined. By adjusting the position of the second tap in the N-side inductor coil branch, the gate voltage swing of the first NMOS transistor or the gate voltage swing of the second NMOS transistor in the cross-coupled transistor is increased to the maximum gate-source voltage.

[0015] Optionally, based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor, the P-side ratio between the inductance value of the first P-side inductor and the total inductance value of the P-side inductor coil branch is determined, as shown in the following expression:

[0016] in, The inductance value of the first P-side inductor. The inductance value of the second P-side inductor. This represents the total inductance of the P-side inductor branch. The voltage is the power supply voltage of the voltage-controlled oscillator. This represents the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor configuration.

[0017] Optionally, based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor, the N-side ratio between the inductance value of the first N-side inductor and the total inductance value of the N-side inductor coil branch is determined, as shown in the following expression:

[0018] in, The inductance value of the first N-side inductor. The inductance value of the second N-side inductor. This represents the total inductance of the N-side inductor branch. The voltage is the power supply voltage of the voltage-controlled oscillator. This represents the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor configuration.

[0019] Compared with the prior art, the beneficial effects of the inductor coil of the present invention are as follows: the passive gain of the P-side MOS transistor is increased by the first tap and the passive gain of the N-side MOS transistor is increased by the second tap, which can effectively improve the passive gain of the inductor coil itself without additional power consumption and chip area; when the inductor coil is applied to the resonant cavity of the voltage-controlled oscillator, the increased passive gain can be used to improve the gate voltage swing, thereby significantly reducing its saturation time under the condition that the transistor size and power supply voltage remain unchanged, achieving more effective suppression of current noise, and avoiding the additional power consumption and chip area caused by the noise optimization of traditional voltage-controlled oscillators being limited by power supply voltage or noise suppression effect. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a voltage-controlled oscillator (CMOS type) using a stacked P / NMOS transistor pair; Figure 2 This is a schematic diagram of the inductor coil of the present invention. Figure 1 ; Figure 3This is a schematic diagram of the inductor coil of the present invention. Figure 2 ; Figure 4 This is a schematic diagram of the voltage-controlled oscillator of the present invention; Figure 5 This is a schematic diagram of the cross-coupled tubes of the present invention; Figure 6 This is a schematic diagram of the output oscillation waveform of a voltage-controlled oscillator; Figure 7 A waveform diagram showing the current pulses injected at different positions during the oscillation period; Figure 8 This is a schematic diagram showing the time during which all cross-coupled transistors in a current voltage-controlled oscillator are in the saturation region. Figure 9 This is a schematic diagram showing the time during which all cross-coupled transistors in the voltage-controlled oscillator of the present invention are in the saturation region; Figure 10 This is a schematic diagram of the simulation results of the voltage-controlled oscillator of the present invention; Figure 11 A schematic diagram showing the phase noise simulation results of a prior art voltage-controlled oscillator and the voltage-controlled oscillator of the present invention; The attached diagram shows the following symbols: 1. Inductor coil; 101. P-side inductor coil branch; 102. N-side inductor coil branch; 2. Capacitor unit. Detailed Implementation

[0021] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0022] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of this application.

[0023] In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims. In the description of this application, it should be understood that the terms "first," "second," "third," etc., are used only to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] See Figure 2-3 As shown, an inductor coil of the present invention includes: a P-side inductor coil branch 101 and an N-side inductor coil branch 102, wherein the P-side inductor coil branch 101 and the N-side inductor coil branch 102 are connected. The P-side inductor branch 101 includes a first P-side inductor L1_P and a second P-side inductor L2_P connected in series. The connection point between the first P-side inductor L1_P and the second P-side inductor L2_P is a first tap, which is used to increase the passive gain on the P-side. The N-side inductor branch 102 includes a first N-side inductor L1_N and a second N-side inductor L2_N connected in series. The connection point between the first N-side inductor L1_N and the second N-side inductor L2_N is a second tap, which is used to increase the passive gain on the N-side. The first P-side inductor L1_P is connected to the first N-side inductor L1_N.

[0025] See Figure 4-5 As shown, a voltage-controlled oscillator of the present invention includes: a cross-coupled pair of transistors and a resonant cavity. The resonant cavity includes an inductor coil 1 and a capacitor unit 2. The inductor coil 1 and the capacitor unit 2 are connected. The cross-coupled pair of transistors is connected to the inductor coil 1 and the capacitor unit 2.

[0026] In one embodiment of the present invention, the cross-coupled transistor includes a first conducting unit and a second conducting unit. The first conducting unit is connected to the second conducting unit, the inductor coil 1, and the capacitor unit 2. The second conducting unit is connected to the inductor coil 1 and the capacitor unit 2.

[0027] In one embodiment of the present invention, the first conduction unit includes a first PMOS transistor PM1 and a first NMOS transistor NM1; the source of the first PMOS transistor PM1 is connected to the power supply voltage VDD and the second conduction unit, the drain of the first PMOS transistor PM1 is connected to the first tap and the second conduction unit, and the gate of the first PMOS transistor PM1 is connected to the second N-side inductor L2_N, capacitor unit 2, and the second conduction unit; the source of the first NMOS transistor NM1 and the second conduction unit share a common ground, the drain of the first NMOS transistor NM1 is connected to the second tap and the second conduction unit, and the gate of the first NMOS transistor NM1 is connected to the second P-side inductor L2_P, capacitor unit 2, and the second conduction unit.

[0028] In one embodiment of the present invention, the second conduction unit includes a second PMOS transistor PM2 and a second NMOS transistor NM2; the source of the second PMOS transistor PM1 is connected to the power supply voltage VDD and the first conduction unit, the drain of the second PMOS transistor PM2 is connected to the second tap and the first conduction unit, and the gate of the second PMOS transistor PM2 is connected to the second P-side inductor L2_P, capacitor unit 2, and the first conduction unit; the source of the second NMOS transistor NM2 is grounded with the first conduction unit, the drain of the second NMOS transistor NM2 is connected to the first tap and the first conduction unit, and the gate of the second NMOS transistor NM2 is connected to the second N-side inductor L2_N, capacitor unit 2, and the first conduction unit.

[0029] In one embodiment of the present invention, the second conduction unit includes a second PMOS transistor PM2 and a second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the power supply voltage VDD and the source of the first PMOS transistor PM1, the drain of the second PMOS transistor PM2 is connected to the second tap and the drain of the first NMOS transistor NM1, the gate of the second PMOS transistor PM2 is connected to the second P-side inductor L2_P, the capacitor unit 2, and the gate of the first NMOS transistor NM1; the source of the second NMOS transistor NM2 and the source of the first NMOS transistor NM1 share a common ground, the drain of the second NMOS transistor NM2 is connected to the first tap and the drain of the first PMOS transistor PM1, and the gate of the second NMOS transistor NM2 is connected to the second N-side inductor L2_N, the capacitor unit 2, and the gate of the first PMOS transistor PM1.

[0030] In one embodiment of the present invention, the capacitor unit 2 includes a capacitor array and a varactor tube. The capacitor array is connected to the varactor tube, the cross-coupled transistor is connected to the capacitor array and the varactor tube, and the inductor coil 1 is connected to the capacitor array and the varactor tube.

[0031] The voltage-controlled oscillator of this invention provides an external excitation signal to the resonant cavity without energy loss. The signal energy exchanges back and forth between the magnetic field generated by the inductor coil 1 and the electric field of the capacitor array, forming a stable sinusoidal voltage swing across the resonant cavity. The oscillation frequency of this sinusoidal voltage is controlled by the inductance of the inductor coil and the capacitance of the capacitor array. The oscillation frequency is controlled by changing the capacitance of the varactor tube through an external voltage. However, due to parasitic resistance and leakage of inductor magnetic field energy in the actual circuit, the resonant cavity cannot maintain oscillation. A cross-coupled pair of transistors connected to the resonant cavity continuously provides energy to maintain the oscillation.

[0032] See Figure 2 and Figure 5 As shown, the cross-coupled transistors and inductor coil 1 are connected via DP port, DN port, GP port, and GN port. The DP port is located at the connection between the drain of the first PMOS transistor PM1 and the drain of the second NMOS transistor NM2, and at the connection between the first P-side inductor L1_P and the second P-side inductor L2_P, i.e., the DP port is located at the first tap. The DN port is located at the connection between the drain of the second PMOS transistor PM2 and the drain of the first NMOS transistor NM1, and at the connection between the first N-side inductor L1_N and the second N-side inductor L2_N, i.e., the DN port is located at the second tap. The GP port is located at the connection between the gate of the first PMOS transistor PM1 and the gate of the second NMOS transistor NM2, and at the end of the second N-side inductor L2_N that is not connected to the first N-side inductor L1_N. The GN port is located at the connection between the gate of the second PMOS transistor PM2 and the gate of the first NMOS transistor NM1, and at the end of the second P-side inductor L2_P that is not connected to the first P-side inductor L1_P.

[0033] The voltage-controlled oscillator of the present invention increases the passive gain by connecting the first and second taps of the inductor coil 1 to the cross-coupled transistor pair. This passive gain increases the gate voltage swing of the MOS transistor in the cross-coupled transistor pair, thereby significantly reducing its saturation time under the condition that the transistor size and power supply voltage remain unchanged. This achieves more effective suppression of current noise and avoids the additional power consumption and chip area caused by the limitation of noise optimization in traditional voltage-controlled oscillators by power supply voltage or noise suppression effect. Figure 1 This invention illustrates a conventional voltage-controlled oscillator (VCO) with DN and GP connections and DP and GN connections. In this VCO, the gate and drain of the MOS transistors in the cross-coupled pair are connected, and the gate voltage swing is the same as the drain voltage swing, meaning the swings at both ends of the differential pair are identical. Furthermore, the drain voltage swing is limited by the power supply voltage of the VCO. Compared to this invention… Figure 1The voltage-controlled oscillator shown in this invention can increase the gate voltage swing to the maximum gate-source voltage set by the MOS transistor process, thereby reducing the saturation time and achieving better noise suppression by increasing the gate swing voltage.

[0034] See Figure 6 As shown, according to phase noise theory, assuming a very small current pulse is injected into the output node of the voltage-controlled oscillator at a certain moment τ, it will cause a change in the phase of the output oscillation waveform of the voltage-controlled oscillator, resulting in a phase shift. This phase shift at the output node can be expressed as:

[0035] in, C is the effective charge injected into the resonant cavity, while C is the loop capacitance in the resonant cavity. It is the maximum charge swing. It is the angular frequency of the voltage-controlled oscillator, and It is a dimensionless time-varying pulse sensitivity function with a period of 2π, used to measure the sensitivity of the output phase to very small current pulses. Normalized With output voltage swing It is irrelevant; therefore, it can be seen that by increasing the maximum charge swing... This can effectively reduce the output phase shift caused by noise, that is, reduce phase noise.

[0036] In addition, see Figure 7 As shown, the waveforms of current pulses injected at different positions in the oscillation period are illustrated. Specifically, when a current pulse is injected into an ideal LC resonant cavity that maintains oscillation, if the current pulse is injected at the peak of the oscillating sine wave, the injected current pulse will not cause a phase change in the oscillation voltage. That is, the injected noise will not cause any phase shift in the voltage-controlled oscillator, nor will it cause the phase noise of the voltage-controlled oscillator to deteriorate. Conversely, if the current pulse is injected at the zero-crossing point of the oscillating sine wave, the phase change of the oscillation voltage caused by the current pulse is the largest. That is, the voltage-controlled oscillator is most sensitive to noise injection at this time.

[0037] Assuming the voltage-controlled oscillator has a sufficiently large swing at both ends, the first and second conduction units of the cross-coupled transistors can switch back and forth between fully on and fully off states without being in a saturation region. That is, when the first PMOS transistor PM1 and the first NMOS transistor NM1 in the first conduction unit are in the on state, the second PMOS transistor PM2 and the second NMOS transistor NM2 in the second conduction unit are in the off state; when the second PMOS transistor PM2 and the second NMOS transistor NM2 in the second conduction unit are in the on state, the first PMOS transistor PM1 and the first NMOS transistor NM1 in the first conduction unit are in the off state.

[0038] However, in practical applications, the voltage oscillation signal of a voltage-controlled oscillator (VCO) is a sine wave. During the oscillation period of a VCO, there is a period where both cross-coupled transistors (the first and second conducting units) are in the saturation region. The longer the cross-coupled transistors remain in the saturation region, the more noise is generated. If current noise is introduced at the zero-crossing point of the oscillating sine wave, it has a significant impact on the phase noise of the VCO. By increasing the gate voltage swing, the slope of the oscillating voltage signal at the zero-crossing point can be increased, reducing the proportion of time the transistors are in the saturation region, i.e., reducing the effective charge injected into the resonant cavity. This also reduces phase noise.

[0039] See Figure 8 The diagram illustrates the time during which all cross-coupled transistors in a prior art voltage-controlled oscillator are in the saturation region. (See attached diagram.) Figure 9 The diagram shows the time during which the cross-coupled transistors in the voltage-controlled oscillator of the present invention are all in the saturation region. The present invention increases the passive gain by using a tapped inductor coil 1 to increase the gate voltage swing, improve the slope of the oscillation voltage signal at the zero crossing point, and thus reduce the proportion of time the transistors are in the saturation region, thereby achieving better noise suppression.

[0040] This invention divides the P-side inductor branch 101 into a first P-side inductor using a first tap. and the second P-side inductor The N-side inductor branch 102 is divided into the first N-side inductor by the second tap. and the second N-side inductor At this time, the gate voltage swing of the four MOS transistors in the cross-coupled pair is... With drain voltage swing The following proportional relationship exists between them:

[0041] This invention achieves passive gain between the gates and drains of four MOS transistors in a cross-coupled transistor pair by using a tapped inductor coil 1. See [link to related documentation]. Figure 10 As shown, the simulation results of the voltage-controlled oscillator of the present invention are presented. The gate voltage swing (red line in the figure) is significantly higher than the drain voltage swing (yellow line in the figure). When the drain voltage swing (yellow line in the figure) reaches the power supply voltage of the voltage-controlled oscillator, the present invention can continuously increase the gate voltage swing (red line in the figure) to avoid the gate voltage swing being limited by the power supply voltage of the voltage-controlled oscillator.

[0042] Because the drain-source voltage of the transistor is limited by the power supply voltage of the voltage-controlled oscillator. The selection criteria for the tap position of inductor coil 1 are shown in the following formula:

[0043] in, This refers to the maximum gate-source voltage of the PMOS or NMOS transistor. This is the power supply voltage.

[0044] Taking 22nm process as an example, design a voltage-controlled oscillator with a power consumption of 7mA and a center frequency of 9GHz. The power supply voltage... Set to 0.9V, the maximum gate-source voltage of the PMOS or NMOS transistor specified by the process. At a voltage of 1.05V, the oscillation voltage waveform at the output node of the voltage-controlled oscillator at the base frequency can be expressed as:

[0045]

[0046] in, This is the parasitic parallel resistance of the actual inductor coil. This is the angular frequency of the voltage-controlled oscillator, and Ls is the inductance value. For the inductor Q value (designed to be 25), The average power consumption of the voltage-controlled oscillator on one side is approximately 3.5mA.

[0047] Based on the above formula, the gate voltage swing (peak-to-peak value) of the voltage-controlled oscillator. This can be expressed as the following formula:

[0048] The inductance of the main resonant cavity of the voltage-controlled oscillator can then be calculated and designed as follows:

[0049] The design value of the inductance is used as the total inductance of the P-side inductor branch 101 and the total inductance of the N-side inductor branch 102. According to the selection standard for the inductor tap position, the inductor tap position should make the inductance across the drain of the negative resistance module 285.7pH. Finally, the coil length dimensions of each part of the inductor meet the following proportional relationship:

[0050] Measured from the starting end of the first P-side inductor L1_P, the first tap is located at approximately 85.7% of the total length of the P-side inductor branch 101; measured from the starting end of the first N-side inductor L1_N, the second tap is located at approximately 85.7% of the total length of the N-side inductor branch 102.

[0051] See Figure 11The figure shows a schematic diagram of the phase noise simulation results of the prior art voltage-controlled oscillator and the voltage-controlled oscillator of the present invention. The red line in the figure represents the phase noise simulation result of the prior art voltage-controlled oscillator, and the yellow line represents the phase noise simulation result of the voltage-controlled oscillator of the present invention. As can be seen from the figure, the voltage-controlled oscillator of the present invention can achieve a phase noise performance optimization of about 2dB compared with the prior art voltage-controlled oscillator.

[0052] The present invention provides a method for increasing the gate voltage swing, applied to the aforementioned voltage-controlled oscillator, comprising: Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor, the P-side ratio between the inductance value of the first P-side inductor and the total inductance value of the P-side inductor coil branch 101 is determined. Based on the P-side ratio, the position of the first tap in the P-side inductor coil branch 101 is determined. By adjusting the position of the first tap in the P-side inductor coil branch 101, the gate voltage swing of the first PMOS transistor or the gate voltage swing of the second PMOS transistor in the cross-coupled transistor is increased to the maximum gate-source voltage. Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor, the N-side ratio between the inductance value of the first N-side inductor and the total inductance value of the N-side inductor branch 102 is determined. Based on the N-side ratio, the position of the second tap in the N-side inductor branch 102 is determined. By adjusting the position of the second tap in the N-side inductor branch 102, the gate voltage swing of the first NMOS transistor or the gate voltage swing of the second NMOS transistor in the cross-coupled transistor is increased to the maximum gate-source voltage.

[0053] In one embodiment of the present invention, the P-side ratio between the inductance value of the first P-side inductor and the total inductance value of the P-side inductor branch 101 is determined based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor. The expression is as follows:

[0054] in, The inductance value of the first P-side inductor. The inductance value of the second P-side inductor. This represents the total inductance of the P-side inductor branch 101. This refers to the power supply voltage of the voltage-controlled oscillator. This represents the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor configuration.

[0055] In one embodiment of the present invention, the N-side ratio between the inductance value of the first N-side inductor and the total inductance value of the N-side inductor branch 102 is determined based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor, as expressed in the following expression:

[0056] in, The inductance value of the first N-side inductor. The inductance value of the second N-side inductor. This represents the total inductance of the N-side inductor branch 102. This refers to the power supply voltage of the voltage-controlled oscillator. This represents the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor configuration.

[0057] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An inductor coil, characterized in that, include: The P-side inductor branch and the N-side inductor branch are connected; The P-side inductor branch includes a first P-side inductor and a second P-side inductor connected in series. The connection point between the first P-side inductor and the second P-side inductor is a first tap, which is used to increase the passive gain on the P-side. The N-side inductor branch includes a first N-side inductor and a second N-side inductor connected in series. The connection point between the first N-side inductor and the second N-side inductor is a second tap, which is used to increase the passive gain on the N-side. The first P-side inductor is connected to the first N-side inductor.

2. A voltage-controlled oscillator, characterized in that, include: The cross-coupled transistor and resonant cavity, wherein the resonant cavity includes an inductor and a capacitor unit as described in claim 1, wherein the inductor and the capacitor unit are connected, and the cross-coupled transistor is connected to the inductor and the capacitor unit.

3. A voltage-controlled oscillator according to claim 2, characterized in that, The cross-coupled transistor includes a first conducting unit and a second conducting unit. The first conducting unit is connected to the second conducting unit, the inductor coil, and the capacitor unit. The second conducting unit is connected to the inductor coil and the capacitor unit.

4. A voltage-controlled oscillator according to claim 3, characterized in that, The first conducting unit includes a first PMOS transistor and a first NMOS transistor; The source of the first PMOS transistor is connected to the power supply voltage and the second conduction unit; the drain of the first PMOS transistor is connected to the first tap and the second conduction unit; and the gate of the first PMOS transistor is connected to the second N-side inductor, the capacitor unit, and the second conduction unit. The source of the first NMOS transistor shares a common ground with the second conduction unit, the drain of the first NMOS transistor is connected to the second tap and the second conduction unit, and the gate of the first NMOS transistor is connected to the second P-side inductor, the capacitor unit, and the second conduction unit.

5. A voltage-controlled oscillator according to claim 3, characterized in that, The second conduction unit includes a second PMOS transistor and a second NMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage and the first conduction unit; the drain of the second PMOS transistor is connected to the second tap and the first conduction unit; and the gate of the second PMOS transistor is connected to the second P-side inductor, the capacitor unit, and the first conduction unit. The source of the second NMOS transistor shares a common ground with the first conducting unit, the drain of the second NMOS transistor is connected to the first tap and the first conducting unit, and the gate of the second NMOS transistor is connected to the second N-side inductor, the capacitor unit, and the first conducting unit.

6. A voltage-controlled oscillator according to claim 4, characterized in that, The second conduction unit includes a second PMOS transistor and a second NMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage and the source of the first PMOS transistor. The drain of the second PMOS transistor is connected to the second tap and the drain of the first NMOS transistor. The gate of the second PMOS transistor is connected to the second P-side inductor, the capacitor unit, and the gate of the first NMOS transistor. The source of the second NMOS transistor shares a common ground with the source of the first NMOS transistor. The drain of the second NMOS transistor is connected to the first tap and the drain of the first PMOS transistor. The gate of the second NMOS transistor is connected to the second N-side inductor, the capacitor unit, and the gate of the first PMOS transistor.

7. A voltage-controlled oscillator according to claim 2, characterized in that, The capacitor unit includes a capacitor array and a varactor tube. The capacitor array is connected to the varactor tube. The cross-coupled tube is connected to the capacitor array and the varactor tube. The inductor coil is connected to the capacitor array and the varactor tube.

8. A method for increasing the gate voltage swing, applied to a voltage-controlled oscillator according to any one of claims 2-7, characterized in that, include: Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor, the P-side ratio between the inductance value of the first P-side inductor and the total inductance value of the P-side inductor coil branch is determined. Based on the P-side ratio, the position of the first tap in the P-side inductor coil branch is determined. By adjusting the position of the first tap in the P-side inductor coil branch, the gate voltage swing of the first PMOS transistor or the gate voltage swing of the second PMOS transistor in the cross-coupled transistor is increased to the maximum gate-source voltage. Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor, the N-side ratio between the inductance value of the first N-side inductor and the total inductance value of the N-side inductor coil branch is determined. Based on the N-side ratio, the position of the second tap in the N-side inductor coil branch is determined. By adjusting the position of the second tap in the N-side inductor coil branch, the gate voltage swing of the first NMOS transistor or the gate voltage swing of the second NMOS transistor in the cross-coupled transistor is increased to the maximum gate-source voltage.

9. The method for increasing gate voltage swing according to claim 8, characterized in that, Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor, the P-side ratio between the inductance value of the first P-side inductor and the total inductance value of the P-side inductor coil branch is determined as follows: in, The inductance value of the first P-side inductor. The inductance value of the second P-side inductor. This represents the total inductance of the P-side inductor branch. The voltage is the power supply voltage of the voltage-controlled oscillator. This represents the maximum gate-source voltage of the PMOS transistor in the cross-coupled transistor configuration.

10. The method for increasing gate voltage swing according to claim 8, characterized in that, Based on the power supply voltage of the voltage-controlled oscillator and the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor, the N-side ratio between the inductance value of the first N-side inductor and the total inductance value of the N-side inductor branch is determined as follows: in, The inductance value of the first N-side inductor. The inductance value of the second N-side inductor. This represents the total inductance of the N-side inductor branch. The voltage is the power supply voltage of the voltage-controlled oscillator. This represents the maximum gate-source voltage of the NMOS transistor in the cross-coupled transistor configuration.

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