Display device

Abstract

A display device is provided. The display device includes n third transistors connected to a gate of a drive transistor. Each of the n third transistors includes a semiconductor region including a channel region, a source region and a drain region disposed in an extension direction with the channel region therebetween, and a gate overlapping the channel region. The drain region of a third transistor among the n third transistors that is closest to the gate of the first transistor includes a first region and a second region between the first region and the channel region. The second region has a lower doping concentration than the first region, and a width of the second region is smaller than a width of the first region in a reference direction perpendicular to the extension direction.

Description

[Technical field]

[0001] The present invention relates to a display device, and more particularly to a display device including a transistor having improved operating characteristics. [Background technology]

[0002] The display device includes a plurality of pixels and driving circuits (e.g., a scan driving circuit and a data driving circuit) that control the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit that controls the display element. The pixel driving circuit may include a plurality of organically connected transistors.

[0003] The scan driving circuit and / or the data driving circuit may be formed by the same process as the plurality of pixels, and the scan driving circuit and / or the data driving circuit may include a plurality of transistors organically connected to each other. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device with improved display quality. [Means for solving the problem]

[0005] A display device according to an embodiment of the present invention may include a first transistor, a second transistor electrically connected to the first transistor and outputting a data signal to the first transistor, n (where n is a natural number of 2 or more) third transistors electrically connected to a gate of the first transistor and connected in series with each other, a capacitor charging a voltage corresponding to the data signal, and a light emitting element electrically connected to the first transistor. Each of the n third transistors may include a semiconductor region including a channel region, a source region and a drain region disposed in an extension direction with the channel region therebetween, and a gate overlapping the channel region.

[0006] The source region or the drain region of a third transistor among the n third transistors that is closest to the gate of the first transistor may include the first region and a second region between the first region and the channel region. The second region may have a doping concentration lower than that of the first region, and a width of the second region may be smaller than a width of the first region in a reference direction perpendicular to the extension direction.

[0007] For a third transistor among the n third transistors that is located farthest from the gate of the first transistor, the source region or the drain region that is located farther from the gate of the first transistor may include the third region and a fourth region between the third region and the channel region.

[0008] The fourth region may have a doping concentration lower than that of the third region, and a width of the fourth region in the reference direction may be smaller than a width of the third region.

[0009] Among the n third transistors, a region of the source region or the drain region of a third transistor closest to the gate of the first transistor, which is disposed farther from the gate of the first transistor, includes the third region and a fourth region between the third region and the channel region, and the fourth region may have a doping concentration lower than that of the third region.

[0010] In the reference direction, the third region and the fourth region may have substantially the same width.

[0011] The width of the second region in the reference direction may be 1 μm to 2 μm.

[0012] The width of the second region may be 10% to 50% smaller than the width of the first region.

[0013] The length of the second region in the extension direction may be between 0.1 μm and 0.5 μm.

[0014] The first transistor and the n third transistors may include P-type polysilicon transistors, and the n third transistors may be connected in series between the gate of the first transistor and a source or drain of the first transistor.

[0015] The source region of the third transistor closest to the gate of the first transistor and the drain region of the third transistor disposed farthest from the gate of the first transistor may have substantially the same width in the reference direction.

[0016] The drain region and the source region of a third transistor among the n third transistors, which is arranged between the third transistor closest to the gate of the first transistor and the third transistor which is arranged farthest from the gate of the first transistor, may have substantially the same width in the reference direction.

[0017] The first transistor may include a semiconductor region including a channel region overlapping (overlapping) the gate of the first transistor, and a source region and a drain region sandwiching the channel region, and a width of at least one of the source region of the first transistor or the drain region of the first transistor may be greater than a width of the channel region of the first transistor.

[0018] A width of at least one of the source region of the first transistor and the drain region of the first transistor may be 5% to 20% greater than a width of the channel region of the first transistor.

[0019] Each of the source region of the first transistor and the drain region of the first transistor may include a third region and a fourth region between the third region and the channel region, the fourth region having a lower doping concentration than the third region, and the third region and the fourth region may have substantially the same width.

[0020] A width of the source region or the drain region of the first transistor may be greater than a width of the semiconductor region of each of the n third transistors.

[0021] The first transistor and each of the n third transistors may include a P-type polysilicon transistor, and the n third transistors may be coupled between the gate of the first transistor and a voltage line receiving an initialization voltage.

[0022] The capacitor may be electrically coupled between the gate of the first transistor and a voltage line receiving a power supply voltage.

[0023] A display device according to an embodiment of the present invention includes a first transistor, a second transistor electrically connected to the first transistor and outputting a data signal to the first transistor, n (where n is a natural number of 2 or more) third transistors electrically connected to a gate of the first transistor and connected in series with each other, a capacitor charging a voltage corresponding to the data signal, and a light emitting element electrically connected to the first transistor. Each of the n third transistors may include a semiconductor region including a channel region, a source region and a drain region disposed in an extension direction with the channel region therebetween, and a gate overlapping the channel region.

[0024] The source region or the drain region of the n third transistors, which is located farthest from the gate of the first transistor, may include the first region and a second region between the first region and the channel region, The second region may have a lower doping concentration than the first region, and a width of the second region may be smaller than a width of the first region in a reference direction perpendicular to the extension direction.

[0025] A display device according to one embodiment of the present invention may include a first transistor, a second transistor electrically connected to the first transistor and outputting a data signal to the first transistor, a third transistor electrically connected to a gate of the first transistor, and a light-emitting element electrically connected to the first transistor.

[0026] The third transistor may include a semiconductor region including a channel region, a drain region and a source region sandwiching the channel region in an extension direction, and a gate overlapping the channel region. At least one of the drain region and the source region may include a first region and a second region between the first region and the channel region. The second region may have a lower doping concentration than the first region, and a width of the second region may be smaller than a width of the first region in a reference direction perpendicular to the extension direction.

[0027] A display device according to an embodiment of the present invention may include a first transistor, a second transistor electrically connected to the first transistor and outputting a data signal to the first transistor, n (where n is a natural number equal to or greater than 1) third transistors electrically connected to a gate of the first transistor and connected in series with each other, and a light emitting element electrically connected to the first transistor. Each of the first, second and third transistors may include a semiconductor region including a channel region, a source region and a drain region disposed with the channel region therebetween, and a gate overlapping the channel region. Each of the drain region and the source region may include a first region and a second region between the first region and the channel region, the second region may have a lower doping concentration than the first region, and each width of the source region of the first transistor and the drain region of the first transistor may be greater than a width of the channel region of the first transistor.

[0028] A width of the drain region of the first transistor may be 5% to 20% greater than a width of the channel region of the first transistor.

[0029] A width of the second region of the source region in the first transistor and a width of the second region of the drain region in the first transistor may be substantially the same.

[0030] A width of the drain region in the first transistor may be greater than a width of the drain region in the n third transistors.

[0031] A width of at least one of the source regions of the n third transistors and the drain regions of the n third transistors may be substantially equal to a width of the channel regions of the n third transistors. Effect of the Invention

[0032] As described above, the drain / source field reduction effect can be obtained with a small area of ​​doped region, and the resistance of the lightly doped region can be increased to a desired level by reducing the width even though the length is short.

[0033] The drain field of the transistor coupled to the gate of the driving transistor is reduced, thereby reducing the leakage current of the transistor During the light emitting period, the driving transistor provides a current corresponding to the data voltage to the light emitting element.

[0034] By increasing the width of the low-doping region of the drive transistor, it is possible to prevent a decrease in the drive current of the drive transistor. [Brief description of the drawings]

[0035] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Diagram 3] 3 is a waveform diagram of a driving signal for driving the pixel shown in FIG. 2. [Figure 4] 2 is a cross-sectional view of a display panel corresponding to a pixel according to an embodiment of the present invention; [Figure 5a] FIG. 2 is a plan view of a pixel according to an embodiment of the present invention. [Figure 5b] 4A to 4C are plan views showing stacking orders of patterns included in a pixel according to an embodiment of the present invention; [Figure 5c] 4A to 4C are plan views showing stacking orders of patterns included in a pixel according to an embodiment of the present invention; [Figure 5d] 4A to 4C are plan views showing stacking orders of patterns included in a pixel according to an embodiment of the present invention; [Figure 5e] 4A to 4C are plan views showing stacking orders of patterns included in a pixel according to an embodiment of the present invention; [Figure 5f] 4A to 4C are plan views showing stacking orders of patterns included in a pixel according to an embodiment of the present invention; [Figure 5g]4A to 4C are plan views showing stacking orders of patterns included in a pixel according to an embodiment of the present invention; [Figure 6a] FIG. 4 is a plan view of a third transistor according to an embodiment of the present invention. [Figure 6b] FIG. 6b is a cross-sectional view of a third transistor corresponding to II' in FIG. 6a; [Figure 6c] FIG. 6b is a cross-sectional view of a third transistor corresponding to II' in FIG. 6a; [Figure 6d] 4 is a voltage-current graph of a transistor according to a comparative example and a transistor according to an embodiment of the present invention. [Figure 6e] 1A to 1C are cross-sectional views showing a doping process for a transistor. [Figure 6f] 10 is a circuit diagram showing the operation of a first transistor and a third transistor in a light-emitting section corresponding to a high-gradation data signal. FIG. [Figure 6g] 4 is a circuit diagram showing the operation of a first transistor and a third transistor in a light-emitting section corresponding to a middle gradation data signal. FIG. [Figure 7a] FIG. 4 is a circuit diagram of a third transistor according to an embodiment of the present invention. [Figure 7b] FIG. 4 is a plan view of a third transistor according to an embodiment of the present invention. [Figure 7c] FIG. 4 is a circuit diagram of a third transistor according to an embodiment of the present invention. [Figure 7d] FIG. 4 is a plan view of a third transistor according to an embodiment of the present invention. [Figure 8a] FIG. 13 is a plan view of a fourth transistor according to an embodiment of the present invention. [Figure 8b] 4 is a circuit diagram showing the operation of a first transistor and a fourth transistor in a light emitting section. FIG. [Figure 9a] FIG. 2 is a plan view of a first transistor according to an embodiment of the present invention. [Figure 9b] 9b is a cross-sectional view of the first transistor corresponding to II-II' in FIG. 9a; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on" or "coupled" to another component, it means that it may be directly disposed, coupled, or connected to the other component, or that a third component may be disposed therebetween.

[0037] The same reference numerals refer to the same components. Also, in the drawings, thicknesses, ratios, and dimensions of the components are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all combinations of one or more of the components defined by the associated components.

[0038] Terms such as "first" and "second" are used to describe various components, but the components are not limited to the terms. The terms are used only to distinguish one component from another. For example, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the present invention. A singular surface includes a plural expression unless the context clearly dictates otherwise.

[0039] In addition, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described based on the directions shown in the drawings.

[0040] It should be understood that terms such as "comprise" or "have" specify the presence of any feature, number, step, operation, component, part, or combination thereof described hereinabove in the specification, but do not preclude the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless expressly defined herein.

[0042] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0043] FIG. 1 is a block diagram of a display device DD according to an embodiment of the present invention.

[0044] The display device DD includes a timing controller TC, a scan driver SDC, a data driver DDC, and a display panel DP. In this embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel or an inorganic light-emitting display panel.

[0045] The timing controller TC receives an input video signal, converts the timing format of the input video signal to match the interface specifications with the scan driver circuit SDC, and generates video data D-RGB. The timing controller TC outputs the video data D-RGB and various control signals DCS and SCS.

[0046] The scan driving circuit SDC receives a scan control signal SCS from the timing controller TC. The scan control signal SCS may include a vertical start signal for starting the operation of the scan driving circuit SDC and a clock signal for determining the output timing of the signal. The scan driving circuit SDC generates scan signals and sequentially outputs them to corresponding scan signal lines SL11 to SL1n. In addition, the scan driving circuit SDC generates a plurality of light emission control signals in response to the scan control signal SCS and outputs the plurality of light emission control signals to corresponding light emission control lines ECL1 to ECLn.

[0047] 1, a plurality of scan signals and a plurality of light emission control signals are shown as being output from one scan driving circuit SDC, but the present invention is not limited thereto. In one embodiment of the present invention, the display device DD may include a plurality of scan driving circuits. Also, in one embodiment of the present invention, a driving circuit that generates and outputs a plurality of scan signals and a driving circuit that generates and outputs a plurality of light emission control signals may be formed separately.

[0048] The data driving circuit DDC receives a data control signal DCS and image data D-RGB from the timing controller TC. The data driving circuit DDC converts the image data D-RGB into a data signal and outputs the data signal to a number of data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data D-RGB.

[0049] The light-emitting display panel DP includes scan signal lines SL11 to SL1n, light-emitting control lines ECL1 to ECLn, data lines DL1 to DLm, a first voltage line VL1, a second voltage line VL2, and a plurality of pixels PX.

[0050] The scan signal lines SL11 to SL1n and the emission control lines ECL1 to ECLn may be extended in a first direction DR1 and arranged in a second direction DR2. The data lines DL1 to DLm may cross the scan signal lines SL11 to SL1n.

[0051] The first voltage line VL1 receives the first power supply voltage ELVDD. Although not shown, a voltage line receiving the second power supply voltage ELVSS may be further arranged. The second power supply voltage ELVSS has a lower level than the first power supply voltage ELVDD. The second voltage line VL2 receives the initialization voltage Vint. The initialization voltage Vint has a lower level than the first power supply voltage ELVDD.

[0052] Although the display device DD according to an embodiment has been described with reference to FIG. 1, the display device DD of the present invention is not limited thereto. Signal lines may be added or omitted depending on the configuration of the pixel driving circuit. In addition, the electrical connection relationship between one pixel PX and a signal line may be changed.

[0053] The pixels PX may include a plurality of groups that generate different colors of light, for example, a first group of pixels that generate red light, a second group of pixels that generate green light, and a third group of pixels that generate blue light. The red pixel light emitting diodes, the green pixel light emitting diodes, and the blue pixel light emitting diodes may include light emitting layers made of different materials.

[0054] The pixel driving circuit may include a plurality of transistors and at least one capacitor. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a plurality of transistors formed by the same process as the pixel driving circuit.

[0055] The above-mentioned signal lines, a plurality of pixels PX, a scan driving circuit SDC, and a data driving circuit DDC can be formed on the base substrate by performing photolithography and etching processes multiple times.

[0056] Fig. 2 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present invention, and Fig. 3 is a waveform diagram of a driving signal for driving the pixel PXij shown in Fig. 2.

[0057] The pixel PX may include a light emitting element LD and a pixel circuit CC. The pixel circuit CC may include first to seventh transistors T1 to T7 and a capacitor CP. The pixel circuit CC controls the amount of current flowing through the light emitting element LD in response to a data signal. The light emitting element LD may emit light at a predetermined luminance in response to the amount of current provided by the pixel circuit CC.

[0058] Each of the first to seventh transistors T1 to T7 includes a source, a drain, a channel, and a gate. The source, the drain, and the channel may be implemented in different regions of a semiconductor pattern. In this embodiment, each of the first to seventh transistors T1 to T7 is described as a P-type transistor. However, without being limited thereto, at least some of the first to seventh transistors T1 to T7 may be an N-type transistor. The source and the drain of a P-type transistor may correspond to the source and the drain of an N-type transistor, respectively. In particular, the third transistors T3-1, T3-2 and the fourth transistors T4-1, T4-2 may be N-type. The drain / source field reduction effect described later may also occur in the N-type third transistors T3-1, T3-2 and the fourth transistors T4-1, T4-2.

[0059] The source of the first transistor T1 is electrically connected to the first voltage line W1 via the fifth transistor T5, and the drain of the first transistor T1 is electrically connected to the anode of the light emitting element LD via the sixth transistor T6. The first transistor T1 may be referred to as a driving transistor. The first transistor T1 controls the amount of current flowing through the light emitting element LD in response to a voltage applied to the gate. The gate of the first transistor T1 may be referred to as a reference node ND.

[0060] The second transistor T2 is electrically connected between the data line DL and the first transistor T1, and the gate of the second transistor T2 is electrically connected to the i-th scan line SLi. The second transistor T2 may be referred to as a switching transistor.

[0061] The third transistors T3-1 and T3-2 are electrically connected between the gate and drain of the first transistor T1. In this embodiment, two third transistors T3-1 and T3-2 connected in series to each other are illustrated as an example. However, the present invention is not limited thereto, and n (where n is a natural number equal to or greater than 1) third transistors may be connected in series between the gate and drain of the first transistor T1. The gates of the third transistors T3-1 and T3-2 are electrically connected to the i-th scan line SLi.

[0062] The fourth transistors T4-1 and T4-2 are electrically connected between the reference node ND and the second voltage line VL2. In this embodiment, two fourth transistors T4-1 and T4-2 connected in series to each other are illustrated as an example. However, the present invention is not limited thereto, and n (here, n is a natural number equal to or greater than 1) fourth transistors may be electrically connected between the reference node ND and the second voltage line VL2. The gates of the fourth transistors T4-1 and T4-2 are electrically connected to the i-1th scan line SLi-1.

[0063] The fifth transistor T5 is electrically connected between the first voltage line VL1 and the source of the first transistor T1. The gate of the fifth transistor T6 is electrically connected to the i-th emission control line ECLi.

[0064] The sixth transistor T6 is electrically connected between the drain of the first transistor T1 and the anode electrode of the light emitting element LD, and the gate of the sixth transistor T6 is electrically connected to the i-th emission control line ECLi.

[0065] The seventh transistor T7 is electrically connected between the second voltage line VL2 and the anode electrode of the light emitting element LD, and the gate of the seventh transistor T7 is electrically connected to the (i+1)th scan line SLi+1.

[0066] The capacitor CP is disposed between the first voltage line VL1 and the reference node ND. The capacitor CP stores a voltage corresponding to a data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined according to the voltage stored in the capacitor CP.

[0067] 2 and 3, the light emission control signal Ei may have a high level E-HIGH or a low level E-LOW, and the scan signals SLi-1, SLi, and SLi+1 may have a high level S-HIGH or a low level S-LOW.

[0068] When the emission control signal Ei has a high level E-HIGH, the fifth transistor T5 and the sixth transistor T6 are turned off. The period when the emission control signal Ei has a high level E-HIGH may be defined as a non-emission period of the light emitting element LD.

[0069] If the (i-1)th scan signal Si-1 provided to the (i-1)th scan line SLi-1 has a low level S-LOW, the fourth transistors T4-1 and T4-2 are turned on. When the fourth transistors T4-1 and T4-2 are turned on, the initialization voltage Vint is provided to the reference node ND. The reference node ND and the capacitor CP are initialized to the initialization voltage Vint.

[0070] If the i-th scan signal Si provided to the i-th scan line SLi has a low level S-LOW, the second transistor T2 and the third transistor T3 are turned on. If the second transistor T2 is turned off, the data signal is provided to the first transistor T1. If the i-th scan signal Si has a low level S-LOW, the first transistor T1 is connected in the form of a diode between the second transistor T2 and the third transistor T3. If the first transistor T1 is turned on, a voltage corresponding to the data signal is provided to the reference node ND. The voltage corresponding to the data signal may be a voltage that is reduced from the data signal by a threshold voltage of the first transistor T1. The capacitor CP stores the voltage corresponding to the data signal.

[0071] If the (i+1)th scan signal Si+1 has a low level S-LOW, the seventh transistor T7 is turned on, and the initialization voltage Vint is provided to the anode electrode of the light emitting element LD, thereby discharging the parasitic capacitor of the light emitting element LD.

[0072] When the emission control signal Ei provided to the i-th emission control line ECLi has a low level E-LOW, the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the first power supply voltage EVLDD is provided to the first transistor T1. When the sixth transistor T6 is turned on, the first transistor T1 and the light emitting element LD are electrically connected. Then, the light emitting element LD generates light of a predetermined brightness corresponding to the amount of current provided. Therefore, the section in which the emission control signal Ei has a low level E-LOW can be defined as the light emitting section of the light emitting element LD.

[0073] FIG. 4 is a cross-sectional view of a display panel DP corresponding to a pixel PX according to an embodiment of the present invention.

[0074] Fig. 5a is a plan view of a pixel PX according to an embodiment of the present invention, and Figs. 5b to 5g are plan views showing stacking orders of patterns included in the pixel PX according to an embodiment of the present invention.

[0075] 4, the display panel DP may include a base layer BS, a circuit element layer DP-CL disposed on the base layer BS, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. The display panel DP may further include a functional layer such as an anti-reflection layer or a refractive index adjustment layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. The insulating layers described below may include an organic layer and / or an inorganic layer.

[0076] An insulating layer, a semiconductor layer, and a conductive layer are formed by processes such as coating, deposition, etc. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography and etching processes. By such processes, a semiconductor pattern, a conductive pattern, a signal line, etc. are formed. Patterns disposed in the same layer are formed by the same process.

[0077] The base layer BS may include a synthetic resin film. The synthetic resin film may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, but the material is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a ferrylene resin. In addition, the base layer may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0078] At least one inorganic layer is formed on the upper surface of the base layer BS. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of multiple layers. The multiple inorganic layers may constitute a barrier layer BRL and / or a buffer layer BFL, which will be described later. The barrier layer BRL and the buffer layer BFL may be disposed optionally.

[0079] The barrier layer BRL reduces or prevents foreign matter from entering from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. A plurality of each of these may be provided, and the silicon oxide layers and the silicon nitride layers may be stacked alternately.

[0080] The buffer layer BFL improves the bonding strength between the base layer BS and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0081] A semiconductor pattern SCP may be disposed on the buffer layer BFL. The semiconductor pattern may include an amorphous or crystalline silicon semiconductor. As shown in FIG. 4, the semiconductor pattern SCP may include a first semiconductor region AC1 and a second semiconductor region AC2. The first semiconductor region AC1 may include a source region S1, a channel region A1, and a drain region D1 of the first transistor T1, and the second semiconductor region AC2 may include a source region S2, a channel region A2, and a drain region D2 of the second transistor T2. The source and drain of the transistor described with reference to FIG. 2 may be described as a source region and a drain region in describing the semiconductor region.

[0082] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 covers the semiconductor pattern SCP. The first insulating layer 10 is an organic layer or an inorganic layer. The second to sixth insulating layers 20 to 60 described later are also organic layers or inorganic layers, but are not limited thereto.

[0083] A first conductive layer CL1 is disposed on the first insulating layer 10. The first conductive layer CL1 may include a plurality of conductive patterns. The first insulating layer CL1 may include a gate G1 of the first transistor and a gate G2 of the second transistor.

[0084] A second insulating layer 20 is disposed on the first insulating layer 10, covering the first conductive layer CL1. A second conductive layer CL2 is disposed on the second insulating layer 20. The second conductive layer CL2 includes a plurality of conductive patterns. The second conductive layer CL2 includes an upper electrode UE. The upper electrode UE overlaps the gate G1 of the first transistor T1, and an opening UE-OP is formed. The overlapping upper electrode UE and the gate G1 of the first transistor T1 define a capacitor CP (see FIG. 2).

[0085] A third insulating layer 30 is disposed on the second insulating layer 20 to cover the second conductive layer CL2. A third conductive layer CL3 is disposed on the third insulating layer 30. The third conductive layer CL3 includes a plurality of conductive patterns. The third conductive layer CL3 includes a connecting electrode CNE-G3. One connecting electrode CNE-G3 is connected to the gate G1 of the first connecting electrode T1 through a contact hole CH10 penetrating the second insulating layer 20 and the third insulating layer 30. The contact hole CH10 passes through the opening UE-OP. The other connecting electrode CNE-G3 may be connected to the source region S2 of the second transistor T2 through a contact hole CH20 penetrating the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The third conductive layer CL3 may further include a plurality of connecting electrodes (not shown).

[0086] A fourth insulating layer 40 is disposed on the third insulating layer 30 to cover the third conductive layer CL3. A fourth conductive layer CL4 is disposed on the fourth insulating layer 40. The fourth conductive layer CL4 may include a plurality of conductive patterns. The fourth conductive layer CL4 may include connecting electrodes CNE-D1. The connecting electrodes CNE-D1 may be connected to corresponding connecting electrodes CNE-G3 via contact holes CH11 and CH21 penetrating the fourth insulating layer 40.

[0087] A fifth insulating layer 50 is disposed on the fourth insulating layer 40 to cover the fourth conductive layer CL4. A fifth conductive layer CL5 is disposed on the fifth insulating layer 50. The fifth conductive layer CL5 may include a plurality of conductive patterns. The fifth conductive layer CL5 may include a data line DL. The data line DL may be connected to a corresponding connecting electrode CNE-D1 through a contact hole CH22 penetrating the fifth insulating layer 50.

[0088] A sixth insulating layer 60 covering the fifth conductive layer CL5 is disposed on the fifth insulating layer 50. A light emitting element LD is disposed on the sixth insulating layer 60. A first electrode AE ​​of the light emitting element LD is disposed on the sixth insulating layer 60. The first electrode AE ​​may be an anode. A pixel defining film PDL is disposed on the sixth insulating layer 60.

[0089] The opening OP of the pixel defining film PDL exposes at least a portion of the first electrode AE. The opening OP of the pixel defining film PDL defines a light emitting region. An emitting layer EML is disposed on the first electrode AE. In this embodiment, a patterned emitting layer EML is illustrated as an example, but the emitting layer EML may be disposed in common to a plurality of pixels PX (see FIG. 1). The emitting layer EML disposed in common may generate white light or blue light. The emitting layer EML may have a multi-layer structure.

[0090] Although not shown, a hole transport layer may be further disposed between the first electrode AE ​​and the light emitting layer EML. A hole injection layer may be further disposed between the hole transport layer and the first electrode AE. The hole transport layer or the hole injection layer may be disposed in common to a plurality of pixels PX (see FIG. 1).

[0091] A second electrode CE is disposed on the light-emitting layer EML. Although not shown, an electron transport layer may be further disposed between the second electrode CE and the light-emitting layer EML. An electron injection layer may be further disposed between the electron transport layer and the second electrode CE. The electron transport layer or the electron injection layer may be disposed in common to a plurality of pixels PX (see FIG. 1).

[0092] A thin film encapsulation layer TFE is disposed on the second electrode CE. The thin film encapsulation layer TFE is disposed in common to a plurality of pixels PX (see FIG. 1). In this embodiment, the thin film encapsulation layer TFE directly covers the second electrode CE. In one embodiment of the present invention, a capping layer directly covering the second electrode CE may be further disposed. The thin film encapsulation layer TFE includes at least an inorganic layer or an organic layer. In one embodiment of the present invention, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed therebetween. In one embodiment of the present invention, the thin film encapsulation layer TFE includes a plurality of inorganic layers and a plurality of organic layers that are alternately stacked.

[0093] 5a, the first to seventh transistors T1 to T7 of the pixel PX are shown, as well as scan lines SLi-1, SLi, SLi+1, a light emitting control line ECLi, a first voltage line VLi, and a second voltage line VL2.

[0094] Referring to Fig. 5b, a semiconductor pattern SCP is disposed on a base layer BS (see Fig. 4). The semiconductor pattern SCP includes first to seventh semiconductor regions AC1 to AC7 corresponding to first to seventh transistors T1 to T7 (see Fig. 2).

[0095] Each of the first to seventh semiconductor regions AC1 to AC7 includes a corresponding source region S1 to S7, a corresponding channel region A1 to A7, and a corresponding drain region D1 to D7. The source regions S1 to S7 and the drain regions D1 to D7 are highly doped and substantially conductive regions, and the channel regions A1 to A7 are lightly doped regions disposed between the source regions S1 to S7 and the drain regions D1 to D7. The source and drain of each of the first to seventh transistors T1 to T7 are substantially defined by the respective source regions S1 to S7 and drain regions D1 to D7 of the first to seventh semiconductor regions AC1 to AC7.

[0096] The first to seventh semiconductor regions AC1 to AC7 may have an integral shape. The source regions S1 to S7 and the drain regions D1 to D7 of adjacent semiconductor regions among the first to seventh semiconductor regions AC1 to AC7 may not be separated from each other. In FIG. 5b, the source regions S1 to S7 and the drain regions D1 to D7 of adjacent semiconductor regions are shown separated for convenience of explanation. Also, the signal cut-off region STA is shown to be disposed between the source regions S1 to S7 and the drain regions D1 to D7 of different semiconductor regions among the first to seventh semiconductor regions AC1 to AC7, but is not limited thereto. The signal cut-off region STA may be a region having the same doping concentration as the source regions S1 to S7 or the drain regions D1 to D7.

[0097] 5c, a first conductive layer CL1 is disposed on a first insulating layer 10 (see FIG. 4). The first conductive layer CL1 may include scan lines SLi-1, SLi, and SLi+1 extending in a first direction DR1, a light emission control line ECLi, and a first gate G1.

[0098] A portion of the i-th scan line SLi overlapping the semiconductor pattern SCP may be the gate G2 of the second transistor T2, another portion of the i-th scan line SLi may be the gate G31 of one third transistor T3-1, and still another portion of the i-th scan line SLi may be the gate G32 of another third transistor T3-2.

[0099] Figure 5c shows gates G41 and G42 of the fourth transistors T4-1 and T4-2 arranged on the i-1th scan line SLi-1, shows a gate G72 of the seventh transistor T7 arranged on the i+1th scan line SLi+1, and shows a gate G5 of the fifth transistor T5 and a gate G6 of the sixth transistor T6 arranged on the i-th light emission control line ECLi.

[0100] Referring to Fig. 5d, a second conductive layer CL2 is disposed on the second insulating layer 20 (see Fig. 4). The second conductive layer CL2 includes an upper electrode UE and a second voltage line VL2. The second voltage line VL2 extends in a first direction DR1. The second conductive layer CL2 includes a plurality of second voltage lines VL2, which are arranged in a second direction DR2.

[0101] 5e, a third conductive layer CL3 is disposed on the third insulating layer 30 (see FIG. 4). The third conductive layer CL3 includes the connecting electrode CNE-G3 described with reference to FIG.

[0102] The third conductive layer CL3 may further include a dummy line DML. The dummy line DML may extend in a first direction DR1. The third conductive layer CL3 may include a plurality of dummy lines DML, and the plurality of dummy lines DML are arranged in a second direction DR2. The plurality of dummy lines DML according to this embodiment is merely an example, and the plurality of dummy lines DML may extend in the second direction DR2.

[0103] The plurality of dummy lines DML may receive a ground voltage or may be floating. In one embodiment of the present invention, the plurality of dummy lines DML may be electrically connected to a plurality of second voltage lines VL2 shown in Fig. 5d. In one embodiment of the present invention, the plurality of dummy lines DML may be electrically connected to a plurality of first voltage lines VL1 shown in Fig. 5f, which will be described later.

[0104] 5f, a fourth conductive layer CL4 is disposed on the fourth insulating layer 40 (see FIG. 4). The fourth conductive layer CL4 may include a first voltage line VL1 and a plurality of connecting electrodes. The plurality of connecting electrodes may include the connecting electrode CNE-D1 described with reference to FIG. 4.

[0105] 5g, a fifth conductive layer CL5 is disposed on the fifth insulating layer 50 (see FIG. 4). The fifth conductive layer CL5 may include a data line DL and a connecting electrode CNE. The first electrode AE ​​in FIG. 4 may be connected to the connecting electrode CNE in FIG. 5g.

[0106] 6a is a plan view of the third transistors T3-1 and T3-2 according to an embodiment of the present invention. FIGs. 6b and 6c are cross-sectional views of the third transistors T3-1 and T3-2 corresponding to I-I' in FIG. 6a. FIG. 6d is a graph showing the voltage V of the transistor according to the comparative example and the transistor according to the embodiment of the present invention. GS -Current I DS 6c is a graph showing the operation of the first transistor T1 and the third transistors T3-1 and T3-2 in a light emission period corresponding to a high gray level data signal. FIG. 6e is a cross-sectional view showing a doping process of the transistor T3-1. FIG. 6f is a circuit diagram showing the operation of the first transistor T1 and the third transistors T3-1 and T3-2 in a light emission period corresponding to a high gray level data signal. FIG. 6g is a circuit diagram showing the operation of the first transistor T1 and the third transistors T3-1 and T3-2 in a light emission period corresponding to a middle gray level data signal.

[0107] FIG. 6a shows an enlarged view of the third transistors T3-1 and T3-2 shown in FIG. 2, FIG. 5a to FIG. 5g. Referring to FIG. 6a and FIG. 6b, the third transistor T3-1, which is closer to the gate of the first transistor T1 (see FIG. 2) in the current path of the two third transistors T3-1 and T3-2, is defined as the left transistor T3-1, and the third transistor T3-2, which is disposed farther from the gate of the first transistor T1 (see FIG. 2), is defined as the right transistor T3-2. Referring to FIG. 6b, the semiconductor pattern SCP shows the semiconductor region AC31 of the left transistor T3-1 and the semiconductor region AC32 of the right transistor T3-2.

[0108] 6a and 6b, as described above, since the third transistors T3-1 and T3-2 are P-type transistors, the drain region D31 of the left transistor T3-1 is arranged to be closer to the gate region of the first transistor T1 (see FIG. 2) than the source region S31 of the left transistor T3-1, and the drain region D32 of the right transistor T3-2 is arranged to be closer to the gate of the first transistor T1 (see FIG. 2) than the source region S32 of the right transistor T3-2.

[0109] Each of the drain regions D31, D32 and source regions S32, S32 of the third transistors T3-1, T3-2 may include a high doping region 1 having a relatively high doping concentration and a low doping region 2 having a relatively low doping concentration. The low doping region 2 may be disposed between the high doping region 1 and the corresponding channel region A31, A32.

[0110] Hereinafter, the highly doped region 1 of each of the drain regions D31, D32 and the source regions S31, S32 may be referred to as a first region, and the lightly doped region 2 may be referred to as a second region. If the highly doped region 1 and the lightly doped region 2 in any one of the drain regions D31, D32 and the source regions S31, S32 are referred to as a first region and a second region, respectively, in order to distinguish the highly doped region 1 or the lightly doped region 2, the highly doped region 1 and the lightly doped region 2 in the other one of the drain regions D31, D32 and the source regions S31, S32 may be referred to as a third region and a fourth region, respectively.

[0111] The doping concentration of the first region 1 is about 1×10 20 / cm 3 The doping concentration of the second region 2 may be about 5% to 20% of the doping concentration of the first region 1. Meanwhile, since the gates G31 and G32 of the third transistors T3-1 and T3-2, respectively, act as masks, the channel regions A31 and A32 may have a very low doping concentration.

[0112] 6a and 6b, each of the source region S31 of the left transistor T3-1 and the drain region D32 of the right transistor T3-2 may not include the second region 2. Although the doping concentrations of the first region 1 and the second region 2 are determined by a doping method, the doping concentrations of the source region S31 of the left transistor T3-1 and the drain region D32 of the right transistor T3-2 may be controlled to be substantially the same.

[0113] For example, additional doping may be performed on the second region 2 of each of the source region S31 of the left transistor T3-1 and the drain region D32 of the right transistor T3-2 such that the second region 2 is removed. In one embodiment of the present invention, the doping concentration of the source region S31 of the left transistor T3-1 and the drain region D32 of the right transistor T3-2 may be increased to control the difference in doping concentration between the first region 1 and the second region 2 to a lower level than the doping concentration of the first region 1 and the second region 2.

[0114] As shown in Fig. 6b, the boundary between the first region 1, the second region 2, and the channel regions A31, A32 may be straight on the cross section, but as shown in Fig. 6c, the boundary between the first region 1, the second region 2, and the channel regions A31, A32 may be curved on the cross section. In Fig. 6c, the doping concentration of the second region 2 adjacent to the channel regions A31, A32 may have a Gaussian distribution according to the linear distance from the top surface of the semiconductor pattern SCP.

[0115] The second region 2 prevents a sudden increase in the electric field between the channel regions A31, A32 and the drain regions D31, D32 or the source regions S31, S32 (hereinafter referred to as the drain / source field reduction effect). This reduces the off-current (or leakage current) of the third transistors T3-1, T3-2, and also suppresses the hot carrier effect (HCE) that occurs due to the shortened length of the channel regions A31, A32.

[0116] 6d shows the off-current of a transistor with and without the second region 2. The first graph G10 shows the voltage V GS -Current I DS The second graph G10 shows the characteristics of the voltage V GS -Current I DS The gate-source voltage V GSIt can be seen that the leakage current of the P-type transistor according to this embodiment is reduced in the range where the voltage is 5V or more.

[0117] This is due to the drain / source field reduction effect, which reduces the gate induced drain leakage current (I GIDL This is because the leakage current I GIDL is given by the following formula, where the drain-gate field is reduced and the leakage current I GIDL In the formula, the exponential factor E x(DL) denotes the field value formed between the drain and gate.

[0118] TIFF2024527731000002.tif19161

[0119] In order for the drain / source field reduction effect to occur, the second region 2 should have a certain resistance. The resistance of the second region 2 is inversely proportional to the thickness, the length, and the width. In the integral semiconductor pattern SCP, the length and the width of the second region 2 can be controlled to control the resistance of the second region 2.

[0120] As shown in Figures 6a and 6b, the resistance of the second region 2 may be controlled by changing the width. The width W1 of the second region 2 in the drain region D31 of the left transistor T3-1 may be smaller than the width W0 of the first region 1 in the drain region D31 of the left transistor T3-1. The width W2 of the second region 2 in the source region S32 of the right transistor T3-2 may be smaller than the width W0 of the first region 1 in the source region S32 of the right transistor T3-2. The width is measured in a reference direction perpendicular to the extension direction of the semiconductor pattern SCP, while the length is measured in the extension direction of the semiconductor pattern SCP.

[0121] Assuming that the lengths of the second regions 2 are the same, a relatively large drain / source field reduction effect occurs in the second region 2 of the drain region D31 of the left transistor T3-1 and the second region 2 of the source region S32 of the right transistor T3-2. If the length of the second region 2 is shorter than a reference value, some of the second regions 2 may have a relatively small resistance, and the drain / source field reduction effect may not occur in the second region 2. Even if the second regions 2 have the same length, some of the second regions 2 may have a relatively small width and therefore may have a relatively large resistance. The drain / source field reduction effect may occur in the second region 2 having a relatively small width. For example, the second region 2 of the drain region D31 of the left transistor T3-1 and the second region 2 of the source region S32 of the right transistor T3-2 each have a large resistance due to the small widths W1 and W2, and therefore the drain / source field reduction effect may occur.

[0122] The width W0 of the first region 1 and the second region 2 in the source region S31 of the left transistor T3-1 may be substantially the same, and the width W0 of the first region 1 and the second region 2 in the drain region D32 of the right transistor T3-2 may be substantially the same. The width W0 of the source region S31 of the left transistor T3-1 and the drain region D32 of the right transistor T3-2 may be substantially the same. It is possible that the drain / source field reduction effect does not occur in the source region S31 of the left transistor T3-1 and the drain region D32 of the right transistor T3-2, which have a relatively large width W0.

[0123] The widths W1 and W2 of the second region 2 in the drain region D31 of the left transistor T3-1 and the source region S32 of the right transistor T3-2 may be 1 μm to 2 μm. The widths W1 and W2 of the second region 2 may be 1.5 μm. The width W1 of the second region 2 in the drain region D31 of the left transistor T3-1 and the width W2 of the second region 2 in the source region S32 of the right transistor T3-2 are not limited to be the same. The widths W1 and W2 of the second region 2 in the drain region D31 of the left transistor T3-1 and the source region S32 of the right transistor T3-2 may be 10% to 50% smaller than the width of the first region 1.

[0124] 6e shows a doping step according to an embodiment. According to this embodiment, after forming the second insulating layer 20, the semiconductor region AC3 of the transistor T3-1 can be doped using the gate G31 as a mask. For example, 1×10 15 / cm 2 The doping concentration may be 0.01 to 0.01.

[0125] Fig. 6e shows a cross section corresponding to X-X' of Fig. 5c by way of example. The first, second, fourth to seventh semiconductor regions AC1, AC2, AC4 to AC7 may also be doped as shown in Fig. 6e or may be doped using an additional mask, and the method is not particularly limited.

[0126] Referring to FIG. 6e, the second insulating layer 20 is disposed along the inclined side surface of the gate G31. The region of the second insulating layer 20 corresponding to the inclined side surface of the gate G31 (hereinafter, the inclined region) has a thickness greater than that of the region corresponding to the plane of the second insulating layer 20, based on the upper surface of the first insulating layer 10. In the inclined region of the second insulating layer 20, the distance DT2 between the upper surface of the second insulating layer 20 and the semiconductor region AC3 may be greater than the distance DT1 between the upper surface of the second insulating layer 20 and the semiconductor region AC3 in the plane region of the second insulating layer 20. The inclined region corresponds to a region that prevents doping, which may correspond to a mask pattern.

[0127] The drain region D31 and the source region S31 are defined in a second region 2 corresponding to the sloped region of the second insulating layer 20. The length of the sloped region, i.e., the length of the second region 2, may be determined according to the thickness of the gate G31. In this embodiment, the thickness of the gate G31 may be 3000 Å to 5000 Å.

[0128] The lengths L1 and L2 of the drain region D31 of the left transistor T3-1 and the second region 2 of the source region S32 of the right transistor T3-2 may be 0.1 μm to 0.5 μm, respectively. The length L1 of the second region 2 in the drain region D31 of the left transistor T3-1 and the length L2 of the second region 2 in the source region S32 of the right transistor T3-2 are not necessarily the same. Depending on the doping process, the length of the second region 2 in the source region S31 of the left transistor T3-1 and the length of the second region 2 in the drain region D32 of the right transistor T3-1 may be determined within the range of the lengths L1 and L2 of the second region 2 described above.

[0129] The operation of the first transistor T1 and the third transistors T3-1 and T3-2 corresponding to the data voltage of a high gray level in the light emitting period will be described with reference to FIG. 6f.

[0130] The voltage of the gate G1 of the first transistor T1 may be 1V to correspond to the high gray level data voltage charged in the capacitor CP (see FIG. 2). At this time, the voltage of the drain D1 of the first transistor T1 may be 2V. The voltage of the source S32 of the right transistor T3-2 may also be 2V. During the light-emitting period, the third transistors T3-1 and T3-2 are turned off, and a leakage current may occur from the source S32 of the right transistor T3-2 to the drain D31 of the left transistor T3-1. In addition, when the third transistors T3-1 and T3-2 are turned off from turned on, the voltage at the intermediate node S31 / D32 between the right transistor T3-2 and the left transistor T3-1 may rise due to the influence of the kickback voltage (or parasitic capacitance), and a leakage current may occur from the intermediate node S31 / D32 to the drain D31 of the left transistor T3-1. If leakage current occurs, the voltage of the gate G1 increases, and the light emitting element LD (see FIG. 2) may emit light with a luminance lower than the desired gray scale.

[0131] 6a and 6b, the above-mentioned drain / source field reduction effect occurs at least in the second region 2 of the drain D31 of the left transistor T3-1, and the leakage current can be reduced or prevented.

[0132] The operation of the first transistor T1 and the third transistors T3-1 and T3-2 corresponding to the data voltage of the intermediate gray level in the light emitting section will now be described with reference to FIG. 6g.

[0133] The voltage of the gate G1 of the first transistor T1 may be 3V to correspond to the data voltage of the intermediate gray scale charged in the capacitor CP (see FIG. 2). In this case, the voltage of the source S32 of the right transistor T3-2 may be 2V. Although the third transistors T3-1 and T3-2 are turned off during the light emitting period, a leakage current may occur from the drain D31 of the left transistor T3-1 or the intermediate node S31 / D32 to the source S32 of the right transistor T3-2. If a leakage current occurs, the voltage of the gate G1 decreases, and the light emitting element LD (see FIG. 2) may emit light with a brightness brighter than the desired gray scale.

[0134] 6a and 6b, the above-mentioned drain / source field reduction effect occurs at least in the second region 2 of the source S32 of the right-side transistor T3-2, reducing or preventing the leakage current.

[0135] Fig. 7a is a circuit diagram of the third transistors T3-1 to T3-3 according to an embodiment of the present invention. Fig. 7b is a plan view of the third transistors T3-1 to T3-3 according to an embodiment of the present invention. Fig. 7c is a circuit diagram of the third transistor T3 according to an embodiment of the present invention. Fig. 7d is a plan view of the third transistor T3 according to an embodiment of the present invention. Hereinafter, detailed description of the configurations described with reference to Figs. 1 to 6g will be omitted.

[0136] 7a, n (where n is a natural number equal to or greater than 2) third transistors T3-1 to T3-3 are connected in series between the gate G1 and drain D1 of the first transistor T1. In this embodiment, n is 3.

[0137] 7a and 7b, the drain region D31 of the leftmost transistor T3-1, which is closest to the gate G1 of the first transistor T1 in the current path between the gate G1 and the drain D1 of the first transistor T1, includes a first region 1 and a second region 2. The source region S33 of the rightmost transistor T3-3, which is farthest from the gate G1 of the first transistor T1, includes a first region 1 and a second region 2.

[0138] 7b, the second region 2 of the drain region D31 in the leftmost transistor T3-1 and the second region 2 of the source region S33 in the rightmost transistor T3-3 may have a relatively small width. The source region S31 in the leftmost transistor T3-1 and the drain region D33 in the rightmost transistor T3-3 may have substantially the same width. The drain region D32 and the source region D32 in the intermediate transistor T3-2 may have substantially the same width.

[0139] As described with reference to Figures 6f and 6g, in an emission period corresponding to a high gray level data voltage, leakage current can be reduced or prevented by the leftmost transistor T3-1, and in an emission period corresponding to a mid-gray level data voltage, leakage current can be reduced or prevented by the rightmost transistor T3-3.

[0140] Referring to Fig. 7c, a third transistor T3 is connected between the gate G1 and drain D1 of the first transistor T1. Referring to Fig. 7d, the second region 2 of the drain region D31 and the second region 2 of the source region S31 of the third transistor T3 may have a width smaller than other regions of the semiconductor pattern SCP. It is possible that no leakage current occurs in the third transistor T3.

[0141] Fig. 8a is a plan view of the fourth transistors T4-1 and T4-2 according to an embodiment of the present invention. Fig. 8b is a circuit diagram showing the operation of the first transistor T1 and the fourth transistors T4-1 and T4-2 in the light emitting section. Hereinafter, detailed description of the configurations described with reference to Figs. 1 to 6g will be omitted.

[0142] Although two transistors T4-1 and T4-2 are shown by way of example, one or more than two transistors may be connected in series between the gate G1 of the first transistor T1 and the second voltage line VL2.

[0143] According to this embodiment, in the current path between the gate G1 of the first transistor T1 of the fourth transistors T4-1, T4-2 and the second voltage line VL2, the transistor closer to the gate G1 of the first transistor T1 is the left transistor T4-1, and the transistor located farther from the gate G1 of the first transistor T1 is the right transistor T4-2.

[0144] According to this embodiment, at least the second region 2 of the source region S41 of the left transistor T4-1 and the second region 2 of the drain region D42 of the right transistor T4-2 have a relatively small width. The initialization voltage Vint is a bias voltage of -2V to -3V. Since the gate G1 of the first transistor T1 has a voltage of 1V to 4V during the light-emitting period, a leakage current path is formed from the gate G1 of the first transistor T1 to the second voltage line VL2. The drain region D42 of the right transistor T4-2 reduces or prevents the occurrence of such leakage current.

[0145] The source region S41 of the left transistor T4-1 prevents a temporary leakage current from flowing from the intermediate node S41 / D42 between the fourth transistors T4-1 and T4-2 to the gate G1 of the first transistor T1 during the light-emitting period.

[0146] Fig. 9a is a plan view of a first transistor T1 according to an embodiment of the present invention. Fig. 9b is a cross-sectional view of the first transistor T1 corresponding to II-II' of Fig. 9a. Hereinafter, detailed description of the configuration described with reference to Figs. 1 to 8b will be omitted.

[0147] The first transistor T1 includes a semiconductor region AC1 including a source region S1, a drain region D1, and a channel region A1 disposed therebetween, and a gate G1 overlapping the channel region A1. The first transistor T1 may also be doped in the same manner as described with reference to FIG. 6e. Accordingly, the source region S1 and the drain region D1 may each include a first region 1 and a second region 2.

[0148] If the second region 2 generates a drain / source field reduction effect, the driving current of the first transistor T1 may be reduced when the first transistor T1 is turned on. According to the present embodiment, the resistance of the second region 2 may be designed to be greater than a reference value so that the second region 2 does not have a drain / source field reduction effect. To reduce the resistance of the second region 2, the width W4 of the second region 2 may be greater than the width W3 of the channel region A1. The width W4 of the second region 2 may be 5% to 20% greater than the width W3 of the channel region A1.

[0149] The source region S1 and the drain region D1 may have a width greater than the width of the channel region A1 as a whole. The source region S1 may have a uniform width, and the drain region D1 may have a uniform width.

[0150] The width W4 of the source region S1 or the drain region D1 of the first transistor T1 may be greater than the widths of the source regions S31, S32 or the drain regions D31, D32 of the third transistors T3-1, T3-2 shown in Figures 6a and 6b. The integral semiconductor pattern SCP shown in Figure 5b may be patterned to have different widths depending on the region.

[0151] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or those having ordinary knowledge in the art that various modifications and variations of the present invention can be made without departing from the spirit and technical scope of the present invention as set forth in the claims below.

[0152] Therefore, the technical scope of the present invention should be determined not by the contents described in the detailed description of the specification, but by the claims. [Industrial Applicability]

[0153] According to the present embodiment, the performance of the pixel driving circuit can be improved by changing the transistor design. The pixel driving circuit is an essential component of a display device, and the present invention is highly likely to be applied to the display device.

Claims

1. A first transistor; a second transistor electrically connected to the first transistor and configured to output a data signal; n (where n is a natural number equal to or greater than 2) third transistors electrically connected to the gate of the first transistor and connected in series with each other; a capacitor for charging a voltage corresponding to the data signal; a light emitting element electrically connected to the first transistor, Each of the n third transistors a semiconductor region including a channel region and a source region and a drain region disposed in an extension direction with the channel region therebetween; a gate overlying the channel region; a region of the source region or the drain region of a third transistor among the n third transistors that is closest to the gate of the first transistor includes the first region and a second region between the first region and the channel region; the second region has a lower doping concentration than the first region; A display device in which the width of the second region is smaller than the width of the first region in a reference direction perpendicular to the extension direction.

2. a region of the source region or the drain region of a third transistor that is disposed farthest from the gate of the first transistor among the n third transistors includes the third region and a fourth region between the third region and the channel region; the fourth region has a lower doping concentration than the third region; The display device according to claim 1 , wherein a width of the fourth region in the reference direction is smaller than a width of the third region.

3. a region of the source region or the drain region of a third transistor among the n third transistors that is closest to the gate of the first transistor includes the third region and a fourth region between the third region and the channel region; The display device according to claim 1 , wherein the fourth region has a doping concentration lower than that of the third region.

4. The display device according to claim 3 , wherein the third region and the fourth region have substantially the same width in the reference direction.

5. The display device according to claim 1 , wherein the width of the second region in the reference direction is 1 μm to 2 μm.

6. The display device of claim 1 , wherein the width of the second region is 10% to 50% smaller than the width of the first region.

7. The display device of claim 1 , wherein the length of the second region in the extension direction is 0.1 μm to 0.5 μm.

8. the first transistor and the n third transistors include P-type polysilicon transistors; The display device of claim 1 , wherein the n third transistors are connected in series between the gate of the first transistor and a source region or a drain region of a semiconductor region of the first transistor.

9. 9. The display device according to claim 8, wherein the source region of the third transistor among the n third transistors that is closest to the gate of the first transistor and the drain region of the third transistor that is disposed farthest from the gate of the first transistor have substantially the same width in the reference direction.

10. 9. The display device according to claim 8, wherein the drain region and the source region of a third transistor, among the n third transistors, arranged between the third transistor closest to the gate of the first transistor and the third transistor arranged farthest from the gate of the first transistor, have substantially the same width in the reference direction.

11. the first transistor includes a channel region overlapping the gate of the first transistor, and a semiconductor region including a source region and a drain region sandwiching the channel region therebetween; The display device according to claim 1 , wherein a width of at least one of the source region of the first transistor and the drain region of the first transistor is larger than a width of the channel region of the first transistor.

12. The display device of claim 11, wherein a width of at least one of the source region of the first transistor and the drain region of the first transistor is 5% to 20% larger than a width of the channel region of the first transistor.

13. The source region of the first transistor and the drain region of the first transistor each include a third region and a fourth region between the third region and the channel region; the fourth region has a lower doping concentration than the third region; The display device according to claim 11 , wherein the third region and the fourth region have substantially the same width.

14. The display device according to claim 11 , wherein a width of the source region or the drain region of the first transistor is greater than a width of the semiconductor region of each of the n third transistors.

15. the first transistor and the n third transistors include P-type polysilicon transistors; The display device of claim 1 , wherein the n third transistors are coupled between the gate of the first transistor and a voltage line receiving an initialization voltage.

16. The display device of claim 1 , wherein the capacitor is electrically connected between the gate of the first transistor and a voltage line receiving a power supply voltage.

17. A first transistor; a second transistor electrically connected to the first transistor and configured to output a data signal; n (where n is a natural number equal to or greater than 2) third transistors electrically connected to the gate of the first transistor and connected in series with each other; a capacitor for charging a voltage corresponding to the data signal; a light emitting element electrically connected to the first transistor, Each of the n third transistors a semiconductor region including a channel region and a source region and a drain region disposed in an extension direction with the channel region therebetween; a gate overlying the channel region; a region of the source region or the drain region of a third transistor that is disposed farthest from the gate of the first transistor among the n third transistors includes the first region and a second region between the first region and the channel region; the second region has a lower doping concentration than the first region; A display device in which the width of the second region is smaller than the width of the first region in a reference direction perpendicular to the extension direction.

18. A first transistor; a second transistor electrically connected to the first transistor and configured to output a data signal; a third transistor electrically connected to the gate of the first transistor; a light emitting element electrically connected to the first transistor, The third transistor is a semiconductor region including a channel region and a drain region and a source region disposed on either side of the channel region in an extension direction; a gate overlying the channel region; At least one of the drain region and the source region includes a first region and a second region between the first region and the channel region; the second region has a lower doping concentration than the first region; A display device in which the width of the second region is smaller than the width of the first region in a reference direction perpendicular to the extension direction.

19. A first transistor; a second transistor electrically connected to the first transistor and configured to output a data signal; n (where n is a natural number equal to or greater than 1) third transistors electrically connected to the gate of the first transistor and connected in series with each other; a light emitting element electrically connected to the first transistor, Each of the first, second, and third transistors comprises: a semiconductor region including a channel region and a source region and a drain region disposed on either side of the channel region; a gate overlying the channel region; Each of the drain region and the source region includes a first region and a second region between the first region and the channel region, the second region having a lower doping concentration than the first region; A display device, wherein a width of each of the source region of the first transistor and the drain region of the first transistor is greater than a width of the channel region of the first transistor.

20. 20. The display device of claim 19, wherein a width of the drain region of the first transistor is 5% to 20% larger than a width of the channel region of the first transistor.

21. The display device according to claim 19 , wherein a width of the second region of the source region in the first transistor and a width of the second region of the drain region in the first transistor are substantially the same.

22. The display device according to claim 19 , wherein a width of the drain region in the first transistor is larger than a width of the drain region in each of the n third transistors.

23. 20. The display device of claim 19, wherein a width of at least one of the source regions of the n third transistors and the drain regions of the n third transistors is substantially the same as a width of the channel region in the n third transistors.

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