Switching amplifier with linearly transitional totem-pole modulation.

Abstract

A switching amplifier (106A) includes a first portion (242) of a power stage (144A), a second portion (252) of the power stage, a pulse width modulation (PWM) control loop (110A) coupled to the control inputs (130A, 132A) of the first portion of the power stage, and a linear amplifier (118A) coupled to the control inputs (134A, 136A) of the second portion of the power stage. The PWM control loop controls a first switch (S1, FIG. 3) and a second switch (S2, FIG. 3) of the first portion of the power stage. Between the current terminals of the first switch and the second switch is a first signal output (147A, FIG. 2; 147B, FIG. 3) of the switching amplifier. The linear amplifier controls a third switch (S3, FIG. 3) and a fourth switch (S4, FIG. 3) of the second portion of the power stage (252). Between the current terminals of the third switch and the fourth switch is a second signal output (149A, FIG. 2; 149B, FIG. 3) of the switching amplifier.

Description

[Technical field]

[0001] As new electronic devices are developed and integrated circuit (IC) technology advances, new IC products are commercialized. One example of an IC product for an electronic device is an analog signal chain or associated switching amplifier (e.g., a class-D amplifier). In some examples, the analog signal chain is part of an audio system for controlling the volume or equalization of an audio signal to be output to a speaker.

[0002] To provide the best sound quality for audio reproduction, a switching amplifier with low switching losses, low harmonic distortion, and low electromagnetic interference is desirable. An exemplary switching amplifier topology includes a power stage having high-side and low-side switches for each output (e.g., OUTP and OUTM), and a modulation control circuit configured to provide control signals for each switch of the power stage. Different modulation control circuit options differ with respect to performance and / or implementation costs.

[0003] In one conventional approach, the modulation control circuit implements "BD" or filterless modulation. With BD modulation, the duty cycle of the difference of the output signals is modulated so that its average value matches the input analog signal. Also, bridge-tied load (BTL) outputs are in phase with each other, not complementary, when idle. This results in zero voltage difference across the load, minimizing quiescent power consumption without the need for filters. With BD modulation, there is significant common mode content at the output, and costly filters are added to remove switching components in the speaker cable.

[0004] In another conventional approach, the modulation control circuit implements totem pole low side recycle (LSR) modulation. With totem pole LSR modulation, OUTP and OUTM may have toggling around zero crossings to ensure good total harmonic distortion (THD). If the toggling time is very short (only around zero crossings), the electromagnetic interference (EMI) pulses are small and no LC filter on OUTM is required. However, the minimum on-time for the driver switch is limited. If the input signal is very low (always around zero crossings), the duty cycle will be less than 10% and there may be many pulses on OUTM. This switching action on OUTM consumes power. Also, with totem pole LSR modulation, a "pop" noise is introduced when OUTM transitions from a switching state to a low dropout regulator (LDO) direct current (DC) voltage. Summary of the Invention

[0005] In one exemplary embodiment, a switching amplifier includes a first portion of a power stage. The first portion includes a first control input, a second control input, a first switch having a first control terminal coupled to the first control input, and a second switch having a second control terminal coupled to the second control input. The switching amplifier also includes a second portion of a power stage. The second portion includes a third control input, a fourth control input, a third switch having a third control terminal coupled to the third control input, and a fourth switch having a fourth control terminal coupled to the fourth control input. The switching amplifier further includes a first signal output between a current terminal of the first switch and the second switch, and a second signal output between a current terminal of the third switch and the fourth switch. The switching amplifier additionally includes a pulse width modulation (PWM) control loop having a first source signal input, a second source signal input, a first feedback input coupled to the first signal output, a second feedback input coupled to the second signal output, a first PWM control loop output coupled to the first control input, and a second PWM control loop output coupled to the second control input. The switching amplifier also includes a linear amplifier having an amplifier input, a first amplifier output, and a second amplifier output. The amplifier input is coupled to the second source signal input. The first amplifier output is coupled to the third control input. The second amplifier output is coupled to the fourth control input.

[0006] In another exemplary embodiment, a system includes a switching amplifier having a first source signal input, a second source signal input, a first signal output, and a second signal output. The switching amplifier is configured to provide a first output signal at the first signal output based on a PWM control loop that receives a first source signal from the first source signal input, a second source signal from the second source signal input, a first feedback signal from the first signal output, and a second feedback signal from the second signal output. The switching amplifier is further configured to provide a second output signal at the second signal output based on the linear amplifier and the second source signal. The system also includes a load coupled to the first signal output and the second signal output via a filter circuit element.

[0007] In yet another exemplary embodiment, a method is described for use with a switching amplifier having a first signal output and a second signal output, the method including receiving a first voltage at a first source signal input and a second voltage at a second source signal input, providing a first output signal at the first signal output based on a PWM control loop receiving the first voltage, the second voltage, a first feedback signal from the first signal output, and a second feedback signal from the second signal output, and providing a second output signal at the second signal output based on a linear amplifier and the second voltage. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram of a system having a switching amplifier in accordance with an example embodiment.

[0009] [Diagram 2] 1 is a block diagram of an audio system having a switching amplifier according to an example embodiment.

[0010] [Diagram 3] 1 is a schematic diagram of a power stage of a switching amplifier coupled to a load via filter circuitry in accordance with an example embodiment.

[0011] [Figure 4] 4 is a diagram of signals associated with a switching amplifier in accordance with an example embodiment.

[0012] [Diagram 5] FIG. 4 is another diagram of signals associated with a switching amplifier in accordance with an example embodiment.

[0013] [Figure 6] 4 is a diagram of signals associated with a switching amplifier having feedforward signaling in accordance with an example embodiment. FIG.

[0014] [Figure 7] FIG. 4 is another diagram of signals associated with a switching amplifier having feedforward signaling in accordance with an example embodiment.

[0015] [Figure 8] 4 is a diagram of signals associated with a switching amplifier in an idle state in accordance with an example embodiment.

[0016] [Figure 9A] 4 is a diagram of signals associated with a switching amplifier in accordance with an example embodiment, illustrating switching losses.

[0017] [Figure 9B] 4 is a diagram of signals associated with a switching amplifier in accordance with an example embodiment, illustrating reduced switching losses.

[0018] [Figure 10] 4 illustrates a diagram showing voltage variation at a second signal output as a function of voltage variation at a second source signal input to a switching amplifier in accordance with an example embodiment.

[0019] [Figure 11]1 is a flow chart illustrating a method for use with a switching amplifier having a first signal output and a second signal output, in accordance with an example embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Described herein is a switching amplifier having a power stage, a pulse width modulation (PWM) control loop, and a linear amplifier. The PWM control loop controls a first switch and a second switch in a first portion of the power stage. A first signal output of the switching amplifier is between current terminals of the first switch and the second switch. The linear amplifier controls a third switch and a fourth switch in a second portion of the power stage. A second signal output of the switching amplifier is between current terminals of the third switch and the fourth switch. The described switching amplifier topology may be referred to herein as a linear transition totem pole topology. As used herein, a "linear transition totem pole" topology provides a high frequency output (e.g., V OUTP ) and low frequency output (e.g., V OUTM ) near the zero crossings of the input signal, the low frequency output transitions slowly and linearly to reduce or eliminate total harmonic distortion (THD) for switching amplifiers. Another feature of the linear transition totem pole topology is that the low frequency output is clamped (e.g., above a threshold V OUTM is clamped to 0 or the power supply voltage "PVDD").

[0021] When using a linear transition totem pole topology, a filter circuit element between the load and the first and second signal outputs of the switching amplifier avoids an inductor, reducing the overall cost of the system. In some exemplary embodiments, the filter circuit element includes a first filter and a second filter. The first filter is between the first signal output and a first end of the load. In some exemplary embodiments, the first filter includes a first capacitor and an inductor. The second filter is between the second signal output and a second end of the load. In some exemplary embodiments, the second filter includes a second capacitor and does not include an inductor. In some exemplary embodiments, the system is an electronic device having a speaker as a load. In some exemplary embodiments, the PWM control loop receives a feedforward signal based on the voltage at the second signal output, the feedforward signal improving the THD of the switching amplifier. As another option, a size and a charging interval of the second capacitor of the filter circuit element are selected to reduce switching losses of the switching amplifier.

[0022] In the drawings, the same reference numbers (or other reference numbers) are used to denote identical or similar (structural and / or functional) features. FIG. 1 is a block diagram of a system 100 having a switching amplifier according to example embodiments. In some example embodiments, the system 100 is an electronic device (e.g., a smartphone, laptop computer, or other electronic device) having an audio subsystem and an analog signal chain. As shown, the system 100 includes a first source signal (V INP ) to a first source signal input 140 of a switching amplifier 106. The input source 102 also includes a second source signal (V INM) to a second source signal input 142 of the switching amplifier 106. In some example embodiments, the input source 102 includes a DAC or other source of an analog audio signal. The system 100 further includes a power supply 104 configured to provide a PVDD to each PVDD input 146 of the switching amplifier 106. The switching amplifier 106 also includes a first signal output 148 and a second signal output 150.

[0023] 1, switching amplifier 106 includes a power stage 144 having a first control input 130, a second control input 132, a third control input 134, and a fourth control input 136. Power stage 144 also includes a power supply input 138 coupled to a PVDD input 146 of switching amplifier 106, a first power stage output 147 coupled to a first signal output 148, and a second power stage output 149 coupled to a second signal output 150.

[0024] 1, switching amplifier 106 also includes a modulation controller 108 configured to provide a first control signal (CS1) to a first control input 130, a second control signal (CS2) to a second control input 132, a third control signal (CS3) to a third control input 134, and a fourth control signal (CS4) to a fourth control input 136. These control signals (CS1, CS2, CS3, CS4) control respective switches (see, e.g., S1-S4 in FIG. 3) of power stage 144.

[0025] In some illustrative embodiments, modulation controller 108 includes a PWM control loop 110 having a loop filter 112 and a comparison circuit 116. As shown, PWM control loop 110 includes a first input 120 coupled to a first source signal input 140, a second input 122 coupled to a second source signal input 142, a first feedback input 124 coupled to a first signal output 148, and a second feedback input 126 coupled to a second signal output 150. Loop filter 112 integrates the difference between the voltages at the first and second source signal inputs 140 and 142 with respect to the voltages at the first and second signal outputs 148 and 150 (i.e., V INP and V INM The difference between V OUTP and V OUTM The output of loop filter 112 is provided to comparison circuitry 116, which compares the output of loop filter 112 with a reference ramp signal. The comparison result is used to generate CS1 and CS2 at PWM control loop outputs 113 and 115. In some example embodiments, V OUTM A feed-forward (FF) circuit element 114 is included in the PWM control loop 110. In such a case, V OUTM The feedforward circuit element 114 is V OUTM The PWM control loop 110 is configured to adjust the result of the PWM control loop 110 based on the OUTM The feedforward circuit element 114 is V OUTM Or V OUTM A scaled version of V may be added to the loop filter output. In such a case, comparison circuitry 116 uses the sum of the loop filter output and the feedforward signal as one of its inputs. OUTM When using feedforward circuitry 114, the THD of switching amplifier 106 is OUTM This is an improvement over switching amplifier 106 without feedforward circuitry 114 .

[0026] 1, the modulation controller 108 also includes a linear amplifier 118 having an amplifier input 121, a first amplifier output 117, and a second amplifier output 119. In some example embodiments, the linear amplifier 118 has a V INM and the gain of linear amplifier 118, to provide CS3 at first amplifier output 117 and CS4 at second amplifier output 119. In response to CS1, CS2, CS3, and CS4, power stage 144 provides a voltage (V OUTP ) and the voltage at the second signal output 150 (V OUTM ) and controls.

[0027] When using the modulation controller 108, the filter circuitry 160 (e.g., for reducing electromagnetic interference or “EMI”) between the load 162 and the first and second signal outputs 148 and 150 is simplified compared to other filter options because the number of inductors in the filter circuitry 160 is reduced (e.g., from two inductors to one inductor). The filter circuitry 160 includes, for example, a first filter and a second filter. The first filter is between the first signal output 148 and a first end 164 of the load 162. In some example embodiments, the first filter includes a first capacitor (e.g., C1 in FIGS. 2 and 3 ) and an inductor (e.g., L1 in FIGS. 2 and 3 ). The second filter is between the OUTM output 150 and a second end 166 of the load 162. In some example embodiments, the second filter includes a second capacitor (e.g., C2 in FIGS. 2 and 3 ) and does not include an inductor.

[0028] This simplification of the filter circuitry 160 is a significant cost savings due to the size of the inductor. To improve the performance of the switching amplifier 106, the PWM control loop 110 is configured to reduce the V OUTM, thereby improving the THD of switching amplifier 106. As another option, the size and charging interval of the second capacitor (e.g., C2 in FIGS. 2 and 3) of filter circuitry 160 is selected to reduce switching losses of switching amplifier 106.

[0029] 2 is a block diagram of an audio system 200 having a switching amplifier 106A (an example of the switching amplifier 106 in FIG. 1) according to an example embodiment. The audio system 200 may be part of a system (e.g., the system 100 in FIG. 1) having audio signal amplification provided by the switching amplifier 106A. As shown, the audio system 200 includes a switching amplifier 106A coupled to a speaker 162A (an example of the load 162 in FIG. 1) via a filter circuit element 160A (an example of the filter circuit element 160 in FIG. 1).

[0030] In the example of FIG. 2, switching amplifier 106A includes modulation controller 108A (an example of modulation controller 108 in FIG. 1) having PWM control loop 110A (an example of PWM control loop 110 in FIG. 1) and linear amplifier 118A (an example of linear amplifier 118 in FIG. 1). PWM control loop 110A and linear amplifier 118A are coupled to power stage 144A (an example of power stage 144 in FIG. 1). More specifically, power stage 144A includes a first portion 242 (labeled "OUTP portion") and a second portion 252 (labeled "OUTM portion"). First portion 242 of power stage 144A includes a first control input 130A (an example of first control input 130 in FIG. 1) and a second control input 132A (an example of second control input 132 in FIG. 1). In some illustrative embodiments, the first portion 242 of the power stage 144A includes a first switch (e.g., S1 in FIG. 3) having a first control terminal (e.g., CT1 in FIG. 3) coupled to the first control input 130A and a second switch (e.g., S2 in FIG. 3) having a second control terminal (e.g., CT2 in FIG. 3) coupled to the second control input 132A. The second portion 252 of the power stage 144A includes a third control input 134A (an example of the third control input 134 in FIG. 1) and a fourth control input 136A (an example of the fourth control input 136 in FIG. 1). In some illustrative embodiments, the second portion 252 of the power stage 144A includes a third switch (e.g., S3 in FIG. 3) having a third control terminal (e.g., CT3 in FIG. 3) coupled to the third control input 134A, and a fourth switch (e.g., S4 in FIG. 3) having a fourth control terminal (e.g., CT4 in FIG. 3) coupled to the fourth control input 136A.

[0031] 2, switching amplifier 106A also includes a first signal output 148A (an example of first signal output 148 in FIG. 1). As shown, first signal output 148A is coupled to a first power stage output 147A (an example of first power stage output 147 in FIG. 1) of a first portion 242 of power stage 144A. In some illustrative embodiments, first power stage output 147A, and thus first signal output 148, is between current terminals of a first switch (e.g., S1 in FIG. 3) and a second switch (e.g., S2 in FIG. 3) of the first portion 242 of power stage 144A.

[0032] Switching amplifier 106A further includes a second signal output 150A (an example of second signal output 150 in FIG. 1). As shown, second signal output 150A is coupled to second power stage output 149A (an example of second power stage output 149 in FIG. 1) of second portion 252 of power stage 144A. In some example embodiments, second power stage output 149A, and thus second signal output 150A, is between current terminals of a third switch (e.g., S3 in FIG. 3) and a fourth switch (e.g., S4 in FIG. 3) of second portion 252 of power stage 144A.

[0033] 2, the PWM control loop 110A includes a first input 120A (an example of the first input 120 in FIG. 1), which is coupled to a first source signal input 140A (an example of the first source signal input 140 in FIG. 1) for receiving a first source signal (e.g., V INP ). The PWM control loop 110A further includes a second input 122A (an example of the second input 122 in FIG. 1) that is coupled to a second source signal input 142A (an example of the second source signal input 142 in FIG. 1) for receiving a second source signal (e.g., V INM1 ). PWM control loop 110A additionally includes a first feedback input 124A (an example of first feedback input 124 in FIG. 1 ) coupled to first signal output 148A and a second feedback input 126A (an example of second feedback input 126 in FIG. 1 ) coupled to second signal output 150A. PWM control loop 110A further includes a first PWM control loop output 113A (an example of first PWM control loop output 113 in FIG. 1 ) coupled to first control input 130A and a second PWM control loop output 115A (an example of second PWM control loop output 115 in FIG. 1 ) coupled to second control input 132A.

[0034] As shown, linear amplifier 118A has an amplifier input 121A (an example of amplifier input 121), a first amplifier output 117A (an example of first amplifier output 117 in FIG. 1), and a second amplifier output 119A (an example of second amplifier output 119 in FIG. 1). Amplifier input 121A is connected to V INM The first amplifier output 117A is coupled to a second source signal input 142A to receive a first control signal from the first amplifier output 117A. The second amplifier output 119A is coupled to a fourth control input 136A.

[0035] 2, switching amplifier 106A also includes a first resistor (R1) between first source signal input 140A and first feedback input 124A, a second resistor (R2) between second source signal input 142A and second feedback input 126A, a third resistor (R3) between first feedback input 124A and first signal output 148A, and a fourth resistor (R4) between second feedback input 126A and second signal output 150A. With resistors R1, R2, R3, and R4, loop filter 202 of PWM control loop 110A has a resistance of V INP , V INM , V OUTP , and V OUTM It works with a scaled version of

[0036] As shown, the loop filter 202 includes a first filter input 204, a second filter input 206, and a filter output 210. The first filter input 204 is coupled to the first feedback input 124A, and the second filter input 206 is coupled to the second feedback input 126A. In operation, the loop filter 202 is coupled to a first feedback input 124A, and the second filter input 206 is coupled to the second feedback input 126A. INP and V INM The difference between V OUTP and V OUTM The result is that V INTP and V INTM In some example embodiments, the PWM control loop 110A further includes a summer 212 having a first summer input 214, a second summer input 216, and a summer output 218. The first summer input 214 is V INTM A second summer input 216 is coupled to a filter output 210 that provides the voltage at the second signal output 150A (e.g., V OUTM ) An example feedforward signal is (V OUTM The PWM control loop 110A may include, but is not limited to, a comparator 222 (one example of the comparison circuitry 116 in FIG. 1) having a first comparator input 224, a second comparator input 226, and a comparator output 228. The first comparator input 224 is coupled to the summer output 218. The second comparator input 226 receives a reference ramp signal 227 (e.g., PVDD / 7). The reference ramp signal 227 may be provided by, for example, a ramp generator 220.

[0037] 2, the PWM control loop 110A additionally includes a gate driver circuit 232 coupled to the comparator output 228. In some example embodiments, there is logic 230 between the comparator output 228 and the gate driver circuit 232. The logic 230 may also be referred to as non-overlapping logic. In operation, the logic 230 ensures that there is a dead time between the control signals (e.g., CS1 and CS2) output from the gate driver circuit 232 to avoid shoot-through current in the low-side and high-side switches (e.g., S3 and S4) of the second portion 252 of the power stage 144A.

[0038] The gate driver circuit 232 includes a first gate driver input 234, a second gate driver input 236, a first gate driver output 237, and a second gate driver output 239. The first gate driver input 234 and the second gate driver input 236 are coupled (via logic 230) to the comparator output 228. The first gate driver output 237 is coupled to the first PWM control loop output 113A. The second gate driver output 239 is coupled to the second PWM control loop output 115A. In some example embodiments, the gate driver circuit 232 includes level shifter circuitry 235 for shifting voltage / current levels to provide the gate drive control signals (e.g., CS1 and CS2 in FIG. 1).

[0039] In some example embodiments, the linear amplifier 118A receives an input signal (e.g., V INM ) at the second signal output 150A. The gain can be, but is not limited to, at least 160. The gain selection involves a trade-off between THD and loss. With lower gain, the linear transition region takes longer and the THD is improved, resulting in greater low-power linear loss. With higher gain, the THD is worse, but the low-power linear loss is smaller. As another option, the linear amplifier 118A applies a gain to the output signal (e.g., V OUTM ) is clamped. Therefore, V INMWhen V exceeds the threshold, the linear amplifier 118A OUTM V is clamped to PVDD. OUTM Either the high-side switch (e.g., S3 in Figure 3) that controls V OUTM V is clamped to ground. OUTM The low-side switch (for example, S4 in FIG. 4) that controls

[0040] In the example of FIG. 2, the first signal output 148A of the switching amplifier 106A is adapted to be coupled to a first end 164A of the speaker 162A (an example of the first end 164 of the load 162 in FIG. 1) via a first filter of the filter circuit element 160A. In some example embodiments, the first filter includes C1 and L1 in the arrangement shown. The second signal output 150A of the switching amplifier 106A is adapted to be coupled to a second end 166A of the speaker 162A (an example of the first end 166 of the load 162 in FIG. 1) via a second filter of the filter circuit element 160A. In some example embodiments, the second filter includes C2 in the arrangement shown and does not include an inductor. In some example embodiments, the switching amplifier 106A may also include a current sense circuit 260 configured to monitor a current through a switch of the first portion 242 of the power stage 144A. Switching amplifier 106A may also include a current sense circuit 262 configured to monitor the current through the switches of second portion 252 of power stage 144A. Current sense circuits 260 and 262 may be part of an over-current or under-current monitoring system for switching amplifier 106A.

[0041] For the audio system 200, the switching amplifier 106A topology allows for a simplified filter circuit element 160A (inductors may be omitted) compared to other topologies. OUTMA feedforward signal based on (e.g., applied at summer 212) improves the THD of switching amplifier 106A. The size of C2 and the associated charging interval may also be selected to reduce switching losses in switching amplifier 106A.

[0042] In some example embodiments, a system (e.g., system 100 in FIG. 1) includes a switching amplifier (e.g., switching amplifier 106 in FIG. 1 or switching amplifier 106A in FIG. 2) having a first signal source input (e.g., first source signal input 140 in FIG. 1 or first source signal input 140A in FIG. 2), a second source signal input (e.g., second source signal input 142 in FIG. 1 or second source signal input 142A in FIG. 2), a first signal output (e.g., first signal output 148 in FIG. 1 or first signal output 148A in FIG. 2), and a second signal output (e.g., second signal output 150 in FIG. 1 or second signal output 150A in FIG. 2). The switching amplifier generates a first output signal (e.g., V OUTP ) at the first signal output, and the PWM control loop is configured to generate a first source signal (e.g., V INP ) and receives a second source signal (e.g., V INM ) and a first feedback signal (e.g., V OUTP Or V OUTP ) and a second feedback signal (e.g., a scaled version of V) from the second signal output. OUTM Or V OUTM The switching amplifier further receives a second output signal (e.g., a scaled version of V) based on a linear amplifier (e.g., linear amplifier 118 in FIG. 1). OUTM) at the second signal output and the second source signal at the second source signal input. The system also includes a load (e.g., load 162 in FIG. 1 or load 162A in FIG. 2) coupled to the first signal output and the second signal output via a filter circuit element (e.g., filter circuit element 160 in FIG. 1).

[0043] In some example embodiments, the switching amplifier includes a first resistor (e.g., R1 in FIG. 2) having a first end and a second end. The first end of the first resistor is coupled to the first source signal input, and the second end of the first resistor is coupled to the first feedback input of the PWM control loop. The switching amplifier also includes a second resistor (e.g., R2 in FIG. 2) having a first end and a second end. The first end of the second resistor is coupled to the second source signal input, and the second end of the second resistor is coupled to the second feedback input of the PWM control loop. The switching amplifier further includes a third resistor (e.g., R3 in FIG. 2) having a first end and a second end. The first end of the third resistor is coupled to the first signal output, and the second end of the third resistor is coupled to the first feedback input. The switching amplifier additionally includes a fourth resistor (e.g., R4 in FIG. 2) having a first end and a second end, the first end of the fourth resistor being coupled to the second signal output and the second end of the fourth resistor being coupled to the second feedback input.

[0044] In some example embodiments, the PWM control loop generates a loop filter output (e.g., the output of loop filter 202 in FIG. 2) based on the first source signal, the second source signal, the first feedback signal, and the second feedback signal, and generates a voltage at the loop filter output and the second signal output (e.g., V OUTM 2 ) and determines a comparison result between the added value and a reference ramp signal (e.g., the output of comparator 222 in FIG. 2 ).

[0045] In some example embodiments, the switching amplifier includes a first portion of a power stage (e.g., power stage 144B in FIG. 3) having a first set of switches (e.g., S1 and S2 in the arrangement shown in FIG. 3). In such example embodiments, the PWM control loop includes a gate driver circuit (e.g., gate driver circuit 232 in FIG. 2) configured to generate drive signals (e.g., CS1 and CS2 in FIGS. 1 and 3) for the first set of switches (e.g., S1 and S2 in FIG. 3) based on the comparison result. In some example embodiments, the gate driver circuit includes level shifter circuitry (e.g., level shifter circuitry 235 in FIG. 2).

[0046] In some example embodiments, the switching amplifier includes a second portion of a power stage (e.g., power stage 144B in FIG. 3) having a second set of switches (e.g., S3 and S4 in the arrangement shown in FIG. 3). In such example embodiments, the linear amplifier is configured to apply a gain to the second source signal to generate a drive signal for the second set of switches (e.g., CS3 and CS4 in FIGS. 1 and 3), the gain being at least 100. The linear amplifier may also be configured to clamp the second output signal at the second signal output.

[0047] In some exemplary embodiments, the filter circuit element (e.g., filter circuit element 160 in FIG. 1 or filter circuit element 160A in FIG. 2) includes a first filter (e.g., L1 and C1 in the arrangement shown in FIG. 2 or FIG. 3) and a second filter (e.g., C2 in the arrangement shown in FIG. 2 or FIG. 3). The first filter is between the first signal output and a first end of the load. In some exemplary embodiments, the first filter includes a first capacitor and an inductor. The second filter is between the second signal output and a second end of the load. In some exemplary embodiments, the second filter includes a second capacitor (e.g., C2) and does not include an inductor. In some exemplary embodiments, the size of the second capacitor and the associated charging interval are selected to reduce switching losses of the switching amplifier. In some exemplary embodiments, the load is a speaker and the first and second source signals are audio signals.

[0048] 3 is a schematic diagram 300 of a power stage 144B (an example of power stage 144 in FIG. 1 or power stage 144A in FIG. 2) of a switching amplifier (e.g., switching amplifier 106 in FIG. 1 or switching amplifier 106A in FIG. 2) coupled to a load 162B (an example of load 162 in FIG. 1 or load 162A in FIG. 2) via a filter circuit element 160B (an example of filter circuit element 160 in FIG. 1 or filter circuit element 160A in FIG. 2) in accordance with an example embodiment. In the example of FIG. 3, power stage 144B includes four switches (S1, S2, S3, S4) in the form of n-type metal oxide semiconductor field effect (nMOSFET or simply "nMOS") transistors.

[0049] As shown, a first current terminal of S1 is coupled to PVDD, a second current terminal of S1 is coupled to a first current terminal of S2, and a second current terminal of S2 is coupled to ground. Also, a control terminal (CT1) of S1 is configured to receive CS1, and a control terminal (CT2) of S2 is configured to receive CS2. As shown, a first power stage output 147B (an example of the first power stage output 147 in FIG. 1 or the first power stage output 147A in FIG. 2) is between the second current terminal of S1 and the first current terminal of S2. In FIG. 3, S1 and S2 in the illustrated arrangement are an example of the first portion 242 of the power stage 144A in FIG. 2.

[0050] Also, a first current terminal of S3 is coupled to PVDD, a second current terminal of S3 is coupled to a first terminal of S4, and a second current terminal of S4 is coupled to ground. Also, a control terminal (CT3) of S3 is configured to receive CS3, and a control terminal (CT4) of S4 is configured to receive CS4. As shown, a second power stage output 149B (an example of the second power stage output 149 in FIG. 1 or the second power stage 149A in FIG. 2) is between the second current terminal of S3 and the first current terminal of S4. In FIG. 3, S3 and S4 in the illustrated arrangement are an example of the second portion 252 of the power stage 144A in FIG. 2.

[0051] In the example of FIG. 3, the load 162B is a speaker having a resistive load and a capacitive load in series. As shown, a first end of the load 162B is coupled to the first power stage output 147B via a filter circuit element 160B including L1, C1, and C2. More specifically, the first power stage output 147B is coupled to a first end of L1, while a second end of L1 is coupled to a first end of the load 162B. Also, a second end of the load 162B is coupled to the second power stage output 149B via the filter circuit element 160B. Also, the second power stage output 149B is coupled to a second end of the load 162B and a first terminal of C2. The second terminal of C2 is coupled to ground. In the example of FIG. 3, a first terminal of C1 is coupled to a second end of L1, and a second terminal of C1 is coupled to a first terminal of C2.

[0052] In the example of FIG. 3, CS1 and CS2 are provided by a PWM control loop (e.g., PWM control loop 110 in FIG. 1 or PWM control loop 110A in FIG. 2) resulting in a V OUTP Also, CS3 and CS4 are provided by a linear amplifier (e.g., linear amplifier 118 in FIG. 1 or linear amplifier 118A in FIG. 2), resulting in a switching behavior for V at the second power stage output 149B. OUTM A linear behavior for

[0053] As described herein, by providing CS1, CS2, CS3, and CS4 using a linear transition totem pole topology, filter circuitry 160B is simplified (inductors may be omitted) compared to other switching amplifier topologies. OUTM A feedforward signal based on (e.g., applied to a summer such as summer 212 in FIG. 2) improves the THD of a switching amplifier with a linear transition totem pole topology. As another option, the dimensions of C2 and the associated charging interval can be selected to reduce switching losses of a switching amplifier with a linear transition totem pole topology.

[0054] 4 is a graph 400 of a signal associated with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) in accordance with an example embodiment. In graph 400, the signal INM , V OUTM , V OUTP , V net0174 , V INTM , V INTP , and V net065 As described herein, V INM V is the input voltage to the second source signal input of the switching amplifier (e.g., second source signal input 142 in FIG. 1 or second source signal input 142A in FIG. 2). OUTMis the output voltage at the second signal output of the switching amplifier (e.g., second signal output 150 in FIG. 1 or second signal output 150A in FIG. 2). OUTP V is the output voltage at the first signal output of the switching amplifier (e.g., first signal output 148 in FIG. 1 or first signal output 148A in FIG. 2). INTP is the first loop filter output signal. V INTP is the second loop filter output signal. V CMP To generate CS1 and CS2, V INTP and V INTM A high frequency (e.g. 2.1MHz) signal (e.g. triangular wave) that is compared with V SPKR is the voltage across the speaker (the output signal from the switching amplifier). As shown in the graph 400, V INM is a sine wave, while V OUTM is more linear, except that it is clamped, V OUTM is V INM Follows the shape of.

[0055] 5 is another graph 500 of a signal associated with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) in accordance with an example embodiment. In graph 500, the signal OUTP , V OUTM , V G_HS , V G_LS , V L2 / PLUS , V SPKR , V INTM , and V INTP Includes: V G_HS V is a high-side switch control signal (e.g., CS3) associated with a second signal output to the switching amplifier. G_LS V is the low-side switch control signal (e.g., CS4) associated with the second signal output to the switching amplifier. IL1 is the voltage representative of the inductor current measured through L1. As shown in graph 500, V OUTM The nearly linear increase and decrease in slope of V G_HSand V G_LS Based on multi-step values ​​for

[0056] 6 is a graph 600 of a signal associated with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) having feedforward signaling in accordance with an example embodiment. In graph 600, the signal is OUTP , V OUTM , V SPKR , V feedforward , V ramp , and V INTP As shown in graph 600, V feedforward V OUTM is a scaled version of V OUTM is approximately linear and clamped.

[0057] 7 is another graph 700 of a signal associated with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) having feedforward signaling in accordance with an example embodiment. In graph 700, the signal is OUTP , V OUTM , V SPKR , V feedforward , V ramp , and V INTP As shown in the graph 700, V feedforward V OUTM is a scaled version of V OUTM is approximately a sine wave.

[0058] 8 is a graph 800 of a signal associated with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) in an idle state in accordance with an example embodiment. In graph 800, the signal CMP , V INTP , V INTM , V OUTP , V OUTM , and V SPKRAs shown in graph 800, the input signal is 0 (idle mode), so V SPKR During idle mode, V OUTM is PVDD / 2 (for example, PVDD=14.4V, V OUTM = 7.2V), and the PWM control loop OUTP V has a duty cycle close to 50%. OUTP The average of V OUTM As a result, the audio frequency voltage across the speaker (after the filter circuit element LC filter) is zero (V OUTP -V OUTM =0).

[0059] 9A is a graph 900 of a signal indicative of switching losses associated with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) in accordance with an example embodiment. In graph 900, the signal OUTM , V IL_fund , and V G_LS Includes: V IL_fund is the inductor current to the left of L1. As shown, V OUTM includes a first portion 902 and a second portion 904. OUTM The first portion 902 of V relates to the charging interval for the filter circuitry C2 based on the inductor current. OUTM The second portion 904 of the equation relates to the charging interval for the filter circuitry C2 based on the switching current, which is inefficient.

[0060] For graph 900, the losses on C2 are V OUTM This relates to the second portion 904 of C2, which is V OUTM When V is PVDD, it becomes PVDD. OUTM This is because it becomes 0 when V is 0. If the inductor current is not in the right direction, C2 will be OUTM 2 This is called a hard charge state for C2. OUTMLosses are avoided when the voltage on C2 decreases due to the inductor current, as in the first portion 902 of V. This is referred to as a soft charge state for C2. More specifically, OUTM In the first portion 902 of V, the voltage on C2 decreases and the L1 current is negative. Thus, current flows back from the second power stage output (e.g., second power stage output 149 in FIG. 1, second power stage output 149A in FIG. 2, or second power stage output 149B in FIG. 3) to the first power stage output (e.g., first power stage output 147 in FIG. 1, first power stage output 147A in FIG. 2, or first power stage output 147B in FIG. 3), causing charge on C2 to be drawn by L1. Thus, V OUTM This first portion 902 of V corresponds to a soft charging state for C2. In the second portion 904, the voltage on C2 decreases and the inductor current is positive, which means that current is flowing to the second power stage output. Thus, V OUTM In the second portion 904, the voltage change on C2 is due to the low-side switch (e.g., S3) being turned on, which is V G_LS Therefore, V OUTM This second portion 904 of is associated with a hard charge state for C2 with associated losses.

[0061] 9B is a graph 910 of a signal illustrating reduced switching losses associated with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) in accordance with an example embodiment. In graph 910, the signal OUTM , V IL_fund , and V G_LS Includes: V OUTM A first portion 912 of V relates to the charging interval for the filter circuitry C2 based on the inductor current. OUTMA second portion 914 of V relates to the charging interval for filter circuitry C2 based on the switching current, which is inefficient. By controlling the size of C2 and the associated charging interval represented by the first and second portions 912 and 914, switching losses of the switching amplifier can be reduced. More specifically, V OUTM In the first portion 91 of V, the inductor current is measured on the left side of L1. If the inductor current is positive, it means that current is flowing from the first power stage output to the second power stage output. OUTM To increase the size of the first positive portion of V (to make the soft charge interval as large as possible), V is OUTM The voltage at V OUTM The first portion 912 increases relative to the second portion 914. Note: OUTM The first portion 912 of the graph 900 corresponds to the V OUTM is larger than the first portion 902.

[0062] FIG. 10 illustrates a V OUTM 2 ) at a second source signal input (second source signal input 142 in FIG. 1 or second source signal input 142A in FIG. 2 ) to a switching amplifier (e.g., switching amplifier 106 in FIG. 1 , switching amplifier 106A in FIG. 1 ) according to an example embodiment. INM 1 is a graph 1000 showing a change in voltage at the input of the power supply 100 as a function of the voltage change at the input of the power supply 100 INM A smaller value of V (for example, V less than 500 mV) INM ), then V OUTM is approximately sinusoidal and not clamped. V INM A larger value of V (for example, V above 600mV) INM ), then V OUTM is approximately trapezoidal and is clamped.

[0063] 11 is a flow chart illustrating a method 1100 for use with a switching amplifier (e.g., switching amplifier 106 in FIG. 1, switching amplifier 106A in FIG. 1) having a first signal output (e.g., first signal output 148 in FIG. 1, or first signal output 148A in FIG. 2) and a second signal output (e.g., second signal output 150 in FIG. 1, or second signal output 150A in FIG. 2) in accordance with an example embodiment. As shown, the method 1100 includes, at block 1102, selecting a first source signal (e.g., V INP ) and a second source signal (e.g., V INM In block 1104, the first source signal, the second source signal, and a first feedback signal (e.g., V OUTP ) and a second feedback signal from a second signal output (e.g., V OUTM 1 or 110A in FIG. 2 ) based on a PWM control loop that receives a first output signal (V OUTP ) is provided at a first signal output (e.g., a first switching converter). In some example embodiments, providing the first output signal at the first signal output in block 1104 further includes providing a voltage (e.g., V OUTM 2) with a feedforward signal based on V. In block 1106A, a second output signal (e.g., V OUTM ) is provided at the second signal output.

[0064] In some example embodiments, the method 1100 may also include scaling the first feedback signal to the first output signal and scaling the second feedback signal to the second output signal. As another option, the method 1100 may further include coupling the first output signal and the second output signal to a load (e.g., load 162 in FIG. 1 or load 162A in FIG. 2) via a filter circuit element (e.g., filter circuit element 160 in FIG. 1 or filter circuit element 160A in FIG. 2). The filter circuit element includes a first filter (e.g., L1 and C1 shown in the arrangement of FIG. 2 or FIG. 3) and a second filter (e.g., C2 in the arrangement of FIG. 2 or FIG. 3). The first filter is between the first signal output and a first end of the load. In some example embodiments, the first filter includes a first capacitor (e.g., C1 in FIG. 2 and FIG. 3) and an inductor (e.g., L1 in FIG. 2 and FIG. 3). The second filter is between the second signal output and a second end of the load. The second filter includes a second capacitor (e.g., C2 in FIG. 2 and FIG. 3) and does not include an inductor. In some example embodiments, the method 1100 includes selecting a size of the second capacitor and an associated charging interval to reduce switching losses of the switching amplifier.

[0065] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with the explanation of this description. For example, if device A generates a signal that controls a control device B to perform a certain action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C, such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0066] As used herein, the terms "terminal," "node," "interconnect," "pin," "contact," and "connection" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to mean an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0067] Although the exemplary embodiments described above utilize nMOS transistors, other exemplary embodiments may utilize pMOS transistors, NPN bipolar junction transistors (BJTs), PNP BJTs, or any other type of transistor. Thus, when referring to a current terminal, such terminal may be an emitter, collector, source, or drain. Also, a control terminal may be a base or gate.

[0068] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, or through the configuration and / or layout of hardware components, device interconnections, or a combination thereof.

[0069] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be adapted to be coupled to at least some of the passive elements and / or sources, thereby forming the described structure, either at the time of manufacture or at a time thereafter, e.g., by an end user and / or a third party.

[0070] The circuits described herein may be reconfigurable to include replaced components and provide functionality at least partially similar to the functionality available prior to the replacement of the components. Unless otherwise indicated, a component illustrated as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the illustrated resistor. For example, a resistor described herein as a single component may instead be multiple resistors or capacitors, each of which may be multiple resistors coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes, each of which may be a single resistor or capacitor.

[0071] Use of the term "ground" herein includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other type of ground connection applicable or suitable to the teachings of the present description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a number means + / - 10 percent of the stated value.

[0072] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. An apparatus, comprising: a control circuit having a first input, a first control output, and a second control output, the control circuit including a modulating signal generator coupled between the first input and the first control output, and an amplifier coupled between the first input and the second control output; a first power stage having a first control input coupled to the first control output and a first power stage output; a second power stage having a second control input coupled to the second control output and a second power stage output; 1. An apparatus comprising:

2. The device according to claim 1, the control circuit further has a second input, the control circuit further including a loop filter having a first filter input coupled to the first input and the first power stage output, a second filter input coupled to the second input and the second power stage output, and a filter output coupled to an input of the modulated signal generator.

3. The device according to claim 2, The control circuit a first resistor coupled between the first input and the first filter input; a second resistor coupled between the second input and the second filter input; a third resistor coupled between the first filter input and the first power stage output; a fourth resistor coupled between the second filter input and the second power stage output; The apparatus further comprises:

4. The device according to claim 2, The control circuit 11. The apparatus further comprising: a signal combining circuit having a first input coupled to the filter output, a second input coupled to one of the first or second power stage outputs, and an output coupled to an input of the modulation signal generator.

5. The device according to claim 4, The apparatus, wherein the signal combining circuit is a summing circuit.

6. The device of claim 2, The modulation signal generator a comparator having a first input coupled to the input of the modulation signal generator and a second input; a multi-cycle ramp generator coupled to a second input of the comparator; 1. An apparatus comprising:

7. The device of claim 1, The apparatus, wherein the modulation signal generator is a pulse width modulation (PWM) signal generator.

8. The device of claim 1, The apparatus further includes a non-overlapping logic circuit coupled between the modulation signal generator and the first control input.

9. The device of claim 1, The apparatus, wherein the amplifier is a linear amplifier.

10. The device of claim 1, the first power stage further having a first power supply terminal, and the second power stage further having a second power supply terminal; The apparatus, wherein the amplifier is configured to generate a control signal to clamp the second power stage to a voltage at the second power supply terminal.

11. The apparatus of claim 10, the first power stage: a first transistor coupled between the first power supply terminal and the first power stage output, the first transistor having a first control terminal coupled to a first control input of the first control input; a second transistor coupled between the first power stage output and a ground terminal, the second transistor having a second control terminal coupled to a second control input of the second control input; Including, the second power stage: a third transistor coupled between the second power supply terminal and the second power stage output, the third transistor having a third control terminal coupled to a first control input of the second control input; a fourth transistor coupled between the second power stage output and the ground terminal, the fourth transistor having a fourth control terminal coupled to a second control input of the second control input; 1. An apparatus comprising:

12. The apparatus of claim 1, The apparatus, wherein the first power stage output is coupled to an inductor terminal and the second power stage output is coupled to a capacitor terminal.

13. The device of claim 1, an inductor coupled between the first power stage output and a first speaker terminal; a first capacitor coupled between the first speaker terminal and a second speaker terminal; a second capacitor coupled between the second speaker terminal and a reference terminal; Further comprising: The apparatus, wherein the first input is an audio input and the second speaker terminal is coupled to the second power stage output.

14. The device of claim 1, The apparatus, wherein the control circuit and the first and second power stages are part of an integrated circuit.

15. The apparatus of claim 1, The apparatus, wherein the control circuit and the first and second power stages are part of an audio amplifier circuit.

16. An apparatus comprising: a control circuit having a first input, a first control output, and a second control output, the control circuit including a modulating signal generator coupled between the first input and the first control output, and an amplifier coupled between the first input and the second control output; a first transistor coupled between a power terminal and a first output, the first transistor having a first control terminal coupled to the first control output; a second transistor coupled between the first output and a reference terminal, the second transistor having a second control terminal coupled to the first control output; a third transistor coupled between the power terminal and a second output, the third transistor having a third control terminal coupled to the second control output; a fourth transistor coupled between the second output and the reference terminal, the fourth transistor having a fourth control terminal coupled to the second control output; 1. An apparatus comprising:

17. The apparatus of claim 16, the control circuit further has a second input, the control circuit further including a loop filter having a first filter input coupled to the first input and the first output, a second filter input coupled to the second input and the second output, and a filter output coupled to an input of the modulated signal generator.

18. The apparatus of claim 17, the control circuit further includes a signal combining circuit having a first input coupled to the filter output, a second input coupled to one of the first or second outputs, and an output coupled to an input of the modulating signal generator.

19. The apparatus of claim 16, The apparatus, wherein the first input is an audio input, the first output is coupled to a first speaker terminal, and the second output is coupled to a second speaker terminal.

20. The apparatus of claim 19, an inductor coupled between the first output and the first speaker terminal; a first capacitor coupled between the first speaker terminal and the second speaker terminal; The apparatus further comprises:

21. The apparatus of claim 20, The apparatus further includes a second capacitor coupled between the second speaker terminal and the reference terminal.

22. A method comprising: receiving a first signal; generating a first control signal from the first signal using a modulation signal generator; generating a second control signal from the first signal using an amplifier; generating a second signal by providing the first control signal to a first power stage; generating a third signal by providing the second control signal to a second power stage; A method comprising:

23. The method of claim 22, comprising: further comprising providing the second signal through a filter to a first speaker terminal; the first signal is an audio signal; the filter includes an inductor coupled between the first power stage and the first speaker terminal, a first capacitor coupled between the first speaker terminal and a second speaker terminal, and a second capacitor coupled between the second speaker terminal and a reference terminal.

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