Display substrate and display device

Abstract

The display substrate includes a first display region and a second display region. At least a portion of the second display region surrounds the first display region. The display substrate includes a first light-emitting element group provided in the first display region, a first pixel circuit group provided in the second display region, a lead group, and a plurality of second pixel circuits provided in the second display region. The first light-emitting element group includes N first light-emitting elements. The first pixel circuit group includes N first pixel circuits. The lead group includes N leads. The i-th first light-emitting element is electrically connected to the i-th first pixel circuit by the i-th lead, and the lengths of the first to N-th leads are gradually increased. N≧2, N is an integer, and i=1 to N. At least one row of second pixel circuits or at least one column of second pixel circuits are provided at intervals between the first first light-emitting element and the first first pixel circuit. The N leads extend from the first display region through at least one row of second pixel circuits or at least one column of second pixel circuits to the second display region.

Description

[Technical field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. [Background technology]

[0002] With the continuous development of science and technology, users have higher requirements for the screen-to-body ratio of display devices.

[0003] In the related art, the concept of full screen has emerged, ie, optical elements such as image capture devices in a display device are placed below the display screen. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a display substrate is provided. The display substrate includes a first display region and a second display region. The second display region at least partially surrounds the first display region. The display substrate includes a first light-emitting element group provided in the first display region, a first pixel circuit group provided in the second display region, a lead group, and a plurality of second pixel circuits provided in the second display region. The first light-emitting element group includes N first light-emitting elements. Along a first direction and pointing from the second display region to the first display region, the N first light-emitting elements are first to Nth first light-emitting elements, respectively. The first pixel circuit group includes N first pixel circuits. The first to Nth first pixel circuits are sequentially provided along a direction away from the first display region. The set direction is an arrangement direction of the N first pixel circuits. The lead group includes N leads provided in parallel. The i-th first light-emitting element is electrically connected to the i-th first pixel circuit by the i-th lead, and the lengths of the first to N-th leads gradually increase. N≧2, N is an integer, and i=1 to N. The second pixel circuits are arranged in a plurality of columns along the first direction and in a plurality of rows along the second direction. The first direction intersects with the second direction. Between the first first light-emitting element and the first first pixel circuit, 、At least one row of second pixel circuits or at least one column of second pixel circuits are provided, and the N leads extend from the first display area, through the at least one row of second pixel circuits or the at least one column of second pixel circuits, to the second display area.

[0005] In some embodiments, the first light emitting element group and the first pixel circuit group electrically connected to the first light emitting element group are provided in the same row along the first direction. 、 At least one column of second pixel circuits is provided, and the N leads extend from the first display area along the first direction through the at least one column of second pixel circuits to the second display area.

[0006] In some embodiments, the display substrate comprises a plurality of second light-emitting elements disposed in the second display region, at least one second light-emitting element is electrically connected to at least one second pixel circuit, and the at least one second light-emitting element and the at least one second pixel circuit are at least partially overlapped in orthogonal projection on a plane on which the display substrate is located. The display substrate comprises a plurality of pixel units, each pixel unit comprises three sub-pixels arranged along the first direction, and each sub-pixel comprises a second light-emitting element and a second pixel circuit electrically connected thereto. Between the first first light-emitting element and the first first pixel circuit, X second pixel circuits belonging to at least one pixel unit are disposed at intervals, where X is a multiple of 3.

[0007] In some embodiments, the display substrate comprises a plurality of second light-emitting elements disposed in the second display region, at least one second light-emitting element electrically connected to at least one second pixel circuit, and the at least one second light-emitting element and the at least one second pixel circuit at least partially overlap each other in orthogonal projection on a plane on which the display substrate is located. The display substrate further comprises a plurality of pixel units, each pixel unit comprising a plurality of sub-pixels, each sub-pixel comprising a second light-emitting element and a second pixel circuit electrically connected thereto. The arrangement of the plurality of pixel units is a pentile arrangement. Between the first first light-emitting element and the first first pixel circuit, Y second pixel circuits belonging to at least one pixel unit are arranged at intervals, where Y is a multiple of 2.

[0008] In some embodiments, the sequence formed by the length values ​​in the first direction of the N leads is an arithmetic sequence.

[0009] In some embodiments, the sequence formed by the resistance values ​​of the N leads is an arithmetic sequence.

[0010] In some embodiments, a parasitic capacitance is formed between each lead and the second pixel circuit and / or the first pixel circuit through which it passes. The progression of parasitic capacitance values ​​formed by the N leads is an arithmetic progression.

[0011] In some embodiments, the display substrate includes a plurality of rows of first light-emitting elements located in the first display area, and the first light-emitting elements in each row are divided into two first light-emitting element groups located on both sides of a reference line. The reference line is a straight line extending along the second direction and passing through the first display area, and the second direction is perpendicular to the first direction. Two first pixel circuit groups electrically connected to the two first light-emitting element groups are respectively located on opposite sides of the first display area in the first direction. Two lead groups electrically connected to the two first light-emitting element groups are respectively located on both sides of the reference line.

[0012] In some embodiments, the two lead groups electrically connected to the two first light-emitting element groups are provided symmetrically with respect to the reference line.

[0013] In some embodiments, the first display area has a center and the reference line is a straight line passing through the center.

[0014] In some embodiments, the first light-emitting element group and the first pixel circuit group electrically connected to the first light-emitting element group are provided in the same row along the first direction. The display substrate further includes a transfer hole group. The transfer hole group includes N transfer holes, which are sequentially arranged along the first direction and correspond to the N first light-emitting elements, respectively. Along the second direction, an i-th lead electrically connected to an i-th first light-emitting element is closer to the transfer hole group than an i+1-th lead electrically connected to an i+1-th first light-emitting element. The second direction is perpendicular to the first direction.

[0015] In some embodiments, the first light-emitting element group and the first pixel circuit group electrically connected to the first light-emitting element group are arranged in the same row along the first direction. The display substrate further includes a transfer hole group. The transfer hole group includes N transfer holes, which are sequentially arranged along the first direction and correspond to the N first light-emitting elements, respectively. An i-th lead electrically connected to an i-th first light-emitting element and an i+1-th lead electrically connected to an i+1-th first light-emitting element are located on opposite sides of the transfer hole group in the second direction. The second direction is perpendicular to the first direction.

[0016] In some embodiments, the display substrate includes a base, a pixel circuit layer provided on the base, the first pixel circuit group and the second pixel circuits being located in the pixel circuit layer, a light emitting element layer provided on a side of the pixel circuit layer away from the base, the first light emitting element group being located in the light emitting element layer, and a plurality of lead layers provided between the pixel circuit layer and the light emitting element layer, the plurality of lead layers being made of a light transmissible conductive material. N leads of the lead group are located in the plurality of lead layers, respectively.

[0017] In some embodiments, the number of the plurality of lead layers is two. In , Odd number of leads, even number of leads, and the first Nth lead teeth, each Two lead layers To Located.

[0018] In some embodiments, the length ratio of the Nth lead to the first lead among the N leads is α, where α≦25.

[0019] In some embodiments, the length ratio α satisfies α≦15.

[0020] In some embodiments, the number of rows or columns of second pixel circuits spaced apart between the first first light emitting element and the first first pixel circuit is β, where β≦30.

[0021] In some embodiments, the ratio of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit is γ, and 5≦γ≦50.

[0022] In some embodiments, the second display region includes a normal region and a compressed region. The first pixel circuit group is located in the compressed region, a portion of the second pixel circuits among the plurality of second pixel circuits is located in the normal region, and another portion of the second pixel circuits is located in the compressed region, and at least one second pixel circuit is provided between two adjacent first pixel circuits in the compressed region along the first direction. A width of a column region in which the first pixel circuits or the second pixel circuits located in the compressed region are located is smaller than a width of a column region in which the second pixel circuits located in the normal region are located.

[0023] In another aspect, a display device is provided, comprising: a display substrate according to any one of the above embodiments; and an optical element provided on a non-light-emitting side of the display substrate, the optical element being located in a first display region of the display substrate. [Brief description of the drawings]

[0024] In order to more clearly explain the technical solutions of the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described below. It is clear that the drawings in the following description are only a part of some embodiments of the present disclosure. Those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not limit the actual dimensions of the products of the embodiments of the present disclosure. [Figure 1] 1 is a structural diagram of a display substrate according to some embodiments of the present disclosure. [Diagram 2] FIG. 2 is a structural diagram of another display substrate according to some embodiments of the present disclosure. [Diagram 3] FIG. 2 is a partial enlarged view of a display substrate according to some embodiments of the present disclosure. [Figure 4] 4 is a cross-sectional view taken along the line EE' of the display substrate shown in FIG. [Diagram 5] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 6] 6 is a cross-sectional view taken along the line FF' of the display substrate shown in FIG. 5. [Figure 7] FIG. 2 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure. [Figure 8] FIG. 2 is a structural diagram of a sub-pixel according to some embodiments of the present disclosure. [Figure 9] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 10] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 11] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 12] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 13] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 14] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 15] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 16] FIG. 2 is a partial enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 17] 17 is a cross-sectional view taken along the line GG' of the display substrate shown in FIG. 16. [Figure 18] FIG. 1 is a structural diagram of a display device according to some embodiments of the present disclosure. [Figure 19] FIG. 2 is a structural diagram of another display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The following clearly and completely describes the technical solutions of some embodiments of the present disclosure with reference to the drawings, but it is clear that the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. Based on some embodiments of the present disclosure, all other embodiments obtained by those skilled in the art are within the scope of protection of the present disclosure.

[0026] Unless the context requires otherwise, throughout this specification and claims, the term "comprise" and other forms, such as the third person singular "comprises" and the present participle form "comprising" should be interpreted in an open, inclusive sense, i.e., "including but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," "specific examples," "some examples," and the like, are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. General expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, a particular feature, structure, material, or characteristic described may be included in any one or more embodiments or examples in any suitable manner.

[0027] In the following, the terms "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying the relative importance or quantity of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of the embodiments of the present disclosure, "plurality" means two or more, unless otherwise specified.

[0028] When describing some embodiments, the term "connected" and expressions derived therefrom may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the present specification.

[0029] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and all of them include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0030] "A and / or B" includes the three combinations of A only, B only, and a combination of A and B.

[0031] As used herein, depending on the context, the word "and" is optionally interpreted to mean "when..." or "upon..." or "in response to determining..." or "in response to detecting...." Similarly, depending on the context, the phrase "if... is determined" or 'if [a described condition or event] is detected' is optionally interpreted to mean "when... is determined," or "in response to determining...," or 'when [a described condition or event] is detected.'

[0032] In this specification, the use of "applied to" or "configured to" is intended to mean open and inclusive language and does not exclude devices that are adapted or configured to perform additional tasks or steps.

[0033] Also, the use of "based on" is meant to be open-ended and inclusive, as a process, step, calculation, or other action that is based on one or more recited conditions or values ​​may, in fact, be based on additional conditions or beyond the recited values.

[0034] As used herein, "about" or "approximately" includes the stated value and the mean within an acceptable range of deviation of the particular value, where the acceptable range of deviation is determined taking into account the measurement contemplated by one of ordinary skill in the art and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

[0035] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances, can be expected. Thus, the exemplary embodiments are not limited to the shapes of regions shown herein, but should be construed as including deviations in shape due to manufacturing or otherwise. For example, an etching region shown as a rectangle will typically have curved features. Thus, the regions shown in the drawings are exemplary in nature, and their shapes are not intended to represent the actual shape of the regions of the facility, nor are they intended to limit the scope of the exemplary embodiments.

[0036] It should be noted that in the circuits provided by the embodiments of the present disclosure, the transistors used may be thin film transistors, field effect transistors, or other switching elements with the same characteristics, and in the embodiments of the present disclosure, thin film transistors are used as examples.

[0037] In some embodiments, the control pole of each transistor in which each circuit is used is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. The source and drain of the transistor may be structurally symmetrical, so that the source and drain may be structurally indistinguishable, i.e., the first pole and the second pole of the transistor in the embodiments of the present disclosure may be structurally indistinguishable. Exemplarily, if the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole is the drain. Exemplarily, if the transistor is an N-type transistor, the first pole of the transistor is the drain, and the second pole is the source.

[0038] In the circuits provided by the embodiments of the present disclosure, the "nodes" do not represent components that actually exist, but represent the junctions of related electrical connections in the circuit diagram, i.e., these nodes are equivalently formed from the junctions of related electrical connections in the circuit diagram.

[0039] The transistors included in the circuits provided by the embodiments of the present disclosure may be either N-type transistors or P-type transistors. Also, some of the transistors included in each circuit may be N-type transistors and another part may be P-type transistors.

[0040] In this disclosure, "effective level" refers to a level that can turn on a transistor.

[0041] In the following, an example will be described in which all the transistors in the circuits provided by the embodiments of the present disclosure are P-type transistors (in this case, the effective level is low). Note that by using the same conductive type of transistors in each of the following circuits, the process flow can be simplified, the process difficulty can be reduced, and the yield of products (e.g., display substrate 100, display device 1000) can be improved.

[0042] In some embodiments of the present disclosure, a display substrate 100 is provided, which has a first display area A1 and a second display area A2, and the second display area A2 at least partially surrounds the first display area A1, as shown in Fig. 1. For example, the area of ​​the second display area A2 is larger than the area of ​​the first display area A1.

[0043] Here, the number of first display regions A1 may be at least 1, and the number of second display regions A2 may be, for example, 1. Below, the structure of the display substrate 100 will be roughly described taking as an example a case where the number of first display regions A1 is 1 as shown in FIG.

[0044] For example, the second display area A2 may surround the first display area A1, and the shape of the first display area A1 may be, for example, a circle, an ellipse, a rectangle, or the like.

[0045] For example, the second display area A2 may surround a portion of the first display area A1, i.e., a portion of the boundary of the second display area A2 overlaps a portion of the boundary of the first display area A1. In this case, the shape of the first display area A1 may be, for example, a rectangle, a rectangle with rounded corners, a teardrop shape, a semicircle, or the like.

[0046] In some embodiments, the above-mentioned display substrate 100 may include a base 1, as shown in FIG.

[0047] There are various types of the above base 1, which can be selected and installed according to actual needs.

[0048] For example, the base 1 may be a rigid base. The rigid base may be a glass base or a PMMA (Polymethyl methacrylate) base, etc.

[0049] For example, the base 1 may be a flexible base. The flexible base may be a PET (Polyethylene terephthalate) base, a PEN (Polyethylene naphthalate two formic acid glycol ester) base, or a PI (Polyimide) base, etc. In this case, the display substrate 100 may realize, for example, a flexible display.

[0050] In some embodiments, the display substrate 100 may further include a pixel circuit layer 2 disposed on a side remote from the base 1, as shown in FIGS.

[0051] 3, 5, and 8, the pixel circuit layer 2 provided on the display substrate 100 may include a semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a source / drain conductive layer, which are sequentially stacked in a direction perpendicular to the base 1 and away from the base 1. Also, a first gate insulating layer may be provided between the semiconductor layer and the first gate conductive layer, a second gate insulating layer may be provided between the first gate conductive layer and the second gate conductive layer, and an interlayer insulating layer may be provided between the second gate conductive layer and the source / drain conductive layer.

[0052] For example, as shown in Figs. 3, 5 and 8, Display board 100 is a transfer layer provided on the side of the source / drain conductive layer away from the base substrate 1. 6 The material of the transfer layer may be the same as that of the source / drain conductive layer. A planarization layer may be provided between the source / drain conductive layer and the transfer layer.

[0053] Exemplarily, the pixel circuit layer 2 may include a plurality of first pixel circuits 21 and a plurality of second pixel circuits 22.

[0054] The above-mentioned first pixel circuit 21 and second pixel circuit 22 have various structures, which can be selected and installed according to actual needs. For example, the structure of the first pixel circuit 21 or the second pixel circuit 22 can have a structure such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C", where "T" represents a transistor, the number before "T" represents the number of transistors, "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors.

[0055] Exemplarily, as shown in FIG. 7, the structure of the first pixel circuit 21 and the structure of the second pixel circuit 22 may be the same, for example. For example, both structures are 7T1C structures. FIG. 7 is an equivalent circuit diagram of the second pixel circuit 22, and FIG. 8 is a structural diagram of one of the second pixel circuits 22 in FIG. 3 or FIG. 5. Hereinafter, the structures of the pixel circuit layer 2 and the second pixel circuit 22 will be roughly described with reference to FIG. 7 and FIG. 8. Of course, the equivalent circuit diagram of the first pixel circuit 21 may be the same as the equivalent circuit shown in FIG. 7, and the structural diagram of the first pixel circuit 21 may be the same as the structural diagram shown in FIG. 8.

[0056] For example, as shown in FIG. 7, the second pixel circuit 22 includes a switching transistor T1, a driving transistor T2, a compensation transistor T3, a first emission control transistor T4, a second emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor Cst.

[0057] When the level of the reset signal transmitted by the reset signal line RST is an effective level, the first reset transistor T6 and the second reset transistor T7 are turned on under the control of the reset signal and can receive the initial signal transmitted from the initial signal line Vinit, and the first reset transistor T6 can transmit the initial signal to one end of the storage capacitor Cst to reset the storage capacitor Cst. The electrode of the light emitting element to be connected to Transmit to Light emitting element can be reset. Now, the drive transistor T2 can be turned on under the control of the initial signal.

[0058] When the level of the scanning signal transmitted by the scanning signal line Gate is an effective level, the switching transistor T1 and the compensation transistor T3 can be turned on under the control of the scanning signal, and the data signal transmitted by the data signal line Data can be sequentially transmitted to the control pole of the driving transistor T2 through the switching transistor T1, the driving transistor T2, and the compensation transistor T3, and can charge the control pole of the driving transistor T2 until the driving transistor T2 is cut off, at which time the compensation of the threshold voltage of the driving transistor T2 is completed.

[0059] When the level of the enable signal transmitted by the enable signal line EM is an effective level, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on under the control of the enable signal and can receive a first voltage signal from the first voltage signal line ELVDD, and the driving transistor T2 generates a driving signal according to the data signal and the first voltage signal, and the driving signal difference is Light emitting element can be transmitted to.

[0060] For example, as shown in FIG. 8, the portions of the semiconductor layer covered by the first gate conductive layer constitute the active layers of the transistors. The portions not covered by the first gate conductive layer may be doped to form conductors. The portions of the first gate conductive layer covering the semiconductor layer constitute the control poles of the transistors, such as the control pole T11 of the switching transistor T1, the control pole T21 of the driving transistor T2, the control pole T31 of the compensation transistor T3, the control pole T41 of the first emission control transistor T4, the control pole T51 of the second emission control transistor T5, the control pole T61 of the first reset transistor T6, and the control pole T71 of the second reset transistor T7.

[0061] For example, a first plate Cst1 of the storage capacitor Cst, a scanning signal line Gate for transmitting a scanning signal, a reset signal line RST for transmitting a reset signal, and an enable signal line EM for transmitting an enable signal may be located in a first gate conductive layer. A second plate Cst2 of the storage capacitor Cst and an initial signal line Vinit for transmitting an initial signal may be located in a second gate conductive layer. A data signal line Data for transmitting a data signal and a first voltage signal line ELVDD for transmitting a first voltage signal may be located in a source-drain conductive layer. The transfer layer may further include a transfer unit 61 for transfer and a shield block 62 for shielding.

[0062] It is understood that the conductors in the semiconductor layers can constitute the first and second poles of each transistor. In this disclosure, in order to clearly identify the first or second pole of a transistor, the portion of the source-drain conductive layer connected to the conductor is referred to as the first or second pole of the transistor.

[0063] As shown in FIG. 8, the first electrode T12 of the switching transistor T1 is integral with the data signal line Data; and Interlayer insulation layer , the second gate insulating layer and the first gate The switching transistor T1 may be connected to an active layer located in the semiconductor layer through a first via hole H1 that passes through the insulating layers in sequence. The control electrode T11 of the switching transistor T1 may be integrally formed with the scanning signal line Gate.

[0064] The second pole of the switching transistor T1 and the second pole of the first light-emitting control transistor T4 are located on a conductor in a semiconductor layer and can be integrated with each other. The first pole T42 of the first light-emitting control transistor T4 is integrated with the first voltage signal line ELVDD. Interlayer insulation layer , the second gate insulating layer and the first gate The fifth via hole H5 may be connected to an active layer located in the semiconductor layer through a fifth via hole H5 that passes through the insulating layers in sequence.

[0065] The first pole of the driving transistor T2 is also located on a conductor in the semiconductor layer and can be integrated with the second pole of the switching transistor T1. The second pole of the driving transistor T2 and the first pole of the compensation transistor T3 are also located on a conductor in the semiconductor layer and can be integrated with each other. The control pole T21 of the driving transistor T2 is integrated with the first plate Cst1 of the storage capacitor Cst. Interlayer insulation layer , the second gate insulating layer and the first gate The second electrode T63 of the first reset transistor T6 may be connected to the second electrode T63 of the first reset transistor T6 through a third via hole H3 that sequentially penetrates the insulating layers.

[0066] The second plate Cst2 of the storage capacitor Cst may be connected to the first voltage signal line ELVDD through a fourth via hole H4 penetrating the interlayer insulating layer.

[0067] The second pole T33 of the compensation transistor T3 can be integrated with the second pole T63 of the first reset transistor T6. The control pole T31 of the compensation transistor T3 can be integrated with the scanning signal line Gate. The compensation transistor T3 is a double-gate transistor.

[0068] The control pole T61 of the first reset transistor T6 may be integral with the reset signal line RST, and the first pole T62 of the first reset transistor T6 may be connected to the initial signal line Vinit through a seventh via hole H7 penetrating the second gate insulating layer.

[0069] The control pole T71 of the second reset transistor T7 can be integral with the reset signal line RST. The first pole T72 of the second reset transistor T7 can be connected to the initial signal line Vinit through an eighth via hole H8 penetrating the second gate insulating layer. The second pole T73 of the second reset transistor T7 is integral with the second pole T53 of the second emission control transistor T5. In the same second pixel circuit 22, the control poles of the first reset transistor T6 and the second reset transistor T7 are connected to different reset signal lines RST, and the first poles of the first reset transistor T6 and the second reset transistor T7 are connected to different initial signal lines Vinit.

[0070] The first electrode of the second light-emitting control transistor T5 is located on the conductor in the semiconductor layer; The first electrode of the second light-emitting control transistor T5 The second pole of the driving transistor T2 and The control electrode T51 of the second light-emitting control transistor T5 is connected to the enable signal line EM and has an integral structure.

[0071] Optionally, as shown in Figures 9 to 11, the above-mentioned multiple second pixel circuits 22 may be arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. The second pixel circuit in each column may include multiple second pixel circuits 22, and the multiple second pixel circuits 22 are sequentially arranged along the second direction Y. The second pixel circuit in each row may include multiple second pixel circuits 22, and the multiple second pixel circuits 22 are sequentially arranged along the first direction X.

[0072] For example, the first direction X intersects with the second direction Y.

[0073] Here, the included angle between the first direction X and the second direction Y can be selected and set according to actual needs, for example, the included angle between the first direction X and the second direction Y is 85°, 88°, or 90°, etc.

[0074] In some examples of the present disclosure, both the first pixel circuit 21 and the second pixel circuit 22 can cover each of the above-mentioned signal lines, but for convenience of explanation, the present disclosure describes the first pixel circuit 21, the second pixel circuit 22, and the signal lines separately.

[0075] In some embodiments, as shown in FIG. 2, FIG. 4 and FIG. 6, the above display substrate 100 may further include a light emitting element layer 3 disposed on the side of the pixel circuit layer 2 away from the base substrate 1.

[0076] For example, the light-emitting element layer 3 may include a plurality of first light-emitting elements 31 and a plurality of second light-emitting elements 32. The structure of the first light-emitting element 31 and the structure of the second light-emitting element 32 may be the same, for example. For example, FIG. 17 As shown in FIG. 1, the first light-emitting element 31 The second light emitting element 32 may also include an anode, a light emitting layer, and a cathode that are stacked in sequence.

[0077] Exemplarily, at least one first pixel circuit 21 may be electrically connected to at least one first light-emitting element 31. For example, the first pixel circuit 21 and the first light-emitting element 31 may be electrically connected in one-to-one correspondence, or one first pixel circuit 21 may be electrically connected to a plurality of first light-emitting elements 31, or a plurality of first pixel circuits 21 may be electrically connected to one first light-emitting element 31. Each first pixel circuit 21 may provide a driving signal to the corresponding first light-emitting element 31 to drive the corresponding first light-emitting element 31 to emit light. As shown in FIG. 7, the present disclosure will be described taking the electrical connection between one first pixel circuit 21 and one first light-emitting element 31 as an example.

[0078] Exemplarily, at least one second pixel circuit 22 may be electrically connected to at least one second light-emitting element 32. For example, the second pixel circuit 22 and the second light-emitting element 32 may be electrically connected in one-to-one correspondence, or one second pixel circuit 22 may be electrically connected to multiple second light-emitting elements 32, or multiple second pixel circuits 22 may be electrically connected to one second light-emitting element 32. Each second pixel circuit 22 may provide a driving signal to the corresponding second light-emitting element 32 to drive the corresponding second light-emitting element 32 to emit light. As shown in FIG. 7, the present disclosure will be described by taking the electrical connection between one second pixel circuit 22 and one second light-emitting element 32 as an example.

[0079] For example, the at least one second light-emitting element 32 and the at least one second pixel circuit 22 at least partially overlap when orthogonally projected on a plane on which the display substrate 100 is located. That is, the second light-emitting element 32 and the second pixel circuit 22 electrically connected to each other may partially or completely overlap when orthogonally projected on a plane on which the display substrate 100 is located.

[0080] The lights emitted from the plurality of first light-emitting elements 31 and the plurality of second light-emitting elements 32 cooperate with each other to realize image display on the display substrate 100. The sum of the areas of the first display region A1 and the second display region A2 is approximately equivalent to the area of ​​the display substrate 100, which is advantageous for increasing the area ratio of the displayable region on the display substrate 100 and increasing the screen-to-body ratio of the display substrate 100, and the display substrate 100 can realize full-screen display.

[0081] In some examples, FIG. 9~ As shown in FIG. 11, the plurality of first pixel circuits 21 and the plurality of second pixel circuits 22 in the pixel circuit layer 2 may all be located in the second display region A2. The plurality of first light-emitting elements 31 in the light-emitting element layer 3 may all be located in the first display region A1, and the plurality of second light-emitting elements 32 may all be located in the second display region A2. The transmittance of the portion of the display substrate 100 located in the first display region A1 is greater than the transmittance of the portion of the display substrate 100 located in the second display region A2.

[0082] Here, the first pixel circuit 21, the second pixel circuit 22 and the signal lines in the pixel circuit layer 2 need to transmit electrical signals well. Based on this, a part of the first pixel circuit 21, a part of the second pixel circuit 22 and the signal lines may be made of a metal material. It is understood that the metal material can block light rays.

[0083] In some examples of the present disclosure, the first pixel circuit 21 that provides a driving signal to the first light-emitting element 31 is provided behind the second display region A2, thereby reducing the structure that can block light in the first display region A1, and external light can also be emitted from one side (e.g., the light-emitting side) of the portion of the display substrate 100 located in the first display region A1 through the gap between any two adjacent first light-emitting elements 31 and out from the other side (e.g., the non-light-emitting side) of the portion of the display substrate 100 located in the first display region A1, so that the portion of the display substrate 100 located in the first display region A1 has high transmittance.

[0084] In this way, when the display substrate 100 is applied to the display device 1000 and the optical element 200 is provided on the non-emitting side of the display substrate 100 in the first display area A1, external light passes through the portion of the display substrate 100 located in the first display area A1, enters the optical element 200, and is collected by the optical element 200, allowing the optical element 200 to operate normally.

[0085] For example, the distribution density of the plurality of first light-emitting elements 31 is the same as the distribution density of the plurality of second light-emitting elements 32. This not only enables the display substrate 100 to realize full-screen display, but also is advantageous in ensuring good image display quality of the display substrate 100.

[0086] Exemplarily, the distribution density of the plurality of first light-emitting elements 31 is smaller than the distribution density of the plurality of second light-emitting elements 32. This increases the interval between any two adjacent first light-emitting elements 31, reduces the blocking of external light by the first light-emitting elements 31, and increases the area of ​​the light-transmittable portion in the portion located in the first display region A1 of the display substrate 100, thereby further increasing the amount of external light that can transmit through the portion located in the first display region A1 of the display substrate 100. After the display substrate 100 is applied to the display device 1000, it is advantageous to improve the amount of external light collected by the optical element 200 and improve the operating performance of the optical element 200.

[0087] In some examples, the above-mentioned display substrate 100 may further include a plurality of leads 41, as shown in FIGS.

[0088] 9 to 11, one end of each lead 41 may be electrically connected to the first pixel circuit 21, and the other end may be electrically connected to the first light-emitting element 31. This allows electrical connection between the first pixel circuit 21 and the first light-emitting element 31 to be realized using the lead 41, and the first pixel circuit 21 may transmit a drive signal to the corresponding first light-emitting element 31 via the lead 41.

[0089] It will be understood that in the process of the lead 41 extending from the first pixel circuit 21 to the first light emitting element 31, a parasitic capacitance may be formed across the first pixel circuit 21 and / or the second pixel circuit 22.

[0090] The presence of the above-mentioned parasitic capacitance is likely to affect the accuracy of the drive signal received by the first light-emitting element 31, and further, is likely to affect the light emission accuracy of the first light-emitting element 31, thereby affecting the display effect of the portion located in the first display region of the display substrate.

[0091] In one implementation, in order to reduce the effect of the parasitic capacitance of the leads, the lead running paths are adjusted so that the parasitic capacitances of different leads tend to match, but this leads to a large variation in the lengths of the different leads, lack of regularity, and the running paths need to be specially designed according to the parasitic capacitances of the different leads, which tends to increase the difficulty of designing and manufacturing the display substrate.

[0092] Based on this, in some examples, as shown in Figs. 9 to 11, the multiple first light-emitting elements 31 located in the first display region A1 can be divided into multiple first light-emitting element groups 31a. The first light-emitting element group 31a can include N first light-emitting elements 31. Correspondingly, the multiple first pixel circuits 21 located in the second display region A2 can be divided into multiple first pixel circuit groups 21a. The first pixel circuit group 21a can include N first pixel circuits 21. The multiple leads 41 can be divided into multiple lead groups 41a. The lead group 41a can include N leads 41. N≧2, where N is an integer.

[0093] For example, the number of first light-emitting elements 31 provided in different first light-emitting element groups 31a may be the same or different. The number of first pixel circuits 21 provided in different first pixel circuit groups 21a may be the same or different. The number of leads 41 provided in different lead groups 41a may be the same or different.

[0094] In the electrically connected first light emitting element group 31a, first pixel circuit group 21a, and lead group 41a, the number of first light emitting elements 31, the number of first pixel circuits 21, and the number of leads 41 are the same.

[0095] For example, in a first light-emitting element group 31a, a first pixel circuit group 21a, and a lead group 41a that are electrically connected, the first light-emitting element group 31a includes 20 first light-emitting elements 31, the first pixel circuit group 21a includes 20 first pixel circuits 21, and the lead group 41a includes 20 leads 41. Each first light-emitting element 31 is electrically connected to a corresponding one of the first pixel circuits 21 by one lead 41.

[0096] For example, along the first direction X from the second display region A2 to the first display region A1, the N first light-emitting elements 31 in the first light-emitting element group 31a are the 1st to Nth first light-emitting elements, respectively.

[0097] It is understood that the second display region A2 surrounds the first display region A1 on both sides facing each other along the first direction X, based on the positional relationship between the first display region A1 and the second display region A2. For example, as shown in FIG. 1, the present disclosure refers to the portions of the second display region A2 located on both sides of the first display region A1 along the first direction X as the first sub-region A21a and the second sub-region A22a, respectively. In this case, the above-mentioned "pointing along the first direction X and from the second display region A2 to the first display region A1" refers to pointing along the first direction X and from the first sub-region A21a to the first display region A1, and / or pointing along the first direction X and from the second sub-region A22a to the first display region A1.

[0098] For example, the above "pointing along the first direction X from the second display region A2 to the first display region A1" means that, when pointing along the first direction X from the first sub-region A21a to the first display region A1, the first first light-emitting element of the N first light-emitting elements 31 in the first light-emitting element group 31a is closest to the first sub-region A21a, i.e., closest to the boundary of the first display region A1. That is, the second, third, fourth, ... N-1th, and Nth first light-emitting elements are successively farther away from the first sub-region A21a.

[0099] Also, for example, the above phrase "pointing along the first direction X from the second display region A2 to the first display region A1" means that, when pointing along the first direction X from the second sub-region A22a to the first display region A1, the first first light-emitting element of the N first light-emitting elements 31 in the first light-emitting element group 31a is closest to the second sub-region A22a, i.e., closest to the boundary of the first display region A1. That is, the second, third, fourth, ... N-1th, and Nth first light-emitting elements are successively farther away from the second sub-region A22a.

[0100] Also, for example, the above "pointing along the first direction X from the second display region A2 to the first display region A1" means that, in the case of pointing along the first direction X from the first sub-region A21a to the first display region A1 and pointing along the first direction X from the second sub-region A22a to the first display region A1, among the first light-emitting element groups 31a of a part of the above-mentioned plurality of first light-emitting element groups 31a, the first first light-emitting element is closest to the first sub-region A21a, the other first light-emitting elements are successively farther away from the first sub-region A21a, and there is a fixed interval between the Nth first light-emitting element and the second sub-region A22a. Among the first light-emitting element groups 31a of another part, the first first light-emitting element is closest to the second sub-region A22a, the other first light-emitting elements are successively farther away from the second sub-region A22a, and there is a fixed interval between the Nth first light-emitting element and the first sub-region A21a.

[0101] For example, the N first pixel circuits 21 in the first pixel circuit group 21a are the first to Nth first pixel circuits, respectively. The first to Nth first pixel circuits are provided sequentially along a direction away from the first display region A1.

[0102] That is, in the first pixel circuit group 21a, the first pixel circuit 21 closest to the first light-emitting element group 31a is the first first pixel circuit. The second, third, fourth, ... N-1th and Nth first pixel circuits are successively farther away from the first light-emitting element group 31a.

[0103] The first pixel circuits may be arranged in various directions, and may be arranged in a manner selected according to actual needs.

[0104] For example, the arrangement direction of the 1st to Nth first pixel circuits may be the first direction X. That is, the arrangement direction of the multiple first pixel circuits 21 in the first pixel circuit group 21a is the same as the arrangement direction of the multiple first light-emitting elements 31 in the first light-emitting element group 31a.

[0105] In addition, for example, the arrangement direction of the first pixel circuits from the 1st to the Nth first pixel circuits may have an included angle with the first direction X. The size of the included angle can be selected and set according to actual needs. Optionally, the included angle may be 45° or 90°.

[0106] 9 to 11, the N leads 41 included in the lead group 41a are arranged in parallel. The extension directions of the N leads 41 are, for example, parallel or approximately parallel.

[0107] For example, the i-th first light-emitting element is electrically connected to the i-th first pixel circuit by the i-th lead, where i=1 to N. That is, the first first light-emitting element may be electrically connected to the first first pixel circuit by the first lead, the second first light-emitting element may be electrically connected to the second first pixel circuit by the second lead, the N-1-th first light-emitting element may be electrically connected to the N-1-th first pixel circuit by the N-1-th lead, and the N-th first light-emitting element may be electrically connected to the N-th first light-emitting element by the N-th lead.

[0108] For example, the lengths of the first to Nth leads gradually increase.

[0109] It will be understood that the first to Nth first pixel circuits in the first pixel circuit group 21a are successively separated from the first light-emitting element group 31a along the arrangement direction, which means that the distance between the first, second, third, ... N-1th, Nth first pixel circuit and the first light-emitting element group 31a gradually increases, and correspondingly, the distance between the first first pixel circuit and the first first light-emitting element, the distance between the second first pixel circuit and the second first light-emitting element ... the distance between the N-1th first pixel circuit and the N-1th first light-emitting element, and the distance between the Nth first pixel circuit and the Nth first light-emitting element gradually increase. As a result, the length of the first lead connecting the first first pixel circuit and the first first light-emitting element, the length of the second lead connecting the second first pixel circuit and the second first light-emitting element...the length of the N-1th lead connecting the N-1th first pixel circuit and the N-1th first light-emitting element, and the length of the Nth lead connecting the Nth first pixel circuit and the Nth first light-emitting element also gradually become longer.

[0110] For example, a portion of each lead 41 located between the corresponding first pixel circuit 21 and the corresponding first light-emitting element 31 is linear. In this case, the length of the lead 41 refers to, for example, the distance between the corresponding first pixel circuit 21 and the corresponding first light-emitting element 31. This not only facilitates the manufacture and formation of the lead 41, but also prevents the lead 41 from having bends or sharp tips, thereby ensuring good transmission of the driving signal through the lead 41.

[0111] By using the above-mentioned installation method and connection method in the present disclosure, it becomes easy to plan the running path of the leads 41, and not only improves the regularity of the difference in length between any two adjacent leads 41 in the lead group 41a, but also reduces the number of leads 41 required to be used, simplifies the structure of the display substrate 100, and reduces the difficulty of manufacturing and forming the display substrate 100.

[0112] Furthermore, the first pixel circuits 21, the second pixel circuits 22, and the signal lines are regularly arranged in the pixel circuit layer 2. This makes it possible to improve the regularity of the difference in the quantity of the first pixel circuits 21 and / or the second pixel circuits 22 straddled by any two adjacent leads 41 in the lead group 41a during the process in which the leads 41 extend, and further makes it easy to improve the uniformity of the change in the parasitic capacitance formed by any two adjacent leads 41 in the lead group 41a.

[0113] Here, the present disclosure may use, for example, an external compensation method, which compensates for the parasitic capacitance formed by the lead 41, improves the accuracy of the driving signal received and the light emitted by the first light emitting element 31, and ensures the display effect of the portion located in the first display region of the display substrate. The above external compensation method includes, but is not limited to, an external optical compensation (demura) method.

[0114] The present disclosure is advantageous for optimizing the algorithm of external optical compensation (demura) by improving the uniformity of the change in parasitic capacitance formed by any two adjacent leads 41 in the lead group 41a, and is useful for improving the display uniformity of the display substrate 100 and improving the quality of the image displayed by the display substrate 100.

[0115] In some examples, as shown in FIGS. 9 to 11, a first light emitting element and a first pixel circuit are 、 At least one row of second pixel circuits or at least one column of second pixel circuits are provided. The N leads 41 in the lead group 41a extend from the first display area A1 through the at least one row of second pixel circuits or the at least one column of second pixel circuits to the second display area A2.

[0116] For example, one, three, four or seven rows of second pixel circuits can be provided with a gap between the first first light-emitting element and the first first pixel circuit, or one, three, four, eight, ten or second columns of second pixel circuits can be provided with a gap between the first first light-emitting element and the first first pixel circuit.

[0117] For example, as shown in FIG. 9 to FIG. 11, between the first first light emitting element and the first first pixel circuit, 、 When at least one column of second pixel circuits is provided, the first lead in the lead group 41a extends from the first display area A1, straddling the at least one column of second pixel circuits, to the second display area A2, and the second, third, ... Nth leads extend from the first display area A1, straddling the at least one column of second pixel circuits, and then continuing to straddle the at least one column of second pixel circuits to the second display area A2.

[0118] In one implementation, the first first light-emitting element and the first first pixel circuit are adjacent to each other, and no second pixel circuit is provided between them with a gap therebetween. In this case, the length of the first lead, which is the shortest in the lead group, is, for example, L. For example, the difference in length between any two adjacent leads in the lead group is m, and the length of the Nth lead, which is the longest, is L+m(N-1). The ratio of the length of the Nth lead to the length of the first lead is shown in the following formula 1.

[0119]

number

[0120] In some examples of the present disclosure, between the first first light-emitting element and the first first pixel circuit 、After at least one row of second pixel circuits or at least one column of second pixel circuits are provided, the length of the first lead connecting the first first light-emitting element and the first first pixel circuit is, for example, L+p. For example, the difference in length between any two adjacent leads in the lead group is m, and in this case, the length of the Nth lead, which is the longest, is L+p+m(N-1). The ratio of the length of the Nth lead to the length of the first lead is shown in the following formula 2.

[0121]

number

number

number

[0122] That is, the present disclosure provides a first light-emitting element and a first pixel circuit. 、 After at least one row of second pixel circuits or at least one column of second pixel circuits are provided, the length of the first lead can be increased by a large multiple, but the length of the Nth lead can be increased by a small multiple, thereby effectively reducing the ratio between the length of the Nth lead and the length of the first lead, and effectively reducing the ratio between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead.

[0123] The smaller the length ratio between the Nth lead having the longest length and the first lead having the shortest length, the smaller the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead, and the smaller the difference between the loss of the driving signal in the Nth lead and the loss in the first lead, so that the display substrate 100 can reduce the difference in the display gray scale and improve the display quality in the process of displaying an image. Furthermore, in the process of compensating for the difference in the gray scale using the external optical compensation (demura) algorithm, the smaller the difference in the display gray scale, the smaller the workload of the external optical compensation (demura) algorithm, which is advantageous for further optimizing the external compensation (demura) algorithm. In addition, after the difference in the display gray scale is reduced to a certain extent, it may become unnecessary to compensate using the external optical compensation (demura) algorithm, that is, good image quality of the display substrate 100 can be ensured.

[0124] As described above, the display substrate 100 provided by some embodiments of the present disclosure includes a first display region A1 and a second display region A2, and includes a first light emitting element 31 in the first display region A1 and a first pixel circuit 21 for providing a driving signal to the first light emitting element 31 in the second display region A2. This avoids the first pixel circuit 21 blocking light incident on the first display region A1 and improves the transmittance of the portion of the display substrate 100 located in the first display region A1. After the display substrate 100 is applied to the display device 1000, external light can pass through the portion of the display substrate 100 located in the first display region A1 and enter the optical element 200 of the display device 1000. This allows the optical element 200 to operate normally, increases the ratio of the displayable area of ​​the display substrate 100, and allows the display substrate 100 and the display device 1000 to realize full-screen display.

[0125] Furthermore, in the present disclosure, a lead 41 is provided to connect the first light-emitting element 31 and the first pixel circuit 21, and N leads 41 are provided in parallel in the lead group, so that the lengths of the first to Nth leads are gradually increased, and a first light-emitting element in the first light-emitting element group 31a and a first pixel circuit in the first pixel circuit group 21a are gradually increased. 、 By providing at least one row of second pixel circuits or at least one column of second pixel circuits, it becomes easy to plan the running path of the leads 41, and the regularity of the difference in length between any two adjacent leads 41 in the lead group 41a is improved, and the uniformity of the change in parasitic capacitance formed by any two adjacent leads 41 in the lead group 41a is improved. To By using at least one row of second pixel circuits or at least one column of second pixel circuits provided, the length of the first lead can be significantly increased, and the ratio between the length of the Nth lead and the length of the first lead can be reduced, the ratio between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead can be reduced, the difference in the display gray scale of the display substrate 100 can be reduced, the algorithm of external optical compensation (DEMURA) can be optimized, and the algorithm of external optical compensation (DEMURA) can be saved.

[0126] In some embodiments, among the N leads 41 included in the lead group 41a, the ratio of the length of the Nth lead to the length of the first lead is α, where α≦25.

[0127] In some examples, α=25, α≦24, α≦22, α≦20, or α≦18, etc.

[0128] By setting the length ratio between the Nth lead and the first lead to be 25 or less, the length ratio between the Nth lead having the longest length and the first lead having the shortest length can be effectively reduced, thereby reducing the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead, and further reducing the difference in gray scale of the image displayed by the display substrate 100. Furthermore, in the process of compensating for the difference in gray scale using a subsequent external optical compensation (demura) algorithm, the workload of the external optical compensation (demura) algorithm can be reduced, and the external compensation (demura) algorithm can be optimized.

[0129] For example, the length ratio α satisfies α≦15.

[0130] By setting the length ratio between the Nth lead and the first lead to 15 or less, the length ratio between the Nth lead having the longest length and the first lead having the shortest length can be further reduced, and the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead can be further reduced, thereby further reducing the difference in gray scale of the image displayed by the display substrate 100. Furthermore, in the process of compensating for the difference in gray scale using the external optical compensation (demura) algorithm thereafter, the workload of the external optical compensation (demura) algorithm can be further reduced, and the external compensation (demura) algorithm can be further optimized.

[0131] For example, the value range of the length ratio α may be 5-10, 10-15, 15-20, or 7-13, etc.

[0132] For example, the value of the length ratio α may be 5, 6, 7.5, 9.1, 10, 12, 14, or 15, etc.

[0133] In some embodiments, the number of rows or columns of the second pixel circuits spaced apart between the first first light emitting element and the first first pixel circuit is β, where β≦30.

[0134] 9 to 11, in some examples, the N first pixel circuits in the first pixel circuit group 21a are sequentially arranged along the first direction X. At this time, at least one column of second pixel circuits is arranged at intervals between the first first light-emitting element and the first first pixel circuit. The number of columns of the spaced second pixel circuits 22 is β, where β≦30.

[0135] For example, the above β satisfies β=30, β≦28, β≦25, β≦21, β≦20, or β≦15, etc.

[0136] By using the above installation method, the multiple of the increase in length of the Nth lead can be kept small, so that the ratio of the length of the Nth lead to the first lead can be kept small, thereby ensuring good improvement effects on the gray scale difference of the image displayed by the display substrate 100 and good optimization effects on the external compensation (DEMURA) algorithm.

[0137] In some embodiments, the ratio of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit is γ, where 5≦γ≦50.

[0138] It is understood that in addition to the first first light-emitting element and the first first pixel circuit, a first pixel circuit 21 and a second pixel circuit 22 are provided at an interval between the i-th first light-emitting element and the i-th first pixel circuit. That is, the pixel circuit provided at an interval between the N-th first light-emitting element and the N-th first pixel circuit includes a first pixel circuit and a second pixel circuit.

[0139] In addition, since the shape of the first display region A1 is deformable, the number of first light-emitting elements 31 provided in different first light-emitting element groups 31a may be different. For example, as shown in Fig. 1, the closer the first light-emitting element group 31a is to the upper or lower boundary of the first display region A1 along the second direction Y, the fewer the number of first light-emitting elements 31 provided in the first light-emitting element group 31a, and the closer the first light-emitting element group 31a is to the central boundary of the first display region A1, the greater the number of first light-emitting elements 31 provided in the first light-emitting element group 31a.

[0140] In the first light-emitting element group 31a having a small number, the ratio γ of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit may be small. In the first light-emitting element group 31a having a large number, the ratio γ of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit may be large.

[0141] By using the above installation method, the length of the Nth lead is not too long, and the length ratio between the Nth lead and the first lead can be ensured to be small, thereby ensuring a good improvement effect on the gray scale difference of the image displayed by the display substrate 100, and a good optimization effect on the external compensation (DEMURA) algorithm.

[0142] In some embodiments, the sequence formed by the length values ​​of the N reeds 41 in the reed group 41a is an arithmetic progression. That is, the difference in length between any two adjacent reeds 41 is equal. Or, the sequence formed by the length values ​​of the N reeds 41 in the first direction X in the reed group 41a is an arithmetic progression. That is, the difference in length between any two adjacent reeds 41 is equal.

[0143] It will be understood that when there is an included angle between the extension direction of the lead 41 and the first direction X, the length of the lead 41 in the first direction X is the amount of the actual length of the lead 41 in the first direction X.

[0144] For example, the length of the first lead is, for example, L, and the difference in length between any two adjacent leads 41 in the lead group 41a is m. In this case, the sequence formed by the length values ​​of the above N leads 41 is L, L+m, L+2m, L+3m....L+m(N-2), L+m(N-1). For the length values ​​of the leads 41 in the first direction X, please refer to the description here and will not be described repeatedly.

[0145] By arranging the sequence formed by the length values ​​of the N leads 41 or the length values ​​in the first direction X in an arithmetic progression, it is possible to ensure that the length values ​​of the N leads 41 change uniformly, which is advantageous for optimizing the algorithm of external optical compensation (demura) and improving the display quality of the display substrate 100. Furthermore, using this arrangement is also advantageous for improving the uniformity of the change in the parasitic capacitance formed by the N leads 41, which is advantageous for further optimizing the algorithm of external optical compensation (demura) and further improving the display quality of the display substrate 100.

[0146] In some embodiments, the progression formed by the resistance values ​​of the N leads 41 in the lead group 41a is an arithmetic progression, i.e., the difference in resistance value between any two adjacent leads 41 is equal.

[0147] For example, the resistance value of the first lead is R, and the difference in resistance value between two adjacent leads 41 in the lead group 41a is t. In this case, the sequence formed by the resistance values ​​of the above N leads 41 is R, R+t, R+2t, R+3t...R+t(N-2), R+t(N-1).

[0148] It is understood that after the drive signal provided by the first pixel circuit 21 is transmitted to the lead 41, the presence of resistance in the lead 41 will cause some loss in the drive signal, reducing the accuracy of the drive signal received by the first light-emitting element 31.

[0149] By arranging the sequence formed by the resistance values ​​of the above N leads 41 in an arithmetic progression, it is possible to ensure that the resistance values ​​of the N leads 41 change uniformly, which is advantageous in reducing the difficulty of compensating for the resistance of the leads 41 and improves the display quality of the display substrate 100.

[0150] In some embodiments, a parasitic capacitance is formed between each lead 41 and the second pixel circuit 22 and / or the first pixel circuit 21 through which it passes. The progression formed by the parasitic capacitance values ​​formed by the above N leads 41 is an arithmetic progression. That is, the difference between the parasitic capacitances formed by any two adjacent leads 41 is equal.

[0151] For example, the parasitic capacitance value formed by the first lead is, for example, Cs, and the parasitic capacitance difference between any two adjacent leads 41 in the lead group 41a is u. The parasitic capacitance value formed by The sequence constructed by this is Cs, Cs+u, Cs+2u, Cs+3u……Cs+u(N-2), Cs+u(N-1).

[0152] It is understood that after the driving signal provided by the first pixel circuit 21 is transmitted to the lead 41, the presence of parasitic capacitance in the lead 41 will cause a large loss in the driving signal, significantly reducing the accuracy of the driving signal received by the first light-emitting element 31, and delaying the time at which the first light-emitting element 31 receives the driving signal.

[0153] By arranging the sequence of parasitic capacitance values ​​formed by the N leads 41 in an arithmetic progression, it is possible to ensure that the parasitic capacitance values ​​formed by the N leads 41 are uniformly changed. This makes it easy to compensate for the parasitic capacitance values ​​and delay times, which is advantageous for optimizing the algorithm for external optical compensation (demura), and is advantageous for improving the display quality of the display substrate 100.

[0154] It will be understood that there may be a plurality of arrangement methods for the arrangement direction of the 1st to Nth first pixel circuits in the first pixel circuit group 21a.

[0155] In some examples, the arrangement direction is a first direction X, as shown in FIGS.

[0156] Exemplarily, the first light-emitting element group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting element group 31a are provided in the same row. That is, the first light-emitting element group 31a and the first pixel circuit group 21a are located in the same row along the first direction X. Correspondingly, the N leads 41 in the lead group 41a can extend along the first direction X.

[0157] At this time, between the first first light emitting element and the first first pixel circuit 、 At least one column of second pixel circuits may be provided. Correspondingly, the N leads 41 may extend from the first display area A1 through the at least one column of second pixel circuits along the first direction X to the second display area A2.

[0158] Array Direction in the first direction X, and by arranging the first light-emitting element group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting element group 31a in the same row, it is possible to facilitate the arrangement of signal lines (e.g., gate lines) in the pixel circuit layer 2, facilitate the driving of the first pixel circuit group 21a, and reduce the difficulty of designing and manufacturing the display substrate 100.

[0159] It is understood that since the first pixel circuit group 21a can be installed in the same row as the second pixel circuit of one row, it is advantageous to simultaneously drive the pixel circuit group 21a and the second pixel circuit of one row. Since at least one second pixel circuit 22 can be installed between any two adjacent first pixel circuits 21, it is possible to reduce the positional deviation between the second pixel circuit 22 and the corresponding second light-emitting element 32. For example, the number of second pixel circuits 22 spaced apart from each other between any two adjacent first pixel circuits 21 is the same. This is advantageous in improving the uniformity of the change in length of the N leads 41 in the lead group 41a and improving the uniformity of the change in parasitic capacitance formed by the N leads 41.

[0160] 9, the first pixel circuit group 21a may include 20 first pixel circuits 21, the first light emitting element group 31a may include 20 first light emitting elements 31, and the lead group 41a may include 20 leads 41. A space is provided between the first first light emitting element and the first first pixel circuit. 4 The second pixel circuit of the column can be disposed between any two adjacent first pixel circuits 21. 、 Two second pixel circuits 22 are provided, that is, one first pixel circuit 21 is provided between each two second pixel circuits 22 with a gap therebetween.

[0161] For example, as shown in FIG. 9, along the first direction X, the dimension of the area occupied by each second pixel circuit 22 or each first pixel circuit 21 is b, the dimension of the area occupied by each first light-emitting element 31 is c, and 3b=2c.

[0162] In this case, if a second pixel circuit is not provided with a gap between the first first light emitting element and the first first pixel circuit, the length of the first lead is the sum of the dimensions of the area occupied by the first first pixel circuit and the first first pixel circuit, i.e., b+c=2.5b. The length difference between any two adjacent leads is the sum of the dimensions of the area occupied by two second pixel circuits, one first pixel circuit, and one first light emitting element, i.e., 2b+b+c=3b+c. Nth lead ( for example The length of the first reed (b+c, 20th reed) is (b+c)+19(3b+c)=88b. The ratio of the length of the 20th reed to the length of the first reed is 35.20.

[0163] In the case where six columns of second pixel circuits are provided between the first first light-emitting element and the first first pixel circuit, the length of the first lead is the sum of the dimensions of the area occupied by the first first pixel circuit, the first first light-emitting element, and the six second pixel circuits provided between the first first pixel circuit and the first first light-emitting element, i.e., b+c+6b=7b+c. Since 3b=2c, 7b+c=8.5b. The length difference between any two adjacent leads is the sum of the dimensions of the area occupied by two second pixel circuits, one first pixel circuit, and one first light-emitting element, i.e., 2b+b+c=3b+c. The length of the Nth (i.e., 20th) lead is (7b+c)+19(3b+c)=94b. The ratio of the length of the 20th lead to the length of the first lead is 11.06 (two decimal places reserved).

[0164] As can be seen from the above, after six rows of second pixel circuits are spaced apart between the first first light emitting element and the first first pixel circuit, the length of the first lead increases by 6b, the increase factor is relatively large, and the length of the Nth lead also increases by 6b, the increase factor is relatively small, compared with the case where the second pixel circuits are not spaced apart. Correspondingly, the ratio between the length of the 20th lead and the length of the first lead is greatly reduced, which is favorable for optimizing the algorithm of external optical compensation (demura).

[0165] Optionally, the present disclosure also provides a second pixel circuit 22 between each of the four second pixel circuits 22. 、 One first pixel circuit 21 can be placed between each of six second pixel circuits 22. 、 One first pixel circuit 21 can be placed between each of seven second pixel circuits 22. 、 One first pixel circuit 21 can be installed, which allows the Nth lead Lengthand the first lead Length The ratio of to can be reduced and the algorithm for external optical compensation (demura) can be optimized.

[0166] In some other examples, the included angle between the arrangement direction and the first direction X is 45°. In this case, the N leads 41 in the lead group 41a can extend, for example, along a direction perpendicular to the first direction X, and extend from the first display area A1 along the direction perpendicular to the first direction X through at least one row or at least one column of second pixel circuits to the second display area A2.

[0167] In some examples, the angle between the arrangement direction and the first direction X is 90°. In this case, the angle between the extension direction of the N leads 41 in the lead group 41a and the first direction X is, for example, 45°. The N leads 41 can extend from the first display area A1 along a direction that forms an angle of 45° with the first direction X, through at least one row or at least one column of second pixel circuits, to the second display area A2.

[0168] It is understood that the number of rows or columns of second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit can be selected and installed according to actual needs, and therefore the ratio of the length of the Nth lead 41 to the first lead 41 can be made equal to or less than a preset value.

[0169] Optionally, the number of rows or columns of the second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit is related to the arrangement manner of the sub-pixels P on the display substrate 100. That is, the arrangement manner of different sub-pixels P may be different, and the number of rows or columns of the second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit may be different. This is advantageous to ensure the normal use of the external optical compensation algorithm (demura) and avoid confusion in the algorithm.

[0170] Exemplarily, the sub-pixel P may include a second pixel circuit 22 and a second light-emitting element 32 electrically connected together. Of course, the sub-pixel P may also include a first pixel circuit 21 and a first light-emitting element 31 electrically connected together.

[0171] Hereinafter, the above-mentioned arrangement direction is defined as the first direction X, and a case where the first light-emitting element group 31a and the first pixel circuit group 21a electrically connected to the light-emitting element group 31a are arranged in the same row will be taken as an example, and a general description will be given of the number of columns of second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit according to different arrangement methods of the sub-pixels P.

[0172] In some examples, as shown in FIG. 12, a display substrate 100 includes a plurality of pixel units, and each pixel unit includes three sub-pixels P arranged along a first direction X.

[0173] Exemplarily, the above three sub-pixels P include a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B), where R, G and B are periodically arranged along the first direction X.

[0174] Exemplarily, X second pixel circuits 22 belonging to at least one pixel unit are provided at intervals between the first first light-emitting element and the first first pixel circuit, where X is a multiple of three.

[0175] For example, three, six, nine, twelve, etc. second pixel circuits 22 can be provided at intervals between the first first light emitting element and the first first pixel circuit.

[0176] 13, the display substrate 100 includes a plurality of pixel units, and each pixel unit includes a plurality of sub-pixels P. The pixel units are arranged in a pentile array.

[0177] For example, the Pentile arrangement means that one sub-pixel is added based on RGB to realize, for example, RGBG, RGBW, RGBY, and some of the sub-pixels P in the Pentile arrangement are "shared", so that a higher resolution than the actual resolution is realized in terms of visual effect. W represents a white sub-pixel, and Y represents a yellow sub-pixel. The number of sub-pixels P provided in each pixel unit can be determined according to the sharing situation, and the present disclosure is not limited thereto.

[0178] Exemplarily, Y second pixel circuits belonging to at least one pixel unit are provided at intervals between a first first light-emitting element and a first first pixel circuit, where Y is a multiple of two.

[0179] For example, two, four, six, eight, etc. second pixel circuits 22 can be provided at intervals between the first first light emitting element and the first first pixel circuit.

[0180] 10 and 11, the display substrate 100 has a straight line extending along the second direction Y and passing through the first display area A1, which may be referred to as the reference line D-D'. The second direction Y is, for example, perpendicular to the first direction X.

[0181] The positional relationship between the first pixel circuit group 21a, the first light-emitting element group 31a, the lead group 41a, and the reference line D-D' provided on the display substrate 100 can be varied and can be selected and installed according to actual needs.

[0182] In some examples, the first pixel circuit group 21a, the first light emitting element group 31a, and the lead group 41a can all be located on the same side of the reference line DD'.

[0183] 10 and 11, the plurality of first light-emitting elements 31 located in the first display area A1 may be arranged in a plurality of rows along the second direction Y, and the first light-emitting elements 31 in each row may include a plurality of first light-emitting elements 31 sequentially arranged along the first direction X. The first light-emitting elements in each row may be divided into two first light-emitting element groups 31a located on both sides of the reference line D-D'.

[0184] Correspondingly, two first pixel circuit groups 21a electrically connected to two first light emitting element groups 31a located in the same row may be located on opposite sides of the first display area A1 in the first direction X. In this case, the two first pixel circuit groups 21a are located on both sides of the reference line D-D'.

[0185] Correspondingly, the two lead groups 41a electrically connected to the two first light-emitting element groups 31a located in the same row are located on both sides of the reference line DD', respectively.

[0186] By disposing the first pixel circuit group 21a, the first light emitting element group 31a, and the lead group 41a on both sides of the reference line D-D', it is possible to reduce the number of first pixel circuits 21 provided in the first pixel circuit group 21a, the number of first light emitting elements 31 provided in the first light emitting element group 31a, and the number of leads 41 provided in the lead group 41a. This is advantageous in reducing the complexity of the running path of the leads 41, and is also advantageous in reducing the pressure of the external optical compensation (demura) algorithm.

[0187] For example, as shown in FIGS. 10 and 11, the two lead groups 41a electrically connected to the two first light-emitting element groups 31a are disposed symmetrically with respect to the reference line DD'.

[0188] This not only further reduces the complexity of the running path of the lead 41, but also is advantageous in making the length change rules of the above two lead groups 41a and the change rules of the parasitic capacitance formed by them the same, thereby further reducing the pressure on the external optical compensation (DEMURA) algorithm and optimizing the external optical compensation (DEMURA) algorithm.

[0189] For example, as shown in FIGS. 10 and 11, the first display area A1 has a center O, and the reference line D-D' is a straight line passing through the center O.

[0190] This allows the number of first light-emitting elements 31 provided in the two first light-emitting element groups 31a located in the same row to be the same, and further allows the number of first light-emitting elements 31 provided in the two corresponding first pixel circuits group The number of first pixel circuits provided in the lead groups 21a can be the same, and the number of leads 41 provided in the two corresponding lead groups 41a can be the same, which is advantageous in reducing the pressure of the external optical compensation (demura) algorithm.

[0191] It is understood that the first light emitting element 31 and the corresponding lead 41 are electrically connected through a transfer hole 5 (ie, a via hole) to avoid short circuit.

[0192] Based on this, in some examples, as shown in Figures 14 and 15, the display substrate 100 further includes a transfer hole group 5a. The transfer hole group 5a includes N transfer holes 5. The N transfer holes 5 are sequentially arranged along the first direction X and respectively correspond to the N first light-emitting elements 31 in the first light-emitting element group 31a.

[0193] For example, the N transfer holes 5 in the transfer hole group 5a and the N first light-emitting elements 31 in the first light-emitting element group 31a are provided in one-to-one correspondence. The N transfer holes 5 in the transfer hole group 5a and the N leads 41 in the lead group 41a are provided in one-to-one correspondence. This allows each first light-emitting element 31 to be electrically connected to the corresponding lead 41 via the corresponding transfer hole 5.

[0194] Optionally, the orthogonal projection shape of the transfer hole 5 on the base 1 can be selected and set according to actual needs. For example, the orthogonal projection shape of the transfer hole 5 on the base 1 can be circular or square, etc.

[0195] Here, the positional relationship between the N leads 41 in the lead group 41a and the transfer hole group 5a may be various. Below, a schematic explanation will be given of an example in which the first light emitting element group 31a and the first pixel circuit group 21a electrically connected to the first light emitting element group 31a are arranged in the same row along the first direction X.

[0196] For example, as shown in FIG. 14, along the second direction Y, the i-th lead electrically connected to the i-th first light-emitting element is closer to the transfer hole group 5a than the i+1-th lead electrically connected to the i+1-th first light-emitting element.

[0197] That is, the N leads 41 in the lead group 41a are located on the same side of the transfer hole group 5a, and along the second direction Y, the first, second, third, ... N-1th, and Nth leads are sequentially separated from the transfer hole group 5a.

[0198] For example, as shown in FIG. 15, the i-th lead electrically connected to the i-th first light-emitting element and the i+1-th lead electrically connected to the i+1-th first light-emitting element are respectively located on opposite sides of the transfer hole group 5a in the second direction Y.

[0199] That is, in the lead group 41a, an odd number of leads can be located on one side of the transfer hole group 5a in the second direction Y, and an even number of leads can be located on the other side of the transfer hole group 5a in the second direction Y.

[0200] 2 to 6, the display substrate 100 may further include a plurality of lead layers 4 provided between the pixel circuit layer 2 and the light emitting element layer 3. The plurality of lead layers 4 may be stacked in sequence along a direction perpendicular to the base 1. For example, the number of lead layers 4 may be two, three or more.

[0201] Between the pixel circuit layer 2 and the plurality of lead layers 4 、 An insulating layer may be provided between any two adjacent lead layers 4. 、 An insulating layer can be provided between the plurality of lead layers 4 and the light emitting element layer 3. 、 An insulating layer can be provided. As shown in Fig. 4, the transfer hole group 5a may be located in the insulating layer between the above-mentioned multiple lead layers 4 and the light emitting element layer 3. In Fig. 4, the light emitting element layer 3 is represented as an anode.

[0202] In some examples, the N leads 41 in the lead group 41a are located on the multiple lead layers 4, respectively.

[0203] Exemplarily, each lead layer 4 may include at least one lead 41 out of the N leads 41 .

[0204] 4, 6 and 17, each lead layer 4 may further include a plurality of connecting portions 42. The connecting portions 42 may change the layer of the lead 41 electrically connected thereto, and the lead 41 may be electrically connected to the corresponding first light emitting element 31 or first pixel circuit 21.

[0205] For example, as shown in Figures 3 and 4, the number of lead layers 4 is three, and as shown in Figure 4, along the vertical direction and the direction away from the base 1, the three lead layers 4 are respectively a first lead layer 4a, a second lead layer 4b, and a third lead layer 4c.

[0206] As shown in FIG. 4, each second pixel circuit 22 can be electrically connected to a corresponding second light-emitting element 32 via a connection portion 42 located on the first lead layer 4a, a connection portion 42 located on the second lead layer 4b, and a connection portion 42 located on the third lead layer 4c, in that order. 4 In the second pixel circuit 22, the anode of the second light emitting element 32 is used to represent the second light emitting element 32. Second light emission control The second pixel circuit 22 is represented using transistor T5.

[0207] For example, a portion of the first pixel circuit 21 may be electrically connected to one end of a lead 41 located on the first lead layer 4a, and the other end of the lead 41 may be electrically connected to a corresponding first light-emitting element 31, sequentially via a connection portion 42 located on the second lead layer 4b and a connection portion 42 located on the third lead layer 4c.

[0208] For example, a portion of the first pixel circuit 21 can be electrically connected to one end of a lead 41 located on the second lead layer 4b via a connection portion 42 located on the first lead layer 4a, and the other end of the lead 41 can be electrically connected to a corresponding first light-emitting element 31 via a connection portion 42 located on the third lead layer 4c.

[0209] For example, a portion of the first pixel circuit 21 can be electrically connected to one end of a lead 41 located on the third lead layer 4c via a connection portion 42 located on the first lead layer 4a and a connection portion 42 located on the second lead layer 4b, and the other end of the lead 41 can be electrically connected to the corresponding first light-emitting element 31.

[0210] For example, as shown in FIG. 5 and FIG. 6, the number of lead layers 4 is two. 61, along the vertical direction and the direction away from the base 1, the two lead layers 4 are a first lead layer 4a and a second lead layer 4b, respectively.

[0211] As shown in FIG. 6, each second pixel circuit 22 can be electrically connected to a corresponding second light-emitting element 32 via a connection portion 42 located on the first lead layer 4a and a connection portion 42 located on the second lead layer 4b in sequence. 6 In the second pixel circuit 22, the anode of the second light emitting element 32 is used to represent the second light emitting element 32. Second light emission control The second pixel circuit 22 is represented using transistor T5.

[0212] For example, a portion of the first pixel circuit 21 may be electrically connected to one end of a lead 41 located on the first lead layer 4a, and the other end of the lead 41 may be electrically connected to a corresponding first light-emitting element 31 by a connection portion 42 located on the second lead layer 4b.

[0213] For example, a portion of the first pixel circuit 21 can be electrically connected to one end of a lead 41 located on the second lead layer 4b by a connection portion 42 located on the first lead layer 4a, and the other end of the lead 41 can be electrically connected to a corresponding first light-emitting element 31.

[0214] In some examples, the material of the plurality of lead layers 4 comprises a light-transmitting conductive material.

[0215] It is understood that a light-transmittable conductive material has a high transmittance. By forming the lead layer 4 using a light-transmittable conductive material, the leads 41 located on the lead layer 4 can have a high transmittance, and blocking of light passing through the portion of the display substrate 100 located in the first display region A1 can be avoided, so that the high transmittance of the portion of the display substrate 100 located in the first display region A1 can be ensured.

[0216] Exemplarily, the above light-transmittable conductive material may include at least one of materials such as indium tin oxide, indium zinc oxide, indium gallium zinc oxide, and the like.

[0217] 3 to 6, in some embodiments, the display substrate 100 further includes a transfer layer 6 provided between the pixel circuit layer 2 and the above-mentioned plurality of lead layers 4. The material of the transfer layer 6 includes a metal material.

[0218] Illustratively, the material of the transfer layer 6 may be the same as the material of the source-drain conductive layer, which can ensure that the transfer layer 6 has good conductive performance.

[0219] For example, the metallic material may include copper or aluminum.

[0220] 4 and 6, the transfer layer 6 is provided with a plurality of transfer sections 61. The plurality of transfer sections 61 are provided corresponding to the plurality of first pixel circuits 21 and the plurality of second pixel circuits 22 provided on the display substrate 100, for example, in one-to-one correspondence. Each transfer section 61 can be connected to the second electrode of the second light-emitting control transistor T5 and the lead layer 4 closest to the base 1.

[0221] Providing the transfer layer 6 is advantageous in increasing the wiring space on the display substrate 100 and reducing the difficulty of wiring.

[0222] In FIG. 16, the broken line is the boundary between the first display area A1 and the second display area A2. The rightmost first light-emitting element 31 is the first first light-emitting element, and the leftmost first pixel circuit 21 is the first first pixel circuit. The lead 41 connecting the first first light-emitting element and the first first pixel circuit is the first lead. The first pixel circuit 21 is provided in a corresponding area surrounded by an H-shaped solid line in FIG. 16, and the second pixel circuit 22 is provided in an area between two adjacent H-shaped solid lines. The following description can be referred to for the virtual pixel circuit, and will not be repeated here.

[0223] In some examples, the number of lead layers 4 provided on the display substrate 100 is two, as shown in FIG. In , 1st, Nth, odd number of leads, even number of leads teeth, Each 2 lead layers 4 To Located.

[0224] This allows a large gap to be provided between any two adjacent leads 41 among the multiple leads 41 located on the same lead layer 4, thereby preventing a short circuit from occurring between the two adjacent leads 41 and ensuring the transmission accuracy of the drive signal.

[0225] In addition, there are various installation methods between the first pixel circuit 21 and the second pixel circuit 22 located in the second display area A2, and the installation method can be selected according to actual needs.

[0226] 10, the second display region A2 includes a normal region A21b and a compressed region A22b. The first pixel circuit group 21a is located in the compressed region A22b, a portion of the second pixel circuits 22 among the plurality of second pixel circuits 22 is located in the normal region A21b, another portion of the second pixel circuits 22 is located in the compressed region A22b, and in the compressed region A22b, at least one second pixel circuit 22 is provided between two adjacent first pixel circuits 21 along the first direction X. The width of the column region in which the first pixel circuits 21 or the second pixel circuits 22 located in the compressed region A22b are located is smaller than the width of the column region in which the second pixel circuits 22 located in the normal region A21b are located.

[0227] For example, the width of the column region in which the first pixel circuits 21 are located is First pixel circuit The width of the column region in which the second pixel circuit 22 is located means the size of the region in the first direction X that the pixel circuit column in which the second pixel circuit 21 is located occupies. Second pixel circuit 22 indicates the size of the area occupied in the first direction X by the pixel circuit column in which it is located.

[0228] The width of the column region in which the first pixel circuit 21 or the second pixel circuit 22 located in the compressed region A22b is located is smaller than the width of the column region in which the second pixel circuit 22 located in the normal region A21b is located. In other words, the width of the column region in which the first pixel circuit 21 or the second pixel circuit 22 located in the compressed region A22b is located is compressed, and the width of the column region in which the second pixel circuit 22 located in the normal region A21b is located is not compressed.

[0229] By compressing the width of the column region in which the first pixel circuit 21 or the second pixel circuit 22 located in the compressed region A22b is located, a space for arranging the first pixel circuit 21 can be created in the compressed region A22b.

[0230] In some other embodiments, as shown in FIG. 、 In the first direction X, the width of the column region in which the first pixel circuit 21 or the second pixel circuit 22 is located is compressed.

[0231] This is advantageous in that the space in which the first pixel circuits 21 can be arranged can be further expanded, making it easier to arrange more first pixel circuits 21 in the second display region A2.

[0232] 9, 14, 15, and 16 means that no pixel circuit is provided in an area occupied by a rectangular pattern, and the width of the rectangular pattern in the first direction X is the same as the width of the column area in which the first pixel circuits 21 or the second pixel circuits 22 are located. This is advantageous in improving the regularity of the arrangement of the second pixel circuits 22 and improving the regularity of the change in the length of the leads 41.

[0233] Some embodiments of the present disclosure provide a display device 1000. As shown in Fig. 18 and Fig. 19, the display device 1000 includes a display substrate 100 according to any of the above embodiments, and an optical element 200 provided on a non-light-emitting side of the display substrate 100. The optical element 200 is located in a first display region A1 of the display substrate 100.

[0234] In some examples, the optical element 200 may comprise a light-sensitive device. Illustratively, the light-sensitive device may comprise an image capture device (e.g., a camera) or an infrared receiving device.

[0235] Here, the number of optical elements 200 to be installed can be selected according to actual needs.

[0236] For example, after the optical element 200 is provided in the first display area A1 and positioned on the non-emitting side of the display substrate 100, external light can pass through the portion of the display substrate 100 located in the first display area A1 and enter the optical element 200, thereby operating the optical element 200.

[0237] For example, when the optical element 200 is not operating, a portion of the display substrate 100 located in the first display area A1 can display an image, so that the display substrate 100 and the entire display device 1000 can display an image.

[0238] Exemplarily, when the optical element 200 (e.g., an image collecting device) is operating (e.g., a user is taking a selfie), the first display area A1 may display a black screen and the second display area A2 may display a screen in which the user is taking a selfie, so as to more clearly display the location of the image collecting device. Alternatively, the first display area A1 and the second display area A2 may display a screen in which the user is taking a selfie, and may not display the location of the image collecting device.

[0239] The beneficial effects that can be achieved by the display device 1000 provided by some embodiments of the present invention are the same as the beneficial effects that can be achieved by the display substrate 100 described in the above some embodiments, and will not be repeated here.

[0240] In some examples, the display device 1000 may further include a frame, a circuit board provided in the frame, a display driving IC (Integrated Circuit), other electronic elements, and the like.

[0241] In some embodiments, the above display device 1000 may be any product or component having a display function and an image collection function, such as a mobile phone, a tablet computer, a notebook computer, a laptop computer, a personal computer, a display, a wearable device, etc.

[0242] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and all modifications or replacements that can be easily conceived by a person skilled in the art within the technical scope of the present disclosure are included within the technical scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be governed by the scope described in the claims.

Claims

1. a display substrate including a first display area and a second display area, the second display area at least partially surrounding the first display area; a first light-emitting element group provided in the first display area, the first light-emitting element group including N first light-emitting elements, the N first light-emitting elements being 1st to Nth first light-emitting elements along a first direction from the second display area to the first display area; a first pixel circuit group provided in the second display region, the first pixel circuit group including N first pixel circuits, the first pixel circuit to the Nth first pixel circuit being sequentially provided along a direction away from the first display region; a lead group including N leads arranged in parallel, the i-th first light emitting element being electrically connected to the i-th first pixel circuit by the i-th lead, the lengths of the first to N-th leads gradually increasing, N≧2, N is an integer, and i=1 to N; a plurality of second pixel circuits provided in the second display area, the plurality of second pixel circuits being arranged in a plurality of columns along the first direction and in a plurality of rows along a second direction, the first direction intersecting the second direction; Equipped with At least one row of second pixel circuits or at least one column of second pixel circuits are provided between a first first light-emitting element and a first first pixel circuit, and the N leads extend from the first display area through the at least one row of second pixel circuits or the at least one column of second pixel circuits to the second display area. Display board.

2. the first light emitting element group and the first pixel circuit group electrically connected to the first light emitting element group are provided in the same row along the first direction, At least one column of second pixel circuits is provided between the first light-emitting element and the first pixel circuit, the N leads extend from the first display area through the at least one column of second pixel circuits along the first direction to the second display area; The display substrate according to claim 1 .

3. a plurality of second light-emitting elements provided in the second display area, at least one second light-emitting element being electrically connected to at least one second pixel circuit, the at least one second light-emitting element and the at least one second pixel circuit being at least partially overlapped with each other in orthogonal projection on a plane on which the display substrate is located; the display substrate includes a plurality of pixel units, each pixel unit including three sub-pixels arranged along the first direction, each sub-pixel including a second light-emitting element and a second pixel circuit electrically connected thereto; Between the first first light-emitting element and the first first pixel circuit, X second pixel circuits belonging to at least one pixel unit are provided at intervals, where X is a multiple of 3; The display substrate according to claim 2 .

4. a plurality of second light-emitting elements provided in the second display area, at least one second light-emitting element being electrically connected to at least one second pixel circuit, the at least one second light-emitting element and the at least one second pixel circuit being at least partially overlapped with each other in orthogonal projection on a plane on which the display substrate is located; the display substrate further comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a second light-emitting element and a second pixel circuit electrically connected thereto, and the pixel units are arranged in a pentile array; Between the first first light-emitting element and the first first pixel circuit, Y second pixel circuits belonging to at least one pixel unit are provided at intervals, where Y is a multiple of 2; The display substrate according to claim 2 .

5. a sequence formed by the length values ​​of the N leads in the first direction is an arithmetic sequence; The display substrate according to claim 1 .

6. The sequence formed by the resistance values ​​of the N leads is an arithmetic sequence. The display substrate according to claim 5 .

7. a parasitic capacitance is formed between each lead and the second pixel circuit and / or the first pixel circuit through which it passes; The sequence formed by the parasitic capacitance values ​​formed by the N leads is an arithmetic sequence. The display substrate according to claim 5 .

8. the display substrate includes a plurality of rows of first light-emitting elements located in the first display area, the first light-emitting elements in each row are divided into two first light-emitting element groups located on both sides of a reference line, the reference line is a straight line extending along the second direction and passing through the first display area, and the second direction is perpendicular to the first direction; two first pixel circuit groups electrically connected to the two first light emitting element groups are located on opposite sides of the first display area in the first direction, two lead groups electrically connected to the two first light emitting element groups are located on both sides of the reference line, The display substrate according to claim 1 .

9. The two lead groups electrically connected to the two first light-emitting element groups are provided symmetrically with respect to the reference line. The display substrate according to claim 8 .

10. the first display area has a center, and the reference line is a straight line passing through the center; The display substrate according to claim 8 or 9.

11. the first light emitting element group and the first pixel circuit group electrically connected to the first light emitting element group are provided in the same row along the first direction, the display substrate further includes a transfer hole group, the transfer hole group including N transfer holes, the N transfer holes being sequentially arranged along the first direction and corresponding to the N first light emitting elements, respectively; Along the second direction, an i-th lead electrically connected to an i-th first light emitting element is closer to the group of transfer holes than an i+1-th lead electrically connected to an i+1-th first light emitting element, and the second direction is perpendicular to the first direction. The display substrate according to claim 1 .

12. the first light emitting element group and the first pixel circuit group electrically connected to the first light emitting element group are provided in the same row along the first direction, the display substrate further includes a transfer hole group, the transfer hole group including N transfer holes, the N transfer holes being sequentially arranged along the first direction and corresponding to the N first light emitting elements, respectively; an i-th lead electrically connected to an i-th first light-emitting element and an i+1-th lead electrically connected to an i+1-th first light-emitting element are located on opposite sides of the transfer hole group in the second direction, and the second direction is perpendicular to the first direction; The display substrate according to claim 1 .

13. With the base, a pixel circuit layer provided on the base, the first pixel circuit group and the second pixel circuits being located on the pixel circuit layer; a light emitting element layer provided on a side of the pixel circuit layer away from the base, the first light emitting element group being located in the light emitting element layer; a plurality of lead layers provided between the pixel circuit layer and the light emitting element layer, the plurality of lead layers being made of a material having a light-transmitting conductive material; Equipped with The N leads of the lead group are located on the plurality of lead layers, respectively. The display substrate according to claim 1 .

14. The number of the plurality of lead layers is two; Among the N leads, the odd numbered leads, the even numbered leads, and the first Nth lead are located on two lead layers, respectively. The display substrate according to claim 13.

15. Among the N leads, a length ratio between the Nth lead and the first lead is α, and α≦25. The display substrate according to claim 1 .

16. The number of rows or columns of the second pixel circuits spaced apart between the first light-emitting element and the first pixel circuit is β, and β≦30. The display substrate according to claim 1 .

17. a ratio of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit is γ, and 5≦γ≦50; The display substrate according to claim 1 .

18. the second display area includes a normal area and a compressed area, the first pixel circuit group is located in the compressed area, a portion of the second pixel circuits among the plurality of second pixel circuits is located in the normal area, and another portion of the second pixel circuits is located in the compressed area, and in the compressed area, at least one second pixel circuit is provided between two adjacent first pixel circuits along the first direction; a width of a column region in which the first pixel circuit or the second pixel circuit located in the compressed region is located is smaller than a width of a column region in which the second pixel circuit located in the normal region is located; The display substrate according to claim 1 .

19. A display substrate according to claim 1 ; an optical element provided on a non-light-emitting side of the display substrate, the optical element being located in a first display region of the display substrate; Equipped with Display device.

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