Bus use right arbitration system, bus use right arbitration method, and bus use right arbitration program

Abstract

To control a serial bus so that communication processing related to a plurality of devices connected to each other via a serial bus is executed in an appropriate order.SOLUTION: A bus use right arbitration system 40 includes: an acquisition part 41 for acquiring communication priority 410 related to each of a plurality of devices 50 connected to each other via a serial bus 400; a setting part 42 for setting an address 420 according to the communication priority 410 to each of the devices 50; an imparting part 43 for imparting a bus use right 430 of the serial bus 400, to the address 420 for each of the devices 50, and the device 50 having the highest priority indicated by the arbitration control information 440 indicating use priority of the serial bus 400; and an update part 44 for updating the arbitration control information 440 so that the user priority of the device 50 having no result that the bus use right 430 is imparted thereto becomes higher than that of the device 50 having the result that the bus use right 430 is imparted.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a bus arbitration system, a bus arbitration method, and a bus arbitration program. [Background technology]

[0002] In various computer systems, multiple devices are connected to a serial bus such as I2C (Inter Integrated Circuits: registered trademark) or its successor I3C (Improved Inter Integrated Circuits: registered trademark). In such a serial bus, when communication is performed between a bus controller and multiple devices connected to the bus, arbitration is required to control the right to use the bus.

[0003] For example, I2C and I3C operate using an SDA (Serial Data) line and an SCL (Serial Clock) line. In the above-mentioned arbitration in I2C and I3C, the controller and devices communicating determine, for each bit, whether or not the SDA signal level matches the signal level they sent. If a device detects that the SDA signal level is "0" even though it has sent "1," it recognizes that it has lost the arbitration and turns off the output to SDA. The controller and devices repeat the above-mentioned process, and the device that remains until the end wins the arbitration and can obtain the right to use the bus. A device that loses arbitration requests the right to use the bus again at the start of the next start condition (a signal from the controller to start communication).

[0004] The priority of requests for bus use depends on the address value assigned to each device for use of the serial bus. The lower the address value assigned to a device, the higher the priority for bus use. Therefore, if arbitration for bus use continues between a device assigned a high address value and a device assigned a low address value, there is a problem that it takes a long time for the device assigned the high address value to obtain the bus use.

[0005] In relation to a technique for solving the above-mentioned problem, Patent Document 1 discloses an I2C bus communication device that performs I2C bus communication with other devices via a data line. This device stores at least the values ​​of a slave address and an arbitration bit, which is one bit higher than the slave address, and controls I2C bus communication with other devices. This device performs a first determination to determine whether the stored arbitration bit value matches the signal level of the data line. This device then performs a second determination to determine whether the stored slave address value matches the signal level of the data line. This device then determines whether it wins or loses in arbitration with a master device included in the other devices according to the result of the first determination or the result of the second determination, and if the determination result is a win, it acquires the right to use the data line. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2021-105753 A Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, in the above-mentioned arbitration regarding the right to use a serial bus to which multiple devices are connected, it is highly necessary to give priority to a device that requests the right to use the serial bus from a request function including, for example, interrupt processing. On the other hand, it is less necessary to give priority to a device that requests the right to use the serial bus without being related to such a request function. In a system having a serial bus to which multiple devices are connected, it is required to perform arbitration for each device, taking into account the priority order of using the bus, so that a device does not fail to obtain the right to use the bus for a long period of time. That is, the problem is to control the serial bus so that communication processes related to multiple devices connected via the serial bus are executed in an appropriate order. It cannot be said that the above-mentioned Patent Document 1 is sufficient to solve such a problem.

[0008] A primary object of the present invention is to control a serial bus so that communication processes related to a plurality of devices connected via the serial bus are executed in an appropriate order. [Means for solving the problem]

[0009] A bus arbitration system according to one embodiment of the present invention includes an acquisition means for acquiring a communication priority for each of a plurality of devices connected via a serial bus, a setting means for setting an address for each of the devices according to the communication priority, a granting means for granting bus usage rights for the serial bus to a device having the highest priority as indicated by the address for each of the devices and arbitration control information indicating a usage priority of the serial bus, and an updating means for updating the arbitration control information so that a device that has not been granted bus usage rights has a higher usage priority than a device that has been granted bus usage rights.

[0010] In another aspect of achieving the above object, a bus arbitration method according to one embodiment of the present invention includes an information processing device that obtains communication priorities for each of a plurality of devices connected via a serial bus, sets addresses for each of the devices according to the communication priority, grants bus use of the serial bus to the device having the highest priority as indicated by the address for each of the devices and arbitration control information indicating a usage priority of the serial bus, and updates the arbitration control information so that the usage priority of a device that has not been granted bus use rights is higher than that of a device that has been granted bus use rights.

[0011] In addition, in a further aspect of achieving the above-mentioned object, a bus arbitration program according to one embodiment of the present invention causes a computer to execute an acquisition process of acquiring a communication priority for each of a plurality of devices connected via a serial bus; a setting process of setting an address for each of the devices according to the communication priority; a granting process of granting bus use rights for the serial bus to the device having the highest priority indicated by the address for each of the devices and arbitration control information indicating a usage priority of the serial bus; and an updating process of updating the arbitration control information so that the usage priority is higher for a device that has not been granted a bus use right in the past than for a device that has been granted a bus use right in the past.

[0012] Furthermore, the present invention can also be realized by a computer-readable non-volatile recording medium in which such a bus arbitration program (computer program) is stored. Effect of the Invention

[0013] The present invention can control a serial bus so that communication processes related to a plurality of devices connected via the serial bus are executed in an appropriate order. [Brief description of the drawings]

[0014] [Figure 1] 1 is a block diagram showing a configuration of a bus use arbitration system 1 according to the present disclosure. [Diagram 2] 11 is a diagram illustrating an example of a configuration of device control information 172 according to the present disclosure. FIG. [Diagram 3] 1 is a diagram illustrating a specific example in which the bus arbitration system 1 according to the present disclosure arbitrates the I3C access for a device 20. FIG. [Figure 4] 4 is a flowchart showing the operation of the bus arbitration system 1 according to the present disclosure. [Diagram 5] 1 is a block diagram showing a configuration of a bus use right arbitration system 40 according to the present disclosure. [Figure 6] 4 is a flowchart showing the operation of the bus arbitration system 40 according to the present disclosure. [Figure 7] FIG. 9 is a block diagram showing a configuration of an information processing device 900 capable of realizing the bus arbitration system according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0016] <First embodiment> 1 is a block diagram showing a configuration of a bus arbitration system 1 according to the present disclosure. The bus arbitration system 1 includes a bus arbitration device 10 (controller) and a plurality of devices 20-1 to 20-3 connected to an I3C serial bus, and arbitrates bus use between the bus arbitration device 10 and each of the devices 20-1 to 20-3 in communication between the bus arbitration device 10 and each of the devices 20-1 to 20-3. In this embodiment, any one of the devices 20-1 to 20-3 or all of the devices 20-1 to 20-3 may be referred to as a device 20. The bus arbitration device 10 is implemented in an information processing device such as a server as a controller that controls the I3C.

[0017] The I3C includes an SCL bus related to a clock and an SDA bus related to data, and the devices 20-1 to 20-3 are connected to the SCL and SDA. Note that in the bus arbitration system 1 illustrated in FIG. 1, the number of devices 20 connected to the I3C is not limited to three, and may be any number other than three.

[0018] In systems that use I2C, SCL is connected by an open-drain method, but in systems that use I3C, this has been changed to a push-pull method connection to speed up communication processing. Also, in I3C systems, SDL can be switched between open-drain and push-pull as necessary, and open-drain is used when arbitrating for bus use rights.

[0019] Furthermore, since the open drain is driven low, when the signal from the device 20 is not driven, the SDL (signal line) is automatically set to the state of 1 by the pull-up resistor. Therefore, when the device 20 wants to transmit a value of 1 to the signal line, it does not drive it, and when the device 20 wants to transmit a value of 0, it drives it low. As a result, for example, when one of the devices 20 wants to transmit a value of 1 and the other wants to transmit a value of 0, the SDL is set to the state of 0 by the device 20 that has driven it low, so that the device 20 that transmits the value of 0 can obtain the right to use the bus.

[0020] The management terminal 30 is an information processing device, such as a personal computer, tablet terminal, or smartphone, used by a user of the bus use arbitration device 10, and is an example of a display device. The management terminal 30 accepts input operations by the user, and inputs the information input by the user to the information processing device in which the bus use arbitration device 10 is implemented. The management terminal 30 has a display screen 300, and displays information output from the information processing device on the display screen 300.

[0021] The bus arbitration device 10 includes an acquisition unit 11, a setting unit 12, a grant unit 13, an update unit 14, an output unit 15, a reception unit 16, and a storage unit 17. The acquisition unit 11, the setting unit 12, the grant unit 13, the update unit 14, the output unit 15, and the reception unit 16 are examples of an acquisition means, a setting means, a grant means, an update means, an output means, and a reception means, respectively. At least a part of the functions realized by the above-mentioned components may be provided by the device 20.

[0022] The storage unit 17 is, for example, a storage device such as a RAM (Random Access Memory) 903 or a hard disk 904, which will be described later with reference to Fig. 7. At least a part of the storage unit 17 may be provided in the device 20, or in one or more external devices capable of communicating with the bus arbitration device 10. The storage unit 17 stores communication priority 171, device control information 172 relating to each of the devices 20, and instruction information 173. The information stored in the storage unit 17 will be described later.

[0023] The acquiring unit 11 acquires communication priority 171 of communication via I3C for each of the devices 20, for example, from an information processing device in which the bus arbitration device 10 is implemented, and stores the acquired communication priority 171 in the storage unit 17. The communication priority 171 is information indicating the priority of communication between each of the devices 20 and the bus arbitration device 10, and may indicate, for example, the presence or absence of an interrupt request. In this case, the communication priority 171 is set high in the case of communication generated by a request function including an interrupt process that occurs during operation of the information processing device in which the bus arbitration device 10 is implemented, and is set low in the case of communication not generated by the request function.

[0024] FIG. 2 shows the structure (byte format) of device control information 172 that the bus arbitration device 10 according to the present disclosure transmits to the I3C after a start condition and that is used for arbitration of the bus for each of the devices 20.

[0025] In a typical I3C bus communication system, the most significant 7 bits of the device control information 172 are usually used as a device address. However, the device control information 172 according to the present disclosure includes the most significant bit (MSB) bit A6 of the device address (bits A6 to A0) as an arbitration control bit indicating the use priority of I3C, and includes bits A5 to A0 lower than the arbitration control bit A6 as the device address of the device 20, as illustrated in Fig. 2. The device control information 172 also includes the least significant bit (LSB) as an R / W determination bit indicating whether the access command to the device 20 is a read command or a write command.

[0026] The setting unit 12 sets, for each of the devices 20, a device address corresponding to the communication priority 171 acquired by the acquisition unit 11 in bits A5 to A0 of the device control information 172 illustrated in FIG.

[0027] The granting unit 13 grants the right to use the I3C bus to the device 20 having the highest priority indicated by the device addresses A5 to A0 and the arbitration control bit A6, which are indicated by the device control information 172 relating to each of the devices 20.

[0028] The update unit 14 updates the arbitration control bit A6 of the device control information 172 so that a device 20 that has not been granted the right to use the bus has a higher I3C usage priority than a device 20 that has been granted the right to use the bus (i.e., won arbitration).

[0029] 3 is a diagram illustrating a specific example in which the bus arbitration system 1 according to the present disclosure arbitrates the I3C bus for the device 20. Fig. 3 shows the values ​​of the arbitration control bit A6 and the device addresses A5 to A0 included in the device control information 172 that change as the bus arbitration system 1 proceeds with arbitration of the I3C bus for the device 20.

[0030] 3, the setting unit 12 sets the device addresses A5 to A0 for the devices 20-1 to 20-3 to "00XXXX", "10XXXX", and "11XXXX", respectively, based on the communication priority 171 acquired by the acquisition unit 11. Here, "X" represents any value of "0" or "1". The setting unit 12 sets the device addresses A5 to A0 to smaller values ​​for the device 20 having a higher communication priority 171. Therefore, in the example shown in FIG. 3, the order of priority for the right to use the bus is device 20-1, device 20-2, and device 20-3.

[0031] When arbitration for the right to use the I3C for the device 20 starts, the update unit 14 sets the arbitration control bit A6 of the device control information 172 to "1", which is an initial value.

[0032] The assignment unit 13 identifies the device 20 whose device control information 172 has the smallest values ​​of A6 to A1.

[0033] In the first arbitration illustrated in FIG. 3, the arbitration control bit A6 for all devices 20 has a value of "1", so the granting unit 13 compares the device addresses A5 to A0 for the devices 20. The granting unit 13 then identifies the device 20-1, whose upper bits A5 and A4 of the device address are the smallest, "00", as the device 20 that won the arbitration, and grants the I3C bus access right to the device 20-1. This allows communication between the device 20-1 that has been granted the I3C bus access right and the bus access right arbitration device 10. The updating unit 14 does not update the value of the arbitration control bit A6 for the device 20-1 that won the first arbitration, leaving it at "1", and updates the values ​​of the arbitration control bit A6 for the devices 20-2 and 20-3 that lost the first arbitration from "1" to "0".

[0034] 3, since the value of the arbitration control bit A6 for the device 20-1 is "1" and the value of the arbitration control bit A6 for the devices 20-2 and 20-3 are "0", the granting unit 13 first identifies the device 20-1 as the device 20 that lost the arbitration. The granting unit 13 then compares the device addresses A5 to A0 for the devices 20-2 and 20-3, identifies the device 20-2, whose upper bits A5 and A4 of the device address have smaller values, as the device 20 that won the arbitration, and grants the I3C bus to the device 20-2. This allows communication to be performed between the device 20-2 that has been granted the I3C bus and the bus arbitration device 10. The update unit 14 updates the value of the arbitration control bit A6 for the device 20-2, which won the second arbitration, from "0" to "1," and maintains the values ​​of the arbitration control bit A6 for the devices 20-1 and 20-3 at "1" and "0," respectively.

[0035] In the third arbitration illustrated in FIG. 3, the arbitration control bit A6 for the devices 20-1 and 20-2 has a value of "1", and the arbitration control bit A6 for the device 20-3 has a value of "0", so the granting unit 13 identifies the device 20-3 as the device 20 that won the arbitration, and grants the I3C bus to the device 20-3. This allows communication between the device 20-3 that has been granted the I3C bus and the bus access arbitration device 10. The updating unit 14 updates the value of the arbitration control bit A6 for the device 20-3 that won the third arbitration from "0" to "1", and maintains the values ​​of the arbitration control bit A6 for the devices 20-1 and 20-2 at "1".

[0036] 3 ends, the values ​​of the device control information 172 for each of the devices 20 are restored to the values ​​before the first arbitration. Therefore, the assigning unit 13 and the updating unit 14 perform the fourth arbitration in the same manner as the first arbitration, and thereafter, repeatedly execute the operations related to the first to third arbitrations described above.

[0037] The output unit 15 displays, for example, at least any one of the values ​​of the arbitration control bit A6, device addresses A5 to A0, and communication priority 171, which are represented by the device control information 172 for each device 20, on the display screen 300 of the management terminal 30. This enables the bus arbitration system 1 to provide a user of the bus arbitration system 1 with information necessary for analyzing the operation of the bus arbitration system 1.

[0038] The reception unit 16 receives, for example, instruction information 173 input via an input operation by a user to the management terminal 30, from the management terminal 30, indicating the degree to which the update unit 14 is to increase the use priority of I3C (i.e., the degree to which the update unit 14 is to update the arbitration control bit A6). Then, the update unit 14 may update the arbitration control bit A6 with the degree to which the use priority is to be increased indicated by the instruction information 173 received by the reception unit 16.

[0039] More specifically, for example, the updating unit 14 may update the value of the arbitration control bit A6 for the device 20 that has won arbitration from "0" to "1" only when the device 20-1 has won arbitration twice based on an instruction from the instruction information 173, whereas the updating unit 14 normally updates the value of the arbitration control bit A6 for the device 20-1 that has won arbitration once. In this case, the granting unit 13 grants the bus use right twice to the device 20-1 while the devices 20-2 and 20-3 obtain the bus use right once. In this way, the bus use right arbitration system 1 can control the frequency of use of the I3C by a certain device 20 to be higher than that of the other devices 20.

[0040] Next, the operation (processing) of the bus arbitration system 1 according to the present disclosure will be described in detail with reference to the flowchart of FIG.

[0041] The acquiring unit 11 acquires the communication priority 171 for each of the devices 20 from, for example, an information processing device in which the bus access arbitration device 10 is implemented (step S101). The setting unit 12 sets device addresses corresponding to the communication priority 171 for each of the devices 20 in A5 to A0 of the device control information 172 (step S102). The updating unit 14 sets the arbitration control bit A6 of the device control information 172 for each of the devices 20 to an initial value of "1" (step S103).

[0042] The granting unit 13 identifies the device 20 having the smallest values ​​of A6 to A1 in the device control information 172 from among the devices 20 that have not yet performed communication (step S104). The granting unit 13 grants the I3C bus to the identified device 20 that won the arbitration, and communication is performed between the device 20-1 that has been granted the I3C bus and the bus arbitration device 10 (step S105).

[0043] The update unit 14 sets the arbitration control bit of the device control information 172 for the device 20 that won the arbitration to "1" and sets the arbitration control bit of the device control information 172 for the device 20 that lost the arbitration and has not yet communicated to "0" (step S106). If there is a device 20 that has not yet communicated (Yes in step S107), the process returns to step S104. If there is no device 20 that has not yet communicated (No in step S107), the entire process ends.

[0044] The bus arbitration system 1 according to the present disclosure can control the serial bus so that communication processes for a plurality of devices connected via the serial bus are executed in an appropriate order. The reason for this is that the bus arbitration system 1 sets a device address according to the communication priority 171 acquired for each device 20, grants the bus to the device 20 with the highest priority indicated by the device address and the arbitration control bit, and updates the arbitration control bit so that a device 20 that has not been granted the bus has a higher bus use priority than a device 20 that has been granted the bus.

[0045] The effects achieved by the bus arbitration system 1 according to the present disclosure will be described in detail below.

[0046] In arbitration regarding the right to use a serial bus to which multiple devices are connected, it is highly necessary to give priority to a device that requests the right to use the serial bus from a request function including, for example, interrupt processing. On the other hand, it is less necessary to give priority to a device that requests the right to use the serial bus without being related to such a request function. In a system having a serial bus to which multiple devices are connected, it is required to perform arbitration taking into account the priority order of bus use for each device so that a device does not fail to obtain the right to use the bus for a long period of time. In other words, the challenge is to control the serial bus so that communication processes related to multiple devices connected via the serial bus are executed in an appropriate order.

[0047] In response to such a problem, the bus arbitration system 1 according to the present disclosure obtains a communication priority 171 for each of the devices 20 connected via the I3C. The bus arbitration system 1 sets a device address for each of the devices 20 according to the communication priority 171. The bus arbitration system 1 grants the I3C bus to the device 20 having the highest priority indicated by the device address and the arbitration control bit indicating the I3C usage priority for each of the devices 20. The bus arbitration system 1 then updates the arbitration control bit so that the I3C usage priority is higher for the device 20 that has not been granted the bus than for the device 20 that has been granted the bus. That is, the bus arbitration system 1 sets the device address for each of the devices 20 based on the communication priority 171, and controls the device 20 so that the bus usage priority of the device 20 is increased each time the device 20 loses arbitration. This allows the bus arbitration system 1 to control the serial bus so that communication processes related to a plurality of devices connected via the serial bus are executed in an appropriate order.

[0048] Furthermore, the bus arbitration system 1 according to the present disclosure outputs at least one of the device address and arbitration control bit represented by the device control information 172 and information representing the communication priority 171 for each device 20 to the display screen 300 of the management terminal 30. As a result, the bus arbitration system 1 provides information necessary for analyzing the operation of the bus arbitration system 1 to a user of the bus arbitration system 1, thereby assisting the user in analyzing the operation of the bus arbitration system 1.

[0049] Furthermore, the bus arbitration system 1 according to the present disclosure receives instruction information 173 from the update unit 14 instructing the degree to which the I3C use priority is to be increased, and updates the arbitration control bit of the device control information 172 with the degree to which the I3C use priority is to be increased indicated by the instruction information 173. As a result, the bus arbitration system 1 can flexibly adjust the rate at which each device 20 wins arbitration for the I3C bus in accordance with the desires of the user, and can therefore adjust the frequency of access to each device 20, etc.

[0050] Furthermore, the bus arbitration system 1 according to the present disclosure acquires, for example, a communication priority 171 indicating the presence or absence of an interrupt request. This allows the bus arbitration system 1 to control the serial bus so that communication with the device 20 generated by an interrupt request is given priority.

[0051] Moreover, the setting unit 12 of the bus access arbitration system 1 according to the present disclosure sets a predetermined upper bit of the multiple bits representing a device address in the device control information 172 to a value corresponding to the communication priority 171. The setting unit 12 may have a function of switching bits other than the upper bit of the multiple bits representing a device address from the open drain method to the push-pull method when the upper bit indicates a predetermined value. More specifically, in the bus access arbitration system 1, for example, when the communication priority 171 indicates the presence or absence of an interrupt request, the setting unit 12 sets the bit A5 in the device control information 172 to "0" when there is an interrupt request, and sets the bit A5 to "1" when there is no interrupt request. When there is no interrupt request in which the bit A5 in the device control information 172 is "1", the setting unit 12 switches the lower bits A4 to A0 from the open drain method to the push-pull method, thereby improving the communication speed in I3C.

[0052] In addition, in I3C, an optimization function of arbitration using bit A6 in device control information 172 has been added from I2C. In this optimization function, when the I3C controller assigns a dynamic address from 03H (00000011) to 7BH (1111011) to each device, it assigns an address with bit A6 of "0" to a device with a high communication priority, and an address with bit A6 of "1" to a device with a low communication priority. The I3C controller then controls the arbitration of the bus right using only bit A6. The bus arbitration system 1 according to the present disclosure can also be implemented with such an optimization function of arbitration.

[0053] The configuration of the bus arbitration system 1 according to the present disclosure described above may be applied to a system having a serial bus other than I3C or I2C.

[0054] <Second embodiment> FIG. 5 is a block diagram showing a configuration of a bus arbitration system 40 according to the present disclosure.

[0055] The bus use right arbitration system 40 according to the present disclosure includes an acquisition unit 41, a setting unit 42, a granting unit 43, and an update unit 44. The acquisition unit 41, the setting unit 42, the granting unit 43, and the update unit 44 are examples of an acquisition means, a setting means, a granting means, and an update means, respectively.

[0056] The acquiring unit 41 acquires a communication priority 410 for each of a plurality of devices 50 connected via a serial bus 400. The serial bus 400 is, for example, a bus similar to the I3C in the bus arbitration system 1. The device 50 is, for example, a device similar to the device 20 in the bus arbitration system 1. The communication priority 410 is, for example, information similar to the communication priority 171 in the bus arbitration system 1. The acquiring unit 41 operates in the same manner as the acquiring unit 11 in the bus arbitration system 1, for example.

[0057] The setting unit 42 sets an address 420 corresponding to the communication priority 410 for each device 50. The address 420 is, for example, an address similar to a device address indicated by the device control information 172 related to the bus use arbitration system 1. The setting unit 42 operates in the same manner as the setting unit 12, for example.

[0058] The granting unit 43 grants bus access 430 of the serial bus 400 to the device 50 having the highest priority indicated by the address 420 and arbitration control information 440 indicating the use priority of the serial bus 400 for each of the devices 50. The arbitration control information 440 is, for example, information similar to the arbitration control bit A6 included in the device control information 172 related to the bus access arbitration system 1. The bus access 320 is, for example, information similar to the bus access granted by the granting unit 13 related to the bus access arbitration system 1. The granting unit 43 operates in the same manner as the granting unit 13 related to the bus access arbitration system 1.

[0059] The update unit 44 updates the arbitration control information 440 so that a device 50 that has not been granted the bus access 430 has a higher usage priority than a device 50 that has been granted the bus access 430. The update unit 44 operates in the same manner as the update unit 14 in the bus access arbitration system 1, for example.

[0060] Next, the operation (processing) of the bus arbitration system 40 according to the present disclosure will be described in detail with reference to the flowchart of FIG.

[0061] The acquiring unit 41 acquires the communication priority 410 for each of the devices 50 (step S201). The setting unit 42 sets the address 420 for each of the devices 50 according to the communication priority 410 (step S202). The granting unit 43 grants the bus use right 430 to the device 50 having the highest priority indicated by the address 420 and the arbitration control information 440 for each of the devices 50 (step S203). The updating unit 44 updates the arbitration control information 440 so that the use priority of the device 50 that has not been granted the bus use right 430 is higher than that of the device 50 that has been granted the bus use right 430 (step S204), and the entire process ends.

[0062] The bus arbitration system 40 according to the present disclosure can control the serial bus so that communication processes for a plurality of devices connected via the serial bus are executed in an appropriate order. The reason is that the bus arbitration system 40 sets an address 420 according to the communication priority 410 acquired for each device 50, grants the bus use right 430 to the device 50 having the highest priority indicated by the address 420 and the arbitration control information 440, and updates the arbitration control information 440 so that the device 50 that has not been granted the bus use right 430 has a higher priority for using the serial bus 400 than the device 50 that has been granted the bus use right 430.

[0063] <Hardware configuration example> In each of the above-mentioned embodiments, each unit in the bus arbitration system shown in Figures 1 and 5 can be realized by a dedicated HW (Hardware) (electronic circuit). In Figures 1 and 5, at least the following components can be considered as functional (processing) units (software modules) of a software program including instructions executed by a processor. Acquisition units 11 and 41, Setting units 12 and 42, · Grants 13 and 43, Update parts 14 and 44, Output section 15, Reception desk 16, Memory control function in the memory unit 17.

[0064] However, the division of the various parts shown in these drawings is for the convenience of explanation, and various configurations may be assumed for implementation. An example of the hardware environment in this case will be described with reference to FIG.

[0065] Fig. 7 is a diagram for explaining an example of the configuration of an information processing device 900 (computer) capable of realizing the bus arbitration system according to the present disclosure. That is, Fig. 7 shows the configuration of a computer (information processing device) capable of realizing the bus arbitration system shown in Figs. 1 and 5, and shows a hardware environment capable of realizing each function in the above-mentioned embodiment. However, each unit in the above-mentioned bus arbitration device may be provided in a distributed manner in multiple information processing devices 900, or at least some of the functions may be provided in a server or the like that constitutes a cloud computing environment.

[0066] The information processing device 900 shown in FIG. ·CPU(Central_Processing_Unit)901, ROM (Read_Only_Memory) 902, ·RAM(Random_Access_Memory)903, Hard disk (storage device) 904, A communication interface 905; Bus 906 (communication line), A reader / writer 908 capable of reading and writing data stored in a recording medium 907 such as a CD-ROM (Compact Disc Read Only Memory), · Input / output interfaces 909 such as monitors, speakers, keyboards, etc.

[0067] That is, the information processing device 900 having the above components is a general computer in which these components are connected via a bus 906. The information processing device 900 may have a plurality of CPUs 901, or may have a CPU 901 configured with a multi-core. The information processing device 900 may not have some of the above components.

[0068] The present invention, explained using the above-mentioned embodiment as an example, supplies a computer program capable of realizing the following functions to the information processing device 900 shown in Fig. 7. The functions are the above-mentioned configurations in the block configuration diagrams (Figs. 1 and 5) referred to in the explanation of the embodiment, or the functions of the flowcharts (Figs. 4 and 6). The present invention is then achieved by reading the computer program into the CPU 901 of the hardware, interpreting it, and executing it. The computer program supplied to the device may be stored in a readable and writable volatile memory (RAM 903), or a non-volatile storage device such as a ROM 902 or a hard disk 904.

[0069] In the above case, the method of supplying the computer program to the hardware can be a currently common procedure, such as installing the program in the device via a recording medium 907 such as a CD-ROM, or downloading the program from an external source via a communication line such as the Internet. In such a case, the present invention can be considered to be configured by the code constituting the computer program, or the recording medium 907 on which the code is stored.

[0070] The present invention has been described above by taking the above-mentioned embodiment as an exemplary example. However, the present invention is not limited to the above-mentioned embodiment. That is, the present invention can be applied in various aspects that can be understood by a person skilled in the art within the scope of the present invention.

[0071] Note that some or all of the above-described embodiments can be described as follows: However, the present invention described by way of example in the above-described embodiments is not limited to the following.

[0072] (Appendix 1) An acquisition means for acquiring a communication priority for each of a plurality of devices connected via a serial bus; a setting means for setting an address corresponding to the communication priority for each of the devices; a granting means for granting a bus use right of the serial bus to the device having the highest priority indicated by the address and arbitration control information indicating a use priority of the serial bus for each of the devices; an updating means for updating the arbitration control information so that the device that has not been granted the bus use right in the past has a higher usage priority than the device that has been granted the bus use right in the past; A bus arbitration system comprising:

[0073] (Appendix 2) further comprising an output unit for outputting at least one of the address, the arbitration control information, and the information indicating the communication priority for each of the devices to a display device; 2. A bus arbitration system according to claim 1.

[0074] (Appendix 3) a receiving unit for receiving instruction information instructing a degree to which the update unit is to increase the use priority level, the updating means updates the arbitration control information with a degree of increasing the use priority level represented by the instruction information. 3. A bus arbitration system according to claim 1 or 2.

[0075] (Appendix 4) the acquiring means acquires the communication priority level indicating the presence or absence of an interrupt request. 3. A bus arbitration system according to claim 1 or 2.

[0076] (Appendix 5) the setting means sets a predetermined upper bit of the plurality of bits representing the address to a value corresponding to the communication priority. 3. A bus arbitration system according to claim 1 or 2.

[0077] (Appendix 6) the setting means switches bits other than the most significant bit among the plurality of bits representing the address from an open-drain system to a push-pull system when the most significant bit indicates a predetermined value; 6. A bus arbitration system as set forth in claim 5.

[0078] (Appendix 7) The most significant bit is 1 bit. 6. A bus arbitration system as set forth in claim 5.

[0079] (Appendix 8) The serial bus is I2C (Inter Integrated Circuits) or I3C (Improved Inter Integrated Circuits), The arbitration control information is 1 bit. 3. A bus arbitration system according to claim 1 or 2.

[0080] (Appendix 9) By the information processing device, Obtaining communication priority for each of a plurality of devices connected via a serial bus; setting an address for each of the devices according to the communication priority; granting a bus right to use the serial bus to the device having the highest priority indicated by the address and arbitration control information indicating a priority of use of the serial bus for each of the devices; updating the arbitration control information so that the use priority of the device that has not been granted the bus use right in the past is set to be higher than that of the device that has been granted the bus use right in the past; A method for arbitrating bus rights.

[0081] (Appendix 10) outputting at least one of the address, the arbitration control information, and the information indicating the communication priority for each of the devices to a display device; 10. A bus arbitration method as claimed in claim 9.

[0082] (Appendix 11) receiving instruction information instructing a degree of increasing the use priority; updating the arbitration control information according to a degree of increasing the use priority level represented by the instruction information; 11. A bus arbitration method according to claim 9 or 10.

[0083] (Appendix 12) acquiring the communication priority level indicating the presence or absence of an interrupt request; 11. A bus arbitration method according to claim 9 or 10.

[0084] (Appendix 13) setting a predetermined upper bit of the plurality of bits representing the address to a value corresponding to the communication priority; 11. A bus arbitration method according to claim 9 or 10.

[0085] (Appendix 14) when the most significant bit indicates a predetermined value, switching bits other than the most significant bit among the plurality of bits representing the address from an open-drain system to a push-pull system; 14. A bus arbitration method as claimed in claim 13.

[0086] (Appendix 15) The most significant bit is 1 bit. 14. A bus arbitration method as claimed in claim 13.

[0087] (Appendix 16) The serial bus is I2C (Inter Integrated Circuits) or I3C (Improved Inter Integrated Circuits), The arbitration control information is 1 bit. 11. A bus arbitration method according to claim 9 or 10.

[0088] (Appendix 17) An acquisition process for acquiring communication priority for each of a plurality of devices connected via a serial bus; a setting process for setting an address corresponding to the communication priority for each of the devices; a granting process for granting the right to use the serial bus to the device having the highest priority indicated by the address and arbitration control information indicating a priority of use of the serial bus for each of the devices; an updating process for updating the arbitration control information so that the device that has not been granted the bus use right has a higher usage priority than the device that has been granted the bus use right; A bus arbitration program for causing a computer to execute the above.

[0089] (Appendix 18) and causing the computer to execute an output process of outputting at least one of the address, the arbitration control information, and the information indicating the communication priority for each of the devices to a display device. 18. A bus arbitration program according to claim 17.

[0090] (Appendix 19) a receiving process for receiving instruction information instructing a degree of increasing the usage priority by the update process; the updating process updates the arbitration control information with a degree of increasing the use priority level represented by the instruction information. A bus arbitration program according to claim 17 or 18.

[0091] (Appendix 20) the acquisition process acquires the communication priority level indicating the presence or absence of an interrupt request; A bus arbitration program according to claim 17 or 18.

[0092] (Appendix 21) the setting process sets a predetermined upper bit of the plurality of bits representing the address to a value corresponding to the communication priority. A bus arbitration program according to claim 17 or 18.

[0093] (Appendix 22) the setting process switches bits other than the most significant bit among the plurality of bits representing the address from an open-drain system to a push-pull system when the most significant bit indicates a predetermined value; 22. The bus arbitration program according to claim 21.

[0094] (Appendix 23) The most significant bit is 1 bit. 22. The bus arbitration program according to claim 21.

[0095] (Appendix 24) The serial bus is I2C (Inter Integrated Circuits) or I3C (Improved Inter Integrated Circuits), The arbitration control information is 1 bit. A bus arbitration program according to claim 17 or 18. [Explanation of symbols]

[0096] 1. Bus use arbitration system 10 Bus use right arbitration device 11 Acquisition Department 12 Setting section 13 Granting Department 14 Update section 15 Output section 16 Reception Department 17 Memory section 171 Communication Priority 172 Device Control Information 173 Instruction information 20 Devices 30 Management terminal 300 display screen 40 Bus Use Rights Arbitration System 400 Serial Bus 41 Acquisition Department 410 Communication Priority 42 Setting section 420 Address 43 Granting Department 430 Bus Use Rights 44 Update section 440 Arbitration Control Information 50 Devices 900 Information processing device 901 CPU 902 ROM 903 RAM 904 Hard disk (storage device) 905 Communication Interface 906 Bus 907 Recording media 908 Reader / Writer 909 Input / Output Interface

Claims

1. An acquisition means for acquiring a communication priority for each of a plurality of devices connected via a serial bus; a setting means for setting an address corresponding to the communication priority for each of the devices; a granting means for granting a bus use right of the serial bus to the device having the highest priority indicated by the address and arbitration control information indicating a use priority of the serial bus for each of the devices; an updating means for updating the arbitration control information so that the device that has not been granted the bus use right in the past has a higher usage priority than the device that has been granted the bus use right in the past; A bus arbitration system comprising:

2. further comprising an output unit for outputting at least one of the address, the arbitration control information, and the information indicating the communication priority for each of the devices to a display device; 2. The bus arbitration system according to claim 1.

3. a receiving unit for receiving instruction information instructing a degree to which the update unit is to increase the use priority level, the updating means updates the arbitration control information with a degree of increasing the use priority level represented by the instruction information.

3. The bus arbitration system according to claim 1.

4. the acquiring means acquires the communication priority level indicating the presence or absence of an interrupt request.

3. The bus arbitration system according to claim 1.

5. the setting means sets a predetermined upper bit of the plurality of bits representing the address to a value corresponding to the communication priority.

3. The bus arbitration system according to claim 1.

6. the setting means switches bits other than the most significant bit among the plurality of bits representing the address from an open-drain system to a push-pull system when the most significant bit indicates a predetermined value; 6. The bus arbitration system according to claim 5.

7. The most significant bit is 1 bit.

6. The bus arbitration system according to claim 5.

8. The serial bus is an I2C (Inter Integrated Circuits) or an I3C (Improved Inter Integrated Circuits), The arbitration control information is 1 bit.

3. The bus arbitration system according to claim 1.

9. By the information processing device, Obtaining communication priority for each of a plurality of devices connected via a serial bus; Setting an address for each of the devices according to the communication priority level; granting a bus right to use the serial bus to the device having the highest priority indicated by the address and arbitration control information indicating a priority of use of the serial bus for each of the devices; updating the arbitration control information so that the use priority of the device that has not been granted the bus use right in the past is set to be higher than that of the device that has been granted the bus use right in the past; A method for arbitrating bus rights.

10. An acquisition process for acquiring communication priority for each of a plurality of devices connected via a serial bus; a setting process for setting an address corresponding to the communication priority for each of the devices; a granting process for granting the right to use the serial bus to the device having the highest priority indicated by the address and arbitration control information indicating a priority of use of the serial bus for each of the devices; an updating process for updating the arbitration control information so that the device that has not been granted the bus use right has a higher usage priority than the device that has been granted the bus use right; A bus arbitration program for causing a computer to execute the above.

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