Direct digital synthesizer

Abstract

To solve the problem in the conventional direct digital synthesizer in which a clock of a power of 2 is required, a precise frequency is not generated if not the case, and it is difficult that a digit of a decimal point or smaller is increased.SOLUTION: In addition to an accumulator that adds an accumulator output and frequency setting data, in the case where an accumulator output exceeds a predetermined value, the predetermined value is subtracted, and a clock of a power of 2 is not required. Also, by setting each of quotients and remainders obtained by dividing the frequency setting data with the predetermined value to a high-order digit and a low-order digit, a frequency setting range is increased. Also, by separately setting an accumulator of which a digit of a decimal point or smaller, a setting of the digit of the decimal point or smaller can be easily made.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a direct digital synthesizer (hereinafter abbreviated as "DDS") that can obtain a set frequency with high precision. [Background technology]

[0002] DDS, which can obtain any frequency from a reference clock, is widely used in various fields. Conventional DDSs have the problem that they cannot obtain a precise frequency when using a readily available crystal oscillator as the reference clock, resulting in poor accuracy. For this reason, the current practice is to use a high-resolution DDS to set a frequency as close as possible to the target frequency.

[0003] Some systems use a crystal oscillator with a frequency that is a power of two as the reference clock to obtain a precise frequency, but these systems require a custom-made crystal oscillator or are limited in the frequency range that can be set. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-83250 [Non-patent literature]

[0005] [Non-Patent Document 1] ANALOG DEVICES AD9833 Datasheet Publication date unknown Summary of the Invention [Problem to be solved by the invention]

[0006] The problem we are trying to solve is that when using a readily available crystal oscillator as a reference clock, it is not possible to generate a precise frequency. For example, the conventional DDS AD9833 has a 28-bit accumulator, and when using a 25 MHz clock, the resolution is 25,000,000 / 2 28 =0.093, so you get a high resolution of 0.093Hz, but it's not exactly 0.1Hz. To get the resolution to exactly 0.1Hz, you need to multiply it by 0.1 x 2. 28 =26843545.6, so a clock of 26.8435456Hz is required, which is not widely available commercially and is difficult to obtain in small-scale production.

[0007] The object of the present invention is to provide a DDS that can generate precise and accurate frequencies even when using a readily available crystal oscillator as the reference clock.

[0008] Another object of the present invention is to provide a DDS that can easily generate frequencies that include fractions below the decimal point. [Means for solving the problem]

[0009] The present invention makes it easy and accurate to set a target frequency by dividing the clock frequency / set frequency unit by a power of 2, and when the updated value of the accumulator exceeds the predetermined value, subtracting this value from the value and updating the accumulator. (The power includes 0.)

[0010] Furthermore, by allowing the upper accumulator to be updated when the value obtained by subtracting this value is selected, the quotient and remainder obtained by dividing the target frequency setting data by the value obtained by dividing the clock frequency / setting frequency unit by a power of 2 are set in the upper and lower digits as the second frequency setting data and the first frequency setting data, respectively, thereby enabling support for high frequencies.

[0011] In addition, when the target frequency has a decimal point, the lower accumulator subtracts 10 if the decimal point is one digit, 100 if it is two digits, or 1000 if it is three digits, and allows the upper accumulator to be updated, making it easy to set the frequency after the decimal point. [Effects of the Invention]

[0012] The DDS of the present invention has the advantages of being easy to set the target frequency, providing a precise frequency, and also being easy to set decimal points, which means that it is possible to obtain a frequency with the same precision as the precision of the reference clock. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram showing a first embodiment of a DDS according to the present invention. (Embodiment 1) [Figure 2] FIG. 2 is a block diagram showing a second embodiment of the DDS of the present invention. (Embodiment 2) [Figure 3] FIG. 3 is a block diagram showing a third embodiment of the DDS of the present invention. (Embodiment 3) [Figure 4] FIG. 4 is a block diagram showing a fourth embodiment of the DDS of the present invention. (Embodiment 4) [Figure 5] FIG. 5 is a block diagram showing a fifth embodiment of the DDS of the present invention. (Embodiment 5) [Figure 6] FIG. 6 is a block diagram showing a sixth embodiment of the DDS of the present invention. (Embodiment 6) DETAILED DESCRIPTION OF THE INVENTION

[0014] The objectives were achieved by making it easy to set the target frequency and also to easily set the decimal point, and by eliminating the need for a crystal oscillator with a special frequency for the clock, allowing it to be configured using a crystal oscillator that is generally easy to obtain. [Example]

[0015] 1 is a block diagram of a first embodiment of the device of the present invention, in which frequency setting data is set in register 1, and the output value of accumulator 2 and the set value of register 1 are added in first arithmetic unit 3. A second arithmetic unit 4 subtracts a predetermined value from the output value of first arithmetic unit 3, and the outputs of first arithmetic unit 3 and second arithmetic unit 4 are input to selector 5, and if the output of second arithmetic unit 4 is a negative value, the output of first arithmetic unit 3 is selected, and if not, the output of second arithmetic unit 4 is selected and output from selector 5. The output of selector 5 is input to accumulator 2, and the accumulator value is updated to the output value of selector 5 in synchronization with the clock.

[0016] With this configuration, the most significant bit of the accumulator 2 outputs a pulse having a frequency based on the frequency setting data set in the register 1. Here, the frequency setting data is data obtained by calculating output frequency / setting unit frequency, and the output frequency is frequency setting data x setting unit frequency.

[0017] For example, if the clock is 16 MHz and the predetermined value is 16,000,000, accumulator 2 will increase with each clock by the value set in register 1, and if it exceeds 16,000,000, it will return to the value minus 16,000,000. As a result, a frequency of 1 Hz multiplied by the set value of register 1 is output from the most significant bit of accumulator 2, and the set unit frequency is 1 Hz. In this case, the accumulator has a value between 0 and 15,999,999, so 24 bits are sufficient. The same applies to the number of bits of register 1. The frequency setting range is 1 to 15,999,999 Hz.

[0018] If the clock is 16MHz and the specified value is 160000000, a frequency of 0.1Hz multiplied by the setting value of register 1 is output from the most significant bit of accumulator 2, making the setting unit frequency 0.1Hz. In this case, the accumulator has a value between 0 and 159999999, so 28 bits are required. The same applies to the number of bits of register 1. The frequency setting range is 0.1 to 15999999.9Hz.

[0019] The register referred to here refers to a register that holds a value set from a logic device such as a microcomputer (not shown), or an output port register of a microcomputer. Frequency setting data is set in register 1 from the logic device, and this value is supplied to adder 3. An accumulator is a register for cumulative addition, and its value is replaced with the addition result in synchronization with the clock by an enable signal. In Example 1, it is always enabled, and its value is updated with each clock. [Example]

[0020] 2 is a block diagram of a second embodiment of the device of the present invention, which is configured to output an analog waveform such as a sine wave by adding an incrementer 6, a ROM 7, and a DAC (digital-to-analog converter) 8 to the first embodiment. The register 1, the accumulator 2, the first arithmetic unit 3, the second arithmetic unit 4, and the selector 5 operate in the same way as in the first embodiment.

[0021] If the clock is 16MHz and the set frequency unit is 1Hz, then 16000000 / 1=2 10 × 15625, the incrementer 6 is set to 10 bits, the predetermined value is set to 15625, and the incrementer 6 is enabled so that its value increases by one when the output value of the fourth calculator becomes positive or 0. The incrementer 6 increases within a 10-bit range and returns to 0 when it overflows. The monotonically increasing output is input to ROM 7, which converts it to a sine wave, and when the converted sine wave value is input to DAC 8, a sine wave is output from its output. The frequency setting range is 1 to 15625 Hz.

[0022] If the clock is 16MHz and the set frequency unit is 10Hz, then 16000000 / 10=2 9× 3125, the incrementer 6 is set to 9 bits, the predetermined value is set to 3125, and the incrementer 6 is enabled so that its value increases by one when the output value of the fourth calculator becomes positive or 0. The incrementer 6 increases within a 9-bit range and returns to 0 when it overflows. The monotonically increasing output is input to ROM 7, which converts it to a sine wave, and when the converted sine wave value is input to DAC 8, a sine wave is output from its output. The frequency setting range is 10 to 31250 Hz.

[0023] If you want to output 12 bits to ROM7, set the frequency unit to 1 / 4Hz, then 16000000 / (1 / 4)=2 12 ×15625, and the incrementer 6 is 12 bits, so the output to the ROM 7 can be 12 bits. The predetermined value here is 15625.

[0024] In this way, by setting the frequency unit to 1 / power of 2, the number of bits output to the ROM 7 can be increased according to the power value.

[0025] Of course, the waveform to be converted does not have to be a sine wave; triangular waves, square waves, or any other waveform can be output depending on the data in ROM7.

[0026] An incrementer is a device that increments a value by one in synchronization with a clock when an enable signal is input. (It is a type of accumulator, but is called an incrementer because the increment value is one.) [Example]

[0027] Figure 3 is a block diagram of a third embodiment of the device of the present invention. In the second embodiment, only low frequencies up to 15625 Hz could be set when the set frequency unit was 1 Hz, but this embodiment has been improved to allow higher frequencies to be set. Instead of the incrementer 6, a register 9, a second accumulator 10, and a third calculator 11 are provided. The second register 9 stores high-order data for the frequency setting, and the output value of the second accumulator 10 and the set value of the second register 9 are added by the third calculator 11. The third calculator 11 is an adder with a carry input, the output of which is input to the second accumulator 10, and when the output value of the second arithmetic unit 4 becomes positive or 0, the signal to carry the accumulator 2 is input to the carry input of the third arithmetic unit 11, and when the output of the third arithmetic unit 11 is carried, it becomes the output value of the second accumulator 10 + the second register 9 + 1, In synchronization with the clock, the value of the second accumulator 10 is updated to the output value of the third arithmetic unit 11. The register 1, accumulator 2, first arithmetic unit 3, second arithmetic unit 4, selector 5, ROM 7, and DAC 8 operate in the same manner as in the second embodiment.

[0028] Here, if the clock is 16 MHz and the set frequency unit is 1 Hz, the quotient and remainder of the frequency setting data divided by 15625 are obtained, and the quotient is set as the second frequency data in the second register 9, and the remainder is set as the first frequency data in the register 1, and the predetermined value input to the second calculator 4 is set to 15625. By doing so, the maximum value of the frequency setting range is 1023 x 15625 + 15624 = 15999999 Hz, and frequencies from 1 to 15999999 Hz can be generated. Here, 15625 is 2, which is the power of 2 of 16000000, which is 16 MHz. 10 This is the value divided by .

[0029] Accumulator 10 is 2 10 Since the accumulator 2 makes one revolution at a power of 2, DAC8 output is possible via ROM7 with a 10-bit address, but since the accumulator 2 does not make one revolution at a power of 2, if DAC output is made via ROM, the waveform will be discontinuous and the target waveform cannot be output. Therefore, if you want to output with more bits, you can increase the number of output bits according to the value of the power by setting the set frequency unit to 1 / power of 2 as explained in Example 2. [Example]

[0030] 4 is a block diagram of a fourth embodiment of the device of the present invention, in which, in the third embodiment, when the set frequency unit is 1 Hz, it was only possible to set the frequency in 1 Hz units, but in this embodiment, it is possible to set the frequency to decimal points by adding a third register 12, a third accumulator 13, a fourth arithmetic unit 14, a fifth arithmetic unit 15, and a second selector 16. Also, register 1, accumulator 2, first arithmetic unit 3, second arithmetic unit 4, selector 5, ROM 7, DAC 8, second register 9, second accumulator 10, and third arithmetic unit 11 operate in the same way as in the third embodiment.

[0031] Here, we will explain a configuration in which three decimal places can be set. Data with three decimal places is set in the third register 12, and is added to the output value of the third accumulator 13 by the fourth arithmetic unit 14. A predetermined value is subtracted from the output by the fifth arithmetic unit 15. Here, the predetermined value is 1000. In other words, if the output of the fourth arithmetic unit 14 is less than 1000, the output of the fourth arithmetic unit 14 is selected by the second selector 16. If the output is 1000 or greater, the output of the fifth arithmetic unit 15 minus 1000 is selected, and the third accumulator 13 is replaced with the selected value in synchronization with the clock. In this case, the third accumulator 13 can have a value from 0 to 999, so 10 bits are required.

[0032] The signal that selects the output of the fifth computing unit 15 is input to the enable terminal of the accumulator 2, and the value of the accumulator 2 is updated.

[0033] In a DDS configured in this manner, by setting the quotient described in the third embodiment in the second register 9, the remainder in register 1, and the frequency value after the decimal point in the third register 12, it is possible to generate frequencies from 0.001 to 15999999.999 Hz.

[0034] Here, the predetermined value is 10 if the setting is one decimal place, and 100 if it is two decimal places, and the configuration is the same. Even if the number of digits increases further, the configuration is the same except that the number of bits required for the predetermined value and the third accumulator 13 changes. The number of bits required for the third accumulator 13 is 4 bits when the predetermined value is 10, and 7 bits when it is 100. [Example]

[0035] FIG. 5 is a block diagram of a fifth embodiment of the device of the present invention, which shows an example in which a VF converter that outputs a frequency proportional to an analog value is configured using a DDS of the present invention. This will be explained using an example of a VF converter (voltage-frequency converter) that outputs 25 kHz when the analog value is 1 V and outputs a frequency proportional to the analog value.

[0036] Reference numeral 18 denotes an ADC (analog-to-digital converter) that converts analog values ​​into digital values, and 17 denotes a logic device such as a microcontroller. The register 1, accumulator 2, first arithmetic unit 3, second arithmetic unit 4, selector 5, and incrementer 6 operate in the same manner as in the second embodiment.

[0037] The analog voltage value is converted to a digital value by ADC 18 and input into logic unit 17. If this ADC is 10-bit and the reference voltage is 1.023V, then when the voltage is 1V the digital value becomes 1000, and when it is 0.001V the digital value becomes 1. When the digital value is 1000, the frequency to be output is 25 kHz, and when the digital value is 1, the frequency to be output is 25 Hz.

[0038] If the clock is 16MHz and the setting unit frequency is 25Hz, then 16000000 / 25=2 9 × 1250, so if the incrementer 6 is 9 bits and the specified value is set to 1250, a frequency proportional to the digital value will be output: 25 kHz when the digital value is 1000, and 25 Hz when it is 1. Since the digital value is proportional to the analog value, a frequency proportional to the analog value will be output. [Example]

[0039] FIG. 6 is a block diagram of a sixth embodiment of the present invention. In the previous embodiments, the second arithmetic unit subtracted a predetermined value from the first arithmetic unit, which required calculations to be performed through two arithmetic units within the time of one clock, which posed a problem in that the clock frequency could not be increased too much. This embodiment solves this problem and is a speedup of the third embodiment.

[0040] The register 1, accumulator 2, first arithmetic unit 3, selector 5, ROM 7, DAC 8, second register 9, second accumulator 10, and third arithmetic unit 11 operate in the same manner as in the third embodiment, but the second arithmetic unit 4 is an adder with an additional subtractor 19, unlike in the third embodiment. Also, a D-FF (D flip-flop) 20 is added as a pipeline to increase speed.

[0041] The lower-order data of the frequency setting to be set in the first register 1 is added to the output value of the accumulator 2 by the first arithmetic unit 3, and a value obtained by subtracting a predetermined value by the subtractor 19 is added to the output value of the accumulator 2 by the second arithmetic unit 4. The outputs of the first arithmetic unit 3 and the second arithmetic unit 4 are input to the selector 5, and if the output of the second arithmetic unit 4 is a negative value, the output of the first arithmetic unit 3 is selected, and if not, the output of the second arithmetic unit 4 is selected and output from the selector 5. The output of the selector 5 is input to the accumulator 2, and the accumulator's value is updated to the output value of the selector 5 in synchronization with the clock. Furthermore, if the output of the second arithmetic unit 4 is negative, the D-FF20 is set.

[0042] The output of D-FF20 is connected to the carry input of the third arithmetic unit 11, and when D-FF20 is set, the output of the third arithmetic unit 11 is incremented by 1 as a carry signal for the accumulator 2, The value of the second accumulator 10 is updated to the output value of the third computing unit 11 in synchronization with the clock.

[0043] With this configuration, delays in the first arithmetic unit 3 and the second arithmetic unit 4 are added in the third embodiment, but in this embodiment, they are not added, resulting in high speed. There is no need to worry about the input value of the subtractor 19, as it does not change with each clock. Here, the second register 9 and the first register 1 are registers that are set and held by a logic device such as a microcomputer, or microcomputer output port registers, and the subtractor 19 may perform subtraction calculations within the microcomputer and output the subtraction result to an output port register.

[0044] Furthermore, by using the D-FF 20 as a pipeline, the delay time until the selection of the selector 5 is not accumulated with the calculation delay of the accumulator 10, and therefore becomes fast.

[0045] In the case of the fifth arithmetic unit 15 in the fourth embodiment, the signal line from the output of the fifth arithmetic unit 15 to the accumulator 2 can also be configured in a similar manner to increase the speed.

[0046] In the explanations up to this point, a crystal oscillator has been used to generate the clock, but it is also possible to input the output of a crystal oscillator with a more readily available frequency into a PLL to obtain a clock of the required frequency. When configuring a DDS using an FPGA, the FPGA usually has a PLL for clock generation; for example, a 10 MHz crystal oscillator can be used, multiplied by 64 with the PLL to obtain 640 MHz, and then divided by 40 to obtain a 16 MHz clock. If you want to increase the frequency generated by the DDS, you can divide it by 20 to create a 32 MHz clock, or by 10 to create a 64 MHz clock. [Industrial Applicability]

[0047] DDS is widely used in radio equipment and frequency generators known as function generators. Its ability to generate frequencies easily and with high accuracy is extremely useful. It can also easily accommodate an increase in the number of decimal points. There are many other applications where variable frequency is required, and this invention can be applied to these applications. [Explanation of symbols]

[0048] 1 register (first register) 2 Accumulator (first accumulator) 3 First arithmetic unit 4 Second arithmetic unit 5 Selector (First Selector) 6 Incrementer 7 ROM 8 DAC 9 Second Register 10 Second Accumulator 11 Third arithmetic unit 12 Third Register 13 Third Accumulator 14 Fourth arithmetic unit 15 Fifth arithmetic unit 16 Second selector 17 Logical Units 18 ADC 19 Subtractor 20 D-FF

Claims

1. A direct digital synthesizer comprising: a first accumulator operated by a clock signal; a first arithmetic unit that calculates (the output value of the first accumulator) + (first frequency setting data); a second arithmetic unit that obtains a result of calculating (the output value of the first accumulator) + (first frequency setting data) - (a predetermined value); and a first selector that selects either the output of the first arithmetic unit or the output of the second arithmetic unit depending on the output of the second arithmetic unit, wherein the input of the first accumulator is the output of the first selector.

2. 2. The direct digital synthesizer according to claim 1, further comprising an incrementer that increments a value by one when said first selector selects said second arithmetic unit.

3. 2. The direct digital synthesizer according to claim 1, further comprising a second accumulator and a third arithmetic unit that calculates (the second accumulator) + (second frequency setting data) + carry input, and a signal generated when the first selector selects the output of the second arithmetic unit is used as the carry input of the third arithmetic unit.

4. 2. The direct digital synthesizer of claim 1, further comprising: a third accumulator operated by a clock signal; a fourth arithmetic unit that calculates (the output value of the third accumulator) + (third frequency setting data); a fifth arithmetic unit that obtains a result of calculating (the output value of the third accumulator) + (third frequency setting data) - (second predetermined value); and a second selector that selects either the output of the fourth arithmetic unit or the output of the fifth arithmetic unit depending on the output of the fifth arithmetic unit, wherein the input of the third accumulator is the output of the second selector, the first arithmetic unit is an adder having a carry input, and a signal generated when the second selector selects the fifth arithmetic unit is connected to the carry input.

5. 2. The direct digital synthesizer according to claim 1, wherein the predetermined value is a value obtained by dividing the frequency of the clock signal by a set unit frequency and dividing the value by a power of two (the power includes 0).

6. 5. The direct digital synthesizer according to claim 3, wherein the frequency of the clock signal is divided by a set unit frequency, and the quotient obtained by dividing the result by the predetermined value is used as the second frequency setting data, and the remainder is used as the first frequency setting data.

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