Display panel, method for manufacturing the same, and display device

Abstract

To provide a display panel, a method for manufacturing the same, and a display device.SOLUTION: A display panel includes reset signal line patterns positioned in a plurality of sub-pixel areas and respective sub-pixel areas, an initialization signal line pattern, and a conductive connection part pattern. The initialization signal line pattern includes a first body part and a first projection part which are coupled to each other. Orthogonal projection on the base of the first body part is positioned between orthogonal projection on the base of the first projection part and orthogonal projection on the base of the reset signal line pattern. The orthogonal projection on the base of a first end of the conductive connection part pattern and the orthogonal projection on the base of the first projection part include a first overlap region. In the first overlap region, the first end is coupled to the first projection pattern. A second end of the conductive connection part pattern is coupled to a target coupling part. The orthogonal projection on the base of the reset signal line pattern is positioned between orthogonal projection on the base of the target coupling part and orthogonal projection on the base of the initialization signal line pattern.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present disclosure relates to the technical field of displays, and in particular to a display panel and a manufacturing method thereof, and a display device do. [Background technology]

[0002] Organic Light-Emitting Diode With the rapid development of OLED (light-emitting diode) display technology, the screen occupancy rate and Consumer demands for image quality and resolution are increasing. The active area ratio is the effective display area (active area) of the front panel of the display device. rea, abbreviated as AA area), and the resolution of an OLED display is the ratio of the AA area The larger the screen occupancy rate of an OLED display, the more consumers will be able to use the The higher the resolution of an OLED display, the clearer the images displayed on it. become. Summary of the Invention

[0003] The objective of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.

[0004] A first aspect of the present disclosure is a display panel, comprising: a base; and a functional member provided on the base. a film layer; and a plurality of sub-pixel areas arranged in an array; the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer is a reset signal line pattern provided in each of the sub-pixel areas. the reset signal line pattern extends along a first direction; The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas. the initialization signal line pattern includes a first body portion and a first protruding portion coupled to each other. the first body portion extends along the first direction and in the same sub-pixel area: The orthogonal projection of the first body portion on the base is the orthogonal projection of the first protruding portion on the base. a projection of the reset signal line pattern on the base and a normal projection of the reset signal line pattern on the base; the conductive connection layer includes a conductive connection pattern provided in each of the sub-pixel areas, In the same subpixel area, the positive electrode of the first end of the conductive connection pattern on the base and a first overlap region between the projection and the orthogonal projection of the first protruding portion on the base. and in the first overlap region, the first end is coupled to the first protruding portion. and a second end of the conductive connection pattern is disposed on a target electrode in the sub-pixel area where the second end of the conductive connection pattern is located. The reset signal line pattern is coupled to a base coupling portion, and the orthogonal projection of the reset signal line pattern on the base is orthogonal projection of the target coupling portion on the base and the initialization signal line pattern on the base and a display panel positioned between the orthogonal projection at the

[0005] Optionally, the display panel comprises: The functional film layer has a plurality of sub-pixel areas, and the functional film layer has a plurality of sub-pixel areas. A plurality of light emitting elements located on the opposite side; A plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas, Each of the sub-pixel driving circuits includes a seventh transistor, a first electrode of the seventh transistor connected to the corresponding reset signal line pattern; is used as the target coupling portion, and the second pole of the seventh transistor is connected to the second direction A plurality of sub-pixel drivers extending along the anode of a corresponding light-emitting element are coupled to the anode of the corresponding light-emitting element. and a drive circuit, The conductive connection pattern includes a second body connected between the first end and the second end. the second body portion further includes a second body portion extending along a second direction and in the same subpixel area. In the first direction, a first end of the conductive connection pattern is connected to the seventh transistor. A second body portion projects from the second body portion in a direction away from the second pole of the resistor.

[0006] Optionally, the functional film layer further includes a data line pattern located in each sub-pixel area. the data line pattern includes a portion extending along the second direction; The initialization signal line pattern is orthogonally projected onto the base, and the conductive connection portion pattern is projected onto the base. There is a third overlap region between the orthogonal projection on the base, The orthogonal projection of the initialization signal line pattern on the base and the data line pattern There is a fourth overlap area between the orthogonal projection on the base, Along the second direction of the initialization signal line pattern in the fourth overlap region The width of the initialization signal line pattern in the third overlap region in the second direction is Less than the width along the

[0007] Optionally, in the same subpixel area, an orthogonal projection of the second body portion onto the base and a first gap between the orthogonal projection of the second pole of the seventh transistor on the base. The first gap is greater than a threshold value.

[0008] Optionally, the display panel comprises: Each of the sub-pixel areas has a driving transistor and a second a plurality of subpixel drive circuits including transistors; The gate of the second transistor is adjacent to a previous sub-pixel area in the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern in the the first sub-pixel area of ​​the second transistor; a bipolar transistor coupled to the gate of the drive transistor; The second transistor includes two semiconductor portions spaced apart from each other along the first direction. and a first conductor portion connected to the two semiconductor portions, respectively, The orthogonal projection of the first protruding portion on the base in the front sub-pixel area is does not overlap with the orthographic projection on the source.

[0009] Optionally, an orthogonal projection of the first conductor portion onto the base is within the front sub-pixel area. The conductive connection pattern of the first end of the conductive connection pattern overlaps with an orthogonal projection onto the base.

[0010] Optionally, each of the initialization signal line patterns may include a second projection coupled to the first body portion. and a second protruding portion on the base of the second protruding portion in the same subpixel area. The orthogonal projection is a projection of the first body portion onto the base, and the reset signal line pattern and an orthogonal projection of the first conductor portion on the base. overlaps with an orthogonal projection of the second protruding portion on the base.

[0011] Optionally, the conductive connection pattern is connected between the first end and the second end. a second body portion extending along a second direction; An end of the first conductor portion close to the conductive connection pattern in the previous sub-pixel area extends along the second direction, and the orthogonal projection of the end on the base and the conductive connection portion There is a second gap between the second body portion of the pattern and the orthogonal projection on the base, The gap between the two is greater than the threshold.

[0012] Optionally, in the same sub-pixel area, the first end of the conductive connection pattern may be and a normal projection of the first main body portion of the initialization signal line pattern on the base. A second overlap region is also formed with the shadow, The functional film layer further includes a first connection hole located in each of the sub-pixel areas, In the area, the orthogonal projection of the first connection hole on the base is the first overlap region and the second overlap region, and the conductive connection pattern A first end of the line is coupled to the initialization signal line pattern through the first contact hole.

[0013] Optionally, the orthogonal projection of the first conductor portion of the second transistor on the base is overlapping with an orthogonal projection of the first contact hole on the base in the subpixel area; do not have.

[0014] Optionally, the functional film layer further includes a power supply signal line layer, and the power supply signal line layer is a power supply signal line pattern provided in a pixel area, At least one of the first and second electrodes extends along a second direction. The first conductor portion is far from the conductive connection pattern in the previous sub-pixel area. The edges extend along the second direction, and orthogonal projections of the edges on the base correspond to the same sub-pixel. The power supply signal line pattern located in the area is completely covered by the orthogonal projection on the base. can be.

[0015] Optionally, the display panel comprises: A plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas, Each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor, and the storage capacitor The first electrode plate is connected to the driving transistor. The second plate is opposite to the base of the first substrate. a plurality of subpixel driving circuits disposed on the side of the pixel; The functional film layer further includes a power supply signal line layer, and the power supply signal line layer is connected to each of the sub-pixel areas. At least a part of the power supply signal line pattern is The power supply signal line pattern extends along a second direction, and includes a first power supply portion and a second power supply portion. fruit, The orthogonal projection of the first power supply unit on the base is The set signal line pattern is orthogonally projected onto the base and overlaps the set signal line pattern. The gate line patterns located in the pixel area are orthogonally projected and overlapped on the base. and the orthogonal projection of the second power supply part on the base corresponds to the second plate of the storage capacitor. and the first power supply unit is disposed along the first direction. The width of the second power supply portion is smaller than the width of the second power supply portion.

[0016] Optionally, the functional film layer further includes a power supply signal line layer, and the power supply signal line layer is a power supply signal line pattern provided in a pixel area, At least one of the first and second electrodes extends along a second direction. The functional film layer further includes an auxiliary power supply layer, and the auxiliary power supply layer is provided in each of the sub-pixel areas. an auxiliary power supply pattern provided on the base; and and a orthogonal projection onto the base of a power supply signal line pattern located in the same sub-pixel area. There is an overlapping area, and the auxiliary power supply pattern and the power supply signal line pattern are They are joined in the overlap region.

[0017] Optionally, the display panel has a one-to-one correspondence with the plurality of sub-pixel areas, each of which has a a plurality of subpixel drive circuits each including a drive transistor and a second transistor; The gate of the second transistor is adjacent to a previous sub-pixel area in the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern in the the first sub-pixel area of ​​the second transistor; The bipolar electrode includes a first electrode portion and a second electrode portion coupled to each other, the first electrode portion being coupled to the second electrode portion. the second electrode portion extends along a third direction, and the third direction is The first electrode portion intersects with the second transistor in both the first direction and the second direction. The second electrode portion is located between the semiconductor portion and the second electrode portion. is coupled to the gate of The orthogonal projection of the first electrode portion on the base and the orthogonal projection of the second electrode portion on the base Any shadows are covered by the orthogonal projection of the corresponding auxiliary power pattern onto the base. .

[0018] Optionally, the auxiliary power pattern includes a first auxiliary sub-pattern and a second auxiliary sub-pattern coupled to each other. a first auxiliary sub-pattern extending along a second direction; At least a portion of the second auxiliary sub-pattern extends along the first direction; The orthogonal projection of the first auxiliary sub-pattern on the base is and an orthogonal projection of the second electrode portion on the base.

[0019] Optionally, the width of the first auxiliary sub-pattern along the first direction is It is larger than the width of the source signal line pattern.

[0020] Optionally, an orthogonal projection of the first electrode portion on the base and an orthogonal projection of the second electrode portion on the base Each of the orthogonal projections on the above is obtained by orthogonal projection of the corresponding power supply signal line pattern on the base. It is covered with

[0021] Optionally, the functional film layer may include a gate line pattern, a light emitting control pattern, and a gate insulating film. A signal line pattern is formed on the gate electrode in the same sub-pixel area along a second direction. the light emission control signal line pattern, the reset signal line pattern, and the initial The signal line patterns are arranged in sequence, The functional film layer includes a power supply signal line pattern and a data line pattern located in each sub-pixel area. the power supply signal line pattern and the data line pattern are both in the second direction. a portion extending along the direction of the The display panel includes: a light-emitting element that corresponds one-to-one to the plurality of sub-pixel areas; Each of the sub-pixel areas has a driving transistor, a first A transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor a subpixel drive circuit including a first transistor and a seventh transistor, In the same subpixel area, the gate of the driving transistor is connected to the first transistor. a first electrode of the drive transistor coupled to a second electrode of the fifth transistor; a second pole of the drive transistor coupled to a first pole of the first transistor; And, a gate of the first transistor is coupled to the gate line pattern; The gate of the second transistor is adjacent to a previous sub-pixel area in the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern in the the first sub-pixel area of ​​the second transistor; a bipolar transistor coupled to the gate of the drive transistor; The gate of the fourth transistor is coupled to the gate line pattern. a first electrode of the fourth transistor is coupled to the data line pattern; and a second electrode of the fourth transistor is coupled to the data line pattern. , coupled to a first electrode of the drive transistor; The gate of the fifth transistor is coupled to the light emission control signal line pattern. a first electrode of the transistor is coupled to the power supply signal line pattern; The gate of the sixth transistor is coupled to the light emission control signal line pattern. A first electrode of the transistor is coupled to a second electrode of the drive transistor, and the sixth transistor a second pole of the first electrode is coupled to the corresponding light emitting element; A second electrode of the seventh transistor is coupled to the light emitting element, A gate is coupled to the reset signal line pattern, and a first electrode of the seventh transistor is It is coupled to a second initialization signal line pattern.

[0022] Based on the technical solution of the above display panel, the second aspect of the present disclosure is a display including the above display panel. A display device is provided.

[0023] Based on the above technical solution of the display panel, the third aspect of the present disclosure is a manufacturing method of the display panel. So, A functional film layer is fabricated on a base to form a plurality of sub-pixel areas arranged in an array. Including, the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer is a reset signal line pattern provided in each of the sub-pixel areas. the reset signal line pattern extends along a first direction; The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas. the initialization signal line pattern includes a first body portion and a first protruding portion coupled to each other. the first body portion extends along the first direction and in the same sub-pixel area: The orthogonal projection of the first body portion on the base is the orthogonal projection of the first protruding portion on the base. a projection of the reset signal line pattern on the base and a normal projection of the reset signal line pattern on the base; the conductive connection layer includes a conductive connection pattern provided in each of the sub-pixel areas, In the same subpixel area, the positive electrode of the first end of the conductive connection pattern on the base and a first overlap region between the projection and the orthogonal projection of the first protruding portion on the base. and in the first overlap region, the first end is coupled to the first protruding portion. and a second end of the conductive connection pattern is disposed on a target electrode in the sub-pixel area where the second end of the conductive connection pattern is located. The reset signal line pattern is coupled to a base coupling portion, and the orthogonal projection of the reset signal line pattern on the base is orthogonal projection of the target coupling portion on the base and the initialization signal line pattern on the base The present invention provides a method for manufacturing a display panel that is positioned between an orthogonal projection at a viewing angle.

[0024] The drawings described herein are intended to provide a further understanding of the present disclosure and are not intended to limit the scope of the present disclosure. The illustrative examples and the description thereof are intended to be part of the present disclosure. and do not constitute undue limitations on this disclosure. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is a schematic diagram of a sub-pixel layout in the prior art. [Diagram 2] FIG. 2 is a schematic diagram of a layout of an active layer in FIG. [Diagram 3] FIG. 2 is a schematic diagram of a layout of a first gate metal layer in FIG. [Figure 4] FIG. 2 is a schematic diagram of a layout of a second gate metal layer in FIG. 1. [Diagram 5] FIG. 2 is a schematic diagram of a layout of a source-drain metal layer in FIG. [Figure 6] FIG. 2 is a circuit diagram of a sub-pixel driving circuit according to an embodiment of the present disclosure. [Figure 7] 11 is a driving time chart of a sub-pixel driving circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram of a first layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 9] FIG. 13 is a schematic diagram of a second layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 10] FIG. 9 is a schematic diagram of the layout of the active layer in FIG. 8. [Figure 11] FIG. 9 is a schematic diagram of the layout of the first gate metal layer in FIG. 8. [Figure 12] FIG. 9 is a schematic diagram of a layout of the second gate metal layer in FIG. 8. [Figure 13]FIG. 9 is a schematic diagram of the layout of the source-drain metal layer in FIG. 8. [Figure 14] 9 is a schematic cross-sectional view taken along the A1A2 direction in FIG. 8. FIG. [Figure 15] FIG. 13 is a schematic diagram of a third layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 16] 16 is a first enlarged schematic view of the X1 portion in FIG. 15. FIG. [Figure 17] FIG. 16 is a second enlarged schematic view of the X1 portion in FIG. [Figure 18] 18 is a schematic cross-sectional view taken along the B1B2 direction in FIG. 17. FIG. [Figure 19] FIG. 16 is a schematic diagram of the layout of the active layer in FIG. [Figure 20] FIG. 16 is a schematic diagram of the layout of the first gate metal layer in FIG. [Figure 21] FIG. 16 is a schematic diagram of the layout of the second gate metal layer in FIG. [Figure 22] FIG. 16 is a schematic diagram of the layout of the source-drain metal layer in FIG. [Figure 23] FIG. 13 is a schematic diagram of a fourth layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 24] FIG. 2 is a structural schematic diagram of a power supply signal line pattern according to an embodiment of the present disclosure. [Diagram 25] FIG. 13 is a schematic diagram of a fifth layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 26] FIG. 26 is a schematic diagram of the layout of the active layer in FIG. 25. [Figure 27] FIG. 26 is a schematic diagram of the layout of the first gate metal layer in FIG. 25. [Figure 28] FIG. 26 is a schematic diagram of the layout of the second gate metal layer in FIG. 25. [Figure 29] FIG. 26 is a schematic diagram of the layout of the source-drain metal layer in FIG. 25. [Diagram 30] FIG. 2 is a schematic diagram of a layout of a second source-drain metal layer according to an embodiment of the present disclosure. [Diagram 31]FIG. 2 is a schematic diagram of a layout of a second source-drain metal layer and an anode layer according to an embodiment of the present disclosure. [Diagram 32] FIG. 13 is a schematic diagram of a sixth layout of sub-pixel areas according to an embodiment of the present disclosure. [Diagram 33] FIG. 33 is a schematic diagram of the layout of the second gate metal layer and the second source-drain metal layer in FIG. 32. [Diagram 34] 33 is a schematic cross-sectional view taken along the C1C2 direction in FIG. 32. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] To further describe the display panel, the manufacturing method thereof, and the display device according to the embodiments of the present disclosure, The present invention will be described in detail below with reference to the specification and drawings.

[0027] The structure of an AMOLED display panel is a base and multiple sub-pixel drivers provided on the base. a driving circuit and a plurality of light-emitting elements provided on the opposite side of the base in the subpixel driving circuit; the light emitting element corresponds to the sub-pixel driving circuit in a one-to-one relationship, The driving circuit drives the corresponding light emitting element to emit light, thereby realizing the display function of the display panel. This is for the purpose of

[0028] In the related art, the sub-pixel driving circuit generally comprises a plurality of thin-film 1, the sub-pixel driving circuit includes seven thin film transistors M1 to A specific layout method of the seven thin film transistors including M7 is shown. When the layout is based on this method, the sub-pixel driving circuit is an array as shown in FIG. 3, the first metal layer as shown in FIG. 4, and the second metal layer as shown in FIG. and the active layer includes a third metal layer such that the active layer is disposed over the channel area of ​​each thin film transistor. and an active pattern for forming the above (for example, the portion enclosed by the dashed line in FIG. 2 ); A doped active pattern (e.g., 2) and the first metal layer is a gate electrode of each thin film transistor. a gate connected to a scanning signal line GATE; One electrode plate CE1 of a capacitor, a reset signal line RST, and a light emission control signal line EM; The second metal layer is a layer for connecting an initialization signal line VINT and a storage capacitor in the subpixel driving circuit. The other electrode plate CE2, and the third metal layer includes a data line DATA and a power signal line VD D and several conductive connections (eg, reference numbers 341 to 343).

[0029] Please note that, as shown in FIG. 1, when laying out the subpixel driving circuit, In order to realize the connection between the functional patterns provided on the Reference numerals 381 to 388) may be provided.

[0030] As shown in FIG. 6, FIG. 8 and FIG. 14, the present disclosure provides a display panel, includes a plurality of sub-pixel driving circuits, a power supply signal line pattern 901, a data line pattern 90 8, gate line pattern 902, light emission control signal line pattern 903, reset signal line pattern 905 and an initialization signal line pattern 904. At least a portion of the data line pattern 908 extends along a second direction, and the gate The line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 9 05. The initialization signal line patterns 904 each extend along a first direction, The first direction intersects with the second direction. The two directions include the Y direction.

[0031] As shown in FIG. 9, the plurality of sub-pixel driving circuits are arranged sequentially along the second direction. a plurality of rows of subpixel driving circuits arranged in sequence along the first direction; The sub-pixel driving circuits can be divided into sub-pixel driving circuits, and the sub-pixel driving circuits corresponding to the sub-pixel driving circuits located in the same row can be divided into sub-pixel driving circuits. The initialization signal line pattern 904 is electrically connected in sequence and formed as an integral structure. The gate line patterns 902 corresponding to the sub-pixel driving circuits located in the same row are sequentially electrically connected to each other. are electrically connected to each other and formed as an integral structure, and correspond to the subpixel driving circuits located in the same row. The light emission control signal line pattern 903 is electrically connected in sequence and formed as an integral structure. The reset signal line pattern 905 corresponding to the subpixel driving circuit located in the same row is The subpixel driving circuits are electrically connected in sequence, formed as an integral structure, and located in the same column. The data line patterns 908 corresponding to the paths are electrically connected in sequence to form an integral structure. The power supply signal line pattern 901 corresponding to the sub-pixel driving circuit located in the same column is formed. are electrically connected in sequence and formed as an integral structure.

[0032] For example, each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged sequentially along the X direction. The sub-pixel driving circuit includes the initialization signal line pattern 904, the gate line pattern 902, The light emission control signal line pattern 903 and the reset signal line pattern 905 are both arranged in the X direction. and each of the subpixel driving circuits included in the subpixel driving circuit of each row extends along The corresponding initialization signal line pattern 904, gate line pattern 902, and light emission control signal The sub-pixels of each column can be connected to the signal line pattern 903 and the reset signal line pattern 905. Each pixel driving circuit includes a plurality of sub-pixel driving circuits arranged sequentially along the Y direction; The data line pattern 908 and the power signal line pattern 901 both extend along the Y direction. Each of the subpixel driving circuits included in the subpixel driving circuit of each column is It can be coupled to the corresponding data line pattern 908 and power signal line pattern 901 .

[0033] It should be noted that in the display panel, the physical partition shape for the sub-pixel area is There are many different types of compartments, but two specific compartment types are given below as examples.

[0034] As a first type of partitioning form, as shown in FIG. 8, the first transistor T1 is The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, Transistor T5, sixth transistor T6 and seventh transistor T7 located at the top of FIG. , and a gate line pattern 902, a light emission control signal line pattern 903, located at the top of FIG. 8. The reset signal line pattern 905′ located at the top of FIG. 04′ may be partitioned into one sub-pixel area (i.e., the current sub-pixel area). the second transistor T2 at the bottom in FIG. 8; the seventh transistor T7 at the bottom in FIG. 8 8. The reset signal line pattern 905 located at the bottom of FIG. Any of the line patterns 904 are adjacent to the current subpixel area along the Y direction. It is divided into areas.

[0035] As a second type of partitioning form, as shown in FIG. 8, the first transistor T1 is The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, Transistor T5, sixth transistor T6 and seventh transistor T7 located at the bottom of FIG. , and a gate line pattern 902, a light emission control signal line pattern 903, located at the bottom of FIG. 8. The reset signal line pattern 905 located at the bottom of FIG. 4 may be divided into one sub-pixel area (i.e., the current sub-pixel area). the second transistor T2 at the top in FIG. 8; the seventh transistor T7 at the top in FIG. The reset signal line pattern 905' at the top and the initialization signal line pattern 905 at the top of FIG. Any of the line patterns 904′ are adjacent to the previous subpixel area along the Y direction of the current subpixel area. It is partitioned into pixel areas.

[0036] It should be noted that the partition form of the sub-pixel area described in the present disclosure is the second type In the second partition type, the current sub-pixel area is The subpixel driving circuit corresponding to the structure of FIG. 6 includes a first transistor. 8, a second transistor T2, a third transistor T3, and a fourth transistor T4. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the transistors located at the bottom of FIG. 8. The seventh transistor T7 is located at the top of the second transistor T2. The gate 202g is connected to the reset gate 202 in the previous sub-pixel area adjacent in the second direction. The source S2 of the second transistor T2 is coupled to the first signal line pattern 905'. The initialization signal line pattern 904′ in the subpixel area is coupled to the second transistor T2. The drain D2 is coupled to the gate 203g of the third transistor T3.

[0037] As shown in FIG. 6 and FIG. 8, taking one subpixel driving circuit as an example, The circuit includes seven thin film transistors and one capacitor. Each of the transistors is a P-type transistor. T1 has a double-gate structure, and the gate 201g of the first transistor T1 is connected to the gate line The source S1 of the first transistor T1 is coupled to the pattern 902. 3 (i.e., the drive transistor) and is coupled to the drain D3 of the first transistor T1. The input D1 is coupled to the gate 203g of the third transistor T3.

[0038] The second transistor T2 has a double-gate structure. 02g is a diagram showing the reset signal line pattern in a previous sub-pixel area adjacent in the second direction. The source S2 of the second transistor T2 is coupled to the turn 905′. The drain D of the second transistor T2 is connected to the initialization signal line pattern 904′ in the rear. 2 is coupled to the gate 203g of the third transistor T3.

[0039] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902; The source S4 of the fourth transistor T4 is coupled to the data line pattern 908. The drain D4 of the transistor T4 is coupled to the source S3 of the third transistor T3.

[0040] The gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903. The source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901. The drain D5 of the transistor T5 is coupled to the source S3 of the third transistor T3.

[0041] The gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903. The source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3. The drain D6 of the sixth transistor T6 is coupled to the anode of the light-emitting element EL.

[0042] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905. The drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL. The source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904. can be.

[0043] The first plate Cst1 of the storage capacitance Cst is connected to the gate 203g of the third transistor T3. The second plate Cst2 of the storage capacitor Cst is connected to the power supply signal line pattern 901. will be done.

[0044] As shown in FIG. 7, during the operation of the display subpixel driving circuit having the above structure, Each of the periods includes a reset period P1, a write compensation period P2, and a light emission period P3. E1 is the emission signal transmitted on the emission control signal line pattern 903 in the current sub-pixel area. R1 represents a light control signal, and R2 represents a reset signal line pattern 905 in the current subpixel area. D1 represents the reset signal transmitted in the data line pattern in the current sub-pixel area, and D2 represents the reset signal transmitted in the data line pattern in the current sub-pixel area. 908, G1 represents the data signal transmitted on the gate line pas- 908 in the current sub-pixel area, and G2 represents the data signal transmitted on the gate line pas- 908 in the current sub-pixel area. R1' represents the gate scan signal transmitted on turn 902, and R1' represents the gate scan signal transmitted on turn 902 on the current sub-pixel area. A reset signal line pattern 905' is transmitted in the previous sub-pixel adjacent to the first sub-pixel along the second direction. Represents the reset signal sent.

[0045] In the first reset period P1, the reset signal input from the reset signal line pattern 905′ The reset signal is at an active level, the second transistor T2 is turned on, and the initial The initialization signal transmitted by the initialization signal line pattern 904' is applied to the gate of the third transistor T3. The signal held in the third transistor T3 in the previous frame is input to the third transistor T203g. The gate-source voltage Vgs is cleared, and the gate 203g of the third transistor T3 is A reset is realized.

[0046] In the write compensation period P2, the reset signal input from the reset signal line pattern 905′ When the gate signal is at an inactive level, the second transistor T2 is turned off, and the gate line pad The gate scan signal input from the gate 902 is at an active level, and the first transistor The first transistor T1 and the second transistor T4 are controlled to be turned on, and the data signal is applied to the data line pa 908, the third transistor T3 is turned on through the fourth transistor T4. The first transistor T1 and the fourth transistor T4 are turned on. As a result, the third transistor T3 is formed as a diode structure, and the first transistor The third transistor T1, the third transistor T3 and the fourth transistor T4 cooperate to form a third If threshold voltage compensation for transistor T3 is realized and the compensation time is long enough, The potential of the gate 203g of the transistor T3 finally reaches Vdata+Vth. where Vdata represents the voltage value of the data signal, and Vth represents the third transistor voltage. represents the threshold voltage of transistor T3.

[0047] In the write compensation period P2, the reset signal input from the reset signal line pattern 905 The T7 signal is at an active level, and the seventh transistor T7 is controlled to turn on; The initialization signal transmitted by the initialization signal line pattern 904 is The light emitting element EL is controlled so as not to emit light.

[0048] In the light emission period P3, the light emission control signal written in the light emission control signal line pattern 903 is activated. active level, so that the fifth transistor T5 and the sixth transistor T6 are turned on. By controlling the power supply signal transmitted by the power supply signal line pattern 901, the power supply signal is transmitted to the third transistor. The input to the source S3 of the third transistor T3 is connected to the gate 203g of the third transistor T3. By maintaining the voltage at Vdata+Vth, the third transistor T3 is turned on, and the third transistor The gate-source voltage for transistor T3 is Vdata+Vth-VDD. Here, VDD is a voltage value corresponding to the power supply signal, and is generated based on the gate-source voltage. The generated leakage current flows to the anode of the corresponding light-emitting element EL, Drives the L emission.

[0049] As shown in FIGS. 10 to 13, when the display subpixel driving circuit is manufactured, The layout of each film layer corresponding to the moving circuit is as follows: The active film layer and the gate insulating film are laminated in sequence in a direction away from the base. A first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer, a first so This forms the source / drain metal layer and the third interlayer insulating layer.

[0050] As shown in FIG. 10, the active film layer includes a transistor in the display subpixel driving circuit. The channel area of ​​the FET (e.g., 101pg to 107pg), the source formation area (e.g., 101ps to 107ps) and drain formation area (e.g., 101pd to 107pd) The purpose is to form an active layer corresponding to a source forming area and a drain forming area. The conductive performance of the active film layer is determined by the doping effect. The active film layer is better than the amorphous silicon, polysilicon It should be noted that the source and drain regions may be made of a material other than the semiconductor material, such as an oxide semiconductor material. The n-type region may be a region doped with n-type impurities or p-type impurities.

[0051] Also, please note that the areas corresponding to the source and drain forming areas are The active film layer may be used as is as the corresponding source or drain, or A source contacting the source forming area is made of a metal material, and the drain forming area The drain in contact with the a may be made of a metallic material.

[0052] As shown in FIG. 11, the first gate metal layer is connected to each transistor in the display subpixel driving circuit. The gates of the display substrate (e.g., 201g to 207g) and the gate line patterns included in the display substrate A light emission control signal line pattern 903, a reset signal line pattern 905, etc. are formed. The third transistor T3 in each display subpixel drive circuit is The gate 203g is connected to the first storage capacitor Cst of the display subpixel driving circuit. Also used as electrode plate Cst1.

[0053] As shown in FIG. 12, the second gate metal layer is a second plate Cst2 of the second storage capacitance Cst, Also, it is for forming an initialization signal line pattern 904 included in the display substrate.

[0054] As shown in FIGS. 6, 8 and 13, the first source-drain metal layer is a display subpixel drive circuit. The source (e.g., S1 to S7) and drain (e.g., D1 -D7), as well as the data line pattern 908 and the power signal line pattern 9 01 and for forming several conductive connections.

[0055] More specifically, still referring to FIGS. 10 to 13, the gate 2 of the first transistor T1 01g covers the first channel area 101pg, and the source S1 of the first transistor T1 is , located in the first source forming area 101ps, and the drain D1 of the first transistor T1 is It is located in the first drain forming area 101pd.

[0056] The gate 202g of the second transistor T2 covers the second channel area 102pg. The source S2 of the second transistor T2 is located in the second source forming area 102ps. The drain D2 of the transistor T2 is located in the second drain formation area 102pd.

[0057] The gate 203g of the third transistor T3 covers the third channel area 103pg. The source S3 of the third transistor T3 is located in the third source forming area 103ps. The drain D3 of the transistor T3 is located in the third drain formation area 103pd.

[0058] The gate 204g of the fourth transistor T4 covers the fourth channel area 104pg. The source S4 of the fourth transistor T4 is located in a fourth source forming area 104ps. The drain D4 of the transistor T4 is located in the fourth drain formation area 104pd.

[0059] The gate 205g of the fifth transistor T5 covers the fifth channel area 105pg. The source S5 of the fifth transistor T5 is located in the fifth source forming area 105ps. The drain D5 of the transistor T5 is located in a fifth drain formation area 105pd.

[0060] The gate 206g of the sixth transistor T6 covers the sixth channel area 106pg. The source S6 of the sixth transistor T6 is located in the sixth source forming area 106ps. The drain D6 of the transistor T6 is located in a sixth drain formation area 106pd.

[0061] The gate 207g of the seventh transistor T7 covers the seventh channel area 107pg. The source S7 of the seventh transistor T7 is located in the seventh source forming area 107ps. The drain D7 of the transistor T7 is located in a seventh drain formation area 107pd.

[0062] The gate 203g of the third transistor T3 serves as the first plate Cst1 of the storage capacitance Cst. The second plate Cst2 of the storage capacitor Cst is connected to the power supply signal line pattern 901. do.

[0063] As shown in FIG. 8, in the display panel according to the present disclosure, In this case, the gate 204g of the fourth transistor T4 and the gate 20 1g and the gate 202g of the second transistor T2 are both gates of the driving transistors ( That is, it is located on the first side of the gate 203g of the third transistor T3, and the seventh transistor T 7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 , each of which is located on the second side of the gate of the driving transistor. The first and second sides of the gate of the actuator are opposite to each other along the second direction, and The first side of the gate of the transistor may be above the gate of the drive transistor, The second side of the gate of the differential transistor may be below the gate of the drive transistor. The lower side, for example, the side for bonding an IC on a display substrate, The lower side of the substrate is the lower side of the gate of the driving transistor. The upper side is the side opposite the lower side, e.g. the side closer to the IC that is connected to the driving transistor. It is the side of the star gate that is farther from the IC.

[0064] In a first direction (e.g., the X direction), the gate 204g of the fourth transistor T4 and The gate 205g of the fifth transistor T5 is located on the third side of the gate of the driving transistor. The gate 201g of the first transistor T1 and the gate 206 of the sixth transistor T6 are g are both located on the fourth side of the gate of the driving transistor. The third side and the fourth side of the gate of the actuator are opposite sides along the first direction, and The third side of the gate of the transistor may be the right side of the gate of the drive transistor, The fourth side of the gate of the differential transistor may be to the left of the gate of the drive transistor. For the left and right sides, for example, in the same subpixel area, data line patterns 90 8 is located on the right side of the power supply signal line pattern 901, and the power supply signal line pattern 901 is It is located to the right of line pattern 908.

[0065] Although the resolution of the display panel can be improved, the effect of the improvement is limited. Furthermore, as can be seen from FIG. 8, the second transistor T2 and the seventh transistor T7 The conductive portion 909 is connected to the initialization signal line pattern 904 (904') through a via hole. When a high-resolution display panel is combined with a 3D printer, the layout space is small and the space available for drilling holes is small. Since the via hole size is small, the via hole may be inaccurate due to process variations during the hole drilling process. 905, which is adjacent to the reset signal line pattern 905, may easily lead to signal disturbance.

[0066] Therefore, in order to solve the above problem, the display panel with high resolution is The pixel structure within the filter needs to be further optimized.

[0067] 15 and 16, an embodiment of the present disclosure is a display panel, comprising a base and a front A functional film layer provided on the base, and a plurality of sub-pixel areas arranged in an array. Further comprising: the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer is a reset signal line pattern provided in each of the sub-pixel areas. 905, the reset signal line pattern 905 extending along a first direction; The initialization signal line layer includes an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, the initialization signal line pattern 904 includes a first body portion 9041 coupled to each other. and a first protruding portion 9042, and the first body portion 9041 is Extending over the same subpixel area, the positive electrode 902 extends over the base of the first body portion 9041. The projection is a normal projection of the first protruding portion 9042 on the base and a projection of the reset signal line pas and an orthogonal projection of the turn 905 on said base, The conductive connection layer includes a conductive connection pattern 909 provided in each of the sub-pixel areas. In the same sub-pixel area, the first end 9091 of the conductive connection pattern 909 and the orthogonal projection of the first protruding portion 9042 on the base. In the first overlap region F1, The first end 9091 is coupled to the first protruding portion 9042, and the conductive connection pattern A second end 9092 of 909 couples to a target coupling portion within the subpixel area in which it is located. The orthogonal projection of the reset signal line pattern 905 on the base is Orthogonal projection of the coupling portion on the base and the initialization signal line pattern 904 on the base The display panel is positioned between the orthogonal projection of the display.

[0068] Specifically, the sub-pixel areas arranged in an array are sequentially arranged along the second direction. A plurality of rows of sub-pixel areas arranged in a row, and a plurality of columns of sub-pixel areas arranged sequentially along a first direction. The sub-pixel areas of each row may be spaced apart along a first direction. Each of the sub-pixel areas in each column is aligned in the second direction. The pixel area includes a plurality of sub-pixel areas spaced apart from each other along the first direction and the second direction. The first direction includes an X direction, and the second direction includes a Y direction. Includes direction.

[0069] The reset signal line layer is a reset signal line pattern provided in each of the sub-pixel areas. 905, the reset signal line pattern 905 extending along the first direction. The reset signal line pattern 905 corresponds to the sub-pixel area one-to-one. The dot signal line pattern 905 is located in the corresponding sub-pixel area and is located in the same row. The reset signal line patterns 905 corresponding to the sub-pixel areas are electrically connected in sequence. and formed as a unitary structure.

[0070] The initialization signal line layer includes an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, the initialization signal line pattern 904 corresponds to the sub-pixel area in one-to-one correspondence; The initialization signal line patterns 904 are located in the corresponding sub-pixel areas and are located in the same row. The initialization signal line patterns 904 corresponding to the sub-pixel areas to be placed are sequentially electrically are connected and formed as a unitary structure.

[0071] As shown in FIG. 16, the initialization signal line patterns 904 are all connected to each other. a first body portion 9041 and a first protruding portion 9042, The first pixel areas extend along the first direction and correspond to the sub-pixel areas located in the same row. The first main body portions 9041 of the synchronization signal line pattern 904 are electrically connected in sequence. It should be noted that, taking into account the tolerances of the manufacturing process, The first body portion is not necessarily linear and extends along the first direction.

[0072] The specific shape of the first protruding portion 9042 may be varied. The first protruding portion 9042 protrudes from the first body portion 9041 to which it is connected. In the same subpixel area, the first body portion 9041 The orthogonal projection on the base is a projection of the first protruding portion 9042 on the base. The reset signal line pattern 905 is positioned between the reset signal line pattern 905 and the orthogonal projection on the base. In this way, the first protruding portion 9042 is opposite to the reset signal line pattern 905. Therefore, the first protruding portion 9042 and the reset recess 9044 can be provided so as to be in contact with each other. A large distance can be provided between the signal line pattern 905 and the ground signal line pattern 906.

[0073] It should be noted that in one initialization signal line pattern 904, the first body portion 90 41 and the first protruding portion 9042 may be formed as an integral structure, but is not limited thereto. I can't.

[0074] The conductive connection layer includes a conductive connection pattern 909 provided in each of the sub-pixel areas. The conductive connection pattern 909 corresponds to the sub-pixel area in one-to-one correspondence, and the conductive An electrical contact pattern 909 is located in the corresponding sub-pixel area. an orthogonal projection of a first end 9091 of the conductive connection pattern 909 on the base; The orthogonal projection of one protruding portion 9042 on the base has a first overlap region F1. The first end portion 9091 and the first protruding portion 9042 are disposed in the first overlap region. The conductive connection portion can be connected by opening a hole (for example, a first connection hole 70) in the region F1. A second end 9092 of the pattern 909 is formed by target bonding within the subpixel area in which it is located. The target coupling portion is coupled to a seventh transistor corresponding to the current sub-pixel area. the first pole of the pixel, and the next subpixel adjacent to the current subpixel area along the second direction The area may include a first pole of a second transistor corresponding thereto.

[0075] The target coupling portion may be disposed at various positions, for example, in the same sub-pixel area. The orthogonal projection of the reset signal line pattern 905 on the base is The orthogonal projection of the joint on the base and the initialization signal line pattern 904 on the base It may be provided so as to be located between the orthogonal projection.

[0076] It should be noted that the display panel has an interlayer medium layer (i.e., the above-mentioned second interlayer insulating layer I The interlayer medium layer is formed between the second gate metal layer and the first source metal layer in the display panel. The initialization signal line pattern 904 is disposed between the second gate electrode and the drain metal layer. It can be placed on the same layer as the metal layer and can be formed in the same patterning process. The conductive connection pattern 909 may be formed in the same layer as the first source-drain metal layer. As described above, the present invention can be formed by the same patterning process. A hole is drilled in the first overlap region F1 to expose the first end 9 By realizing the coupling between the first protruding portion 9042 and the first protruding portion 9041, the via hole is , a via hole penetrating the ILD layer, and the position of the via hole is The distance between the patterns 905 becomes greater.

[0077] As can be seen from the specific structure of the display panel described above, the display panel according to the embodiment of the present disclosure has In this case, the initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The conductive connection pattern includes a first protruding portion 9042 on the opposite side. The orthogonal projection of the first end 9091 of the base 909 and the first protruding portion 9042 The orthogonal projection on the base has a first overlap region F1, and the first end 90 91 and the first protruding portion 9042 form a hole in the first overlap region F1. According to this configuration, the conductive connection portion and the A via hole for coupling the initialization signal line pattern 904 and the reset signal line pattern The large distance between the turns 905 reduces the process variation during the drilling process. Due to this, the via hole is misaligned and opens onto the nearby reset signal line pattern 905. This avoids the problem of signal distortion, and improves the yield of the display panel. is suitably guaranteed.

[0078] In addition, the initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The first protruding portion 9042 is disposed on the opposite side of the conductive connection portion and the initialization signal line pattern 904. A via hole for coupling to the first protruding portion 9042 is formed in the first protruding portion 9042. Therefore, the orthogonal projection of the via hole on the base is the same as the initialization signal line pattern 90. 4 on the base, so that the initialization The reliability of the connection between the signal line pattern 904 and the conductive connection pattern 909 is suitably improved. As a result, the stability of the display panel during operation is more preferably ensured.

[0079] As shown in FIG. 15 and FIG. 16, in some embodiments, the display panel includes: The functional film layer has a plurality of sub-pixel areas, and the functional film layer has a plurality of sub-pixel areas. A plurality of light emitting elements located on the opposite side; A plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas, Each of the subpixel driving circuits includes a seventh transistor T7, The gate 207g of T7 is coupled to the corresponding reset signal line pattern 905, The first pole of the seventh transistor T7 is used as the target coupling part, and the seventh transistor The second pole of the transistor T7 (formed in an area of ​​107 pd) extends along the second direction. and a plurality of subpixel drive circuits coupled to the anodes of the corresponding light emitting devices. Including, The conductive connection pattern 909 has a first end 9091 and a second end 9092. a second body portion 9093 connected therebetween, the second body portion 9093 being In the same subpixel area, the conductive connection The first end 9091 of the part pattern 909 is oriented in a direction away from the second pole of the seventh transistor. The second body portion 9093 protrudes from the second body portion 9093 in the forward direction.

[0080] Specifically, the display panel is located on the opposite side of the functional film layer from the base. The light-emitting element further includes a plurality of light-emitting elements, the plurality of light-emitting elements being in one-to-one correspondence with the plurality of sub-pixel areas. Each of the light emitting elements corresponds to the base in a direction away from the base. The display panel includes an anode, a light-emitting pattern, and a cathode, which are stacked together. A drive signal is supplied to the anode and a common signal is supplied to the cathode, An electric field is generated between the anode and the cathode, which results in the light emission pattern being changed by a corresponding The light emitting element is controlled to emit light of a color corresponding to the color of the light emitting element. For example, the light emitting element can emit red light. a red light-emitting element capable of emitting green light, a green light-emitting element capable of emitting blue light, This includes blue light emitting elements that can emit light.

[0081] The display panel includes a plurality of sub-pixel driving circuits each corresponding to one of the sub-pixel areas. Each of the sub-pixel driving circuits further includes a pixel driving circuit for driving a pixel of a corresponding light-emitting element. Illustratively, each of the sub-pixel driving circuits is for providing a driving signal to the sub-pixel driving circuit. Each of the seventh transistors includes a gate of the corresponding reset transistor. 905, and a first electrode of the seventh transistor is connected to the target 909 is used as a conductive connection portion, and the corresponding The second electrode of the seventh transistor T7 can be coupled to the first signal line pattern 904. The light emitting element extends along the second direction and is coupled to the anode of the corresponding light emitting element.

[0082] As shown in FIG. 6, the seventh transistor mainly drives the N2 node before the pixel is charged. The seventh transistor is for resetting. The detailed reset process is as follows: , through the initialization signal line pattern 904 coupled to the conductive connection pattern 909 An initialization signal is supplied, and the initialization signal is transmitted to the N2 node by the seventh transistor. This realizes a reset for the N2 node. Note that the conductive connection The part pattern 909 is used as an intermediate layer to realize a jumper, and the conductive connection The connection between the conductive connection pattern 909 and the seventh transistor, and the conductive connection pattern 909 The connection between the pattern 902 and the initialization signal line pattern 904 may be realized by drilling holes. stomach.

[0083] The specific structure of the conductive connection pattern 909 may be various. For example, the conductive connection pattern 909 may be formed as shown in FIG. Thus, the conductive connection pattern 909 has a first end 9091 and a second end 909 2, the second body portion 9093 being The second direction may extend along the second direction, and the first direction may extend along the first direction in the same sub-pixel area. Thus, the first end 9091 of the conductive connection pattern 909 is connected to the first end 9092 of the seventh transistor. The second body portion 9093 projects away from the bipolar pole. According to the conductive connection pattern 909, the first end 9091 and the seventh Since the conductive connection pattern 909 is spaced far from the second pole of the transistor, A via hole for connecting the first end 9091 of the pattern 909 to the initialization signal line pattern 904. When the via hole is formed on the ILD, the position of the via hole is set to be 100 mm from the second electrode of the seventh transistor. As a result, the via hole is fabricated at a greater distance from the substrate, which is caused by process variations. As a result, the via hole is misaligned and opened above the second electrode of the seventh transistor, which leads to signal distortion. This is advantageous in avoiding the problem that the display panel is easily damaged, and the yield of the display panel is further improved. Guaranteed.

[0084] More specifically, as shown in FIG. 15, the second electrode of the seventh transistor is formed of a ploy layer ( That is, the active layer is fabricated, and the conductive connection pattern 909 is formed as the above structure. In this way, the via hole is prevented from being damaged due to process variations during the manufacture of the via hole. A hole is opened on the ploy layer corresponding to the second electrode of the seventh transistor, This can more effectively avoid the problem of signal disturbance, and the yield of the display panel can be improved. It is further preferably guaranteed.

[0085] As shown in FIG. 15, in some embodiments, the functional film layer is formed in each sub-pixel area. The data line pattern 908 may further include a data line pattern 908 located at The portion includes a portion extending along two directions, The initialization signal line pattern 904 is orthogonally projected onto the base, and the conductive connection pattern and the orthogonal projection of the base 909 on the base has a third overlap region F3. The orthogonal projection of the initialization signal line pattern 904 on the base and the data line pattern 908 and the orthogonal projection on the base there is a fourth overlap region F4; The second overlap region of the initialization signal line pattern 904 in the fourth overlap region F4 The width L5 along the direction is the width of the initialization signal line pattern in the third overlap region F3. 904 in the second direction.

[0086] Specifically, the data line patterns 908 correspond to the sub-pixel areas in a one-to-one manner. The data line pattern 908 is located in the corresponding sub-pixel area. The sub-pixel elements 908 include a portion extending along the second direction and are arranged in the same column. The data line patterns 908 corresponding to the rear are electrically connected in sequence to form an integral structure. It is formed by:

[0087] The data line pattern 908 extends along the second direction, and the initialization signal line pattern A first body portion 9041 of the shaft 904 extends along the first direction and is and the second direction intersect, so that in a direction perpendicular to the base, the initialization signal line The pattern 904 always overlaps at least a portion of the data line pattern 908. It's going to be rapping.

[0088] As described above, the orthogonal projection of the initialization signal line pattern 904 onto the base and the The orthogonal projection of the conductive connection pattern 909 on the base has a third overlap region F 3, the orthogonal projection of the initialization signal line pattern 904 on the base, and the data line The orthogonal projection of the pattern 908 on the base has a fourth overlap region F4. In both cases, the initialization signal line pattern 904 in the fourth overlap region F4 The width in the second direction is The width of the first turn 904 in the second direction is smaller than the width of the first turn 904 in the second direction. The synchronization signal line pattern 904 is formed in several regions (specifically, the third overlapping region, for example). In the second direction, the width of the initialization signal line may be narrowed in the first region F3. Reduction in the overlap area between the pattern 904 and the data line pattern 908, parasitic This is advantageous not only in reducing the capacitance value of the capacitor, but also in improving the layout of the initialization signal line pattern 904. The space required for the display can be effectively reduced, which is more advantageous in saving pixel space and thus improving the display performance. This is beneficial for the development of high-resolution panels.

[0089] As shown in FIGS. 15 to 17, in some embodiments, and the orthogonal projection of the second body portion 9093 on the base and the seventh transistor T7 There is a first gap L1 between the orthogonal projection of the second pole on the base, and the first gap is Greater than the threshold.

[0090] Specifically, as described above, an orthogonal projection of the second body portion 9093 onto the base; A first gap L1 is provided between the second pole of the seventh transistor T7 and the orthogonal projection of the second pole on the base. In the direction perpendicular to the base, the second body portion 90 93 and the second pole of the seventh transistor T7. .

[0091] In addition, by configuring the first gap L1 to be larger than a threshold value, the second body an orthogonal projection of portion 9093 on the base and the base of the second pole of the seventh transistor; A large distance is provided between the orthogonal projection on the second body portion 9093 and the Damage to the second electrode of the seventh transistor during the process is preferably avoided. Importantly, the threshold value can be set according to actual needs. For example, the threshold value is 8 μm to 35 μm and may include the endpoints.

[0092] As shown in FIG. 15 and FIG. 16, in some embodiments, the display panel includes: Each of the sub-pixel areas has a driving transistor and a second a plurality of subpixel drive circuits including transistor T2; The gate 202g of the second transistor T2 is adjacent to the previous transistor T1 in the second direction. The reset signal line pattern 905' is coupled to the second transistor 905 in the pixel area. the first pole of T2 is used as the target coupling portion in the front sub-pixel area; The second pole of the second transistor T2 is connected to the driving transistor (i.e., the third transistor T3) gate, The second transistor T2 includes two semiconductor portion (located in the region denoted by reference numeral 102pg as shown in FIG. 19), and the two semiconductor a first conductor portion 80 connected to the base of each of the first conductor portions 80; The orthogonal projection on the base of the first protruding portion 9042 in the front subpixel area does not overlap with the orthographic projection in

[0093] Specifically, each of the sub-pixel driving circuits includes a driving transistor and a second transistor. the driving transistor generates a driving signal for driving the light emitting element to emit light. The second transistor gate is adjacent to the front gate along the second direction. is coupled to the reset signal line pattern 905 in the subpixel area of ​​the second transistor The first pole of the photodiode is used as the target coupling portion in the front sub-pixel area, and the front A second electrode of the second transistor is coupled to a gate of the drive transistor. The transistor is connected to the initialization signal line pattern 904 to which it is coupled before the pixel is charged. The initialization signal provided by the N1 node (coupled to the gate of the driving transistor) ) to effect a reset for the N1 node.

[0094] Exemplarily, the second transistor is optionally a double gate structure, Specifically, the transistor includes two semiconductor portions spaced apart from each other along the first direction. and a first conductor portion 80 connected to the two semiconductor portions, The conductor portions each correspond to a channel area of ​​the second transistor. The conductor portion and the first conductor portion 80 may be formed as a unitary structure and may be pre-assembled during fabrication. The two semiconductor portions and a third semiconductor portion corresponding to the first conductor portion 80 are formed. Then, the third semiconductor portion is doped to form the third semiconductor portion into the first conductor It may be formed as part 80.

[0095] As described above, the orthogonal projection of the first conductor portion 80 onto the base is The orthogonal projection of the first protruding portion 9042 on the base does not overlap with the orthogonal projection of the first protruding portion 9042 on the base. By configuring the pattern in this manner, the initialization signal line pattern 904 and the conductive connection pattern 9 When forming a via hole to connect the 09, the via may be damaged due to process variations. If the hole is misaligned and drilled on the first conductor portion 80, it may lead to signal distortion. This can more effectively avoid such problems, and the yield of the display panel can be more effectively guaranteed.

[0096] As shown in FIGS. 15 and 16, in some embodiments, the first conductor portion 80 Orthogonal projection on the base results in the conductive connection pattern 909 in the front sub-pixel area. 9091 on the base.

[0097] Specifically, as described above, the orthogonal projection of the first conductor portion 80 on the base is The base of the first end 9091 of the conductive connection pattern 909 in the previous sub-pixel area The conductive connection pattern 90 is configured to overlap with the orthogonal projection on the The first end 9091 of the 9 is a connection via hole between it and the initialization signal line pattern 904. Not only can the conductive connection have a larger area to cover the wire, but the conductive connection The layout position of the first end 9091 of the pattern 909 and the first conductor portion 80 is closer to each other. This is advantageous for saving pixel space and is also expected to contribute to the development of high-resolution display panels. It is favorable for realization.

[0098] As shown in FIGS. 15 and 16, in some embodiments, each of the initialization signal lines The pattern 904 further includes a second protruding portion 9043 coupled to the first body portion 9041. In the same subpixel area, the positive projection of the second protruding portion 9043 on the base The shadow is a result of the orthogonal projection of the first body portion 9041 on the base and the reset signal line pattern. and the orthogonal projection of the first conductor portion 80 on the base. The orthogonal projection on the substrate 9042 of the second protruding portion 9043 and / or the first body portion 9041 It overlaps with the orthographic projection on the base.

[0099] Specifically, each of the initialization signal line patterns 904 further includes a second protruding portion 9043. The second protruding portion 9043 may be specifically formed by connecting the first body portion 9041 and the The second protruding portion 905 may be located between the reset signal line pattern 905. 043, the first protruding portion 9042 and the first body portion 9041 are formed as a unitary structure. may be made.

[0100] As described above, the orthogonal projection of the first conductor portion 80 on the base is part 9043 / or the orthogonal projection of the first body portion 9041 onto the base. With this configuration, the initialization signal line pattern 904 does not shield the first conductor portion 80. Therefore, all the initialization signals transmitted on the initialization signal line pattern 904 can be safely Since the signal is a fixed signal, such shielding prevents the above-mentioned The stability of the signal on the first conductor portion 80 can be guaranteed, and the floating of the first conductor portion 80 can be prevented. When an external data signal changes, the first conductor portion 80 is changed by the effect of capacitive coupling. The problem of signal instability is avoided.

[0101] As shown in FIGS. 15 to 17, in some embodiments, the conductive connection pattern 9 09 is a second body portion connected between the first end 9091 and the second end 9092 9093, the second body portion 9093 extending along a second direction; The conductive connection pattern 9 in the previous sub-pixel area in the first conductor portion 80 The end 801 close to the end 09 extends along the second direction, and on the base of the end 801 and the second body portion 9093 of the conductive connection pattern 909 on the base. There is a second gap L2 between the orthogonal projection, and the second gap L2 is larger than a threshold value.

[0102] Specifically, the first conductor portion 80 may have various shapes. 0 has a “gate” structure, i.e., the previous sub-pixel element in the first conductor portion 80 The end 801 close to the conductive connection pattern 909 in the rear extends along the second direction. The end 802 of the first conductor portion 80 close to the power signal line pattern 901 is A portion of the first conductor portion 80 extending along the second direction and located between these two ends extends along the first direction.

[0103] As described above, the conductive portion 80 in the front subpixel area The orthogonal projection of the end 801 close to the connection pattern 909 on the base and the conductive connection pattern A second gap L2 is provided between the second body portion 9093 of the first body 909 and the orthogonal projection of the second body portion 9093 on the base. In the direction perpendicular to the base, the second body portion 90 93 and the first conductor portion 80.

[0104] In addition, by configuring the second gap L2 to be larger than a threshold value, the second body The orthogonal projection of the portion 9093 on the base and the orthogonal projection of the first conductor portion 80 on the base During the process of fabricating the second body portion 9093, a large distance is provided between the projections. Damage to the first conductor portion 80 at the threshold voltage is preferably avoided. can be set according to actual needs, and for example, the threshold value is 8 μm to 35 μm. and may include endpoint values.

[0105] As shown in FIGS. 15 and 16, in some embodiments, a first end 9091 of the conductive connection pattern 909 projected on the base; The first main body portion 9041 of the initialization signal line pattern 904 is orthogonally projected onto the base. Also, a second overlap region F2 is formed, The functional film layer further includes a first connection hole 70 located in each of the sub-pixel areas, In the pixel area, the orthogonal projection of the first contact hole 70 on the base is The first overlap region F1 and the second overlap region F2 overlap each other, The first end 9091 of the conductive connection pattern 909 is connected to the first connection hole 70. 9. The signal line pattern 904 is coupled to the signal line pattern 904 .

[0106] Specifically, the positive throw of the first end 9091 of the conductive connection pattern 909 on the base The shadow is a positive projection of the first protruding portion 9042 of the initialization signal line pattern 904 on the base. The shadow can have a first overlap region F1, and the initialization signal line A second overlap also occurs with the orthogonal projection of the first body portion 9041 of the turn 904 on the base. It may have a region F2.

[0107] The first end 9091 of the conductive connection portion is connected to the initialization signal line port 70 through the first connection hole 70. When the first connecting hole 70 is connected to the turn 904, the orthogonal projection of the first connecting hole 70 on the base is The first overlap region F1 and the second overlap region F2 are overlapping regions. In this way, the layout space for the first connection hole 70 can be reduced. The conductive connection pattern 909 and the initialization pattern can be connected with each other with a high degree of accuracy. I can prove it.

[0108] As shown in FIG. 18, in some embodiments, the second transistor T2 The orthogonal projection of one conductor portion 80 on the base 40 corresponds to the first conductor portion 80 in the front subpixel area. It does not overlap with the orthogonal projection of the connection hole 70 on the base 40 .

[0109] Specifically, as described above, the base of the first conductor portion 80 of the second transistor The orthogonal projection on the pixel 40 of the base 4 of the first contact hole 70 in the front sub-pixel area 0 and does not overlap with the orthogonal projection on the first contact hole during the manufacturing process. In addition, due to process variations, the via hole may be misaligned and opened on the first conductor portion 80. This can more suitably avoid the problem of the signal being easily disturbed by the interference caused by the light. The yield is further preferably guaranteed.

[0110] As shown in FIG. 15 and FIG. 16, in some embodiments, the functional film layer is The power signal line layer further includes a power signal line provided in each of the sub-pixel areas. a power signal line pattern 901, at least a portion of which is oriented in a second direction; Extending along, The conductive connection pattern 90 in the previous sub-pixel area of ​​the first conductor portion 80 The end 802 remote from the 9 extends along the second direction, and on the base of the end 802 The orthogonal projection of the base of the power supply signal line pattern 901 located in the same sub-pixel area. It is completely covered by the orthographic projection above.

[0111] Specifically, the power signal line pattern 901 corresponds to the sub-pixel area one-to-one; The power supply signal line pattern 901 is located in the corresponding sub-pixel area. The power supply signal line patterns 901 provided in the pixel area are arranged in sequence along the second direction. and can be formed as a unitary structure.

[0112] As described above, the conductive portion 80 in the front subpixel area The end 802 far from the connection portion pattern 909 extends along the second direction, and the end 80 2, the orthogonal projections of the power supply signal line patterns on the base are located in the same sub-pixel area. 901 on the base, the orthogonal projection of the The source signal line pattern 901 is located in the front sub-pixel area of ​​the first conductor portion 80. The end far from the conductive connection pattern 909 can be shielded. Since the power signals transmitted over the 01 are all stable signals, such shielding does not This ensures that the signal on the first conductor portion 80 remains stable when the external data signal changes. Due to the floating of one conductor portion 80, a capacitive coupling occurs when the external data signal changes. The problem of instability of the signal of the first conductor portion 80 due to the action of the ring is avoided.

[0113] In addition, according to the above-mentioned configuration method, the first conductive portion and the power supply signal line pattern 901 The layout space occupied by the display is effectively reduced, the pixel structure is advantageously reduced, and the display This will be advantageous as display panels become more highly resolvable.

[0114] The power signal line pattern 901 may have various structures, as shown in FIG. In this embodiment, the power signal line pattern 901 extends along the second direction and The width of the power supply signal line pattern 901 in a direction perpendicular to the second direction is set to be approximately uniform. It may be configured as follows.

[0115] As shown in FIG. 23 and FIG. 24, in some other embodiments, the display panel includes: A plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas, Each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor, and the storage capacitor The first electrode plate is connected to the driving transistor. The second plate is opposite to the base of the first substrate. a plurality of subpixel driving circuits disposed on the side of the pixel; The functional film layer further includes a power supply signal line layer, and the power supply signal line layer is connected to each of the sub-pixel areas. The power supply signal line pattern 901 is provided on the At least a part of the power supply signal line pattern 901 extends along the second direction. 9011 and a second power supply unit 9012, The orthogonal projection of the first power supply unit 9011 on the base is located in the same sub-pixel area. When each of the reset signal line patterns 905 overlaps with an orthogonal projection on the base, Both on the base of each of the gate line patterns 902 located in the same sub-pixel area. The orthogonal projection of the second power supply unit 9012 on the base overlaps with the orthogonal projection of the second power supply unit 9012 on the base. The orthogonal projection and overlap of the second plate Cts2 of the storage capacitance Cts on the base In the first direction, the width L3 of the first power supply unit 9011 is 12 smaller than width L4.

[0116] Specifically, each of the sub-pixel driving circuits includes a driving transistor and a storage capacitance Ct s, and a first plate Cts1 of the storage capacitance Cts may be The second plate Cts2 of the storage capacitor is also used as the gate of the first plate It is located on the opposite side of the base in Cts1 and can form a facing area with the first electrode plate. It is Noh.

[0117] The power signal line pattern 901 is specifically a first power supply section 9011 and a second power supply section 90 12, for example, the first power supply unit 9011 and the second power supply unit 9012 The first and second portions are alternately arranged along the second direction, and adjacent first and second portions are joined to each other. Exemplarily, the first power supply unit 9011 and the second power supply unit 9012 are formed as an integral structure. It is done.

[0118] The specific layout positions of the first power supply unit 9011 and the second power supply unit 9012 may vary. For example, the orthogonal projection of the first power supply unit 9011 on the base is The orthogonal projection and overlay of each of the reset signal line patterns 905 located in the area on the base. The gate line patterns 902 are overlapped and located in the same sub-pixel area. and the orthogonal projection of the second power supply unit 9012 on the base. The orthogonal projection of the second plate of the storage capacitor on the base overlaps with the orthogonal projection of the second plate of the storage capacitor on the base. As described above, the first power supply unit 90 is configured to be connected to the first direction. 11 is configured to be smaller than the width of the second power supply unit 9012, Since the width of the first power supply unit 9011 in the first direction is effectively narrowed, The overlap area between 9011 and the reset signal line pattern 905 is reduced. At the same time, the overlap between the first power supply part 9011 and the gate line pattern 902 As a result, the area of ​​the power supply signal line pattern 901 and the reset signal line is reduced. The coupling capacitance occurring between them is effectively reduced.

[0119] It should be noted that the width of the first power supply part 9011 in the first direction is The maximum or minimum distance between two opposing boundaries of the first power supply unit 9011 along the direction Similarly, the width of the second power supply unit 9012 in the first direction is the distance The maximum or minimum distance between two opposing boundaries of the second power supply unit 9012 along the direction It is.

[0120] Please note that in FIG. 25, the current power supply signal line pattern 901 is connected to the first power supply unit. 9011 and the corresponding eight sub-pixel elements when the second power supply unit 9012 is used. The first connection hole 70 shown in FIG. 25 is a schematic diagram of the rear of the first connection hole. The diameter of the first connection hole that is actually manufactured is shown in FIG. The specific position of the first connection hole may be larger than the hole diameter shown in The orthogonal projection of a first end 9091 of the conductive connection pattern 909 onto the base and the initial Even if the signal line pattern 904 is located in an overlapping region with the orthogonal projection on the base, good.

[0121] 26 is a schematic diagram of the active layer in FIG. 25, and FIG. 27 is a schematic diagram of the active layer in FIG. FIG. 28 is a schematic diagram of the first gate metal layer in FIG. 25; FIG. 29 is a schematic diagram of the first source-drain metal layer in FIG. 25; 0 is a second source drain when the display panel includes a second source drain metal layer FIG. 2 is a schematic diagram of eight sub-pixel areas corresponding to metal layers.

[0122] It should be noted that, as shown in FIGS. 30 and 31, the second source-drain metal layer Specifically, the power supply compensation pattern 300 and the adapter pattern 310 may be included. The power supply compensation pattern 300 includes a horizontal connection portion 3001 and a vertical connection portion 3002. The power compensation pattern 300 reduces IR drop on the power signal line pattern. The power supply signal line pattern is connected to the power supply signal line pattern included in the display panel so that the adapter The adapter pattern 310 corresponds to the anode included in the display panel in one-to-one correspondence. Each anode 310 has a corresponding anode 320 and a drive signal for supplying the anode 320 to the corresponding anode 320. This is for connecting the sub-pixel driving circuit for the pixel shift register.

[0123] In a specific embodiment, referring to FIG. 34, the adapter pattern 310 and the display pattern A second adapter pattern 906 may be further provided between the anode included in the panel. Preferably, the second adapter pattern 906 is located in the first source-drain metal layer.

[0124] It should be noted that the first source-drain metal layer and / or the second source-drain metal layer A passivation layer may be further provided on the metal layer, the passivation layer comprising For example, inorganic materials such as silicon nitride and silicon oxide may be used. There are no particular limitations on this.

[0125] Continuing to refer to FIGS. 30 to 32, the display panel further includes a pixel defining layer, A pixel opening 330 is formed in the pixel definition layer, and the pixel opening 330 is connected to the anode 32. 0, and each pixel aperture 330 corresponds to at least one of the corresponding anodes 320. The organic light-emitting material layer included in the display panel is formed by exposing the corresponding portions. It is formed within the pixel aperture 330 .

[0126] It should be noted that the display panel may include sub-pixels of multiple colors, and different The light emitted by the light emitting element corresponding to the color sub-pixel has different colors. Each pixel unit of the panel has one red sub-pixel R, two green sub-pixels G and one blue sub-pixel. 31 and 32 show the different color sub-pixels in one pixel unit. The layout scheme of the pixel unit, that is, the arrangement scheme of the GGRB pixels, is shown.

[0127] Of course, the pixel unit in the display panel includes one red sub-pixel R, one green sub-pixel G, and one blue sub-pixel B. The pixel unit of this structure specifically includes: A rip (strip) RGB arrangement may be used, that is, the red sub-pixel R, One green subpixel G and one blue subpixel B are arranged in sequence along the same direction (e.g., the X direction). Or, the pixel unit of this structure is specifically arranged as follows: For example, one red sub-pixel R and one blue sub-pixel B may be X The green subpixel G is located in the same row along the X direction, and the green subpixel G is located in a different row along the X direction. do.

[0128] 33, which shows a second gate metal layer and a second source doped layer corresponding to FIG. In some embodiments, the lane metal layers correspond to different color sub-pixels. The orthogonal projection of the adapter pattern 310 on the base and the corresponding second pole of the storage capacitance Even if the overlap area of ​​the plate Cst2 with the orthogonal projection on the base is different, good.

[0129] More specifically, referring to FIG. 32 and FIG. 33, the adapter pin The orthogonal projection of the turn 310 on the base and the corresponding second plate Cst2 of the storage capacitance A first overlap area J1 is formed between the green sub-pixel G and the orthogonal projection on the base. Correspondingly, the orthogonal projection of the adapter pattern 310 on the base and the corresponding storage capacitance A second overlap area J2 is formed between the second electrode plate Cst2 and the orthogonal projection on the base. For the blue subpixel B, the orthogonal projection of the adapter pattern 310 on the base and the orthogonal projection of the second plate Cst2 of the corresponding storage capacitor on the base, a third overhang is provided. The second overlap area J2 is formed by overlapping the first overlap area J3. The first overlap area J1 is smaller than the third overlap area J2. The tip area is smaller than J3.

[0130] According to the above configuration method, the power supply signal line patterns 901 corresponding to the pixel units of different colors The RC loading can be better balanced. .

[0131] 34 is a cross-sectional view taken along the C1-C2 direction in FIG. 34 and the base 40 in the sixth drain forming area 106pd (i.e., the active area of ​​the region The dielectric layer is for forming the drain of the sixth transistor T6. Other film layers, such as a buffer layer, may also be included but are not shown in FIG. A gate insulating layer 41, a second gate insulating layer 42, an interlayer insulating layer 43, a first planar layer 44 and a second planar layer 45 are formed on the first and second gate insulating layers 41, 42, 43, 44, and 45. A flat layer 45 is also shown.

[0132] As shown in FIG. 15 and FIG. 21, in some embodiments, the functional film layer is The power signal line layer further includes a power signal line provided in each of the sub-pixel areas. a power signal line pattern 901, at least a portion of which is oriented in a second direction; Extending along, The functional film layer further includes an auxiliary power supply layer, and the auxiliary power supply layer is provided in each of the sub-pixel areas. a positive electrode on the base of the auxiliary power supply pattern 60; The projection and the positive polarity of the power supply signal line pattern 901 located in the same sub-pixel area on the base There is an overlapping area between the auxiliary power supply pattern 60 and the power supply signal line. Pattern 901 is joined in the overlapping region.

[0133] Specifically, the auxiliary power supply pattern 60 corresponds to the sub-pixel area in one-to-one correspondence. The auxiliary power pattern 60 is located in the corresponding sub-pixel area. The pattern 60 is provided so as to be in the same layer and made of the same material as the second electrode plate of the storage capacitor. That is, they can be formed in the same patterning process.

[0134] When the auxiliary power supply pattern 60 is laid out, the base of the auxiliary power supply pattern 60 and the base of the power supply signal line pattern 901 located in the same subpixel area. There is an overlapping area between the above orthogonal projection, and the auxiliary power supply pattern 60 and the power supply The signal line pattern 901 is connected through a via hole provided in the overlap region. The configuration may be such that the two sensors can be combined.

[0135] As described above, the auxiliary power supply pattern 60 and the power supply signal line pattern 901 are coupled to each other. By configuring the power supply signal line pattern 901 in such a manner that the RC (resistance capacitance) lo The IR droop on the power supply signal line pattern 901 is preferably reduced. p (voltage drop) is reduced, so that the stability of the display panel operation is better guaranteed. .

[0136] As shown in FIG. 15 and FIG. 19, in some embodiments, the display panel includes A driving transistor and a second transistor are provided in a one-to-one correspondence with a plurality of sub-pixel areas. a plurality of subpixel driving circuits including a plurality of subpixel transistors; The gate of the second transistor is adjacent to a previous sub-pixel area in the second direction. 905, and the first electrode of the second transistor is used as the target coupling portion in the front sub-pixel area, The second pole of the motor includes a first electrode portion 51 and a second electrode portion 52 coupled to each other. The first electrode portion 51 extends along a second direction, and the second electrode portion 52 extends along a third direction. The third direction intersects both the first direction and the second direction, and the first electrode portion 51 is located between the semiconductor portion of the second transistor and the second electrode portion 52, The electrode portion 52 is coupled to the gate of the drive transistor, The orthogonal projection of the first electrode portion 51 on the base and the orthogonal projection of the second electrode portion 52 on the base Each of the orthogonal projections on the base is obtained by orthogonal projection of the corresponding auxiliary power supply pattern 60 on the base. It is covered with

[0137] Specifically, the second electrode of the second transistor is coupled to the gate of the driving transistor. For example, the second electrode is specifically a first electrode bonded to each other. The first electrode portion 51 may be connected to the second transistor. The second electrode portion 52 is disposed between the semiconductor portion of the driving is coupled to the gate of the transistor.

[0138] The specific layout manner of the first electrode portion 51 and the second electrode portion 52 may be various. For example, Illustratively, the first electrode portion 51 extends along a second direction, and the second electrode portion 52 extends along a third direction. The third direction intersects both the first direction and the second direction. As described above, the orthogonal projection of the first electrode portion 51 on the base and the second electrode portion 5 2 on the base, the orthogonal projection of the auxiliary power supply pattern 60 on the base By configuring it so that it is covered by the orthogonal projection on the top, the potential of the N1 node is stable. In addition, the second electrode of the second transistor and the power signal line pattern 90 1 effectively reduces the layout space that needs to be occupied by the pixel structure. The image is preferably scaled down and takes advantage of the development of high resolution display panels.

[0139] As shown in FIG. 15 and FIG. 21, in some embodiments, the auxiliary power supply pattern 6 0 represents the first auxiliary sub-pattern 601 and the second auxiliary sub-pattern 602 that are connected to each other. the first auxiliary sub-pattern 601 extends along a second direction; and the second auxiliary sub-pattern At least a portion of the pattern 602 extends along the first direction. The orthogonal projection of the turn 601 on the base is the orthogonal projection of the first electrode portion 51 on the base. It covers the shadow and the orthogonal projection of the second electrode portion 52 on the base.

[0140] Specifically, the specific structure of the auxiliary power supply pattern 60 may be various. The auxiliary power supply pattern 60 includes a first auxiliary sub-pattern 601 and a second auxiliary sub-pattern 602 which are coupled to each other. pattern 602, the first auxiliary sub-pattern 601 and the second auxiliary sub-pattern 602 may be formed as a unitary structure.

[0141] For example, the first auxiliary sub-pattern 601 extends along a second direction, and the second auxiliary At least a part of the auxiliary sub-pattern 602 extends along the first direction. The auxiliary power supply pattern 60 is formed in a substantially L-shape.

[0142] Since the auxiliary power supply pattern 60 is coupled to the power supply signal line pattern 901, The auxiliary power supply pattern 60 needs to have a stable potential. The orthogonal projection of one auxiliary sub-pattern 601 on the base corresponds to the base of the first electrode portion 51. The orthogonal projection of the second electrode portion 52 on the base and the orthogonal projection of the second electrode portion 52 on the base are formed so as to cover the orthogonal projection of the second electrode portion 52 on the base. This not only ensures the stability of the potential of the N1 node, but also 9, the second pole of the power supply signal line pattern 901 and the auxiliary power supply pattern 60. This effectively reduces the layout space that needs to be allocated, resulting in a favorable reduction in the pixel structure. This is advantageous due to the development of high resolution display panels.

[0143] In some embodiments, the first auxiliary sub-pattern 601 along the first direction The width of each of the power supply signal line patterns 901 is larger than the width of the corresponding power supply signal line pattern 901 .

[0144] As described above, the width of the first auxiliary sub-pattern 601 is equal to the width of the corresponding power signal line pattern. By configuring the auxiliary power supply pattern 60 to be larger than the width of the turn 901, Since the power supply signal line pattern 901 has a larger area, the IR dro p, and the auxiliary power supply pattern 60 and the power supply signal line pattern 901.

[0145] As shown in FIG. 15, FIG. 19 and FIG. 22, in some embodiments, the first electrode portion The orthogonal projection of the first electrode portion 51 on the base and the orthogonal projection of the second electrode portion 52 on the base are both are also covered by the orthogonal projection of the corresponding power supply signal line pattern 901 onto the base.

[0146] As described above, the orthogonal projection of the first electrode portion 51 on the base and the second electrode portion 5 The orthogonal projections of the two patterns on the base are the same as the base of the corresponding power supply signal line pattern 901. By configuring the N1 node so that it is covered by the orthogonal projection on the base, the potential of the N1 node is stabilized. In addition, the second pole of the second transistor and the power signal line pattern 90 1 effectively reduces the layout space that needs to be occupied by the pixel structure. The image is preferably scaled down and takes advantage of the development of high resolution display panels.

[0147] In some embodiments, the functional film layer includes a gate line pattern located in each sub-pixel area. A pattern 902 and a light emission control signal line pattern 903 are included in the same sub-pixel area. , along the second direction, the gate line pattern 902 and the light emitting control signal line pattern 903 The reset signal line pattern 905 and the initialization signal line pattern 904 are arranged in sequence. The functional film layer includes a power supply signal line pattern 901 and a device pattern 902 located in each sub-pixel area. The power supply signal line pattern 901 and the data line pattern 908 are connected to each other. Each of the segments 908 includes a portion that extends along the second direction.

[0148] The display panel includes light emitting elements each corresponding to one of the sub-pixel areas, and Each of the sub-pixel areas has a driving transistor, a first transistor, and a a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a subpixel drive circuit including a seventh transistor.

[0149] In the same subpixel area, the gate of the driving transistor is connected to the first transistor. a first electrode of the drive transistor coupled to a second electrode of the fifth transistor; a second pole of the drive transistor coupled to a first pole of the first transistor; a gate of the first transistor is coupled to the gate line pattern 902; The gate of the second transistor is adjacent to a previous sub-pixel area in the second direction. 905, and the first electrode of the second transistor is used as the target coupling portion in the front sub-pixel area, a second pole of the capacitor coupled to the gate of the drive transistor; The gate of the fourth transistor is coupled to the gate line pattern 902. A first electrode of the transistor is coupled to the data line pattern 908, and the fourth transistor a second pole of the capacitor coupled to the first pole of the drive transistor; The gate of the fifth transistor is coupled to the light emitting control signal line pattern 903. a first electrode of the fifth transistor is coupled to the power signal line pattern 901; The gate of the sixth transistor is coupled to the light emitting control signal line pattern 903. A first electrode of the sixth transistor is coupled to a second electrode of the drive transistor, a second electrode of the transistor is coupled to the corresponding light emitting element; A second electrode of the seventh transistor is coupled to the light emitting element, The gate is coupled to the reset signal line pattern 905, and the first The pole is coupled to a second initialization signal line pattern 904 .

[0150] Exemplarily, each of the sub-pixel driving circuits includes seven thin film transistors and one Each transistor included in the subpixel driving circuit is a P-type transistor. The driving transistor is the third transistor. The first pole of each transistor serves as a source and the second pole of each transistor serves as a drain.

[0151] As shown in FIGS. 6, 15, 19 to 22, the first transistor T1 is a double-gate The gate 201g of the first transistor T1 is coupled to the gate line pattern 902. The source S1 of the first transistor T1 is connected to the source S2 of the third transistor T3 (i.e., the driving transistor The drain D1 of the first transistor T1 is coupled to the drain D3 of the third transistor T2. The input terminal 203c is coupled to the gate 203g of transistor T3.

[0152] The second transistor T2 has a double-gate structure. 02g is a diagram showing the reset signal line pattern in a previous sub-pixel area adjacent in the second direction. The source S2 of the second transistor T2 is coupled to the turn 905′. used as the target coupling portion in the rear and the initialization signal in the front sub-pixel area The drain D2 of the second transistor T2 is coupled to the line pattern 904'. The gate 203g of the first input terminal T1 is coupled to the gate 203g of the second input terminal T2

[0153] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902; The source S4 of the fourth transistor T4 is coupled to the data line pattern 908. The drain D4 of the transistor T4 is coupled to the source S3 of the third transistor T3.

[0154] The gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903. The source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901. The drain D5 of the transistor T5 is coupled to the source S3 of the third transistor T3.

[0155] The gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903. The source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3. The drain D6 of the sixth transistor T6 is coupled to the anode of the corresponding light-emitting element EL. can be.

[0156] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905. The drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL. The source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904. can be.

[0157] The pixel driving circuit further includes a storage capacitance Cst, and a first electrode Cs of the storage capacitance Cst t1 is also used as the gate 203g of the third transistor T3 and is the second The electrode plate Cst2 is coupled to the power supply signal line pattern 901 .

[0158] In the subpixel driving circuit according to the above embodiment, the process of opening holes is not affected by process variations. Due to this, the via hole is misaligned and opened onto the nearby reset signal line pattern 905, This not only avoids the problem of signal distortion, but also improves the yield of the display panel. In addition, the size of the pixel structure using the subpixel driving circuit can be reduced. This is advantageous in achieving high resolution for the display panel.

[0159] An embodiment of the present disclosure further provides a display device, including a display panel according to the above embodiment. .

[0160] In the display panel according to the above disclosed embodiment, the initialization signal line pattern 904 is The first protruding portion 9042 is formed on the side opposite to the signal line pattern 905. At the same time, a first end 9091 of the conductive connection pattern 909 is projected on the base. and the orthogonal projection of the first protruding portion 9042 on the base, there is a first overlap region. region F1, and the first end 9091 and the first protruding portion 9042 are Since the bonding is possible by drilling holes in the wrap area F1, this configuration According to the method, a conductive connection portion and an initialization signal line pattern 904 are connected to each other. A large distance is provided between the via hole and the reset signal line pattern 905. As a result, during the hole drilling process, the via hole may shift due to process variations, resulting in the adjacent via hole being damaged. There is a problem that the reset signal line pattern 905 is easily opened, which leads to signal disturbance. This can avoid the above-mentioned problems, and the yield of the display panel can be further ensured.

[0161] In addition, the initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The first protruding portion 9042 is disposed on the opposite side of the conductive connection portion and the initialization signal line pattern 904. A via hole for coupling to the first protruding portion 9042 is formed in the first protruding portion 9042. Therefore, the orthogonal projection of the via hole on the base is the same as the initialization signal line pattern 90. 4 on the base, so that the initialization The reliability of the connection between the signal line pattern 904 and the conductive connection pattern 909 is suitably improved. As a result, the stability of the display panel during operation is more preferably ensured.

[0162] Therefore, when the display device according to the embodiment of the present disclosure includes the above-mentioned display panel, This has the following beneficial effects, which will not be repeated here.

[0163] It should be noted that the display device may be a television, a display, a digital photo frame, etc. Any products or parts with a display function, such as mobile phones and tablet PCs, .

[0164] The embodiment of the present disclosure provides a method for manufacturing a display panel according to the above embodiment. The present invention further provides a method for producing a semiconductor device, the method comprising the steps of: A functional film layer is fabricated on a base to form a plurality of sub-pixel areas arranged in an array. Including, the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer is a reset signal line pattern provided in each of the sub-pixel areas. 905, the reset signal line pattern 905 extending along a first direction; The initialization signal line layer includes an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, the initialization signal line pattern 904 includes a first body portion 9041 coupled to each other. and a first protruding portion 9042, and the first body portion 9041 is Extending over the same subpixel area, the positive electrode 902 extends over the base of the first body portion 9041. The projection is a normal projection of the first protruding portion 9042 on the base and a projection of the reset signal line pas and an orthogonal projection of the turn 905 on said base, The conductive connection layer includes a conductive connection pattern 909 provided in each of the sub-pixel areas. In the same sub-pixel area, the first end 9091 of the conductive connection pattern 909 and the orthogonal projection of the first protruding portion 9042 on the base. In the first overlap region F1, The first end 9091 is coupled to the first protruding portion 9042, and the conductive connection pattern A second end 9092 of 909 couples to a target coupling portion within the subpixel area in which it is located. The orthogonal projection of the reset signal line pattern 905 on the base is Orthogonal projection of the coupling portion on the base and the initialization signal line pattern 904 on the base It is located between the orthogonal projection of.

[0165] Specifically, the sub-pixel areas arranged in an array are sequentially arranged along the second direction. A plurality of rows of sub-pixel areas arranged in a row, and a plurality of columns of sub-pixel areas arranged sequentially along a first direction. The sub-pixel areas of each row may be spaced apart along a first direction. Each of the sub-pixel areas in each column is aligned in the second direction. The pixel area includes a plurality of sub-pixel areas spaced apart from each other along the first direction and the second direction. The first direction includes an X direction, and the second direction includes a Y direction. Includes direction.

[0166] The reset signal line layer is a reset signal line pattern provided in each of the sub-pixel areas. 905, the reset signal line pattern 905 extending along the first direction. The reset signal line pattern 905 corresponds to the sub-pixel area one-to-one. The dot signal line pattern 905 is located in the corresponding sub-pixel area and is located in the same row. The reset signal line patterns 905 corresponding to the sub-pixel areas are electrically connected in sequence. and formed as a unitary structure.

[0167] The initialization signal line layer includes an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, the initialization signal line pattern 904 corresponds to the sub-pixel area in one-to-one correspondence; The initialization signal line patterns 904 are located in the corresponding sub-pixel areas and are located in the same row. The initialization signal line patterns 904 corresponding to the sub-pixel areas to be placed are sequentially electrically are connected and formed as a unitary structure.

[0168] Each of the initialization signal line patterns 904 is connected to the first body portion 90 41 and a first protruding portion 9042, and the first body portion 9041 extends in the first direction. The initialization signal line patterns 9 extend along the same row and correspond to the sub-pixel areas. The first body portion 9041 in FIG. 04 is electrically connected to one another and formed as a unitary structure. It should be noted that, in consideration of the tolerance of the manufacturing process, the first body portion is necessarily It is not necessarily a straight line extending along the first direction.

[0169] The specific shape of the first protruding portion 9042 may be varied. The first protruding portion 9042 protrudes from the first body portion 9041 to which it is connected. In the same subpixel area, the first body portion 9041 The orthogonal projection on the base is a projection of the first protruding portion 9042 on the base. The reset signal line pattern 905 is positioned between the reset signal line pattern 905 and the orthogonal projection on the base. In this way, the first protruding portion 9042 is opposite to the reset signal line pattern 905. Therefore, the first protruding portion 9042 and the reset recess 9044 can be provided so as to be in contact with each other. A large distance can be provided between the signal line pattern 905 and the ground signal line pattern 906.

[0170] It should be noted that in one initialization signal line pattern 904, the first body portion 9 041 and the first protruding portion 9042 may be formed as a unitary structure, but is not limited thereto. It won't be done.

[0171] The conductive connection layer includes a conductive connection pattern 909 provided in each of the sub-pixel areas. The conductive connection pattern 909 corresponds to the sub-pixel area in one-to-one correspondence, and the conductive An electrical contact pattern 909 is located in the corresponding sub-pixel area.

[0172] an orthogonal projection of a first end 9091 of the conductive connection pattern 909 onto the base; The orthogonal projection of the first protruding portion 9042 on the base has a first overlap region F1. The first end 9091 and the first protruding portion 9042 are overlapped by the first overlapping portion 9091. The second end of the conductive connection pattern 909 can be connected by drilling a hole in the region F1. 9092 is coupled to the target coupling portion in the subpixel area in which it is located, and the target The dot junction is connected to the first pole of the seventh transistor corresponding to the current subpixel area, and the current A second transistor corresponding to a next sub-pixel area adjacent to the sub-pixel area along the second direction. The first pole of the transistor may be included.

[0173] The target coupling portion may be disposed at various positions, for example, in the same sub-pixel area. The orthogonal projection of the reset signal line pattern 905 on the base is The orthogonal projection of the joint on the base and the initialization signal line pattern 904 on the base It may be provided so as to be located between the orthogonal projection.

[0174] It should be noted that the display panel has an interlayer medium layer (i.e., the above-mentioned second interlayer insulating layer I The interlayer medium layer is formed between the second gate metal layer and the first source metal layer in the display panel. The initialization signal line pattern 904 is disposed between the second gate electrode and the drain metal layer. It can be placed on the same layer as the metal layer and can be formed in the same patterning process. The conductive connection pattern 909 may be formed in the same layer as the first source-drain metal layer. As described above, the present invention can be formed by the same patterning process. A hole is drilled in the first overlap region F1 to expose the first end 9 By realizing the coupling between the first protruding portion 9042 and the first protruding portion 9041, the via hole is , a via hole penetrating the ILD layer, and the position of the via hole is The distance between the patterns 905 becomes greater.

[0175] In the display panel manufactured using the manufacturing method according to the embodiment of the present disclosure, the initialization signal line The pattern 904 has a first protruding portion 9 on the side opposite to the reset signal line pattern 905. 042, and the first end 909 of the conductive connection pattern 909 1 on the base, and the orthogonal projection of the first protruding portion 9042 on the base. has a first overlap region F1, and the first end 9091 and the first protruding portion 9 042 can be connected by drilling a hole in the first overlap region F1. According to this configuration, the conductive connection portion and the initialization signal line pattern 90 4 and the reset signal line pattern 905. The distance reduces the risk of via holes being formed due to process variations during the hole drilling process. The hole is opened on the nearby reset signal line pattern 905 due to misalignment, which easily leads to signal disturbance. This avoids the problem of the display panel becoming thinner, and the yield of the display panel is more favorably guaranteed.

[0176] In addition, the initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The first protruding portion 9042 is disposed on the opposite side of the conductive connection portion and the initialization signal line pattern 904. A via hole for coupling to the first protruding portion 9042 is formed in the first protruding portion 9042. Therefore, the orthogonal projection of the via hole on the base is the same as the initialization signal line pattern 90. 4 on the base, so that the initialization The reliability of the connection between the signal line pattern 904 and the conductive connection pattern 909 is suitably improved. As a result, the stability of the display panel during operation is more preferably ensured.

[0177] It should be noted that each embodiment in this specification is described in a progressive manner. The same or similar parts of each embodiment can be referred to each other, and each embodiment can be used in conjunction with other embodiments. The explanation focuses on the differences between the two. In particular, the method examples are basically the same as those of the manufacturing method. Although the embodiments are briefly described because of their similarity to the embodiments of the present invention, the relevant portions are Please refer to the explanation section.

[0178] Unless otherwise defined, technical or scientific terms used in this disclosure are understood by those of ordinary skill in the art. As used in this disclosure, "first," "second," and similar terms have their ordinary meanings. They are not intended to imply any order, quantity or importance, but are intended to distinguish between different components. Similar terms such as "comprises" or "includes" refer to the elements described before the term. or components include those elements or components listed after the term and their equivalents, but not including other elements "Connect," "couple," "join," or "connect" or similar terms are used without excluding any of the following: The term is not limited to physical or mechanical connections, but may refer to either direct or indirect connections. "Top", "bottom", "left", "right" etc. are relative positions. If the absolute position of the object to be explained changes, the relative positional relationship also changes accordingly. There is a possibility that it will become

[0179] It will be understood that an element, such as a layer, film, region, or substrate, may be "on" or "under" another element. When an element is referred to as being located "directly" on or "below" another element, that element is not intended to be located "directly" on or "below" another element. Alternatively, an intermediate element may be interposed.

[0180] In the description of the above embodiments, specific features, structures, materials, or characteristics may be used singly or in combination. In several embodiments or examples, they may be combined in any suitable manner.

[0181] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto. Those skilled in the art will readily appreciate that modifications and substitutions may be made within the technical scope of the present disclosure. However, all of these modifications and replacements should be considered within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be according to the appended claims.

Claims

1. A display panel, comprising: a base; and a functional film layer provided on the base, the functional film layer being arranged in an array. The pixel array further includes a plurality of sub-pixel areas arranged in a the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer has a reset signal line pattern provided in each of the sub-pixel areas. the reset signal line pattern extends along a first direction; The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas. The initialization signal line pattern includes a first body portion and a first protruding portion coupled to each other. The first body portion extends along the first direction and has a front surface in the same sub-pixel area. The orthogonal projection of the first main body portion on the base is a orthogonal projection of the first protruding portion on the base. between a shadow and an orthogonal projection of the reset signal line pattern on the base, The conductive connection layer includes a conductive connection pattern provided in each of the sub-pixel areas, In the same sub-pixel area, the first end of the conductive connection pattern has a positive projection on the base. The shadow and the orthogonal projection of the first protruding portion on the base have a first overlap region. and in the first overlap region, the first end is joined to the first protruding portion. The second end of the conductive connection pattern is a target within the sub-pixel area in which the second end is located. The reset signal line pattern is coupled to a coupling portion, and the orthogonal projection of the reset signal line pattern on the base is A get coupling portion is orthogonally projected on the base, and an initialization signal line pattern is projected on the base. The display panel is located between the orthogonal projection of the image and the

2. The display panel includes: The functional film layer has a plurality of sub-pixel areas, and the functional film layer has a base opposite to the base. A plurality of light emitting elements are disposed on the side of the A plurality of sub-pixel driving circuits each corresponding to the plurality of sub-pixel areas, Each of the sub-pixel driving circuits includes a seventh transistor, and a gate of the seventh transistor is coupled to the corresponding reset signal line pattern, and the first pole of the seventh transistor is a second pole of the seventh transistor is connected to the second electrode of the seventh transistor in the second direction. a plurality of sub-pixel drive electrodes extending along the substrate and coupled to the anodes of corresponding light-emitting elements; and a circuit, The conductive connection pattern includes a second body portion connected between the first end and the second end. the second body portion further includes a second body portion extending along a second direction and In the first direction, a first end of the conductive connection pattern is connected to the seventh transistor.

2. The method of claim 1, wherein the second body portion projects from the second body portion in a direction away from the second pole of the rotor. The display panel described.

3. The functional film layer further includes a data line pattern located in each sub-pixel area, and the data The line pattern includes a portion extending along the second direction, The orthogonal projection of the initialization signal line pattern on the base and the conductive connection portion pattern There is a third overlap area with the orthogonal projection on the base, The orthogonal projection of the initialization signal line pattern onto the base and the orthogonal projection of the data line pattern onto the base are performed. There is a fourth overlap area between the orthogonal projection on the base, The initialization signal line pattern in the fourth overlap region along the second direction The width of the initialization signal line pattern in the third overlap region in the second direction is The display panel of claim 2 , wherein the width is smaller than the longitudinal width.

4. In the same subpixel area, an orthogonal projection of the second body portion on the base and an orthogonal projection of the seventh body portion on the base are formed. A first gap is provided between the second pole of the transistor and the orthogonal projection of the second pole on the base. The display panel of claim 2 , wherein the gap is greater than a threshold value.

5. The display panel includes: The sub-pixel areas are arranged in a one-to-one correspondence with each other, and each of the sub-pixel areas includes a driving transistor and a second transistor. a plurality of subpixel drive circuits each including a transistor; The gate of the second transistor is disposed in a previous sub-pixel area adjacent to the first sub-pixel area along the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern of the The second transistor is used as the target coupling portion in the subpixel area. a pole coupled to the gate of the drive transistor; The second transistor includes two semiconductor portions spaced apart from each other along the first direction; and a first conductor portion connected to the two semiconductor portions, respectively, The orthogonal projection of the first protruding portion in the front sub-pixel area on the base 13. The display panel of claim 1, wherein the display panel has a projection that does not overlap with an orthogonal projection on the display.

6. The orthogonal projection of the first conductor portion on the base corresponds to the conductive contact in the front sub-pixel area.

6. The method of claim 5, wherein the projection of the first end of the extension pattern overlaps the orthogonal projection of the first end of the extension pattern onto the base. Display panel on board.

7. Each of the initialization signal line patterns further includes a second protruding portion coupled to the first body portion. and in the same subpixel area, the orthogonal projection of the second protruding portion on the base is a projection of the first body portion onto the base; and a projection of the reset signal line pattern onto the base. and an orthogonal projection of the first conductor portion on the base is located between the second conductor portion and the orthogonal projection of the first conductor portion on the base. The display panel according to claim 5 , wherein the projection overlaps with an orthogonal projection of the projection on the base. 。

8. The conductive connection pattern includes a second body portion connected between the first end and the second end. the second body portion extending along a second direction; An end of the first conductor portion close to the conductive connection pattern in the previous sub-pixel area extends along the second direction, and the orthogonal projection of the end on the base and the conductive connection portion There is a second gap between the second body portion of the pattern and the orthogonal projection on the base, The display panel of claim 5 , wherein the two gaps are greater than a threshold value.

9. In the same subpixel area, the positive electrode of the first end of the conductive connection pattern on the base and a first main body portion of the initialization signal line pattern is orthogonally projected onto the base. Two overlapping regions are formed, The functional film layer further includes a first connection hole located in each of the sub-pixel areas, In the area, the orthogonal projection of the first connection hole on the base is the first overlap region and the second overlap region, and the conductive connection pattern a first end of the first line is coupled to the initialization signal line pattern through the first connection hole; The display panel according to claim 5.

10. The orthogonal projection of the first conductor portion of the second transistor onto the base is the orthogonal projection of the first contact hole in the element area on the base does not overlap the orthogonal projection of the first contact hole in the element area on the base.

10. The display panel according to claim 9.

11. The functional film layer further includes a power supply signal line layer, and the power supply signal line layer is disposed in each of the sub-pixel areas. At least a portion of the power supply signal line pattern is extending along a second direction; The first conductor portion is far from the conductive connection pattern in the previous sub-pixel area. The edges extend along the second direction, and orthogonal projections of the edges on the base correspond to the same sub-pixel. The power supply signal line pattern located in the area is completely covered by the orthogonal projection on the base. The display panel according to claim 5 .

12. The display panel includes: A plurality of sub-pixel driving circuits each corresponding to the plurality of sub-pixel areas, Each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor, and the storage capacitor is The driving transistor includes a first electrode plate and a second electrode plate disposed opposite to each other, and the first electrode plate is and the second electrode plate is disposed on the opposite side of the first substrate from the base. and a plurality of subpixel drive circuits located at The functional film layer further includes a power supply signal line layer, and the power supply signal line layer is disposed in each of the sub-pixel areas. At least a portion of the power supply signal line pattern is The power supply signal line pattern extends along a second direction, and includes a first power supply portion and a second power supply portion. 、 The orthogonal projection of the first power supply unit on the base is The signal line pattern is orthogonally projected onto the base and overlaps the signal line pattern of the same sub-substrate. The orthogonal projection and overlap of each of the gate line patterns located in the pixel area on the base. The orthogonal projection of the second power supply part on the base corresponds to the second plate of the storage capacitor. The first power supply portion is arranged to overlap with the orthogonal projection on the base along the first direction. The display panel according to claim 1 , wherein the width is smaller than the width of the second power supply portion.

13. The functional film layer further includes a power supply signal line layer, and the power supply signal line layer is disposed in each of the sub-pixel areas. At least a portion of the power supply signal line pattern is extending along a second direction; The functional film layer further includes an auxiliary power supply layer, and the auxiliary power supply layer is provided in each of the sub-pixel areas. an auxiliary power supply pattern attached to the base, the auxiliary power supply pattern being orthogonally projected onto the base; The orthogonal projection of the power supply signal line pattern located in the same sub-pixel area on the base is The auxiliary power supply pattern and the power supply signal line pattern are connected to each other.

10. The display panel of claim 1, wherein the display panel is joined at a flap area.

14. The display panel corresponds to the plurality of sub-pixel areas in a one-to-one manner, and each of the sub-pixel areas has a driving transistor. a plurality of subpixel drive circuits including a first transistor and a second transistor; The gate of the second transistor is disposed in a previous sub-pixel area adjacent to the first sub-pixel area along the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern of the The second transistor is used as the target coupling portion in the subpixel area. The pole includes a first electrode portion and a second electrode portion coupled to each other, the first electrode portion being oriented in a second direction. the second electrode portion extends along a third direction, and the third direction is The first electrode portion intersects with the semiconductor device of the second transistor in both the one direction and the second direction. The second electrode portion is located between the conductor portion and the second electrode portion of the driving transistor. coupled to the gate, An orthogonal projection of the first electrode portion on the base and an orthogonal projection of the second electrode portion on the base are each covered by an orthogonal projection of the corresponding auxiliary power supply pattern on the base. The display panel according to claim 13.

15. The auxiliary power pattern includes a first auxiliary sub-pattern and a second auxiliary sub-pattern that are coupled to each other. the first auxiliary sub-pattern extends along a second direction, and the second auxiliary sub-pattern At least a portion of the pattern extends along the first direction; The orthogonal projection of the first auxiliary sub-pattern on the base is 15. The table of claim 14, wherein the orthogonal projection of the second electrode portion on the base and the orthogonal projection of the second electrode portion on the base are covered by the orthogonal projection of the second electrode portion on the base. Display panel.

16. Along the first direction, the width of the first auxiliary sub-pattern is The display panel of claim 15, wherein the width of the first and second lines is greater than the width of the second lines.

17. An orthogonal projection of the first electrode portion on the base and an orthogonal projection of the second electrode portion on the base are covered by the orthogonal projection of the corresponding power supply signal line pattern on the base. The display panel according to claim 14.

18. The functional film layer includes a gate line pattern and a light emission control signal line pattern located in each sub-pixel area. In the same sub-pixel area, the gate line pattern is arranged along a second direction. The light emission control signal line pattern, the reset signal line pattern and the initialization signal line pattern The lines are arranged in sequence, The functional film layer includes a power supply signal line pattern and a data line pattern located in each sub-pixel area. The power signal line pattern and the data line pattern are arranged in the second direction. and a portion extending along The display panel includes: a light-emitting element that corresponds one-to-one with the plurality of sub-pixel areas; The sub-pixel areas are arranged in a one-to-one correspondence with each other, and each of the sub-pixel areas includes a driving transistor, a first transistor, Transistor, second transistor, fourth transistor, fifth transistor, sixth transistor a subpixel drive circuit including a seventh transistor and a second transistor, In the same subpixel area, the gate of the driving transistor is connected to the first transistor and the first electrode of the drive transistor is coupled to the second electrode of the fifth transistor. and a second electrode of the drive transistor is coupled to a first electrode of the first transistor. R, a gate of the first transistor is coupled to the gate line pattern; The gate of the second transistor is disposed in a previous sub-pixel area adjacent to the first sub-pixel area along the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern of the The second transistor is used as the target coupling portion in the subpixel area. a pole coupled to the gate of the drive transistor; The gate of the fourth transistor is coupled to the gate line pattern. a first pole of the fourth transistor coupled to the data line pattern; and a second pole of the fourth transistor coupled to the data line pattern. coupled to a first pole of the drive transistor; The gate of the fifth transistor is coupled to the light emission control signal line pattern. a first electrode of the transistor is coupled to the power supply signal line pattern; The gate of the sixth transistor is coupled to the light emission control signal line pattern. a first electrode of the sixth transistor coupled to a second electrode of the driving transistor; a second pole of the capacitor is coupled to the corresponding light emitting element; The second electrode of the seventh transistor is coupled to the light emitting element, and the gate of the seventh transistor a first electrode of the seventh transistor coupled to the reset signal line pattern; 10. The display panel of claim 1, coupled to two initialization signal line patterns.

19. A display device comprising the display panel according to any one of claims 1 to 18.

20. A method for manufacturing a display panel, comprising the steps of: A functional film layer is fabricated on a base to form a plurality of sub-pixel areas arranged in an array. and the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer has a reset signal line pattern provided in each of the sub-pixel areas. the reset signal line pattern extends along a first direction; The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas. The initialization signal line pattern includes a first body portion and a first protruding portion coupled to each other. The first body portion extends along the first direction and has a front surface in the same sub-pixel area. The orthogonal projection of the first main body portion on the base is a orthogonal projection of the first protruding portion on the base. between a shadow and an orthogonal projection of the reset signal line pattern on the base, The conductive connection layer includes a conductive connection pattern provided in each of the sub-pixel areas, In the same sub-pixel area, the first end of the conductive connection pattern has a positive projection on the base. The shadow and the orthogonal projection of the first protruding portion on the base have a first overlap region. and in the first overlap region, the first end is joined to the first protruding portion. The second end of the conductive connection pattern is a target within the sub-pixel area in which the second end is located. The reset signal line pattern is coupled to a coupling portion, and the orthogonal projection of the reset signal line pattern on the base is A get coupling portion is orthogonally projected on the base, and an initialization signal line pattern is projected on the base. A method for manufacturing a display panel located between the orthogonal projection of the screen.

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