Self-light-emitting type display device and driving method for self-light-emitting type display device

Abstract

To provide a self-light-emitting type display device capable of in-plane homogenization, and a driving method for a self-light-emitting type display device.SOLUTION: A self-light-emitting type display device includes a substrate including a display region, a first pixel disposed in a first region at an outer edge of the display region, and a second pixel disposed in a second region surrounded by the first region. Each of the first pixel and the second pixel includes a first transistor, a second transistor, a first capacitor element, a third transistor, and a seventh transistor. The capacitance of a capacitor part connected to a gate electrode of the second transistor in the first pixel and the capacitance of a capacitor part connected to a gate electrode of the second transistor in the second pixel are different.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a self-emitting display device and a method for driving the self-emitting display device.

Background Art

[0002] In recent years, self-emitting display devices have been mounted on televisions, smartphones, digital signage (electronic billboards, electronic advertising boards, etc.) and the like, and have become widespread. A self-emitting display device includes, for example, a plurality of pixels and a driver for driving the plurality of pixels. Each of the plurality of pixels includes, for example, a plurality of transistors, a capacitive element, and a light-emitting element. The light-emitting element is, for example, a light-emitting diode (LED), a micro light-emitting diode (micro LED), or an organic electroluminescence (EL) element. In a self-emitting display device, a driver supplies a voltage to each of the plurality of pixels, and a current corresponding to the supplied voltage value flows through the light-emitting elements included in each of the plurality of pixels. Each of the light-emitting elements emits light with a luminance corresponding to the current flowing through the light-emitting element, and a pixel including the light-emitting element can display an image with a gradation corresponding to the luminance. On the other hand, the requirement for in-plane uniformity of the self-emitting display device is increasing.

[0003] For example, Patent Document 1 discloses a pixel including six transistors, one capacitive element, and one light-emitting element, and a self-emitting display device including the pixel.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the self-luminous display device described in Patent Document 1, for example, a phenomenon has been confirmed in which the outermost periphery of the display region emits light more brightly than others at low luminance.

[0006] In view of such problems, one object of an embodiment of the present invention is to provide a self-luminous display device capable of in-plane uniformity of a light-emitting element (self-luminous display device) and a driving method of the self-luminous display device.

Means for Solving the Problems

[0007] A self-luminous display device according to an embodiment of the present invention includes a substrate having a display region, a first pixel disposed in a first region at an outer edge of the display region, and a second pixel disposed in a second region surrounded by the first region. Each of the first pixel and the second pixel is controlled using a second control signal obtained by shifting a first control signal, and includes a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, and a first capacitor electrically connected to a gate electrode of the second transistor. The second transistor is controlled to supply a threshold voltage of the second transistor to the gate electrode of the second transistor and the first capacitor using the first control signal obtained by shifting a third control signal. A third transistor is electrically connected between the second node and the gate electrode of the second transistor, and is controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitor using the third control signal. The self-luminous display device further includes a seventh transistor electrically connected to the second node. The capacitance of a capacitive portion connected to the gate electrode of the second transistor of the first pixel is different from the capacitance of a capacitive portion connected to the gate electrode of the second transistor of the second pixel.

[0008] The self-luminous display device according to an embodiment of the present invention includes a substrate having a display area, a third pixel disposed in a third area including one end of the display area, and a fourth pixel disposed in a fourth area adjacent to the third area. Each of the third pixel and the fourth pixel is controlled using a second control signal obtained by shifting a first control signal, and includes a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a first capacitor electrically connected to a gate electrode of the second transistor, and a third transistor electrically connected between the second node and the gate electrode of the second transistor. The third transistor is controlled to supply a threshold voltage of the second transistor to the gate electrode of the second transistor and the first capacitor using the first control signal obtained by shifting a third control signal. The third transistor is also controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitor using the third control signal, and includes a seventh transistor electrically connected to the second node. The capacitance of the capacitive portion connected to the image data signal line connected to the third pixel is different from the capacitance of the capacitive portion connected to the image data signal line connected to the fourth pixel.

[0009] A driving method of a self-luminous display device according to an embodiment of the present invention includes a substrate having a display area, a sixth pixel disposed in a sixth area including one end of the display area, and a seventh pixel disposed in a seventh area adjacent to the sixth area. Each of the sixth pixel and the seventh pixel is controlled using at least a second control signal obtained by shifting a first control signal, and includes a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a first capacitive element electrically connected to a gate electrode of the second transistor, and is controlled to supply a threshold voltage of the second transistor to the gate electrode of the second transistor and the first capacitive element using the first control signal obtained by shifting a third control signal, a third transistor electrically connected between the second node and the gate electrode of the second transistor, and is controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitive element using the third control signal, and a seventh transistor electrically connected to the second node. In the driving method of the self-luminous display device, a time during which the first control signal and the second control signal supplied to the sixth pixel overlap is longer than a time during which the second control signal supplied to the seventh pixel and a fifth control signal obtained by shifting the second control signal overlap.

[0010] A driving method of a self-emitting display device according to an embodiment of the present invention includes a substrate having a display area, a sixth pixel disposed in a sixth area including one end of the display area, and a seventh pixel disposed in a seventh area adjacent to the sixth area. Each of the sixth pixel and the seventh pixel is controlled using at least a second control signal obtained by shifting a first control signal, and includes a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a first capacitive element electrically connected to a gate electrode of the second transistor, and a third transistor electrically connected between the second node and the gate electrode of the second transistor. Using the first control signal obtained by shifting a third control signal, it is controlled to supply a threshold voltage of the second transistor to the gate electrode of the second transistor and the first capacitive element. A third transistor electrically connected between the second node and the gate electrode of the second transistor, and using the third control signal, it is controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitive element. A driving method of a self-emitting display device including a seventh transistor electrically connected to the second node, wherein a voltage supplied during a time when the first control signal and the second control signal supplied to the sixth pixel overlap is greater than a voltage supplied during a time when the second control signal supplied to the seventh pixel and a fifth control signal obtained by shifting the second control signal overlap.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in many different modes and is not construed as being limited to the description of the embodiments exemplified below. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, configuration, etc. of each part compared to the actual mode, but this is merely an example and does not limit the interpretation of the present invention. Note that the letters “first” and “second” appended to each element are for convenience of distinguishing each element and have no further meaning unless otherwise specified.

[0013] In addition, in this specification, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0014] As an example, the self-luminous display device according to an embodiment of the present invention is a light-emitting device using an EL element as a light-emitting element.

[0015] <1. First Embodiment> <1-1. Outline of the Self-Luminous Display Device 10> With reference to FIGS. 1 and 2, the outline of the self-luminous display device 10 according to the first embodiment will be described. FIGS. 1 and 2 are schematic diagrams showing the configuration of the self-luminous display device 10 according to the first embodiment. The configuration of the self-luminous display device 10 shown in FIGS. 1 and 2 is an example, and the configuration of the self-luminous display device 10 is not limited to the configuration shown in FIGS. 1 and 2.

[0016] As shown in FIG. 1 or FIG. 2, the self-luminous display device 10 includes an array substrate 100, a flexible printed circuit board 160 (FPC 160), and an IC chip 170. In addition, the self-luminous display device 10 includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0017] In the display area 22, a plurality of pixels 180 are arranged in a matrix. The pixel 180 is the minimum unit that constitutes a part of the image to be displayed in the display area 22. Each of the plurality of pixels 180 may correspond to, for example, a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may be formed by three sub-pixels. There is no limitation on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 may be, for example, a stripe arrangement. The arrangement of the self-emitting display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0018] The display area 22 includes an area 22A and an area 22B. The area 22A is arranged on the outer edge of the display area 22 so as to surround the area 22B. The area 22A may include one row and one column of pixels 180A arranged on the outermost periphery of the display area 22, or may include a plurality of rows and a plurality of columns of pixels 180A. Here, when the pixel 180A and the pixel 180B are not distinguished, they are referred to as pixels 180. Although details will be described later, in the present embodiment, the capacity of the pixel 180A and the capacity of the pixel 180B are different. The capacity of the capacitive portion connected to the gate electrode 622 of the second transistor T2 of the pixel 180A is different from the capacity of the capacitive portion connected to the gate electrode 622 of the second transistor T2 of the pixel 180B.

[0019] The sub-pixel R, the sub-pixel G, and the sub-pixel B are configured to display images of different colors. For example, each of the sub-pixel R, the sub-pixel G, and the sub-pixel B may include a light-emitting element including a light-emitting layer that emits the three primary colors of red, green, and blue. An arbitrary voltage or current is supplied to each of the three sub-pixels, and the self-emitting display device 10 can display an image.

[0020] In the peripheral area 24, a source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130 are provided. Each of the source driver circuit 110, the gate driver circuit 120, and the light emission control circuit 130 is connected to the terminal portion 150 using the connection wiring 341. The peripheral area 24 may be called a frame area. The connection wiring 341 may be called the connection wiring 341 alone, or a bundle of a plurality of connection wirings 341 may be called the connection wiring 341.

[0021] In the terminal region 26, a terminal portion 150 and an FPC 160 electrically connected to the terminal portion 150 are provided. The terminal region 26 is a region on the side opposite to the first direction D1 with respect to the region where the display region 22 is provided with respect to the peripheral region 24.

[0022] The FPC 160 is connected to an external device (not shown) outside the self-emitting display device 10. Therefore, the self-emitting display device 10 is connected to the external device via the FPC 160 and the terminal portion 150 connected to the FPC. A control signal and a voltage are transmitted from the external device to the self-emitting display device 10 via the FPC 160 and the terminal portion 150 connected to the FPC. The self-emitting display device 10 drives each pixel 180 provided in the self-emitting display device 10 using the received control signal and voltage from the external device. As a result, the self-emitting display device 10 can display an image in the display region 22.

[0023] The IC chip 170 is provided, for example, on the FPC 160. The IC chip 170 supplies signals, voltages, etc. for driving each pixel 180 to the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the pixel 180 (pixel circuit) via the FPC 160, the terminal portion 150, and the connection wiring 341.

[0024] In the first embodiment, each of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the IC chip 170 may be called a control circuit individually, or a circuit group including a part or all of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the IC chip 170 may be called a control circuit.

[0025] <1-2. Configuration of Source Driver Circuit 110> Referring to FIGS. 1 and 2, the outline of the source driver circuit 110 will be described. As shown in FIG. 1 or FIG. 2, the source driver circuit 110 is provided at a position adjacent to the display area 22 in the first direction D1 (column direction). The image data signal line 321 extends from the source driver circuit 110 in the first direction D1 and is connected to a plurality of pixels 180 arranged in the first direction D1.

[0026] As shown in FIG. 2, the source driver circuit 110 includes, for example, a plurality of selection circuits 112. Each of the plurality of selection circuits 112 is controlled based on, for example, an on signal and an off signal supplied to the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB. The selection circuit 112 is selected by the on signal supplied to the selection signal (for example, the selection signal MUXR), and supplies the image data signal SL(m + 1) including the data signal VDATA supplied to the input terminal 114 to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. Although details will be described later, the data signal VDATA includes, for example, the voltage RDATA(n), the voltage GDATA(n), or the voltage BDATA(n).

[0027] The selection circuit 112 is, for example, a switch 118 including an input terminal 114 and an output terminal 116. For example, the on signal supplied from the IC chip 170 to the selection signal MUXR conducts (connects) the input terminal 114 and the output terminal 116, and the off signal supplied from the IC chip 170 to the selection signal MUXR disconnects (non - connects) the input terminal 114 and the output terminal 116. The on signal is a signal including a voltage that conducts the input terminal 114 and the output terminal 116, and the off signal is a signal including a voltage that disconnects the input terminal 114 and the output terminal 116.

[0028] In the present invention, the on signal may be high (High, HI) and the off signal may be low (Low, LO), or the on signal may be low (Low, LO) and the off signal may be high (High, HI).

[0029] <1 - 3. Configuration of the gate driver circuit 120> Referring to FIGS. 1 and 2, the outline of the gate driver circuit 120 will be described. As shown in FIG. 1 or FIG. 2, the gate driver circuit 120 is provided at a position adjacent to the display area 22 in the second direction D2 (row direction). The scanning signal lines 329, 330, 331, and 332 extend from the gate driver circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0030] As shown in FIG. 2, the gate driver circuit 120 includes a plurality of shift registers (for example, shift registers 121, 122, and 123). The shift registers 121, 122, and 123 sequentially supply scanning signals with different timings (for example, scanning signal G(n - 1), scanning signal G(n), scanning signal G(n + 1)) to each of the scanning signal lines 329, 330, 331, and 332 based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and have a role of driving the pixels 180 (pixel circuits) electrically connected to each scanning signal line. The scanning signal G(n) may be called the first control signal, the scanning signal G(n + 1) may be called the second control signal, and the scanning signal G(n - 1) may be called the third control signal.

[0031] For example, the shift register 121 is electrically connected to the shift register 122, and the shift register 122 is electrically connected to the shift register 123. The shift register 121 is electrically connected to the scanning signal line 329 and supplies, for example, the scanning signal G(n - 1) to the scanning signal line 329. Similarly to the shift register 121, the shift register 122 is electrically connected to the scanning signal line 330 and supplies, for example, the scanning signal G(n) to the scanning signal line 330, and the shift register 123 is electrically connected to the scanning signal line 331 and supplies, for example, the scanning signal G(n + 1) to the scanning signal line 331. Although not shown, the next-stage shift register electrically connected to the shift register 123 is electrically connected to the scanning signal line 332. The scanning signal G(n) includes a pulse width equivalent to that of the scanning signal G(n - 1) and is a signal obtained by shifting the scanning signal G(n - 1). The scanning signal G(n + 1) includes a pulse width equivalent to that of the scanning signal G(n) and is a signal obtained by shifting the scanning signal G(n). Similarly to the scanning signal G(n + 1), the scanning signal G(n + 2) includes a pulse width equivalent to that of the scanning signal G(n + 1) and is a signal obtained by shifting the scanning signal G(n + 1).

[0032] <1-4. Configuration of the light emission control circuit 130> Referring to FIGS. 1 and 2, the outline of the light emission control circuit 130 will be described. As shown in FIG. 1 or FIG. 2, the light emission control circuit 130 is adjacent to the display area 22 in the second direction D2 (row direction) and is provided on the side opposite to the position where the gate driver circuit 120 is arranged with respect to the display area 22. The light emission control signal lines 334, 335, 336, and 337 extend from the light emission control circuit 130 in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits) arranged in the second direction D2.

[0033] As shown in FIG. 2, the light emission control circuit 130 includes a plurality of shift registers (for example, shift registers 131, 132, and 133). The shift registers 131, 132, and 133 supply, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, light emission control signals with different timings (for example, light emission control signal EM(n), light emission control signal EM(n + 1), light emission control signal EM(n + 2), etc.) to each of the light emission control signal lines 334, 335, 336, and 337 in sequence, and have a role of driving the pixel 180 (pixel circuit) electrically connected to each light emission control signal line.

[0034] For example, the shift register 131 is electrically connected to the shift register 132, and the shift register 132 is electrically connected to the shift register 133. The shift register 131 is electrically connected to the light emission control signal line 334 and supplies, for example, the light emission control signal EM(n) to the light emission control signal line 334. Similar to the shift register 131, the shift register 132 is electrically connected to the light emission control signal line 335 and supplies, for example, the light emission control signal EM(n + 1) to the light emission control signal line 335, and the shift register 133 is electrically connected to the light emission control signal line 336 and supplies, for example, the light emission control signal EM(n + 2) to the light emission control signal line 336. Although not shown, the next-stage shift register electrically connected to the shift register 133 is electrically connected to the light emission control signal line 337. The pulse width of the light emission control signal EM(n + 1) is the same as that of the light emission control signal EM(n), and the light emission control signal EM(n + 1) is a signal obtained by shifting the light emission control signal EM(n). Similarly, the pulse width of the light emission control signal EM(n + 2) is the same as that of the first light emission control signal EM(n + 1), and the light emission control signal EM(n + 2) is a signal obtained by shifting the first light emission control signal EM(n + 2). The light emission control signal EM may be called the fourth control signal.

[0035] <1-5. Configuration of Pixel 180> Referring to FIGS. 3 and 4, the outline of pixel 180 will be described. FIG. 3 is a schematic diagram showing input signals to pixel circuit 181 included in pixel 180. FIG. 4 is a circuit diagram showing the configuration of pixel circuit 181. FIGS. 3 and 4 show, as an example, the configuration of pixel circuit 181 of pixel 180 shown in FIGS. 1 and 2. The configurations of pixel 180 and pixel circuit 181 are not limited to the configurations shown in FIGS. 3 and 4. For configurations identical or similar to those in FIGS. 1 and 2, the description here will be omitted.

[0036] Pixel circuit 181 is a circuit for driving pixel 180. The pixel circuits of sub-pixel R, sub-pixel G, and sub-pixel B included in pixel 180 are the same as pixel circuit 181, except that the colors emitted by light-emitting elements OLED are different. In the following description, as an example, the light-emitting element OLED that mainly emits red light will be described.

[0037] As shown in FIG. 3, scanning signal G(n - 1), scanning signal G(n), scanning signal G(n + 1), image data signal SL(m + 1), emission control signal EM(n), reset voltage VSH, and initialization voltage VINI are supplied to pixel circuit 181. Also, as a power source for driving pixel 180, driving voltage VDDEL or driving voltage VDDELL, and reference voltage VSSEL are supplied to pixel circuit 181.

[0038] The reset voltage VSH is supplied to the reset voltage line VC, the initialization voltage VINI is supplied to the initialization voltage line VM, the drive voltages VDDEL and VDDELL are supplied to the drive power supply line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. Each of the reset voltage line VC, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS may be electrically connected to, for example, different connection wirings 341, or may be different connection wirings 341. The reset voltage VSH, the initialization voltage VINI, the drive voltages VDDEL, VDDELL, and the reference voltage VSSEL may be supplied from an external circuit to a plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal portion 150, the reset voltage line VC, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS. Further, the reset voltage VSH, the initialization voltage VINI, the drive voltages VDDEL, VDDELL, and the reference voltage VSSEL may be supplied from the IC chip 170 to a plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal portion 150, the reset voltage line VC, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS. The reset voltage VSH and the initialization voltage VINI are smaller than the drive voltages VDDEL and VDDELL. The drive voltage VDDELL is smaller than the drive voltage VDDEL. The reference voltage VSSEL is smaller than the drive voltage VDDELL. The reset voltage VSH is larger than, for example, the voltage included in the data signal VDATA (for example, the voltage RDATA(n), the voltage GDATA(n), or the voltage BDATA(n)).

[0039] As shown in FIG. 4, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitive element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) composed of a first electrode and a second electrode. Each of the capacitive element CS and the light-emitting element OLED has a pair of electrodes composed of a first electrode and a second electrode. The fourth transistor T4 and the fifth transistor T5 are p-channel type field effect transistors.

[0040] The first transistor T1 has a function of supplying an image data signal SL(m + 1) to the second transistor T2.

[0041] The second transistor T2 is a so-called driving transistor. The second transistor T2 has a function of passing a current through the light-emitting element OLED using the input image data signal SL(m + 1) to cause the light-emitting element OLED to emit light.

[0042] The third transistor T3 conducts between the second node N2 and the gate electrode 622 of the second transistor T2 (and the second electrode 694 of the capacitor element CS). The third transistor T3 has a function of supplying a reset voltage VSH to the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS to reset the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS. Further, the third transistor T3 has a function of accumulating charges corresponding to the threshold voltage Vth of the second transistor T2 in the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS.

[0043] The fourth transistor T4 controls the connection and disconnection between the driving power supply line PVDD and the second transistor T2. That is, the fourth transistor T4 has a function of supplying a driving voltage VDDEL to the second transistor T2.

[0044] The fifth transistor T5 controls the connection and disconnection between the second transistor T2 and the light-emitting element OLED. That is, the fifth transistor T5 has a function of controlling the connection and disconnection between the second transistor T2 and the light-emitting element OLED and supplying a current to the light-emitting element OLED to control the light emission and non-light emission of the light-emitting element OLED.

[0045] The sixth transistor T6 supplies an initialization voltage VINI to the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitor element CS, and has a function of initializing the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitor element CS.

[0046] The seventh transistor T7 supplies a reset voltage VSH to the first electrode 644 of the fourth transistor T4, the second electrode 626 of the second transistor T2, the second electrode 636 of the third transistor T3, etc., and has a function of resetting the first electrode 644 of the fourth transistor T4, the second electrode 626 of the second transistor T2, and the second electrode 636 of the third transistor T3.

[0047] The capacitor element CS has a function of holding a charge (first charge) corresponding to the threshold voltage Vth of the second transistor T2, for example. Further, the capacitor element CS has a function of holding a charge (second charge) corresponding to a data voltage (e.g., RDATA(n) (see FIG. 6)) included in the image data signal SL(m + 1) input to the gate electrode 622 of the second transistor T2.

[0048] The light-emitting element OLED has diode characteristics and has a function of emitting light based on the current flowing through the light-emitting element OLED (i.e., the drain current of the second transistor T2).

[0049] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scanning signal line 331. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 624 of the second transistor T2, and the second electrode 656 of the fifth transistor T5. The scanning signal line 331 is supplied with a scanning signal G(n + 1). The first transistor T1 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal G(n + 1). When the signal supplied to the scanning signal G(n + 1) is low (LO), the first transistor T1 becomes non-conductive. When the signal supplied to the scanning signal G(n + 1) is high (HI), the first transistor T1 becomes conductive.

[0050] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the first electrode 634 of the third transistor T3 and the second electrode 694 of the capacitor element CS. The second electrode 626 is electrically connected to the second node N2, the second electrode 636 of the third transistor T3, the first electrode 674 of the seventh transistor T7, and the first electrode 644 of the fourth transistor T4.

[0051] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scanning signal line 330. The scanning signal line 330 is supplied with a scanning signal G(n). The third transistor T3 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal G(n). When the signal supplied to the scanning signal G(n) is low (LO), the third transistor T3 becomes non-conductive. When the signal supplied to the scanning signal G(n) is high (HI), the third transistor T3 becomes conductive.

[0052] The fourth transistor T4 is a p-channel field-effect transistor. The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the emission control signal line 334. The second electrode 646 is electrically connected to the drive power supply line PVDD. A drive voltage VDDEL is supplied to the drive power supply line PVDD. An emission control signal EM(n) is supplied to the emission control signal line 334. The fourth transistor T4 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the emission control signal EM(n). When the signal supplied to the emission control signal EM(n) is low (LO), the fourth transistor T4 is in a conductive state. When the signal supplied to the second emission control signal EM(n) is high (HI), the fourth transistor T4 is in a non-conductive state.

[0053] The fifth transistor T5 is a p-channel field-effect transistor. The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the emission control signal line 334. The first electrode 654 is electrically connected to the second electrode 666 of the sixth transistor T6, the first electrode 692 of the capacitor element CS, and the second electrode 684 of the light-emitting element OLED. An emission control signal EM(n) is supplied to the emission control signal line 334. The fifth transistor T5 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the emission control signal EM(n). When the signal supplied to the emission control signal EM(n) is low (LO), the fifth transistor T5 is in a conductive state. When the signal supplied to the emission control signal EM(n) is high (HI), the fifth transistor T5 is in a non-conductive state.

[0054] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the emission control signal line 334. The first electrode 664 is electrically connected to the initialization voltage line VM. An emission control signal EM(n) is supplied to the emission control signal line 334, and an initialization voltage VINI is supplied to the initialization voltage line VM. Similar to the fourth transistor T4 and the fifth transistor T5, the sixth transistor T6 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the emission control signal EM(n). When the signal supplied to the emission control signal EM(n) is low (LO), the sixth transistor T6 is in a non-conductive state. When the signal supplied to the emission control signal EM(n) is high (HI), the sixth transistor T6 is in a conductive state.

[0055] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 329. A scan signal G(n - 1) is supplied to the scan signal line 329. The second electrode 676 is electrically connected to the reset voltage line VC. As described above, a reset voltage VSH is supplied to the reset voltage line VC. The seventh transistor T7 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scan signal G(n - 1). When the signal supplied to the scan signal G(n - 1) is low (LO), the seventh transistor T7 is in a non-conductive state. When the signal supplied to the scan signal G(n - 1) is high (HI), the seventh transistor T7 is in a conductive state.

[0056] The capacitor element CS includes a first electrode 692 and a second electrode 694. The first electrode 692 is electrically connected to the second electrode 666 of the sixth transistor T6, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED. The second electrode 694 is electrically connected to the first electrode 634 of the third transistor T3 and the gate electrode 622 of the second transistor T2.

[0057] In this embodiment, the capacitance of the capacitive element CS of the pixel 180A disposed in the region 22A is smaller than the capacitance of the capacitive element CS of the pixel 180B disposed in the region 22B. It is preferable that the capacitance of the capacitive element CS of the pixel 180A is 0.9 times or less the capacitance of the capacitive element CS of the pixel 180B. For example, the areas of the electrodes of the capacitive element CS of the pixel 180A and the electrode of the capacitive element CS of the pixel 180B may be different. The electrode of the capacitive element CS of the pixel 180A may be smaller than the electrode of the capacitive element CS of the pixel 180B. The area of the electrode of the capacitive element CS of the pixel 180A may be smaller than times the area of the electrode of the capacitive element CS of the pixel 180B.

[0058] The region 22A may include pixels 180A arranged in a plurality of rows and columns. In this case, the capacitance of the capacitive element CS of the pixel 180A disposed on the outermost periphery may be different from the capacitance of the capacitive element CS of the pixel 180A adjacent to the pixel 180B in the region 22B. The capacitance of the capacitive element CS of the pixel 180A disposed on the outermost periphery may be smaller than the capacitance of the capacitive element CS of the pixel 180A adjacent to the pixel 180B in the region 22B. In the region 22A, the capacitance of the capacitive element CS may have a positive gradient from the pixel 180A disposed on the outermost periphery to the pixel 180A adjacent to the pixel 180B in the region 22B.

[0059] The first electrode 682 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0060] In the self-luminous display device 10, the conductive state of the transistor means, for example, that the source electrode and the drain electrode of the transistor are conductive and the transistor indicates an on state, and the non-conductive state of the transistor means that the source electrode and the drain electrode of the transistor are non-conductive and the transistor indicates an off state. Note that in each transistor, the source electrode and the drain electrode may be interchanged according to the voltage or potential supplied to each electrode. Also, even when the transistor is in the off state, it is easily understood by those skilled in the art that a slight current flows, such as a leakage current.

[0061] Each transistor shown in FIG. 4 can have a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor characteristics, in the channel region. For example, the channel region of each transistor has low-temperature polysilicon (LTPS). In the self-luminous display device 10, each transistor is formed using a thin-film transistor (TFT), the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors, and the other transistors are n-channel field-effect transistors. Each transistor may have either an n-channel field-effect transistor or a p-channel field-effect transistor. The self-luminous display device 10 may appropriately adapt the configuration of the transistor, the connection of the holding capacitor, the power supply voltage, etc., according to the application and specifications.

[0062] <1-6. Driving method of the self-luminous display device 10> Referring to FIGS. 5A to 14, a driving method of the self-emitting display device 10 will be described. FIGS. 5A, 5B, 6, and 13 are schematic diagrams showing the timing charts of the self-emitting display device 10. FIGS. 7 to 12 are schematic diagrams showing the operating states of the pixel 180 (pixel circuit 181) at the timing shown in FIG. 6. FIG. 14 is a schematic diagram showing the operating state of the pixel 180 (pixel circuit 181) at the timing shown in FIG. 13. The driving method of the self-emitting display device 10 is not limited to the driving method shown in FIGS. 5A to 14. For configurations identical or similar to those in FIGS. 1 to 4, the description here will be omitted. Note that the horizontal axis of the timing chart is time (TIME).

[0063] FIG. 5A is, for example, a timing chart of the driving method of the self-emitting display device 10 when the self-emitting display device 10 is driven at a high frequency. The high frequency is, for example, 60 Hz, which is the frequency at which 1 frame (1 FRAME) is driven at 60 Hz. FIG. 5A shows, for example, the current frame (Kth FRAME), a part of the frame immediately before the current frame (K - 1st FRAME), and a part of the frame immediately after the current frame (K + 1st FRAME). The driving method shown in FIG. 5A is called high-frequency driving, for example.

[0064] As shown in FIG. 5A, the driving method of the self-emitting display device 10 includes at least a reset period PRS, a sampling period PWR, and a light-emitting period PEM within 1 frame. In the pixel 180 (pixel circuit 181) included in the self-emitting display device 10, the sampling period PWR is executed after the reset period PRS, and the light-emitting period PEM is executed after the sampling period PWR. Also, after the light-emitting period PEM of the frame immediately before the current frame, the reset period PRS of the current frame is executed, and after the light-emitting period PEM of the current frame, the reset period PRS and the sampling period PWR of the frame immediately after the current frame are executed.

[0065] FIG. 5B is a timing chart of a driving method of the self-emitting display device 10 when the self-emitting display device 10 is driven at a low frequency, for example. The low frequency is, for example, 1 Hz, which is the frequency at which 1 frame (1 FRAME) is driven at 1 Hz. The driving method shown in FIG. 5B is called low-frequency driving, for example. Low-frequency driving is a driving method in which, during the light-emitting period PEM, a period for displaying black (black period PBWR) is executed a plurality of times as compared with high-frequency driving. In low-frequency driving, the driving other than the black period PBWR is the same as that in high-frequency driving.

[0066] FIG. 6 is a diagram for explaining the reset period PRS, the sampling period PWR, and the light-emitting period PEM of the driving method of the pixel 180 (pixel circuit 181) of the self-emitting display device 10. FIG. 6 shows the light-emitting period PEM of the frame (K-1st FRAME) one frame before the current frame, the reset period PRS, the sampling period PWR, and the light-emitting period PEM of the current frame (Kth FRAME). Further, FIG. 6 shows a plurality of one horizontal periods (horizontal period N-2nd HP, horizontal period N-1st HP, horizontal period Nth HP, horizontal period N+1st HP, horizontal period N+2nd HP). One horizontal period is, for example, a period during which an image data signal SL(m+1) including a data signal VDATA is input to a pixel (pixel circuit) electrically connected to one scanning signal line, and the image data signal SL(m+1) including the data signal VDATA is input to the pixels (pixel circuits) electrically connected to all the scanning signal lines, and the image of the current frame corresponding to 1 FRAME is displayed.

[0067] With reference to FIGS. 6 to 12, an example of a driving method in which the pixel 180 (pixel circuit 181) displays an image based on a voltage RDATA(n) included in the data signal VDATA input in one horizontal period Nth HP will be described. In the description of the driving method according to the first embodiment, as an example, a driving voltage VDDEL or a driving voltage VDDELL is supplied to the driving power supply line PVDD, and a reference voltage VSSEL is supplied to the reference voltage line PVSS.

[0068] First, the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB will be described. In accordance with each horizontal period, an image data signal SL(m + 1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data including, for example, a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. The voltage VDM is a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. In each horizontal period, for example, using the selection signal MUXR, the voltage RDATA is selected and supplied to the image data signal line, using the selection signal MUXG, the voltage GDATA is selected and supplied to the image data signal line, and using the selection signal MUXB, the voltage BDATA is selected and supplied to the image data signal line. During a period when data is not selected using the selection signal MUXG, the data signal VDATA is maintained at, for example, the voltage VDM.

[0069] Next, referring to FIGS. 6 and 7, a driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the frame immediately preceding the current frame (K - 1st FRAME) will be described. The light emission period PEM of the frame immediately preceding the current frame (K - 1st FRAME) is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the voltage RDATA(n - 1).

[0070] The gate electrode 622 of the second transistor T2 is supplied with the voltage RDATA(n - 1). The scan signals G(n - 1), G(n), and G(n + 1) are supplied with LOW (LO), and the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in an off state. Also, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are supplied with LOW (LO) from the light emission control signal EM(n), the fourth transistor T4 and the fifth transistor T5 are in an on state, and the sixth transistor T6 is in an off state.

[0071] The second transistor T2 is in an on state based on the voltage RDATA(n-1). As a result, the second transistor T2 can conduct a current IELA based on the gate-source voltage Vgs and the source-drain voltage Vds corresponding to the voltage RDATA(n-1).

[0072] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on state, and the current IELA flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the current IELA flows through the light-emitting element OLED, and the light-emitting element OLED emits light.

[0073] Next, referring to FIG. 6, a driving method of the pixel 180 (pixel circuit 181) during the period between the light emission period PEM of the frame one frame before this frame (K-1stFRAME) and the reset period PRS of this frame will be described. The period between the light emission period PEM of the frame one frame before this frame (K-1stFRAME) and the reset period PRS of this frame is a period overlapping with a part of one horizontal period N-2ndHP and a part of one horizontal period N-1stHP. During this period, the light emission control signal EM(n) is supplied from low (LO) to high (HI), the fifth transistor T5 and the fourth transistor T4 are in an off state, and the sixth transistor T6 is in an on state. Also, the scanning signal G(n-1) is supplied from low (LO) to high (HI), and the seventh transistor T7 is in an on state. The first transistor T1 and the third transistor T3 remain in an off state.

[0074] Based on the sixth transistor T6 being turned on, an initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are initialized. Also, the fourth transistor T4 and the fifth transistor T5 are in the off state, no current flows from the drive power supply line PVDD to the reference voltage line PVSS, and a current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is a current (substantially 0) corresponding to the potential difference (voltage VINI - reference voltage VSSEL) between the voltage of the second electrode 684 of the light-emitting element OLED and the voltage of the first electrode 682, and the light-emitting element OLED is non-emitting (not emitting light).

[0075] Next, referring to FIGS. 6 and 8, a driving method of the pixel 180 (pixel circuit 181) during the reset period PRS of the current frame will be described. The reset period PRS is a period in which a reset voltage VSH and an initialization voltage VINI are written to the pixel 180 (pixel circuit 181) to initialize the pixel 180 (pixel circuit 181). The reset period PRS of the current frame is a period overlapping a part of the (N - 1)st horizontal period N-1stHP.

[0076] During the reset period PRS, the scan signal G(n) is supplied from low (LO) to high (HI), and the third transistor T3 is in the on state. Also, the sixth transistor T6 and the seventh transistor T7 remain in the on state, and the first transistor T1, the fourth transistor T4, and the fifth transistor T5 remain in the off state.

[0077] Based on the seventh transistor T7 and the third transistor T3 being in the on state, a reset voltage VSH is supplied to the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS. As a result, the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS are reset. Also, since the sixth transistor T6 remains in the on state, the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are maintained at the initialization voltage VINI. As a result, a voltage of reset voltage VSH - initialization voltage VINI (VSH - VINI) is applied to the capacitive element CS.

[0078] Also, since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the drive power supply line PVDD to the reference voltage line PVSS, and a current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is almost 0 as described above, and the light-emitting element OLED is non-emitting (not emitting light).

[0079] Although detailed illustration is omitted, the second transistor T2 shown in FIG. 8 is in the on state, but when the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 (the potential difference between the gate electrode 622 and the first node N1) becomes the same as the threshold voltage Vth of the second transistor T2, the second transistor T2 turns off. As a result, a difference between the reset voltage VSH and the threshold voltage Vth (VSH - Vth) is held at the first node N1 and each electrode electrically connected to the first node N1, and the reset voltage VSH is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS.

[0080] Next, referring to FIGS. 6 and 9, a driving method of the pixel 180 (pixel circuit 181) during the period between the reset period PRS and the sampling period PWR of the frame will be described. The period between the reset period PRS and the sampling period PWR of the frame is a period that overlaps with a part of the (N - 1)st horizontal period N - 1stHP and a part of the Nth horizontal period NthHP.

[0081] During the period between the reset period PRS and the sampling period PWR of the frame, the scanning signal G(n - 1) is supplied from high (HI) to low (LO), and the seventh transistor T7 is in the off state. Also, the third transistor T3 and the sixth transistor T6 remain in the on state, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 remain in the off state.

[0082] Also, during the period between the reset period PRS and the sampling period PWR of the frame, a reset voltage VSH is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Also, since the sixth transistor T6 remains in the on state, an initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Also, since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is not emitting light).

[0083] During the period between the reset period PRS and the sampling period PWR of the frame, based on the supply of an on signal to the selection signal MUXR, the voltage RDATA(n) is selected. Therefore, the image data signal SL(m + 1) includes the voltage RDATA(n). Further, the image data signal SL(m + 1) including the voltage RDATA(n) is supplied to the image data signal line 321. Based on the supply of an off signal to the selection signal MUXR, the image data signal line 321 holds the voltage RDATA(n).

[0084] Next, with reference to FIGS. 6 and 10, a driving method of the pixel 180 (pixel circuit 181) during the sampling period PWR of the frame will be described. The sampling period PWR is a period in which a voltage corresponding to the image data to be displayed by the pixel 180 (pixel circuit 181) is written into the pixel 180 (pixel circuit 181). The sampling period PWR of the frame is a period overlapping a part of one horizontal period NthHP.

[0085] During the sampling period PWR of the frame, the scanning signal G(n + 1) is supplied from low (LO) to high (HI), and the first transistor T1 is in the on state. Also, the third transistor T3 and the sixth transistor T6 remain in the on state, and the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 remain in the off state.

[0086] Based on the first transistor T1 being turned on, a voltage RDATA(n) is supplied to the first node N1 and each electrode electrically connected to the first node N1. Further, when the voltage RDATA(n) is supplied to the first node N1, the voltage between the gate and source of the second transistor T2 also changes, and the second transistor T2 is turned on. As a result, the voltages of the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS drop from the voltage VSH and become the voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth). In this way, the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 becomes the same as the threshold voltage Vth of the second transistor T2, and the voltage drop (discharge) of the second node N2 and the like ends, and the second transistor T2 becomes the off state.

[0087] In the present embodiment, the capacitance of the capacitor element CS of the pixel 180A disposed in the region 22A is smaller than the capacitance of the capacitor element CS of the pixel 180B disposed in the region 22B. When the capacitance of the capacitor element CS is small, the discharge in the sampling period PWR proceeds quickly. Therefore, the voltage held in the capacitor element CS of the pixel 180A disposed in the region 22A becomes smaller than the voltage held in the capacitor element CS of the pixel 180B disposed in the region 22B.

[0088] Further, since the sixth transistor T6 remains in the on state, an initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Further, since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the drive power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is not emitting light).

[0089] Although detailed illustrations are omitted, at this time, since the first transistor T1 remains in the on state, the voltage of the first node N1 and each electrode electrically connected to the first node N1 is fixed to the voltage RDATA(n). Also, a charge corresponding to the threshold voltage Vth is held between the gate electrode 622 of the second transistor T2 and the first electrode 624. Therefore, the sampling period PWR of this frame is a period during which the pixel 180 (pixel circuit 181) writes the voltage corresponding to the image data to be displayed by the pixel 180 (pixel circuit 181), and is also a period (threshold correction period) during which a charge corresponding to the threshold voltage Vth is held between the gate electrode 622 of the second transistor T2 and the first electrode 624 to correct the threshold of the second transistor T2.

[0090] Next, referring to FIGS. 6 and 11, a driving method of the pixel 180 (pixel circuit 181) after the sampling period PWR of this frame will be described. The period after the sampling period PWR of this frame is a period that overlaps a part of one horizontal period NthHP and one horizontal period N + 1stHP.

[0091] In the period after the sampling period PWR of this frame, the scan signal G(n) is supplied from high (HI) to low (LO), and the third transistor T3 is in the off state. Also, the first transistor T1 and the sixth transistor T6 remain in the on state, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 remain in the off state. A high (HI) is supplied to the scan signal G(n + 1), and the first transistor T1 is in the on state. The voltage of the first electrode 614 and the voltage of the second electrode 616 of the first transistor T1 are both the voltage RDATA(n). That is, the voltage of the first electrode 614 and the voltage of the second electrode 616 of the first transistor T1 are the same. Therefore, no current flows through the first transistor T1.

[0092] Since the second transistor T2 and the seventh transistor T7 are in the off state, a voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth) is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Further, since the third transistor T3 is in the off state, the voltages at the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS are decreased (diminished) to a voltage RDATA(n) + threshold voltage Vth - voltage α (RDATA(n) + Vth - α) by capacitive coupling between the gate and drain (gate electrode 632 - first electrode 634) of the third transistor T3. Here, for example, the voltage α is a positive value and is a voltage value that changes according to the capacitance of the capacitor element CS. For example, as the capacitance of the capacitor element CS increases (becomes larger), the voltage α becomes lower (smaller), and as the capacitance of the capacitor element CS decreases (becomes smaller), the voltage α becomes higher (larger). In the present embodiment, the capacitance of the capacitor element CS of the pixel 180A disposed in the region 22A is smaller than the capacitance of the capacitor element CS of the pixel 180B disposed in the region 22B. When the capacitance of the capacitor element CS is small, the diminishment of the voltage α during the sampling period PWR becomes larger. Therefore, the voltage held in the capacitor element CS of the pixel 180A disposed in the region 22A becomes smaller than the voltage held in the capacitor element CS of the pixel 180B disposed in the region 22B.

[0093] Also, since the sixth transistor T6 is in the on state, an initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, a voltage of RDATA(n) + threshold voltage Vth - voltage α - initialization voltage VINI (RDATA(n) + Vth - α - VINI) is held in the capacitor element CS. Similar to the sampling period PWR of the current frame, a current IINI also flows from the initialization voltage line VM to the reference voltage line PVSS in the period after the sampling period PWR of the current frame. The current IINI flowing through the light-emitting element OLED is almost 0, and the light-emitting element OLED is non-emitting (not emitting light).

[0094] As shown in FIG. 6, after the scan signal G(n) is supplied from high (HI) to low (LO) and the third transistor T3 is turned off, the scan signal G(n+1) is supplied from high (HI) to low (LO), and the first transistor T1 is turned off.

[0095] At this time, since the first transistor T1 is in the off state, the voltage RDATA(n) is held at the first node N1 and each electrode electrically connected to the first node N1. Also, since the second transistor T2, the third transistor T3, and the seventh transistor T7 are in the off state, the voltage RDATA(n)+threshold voltage Vth-voltage α(RDATA(n)+Vth-α) is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Further, since the sixth transistor T6 is in the on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Therefore, following the period after the sampling period PWR of the current frame, the current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is almost zero, and the light-emitting element OLED is non-emitting (not emitting light).

[0096] Next, referring to FIGS. 6, 11, and 12, a driving method of the pixel 180 (pixel circuit 181) during the light-emitting period PEM of the current frame will be described. The light-emitting period PEM of the current frame is a period during which the pixel 180 (pixel circuit 181) emits light according to the voltage RDATA(n). The light-emitting period PEM of the current frame is a period overlapping with one horizontal period N+2ndHP.

[0097] As shown in FIGS. 6 and 12, the scan signal G(n - 1), the scan signal G(n), and the scan signal G(n + 1) are supplied with a low (LO), and the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in an off state. Also, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are supplied with a low (LO) from the emission control signal EM(n), the fourth transistor T4 and the fifth transistor T5 are in an on state, and the sixth transistor T6 is in an off state.

[0098] As shown in FIG. 11, the voltage held by the second electrode 656 of the fifth transistor T5 is RDATA(n), and the voltage held by the first electrode 654 of the fifth transistor T5 is the initialization voltage VINI.

[0099] When the voltage of the second electrode 656 and the voltage of the first electrode 654 of the fifth transistor T5 are in the state of the voltage RDATA(n) (RDATA(n)) and the initialization voltage VINI (VINI), and the fifth transistor T5 shown in FIGS. 6 and 12 becomes on, a current flows from the second electrode 656 to the first electrode 654 of the fifth transistor T5, charge redistribution occurs, and the voltage of the second electrode 656 and the voltage of the first electrode 654 become the initialization voltage VINI (VINI). At this time, the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitive element CS become the voltage RDATA(n) + threshold voltage Vth - voltage α - initialization voltage VINI (RDATA(n) + Vth - α - VINI). Depending on the value of the voltage RDATA(n), the second transistor T2 is in an on state or an off state.

[0100] Also, for example, as shown in FIGS. 6 and 12, based on the fact that the fifth transistor T5 is in the on state, current flows from the second electrode 656 of the fifth transistor T5 to the first electrode 654, and when the voltages of the first electrode 654 and each electrode electrically connected to the first electrode 654 (the second electrode 684 of the light-emitting element OLED, the second electrode 666 of the sixth transistor T6, and the first electrode 692 of the capacitor element CS) rise from the voltage VINI to the voltage VINI + voltage β, the voltage held by the first node N1 (the second electrode 656 of the fifth transistor T5 and the first electrode 624 of the second transistor T2) decreases from RDATA(n). As the first electrode 692 of the capacitor element CS rises to the voltage VINI + voltage β, due to capacitive coupling, the voltages of the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS rise from the voltage RDATA(n) + threshold voltage Vth - voltage α (RDATA(n) + Vth - α) to the voltage RDATA(n) + threshold voltage Vth - voltage α + voltage β (RDATA(n) + Vth - α + β). As a result, since the gate-source voltage between the gate electrode 622 of the second transistor T2 and the first electrode 624 becomes higher than the threshold voltage Vth of the second transistor T2, the second transistor T2 becomes in the on state.

[0101] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on state, and a current IELA flows from the drive power supply line PVDD to the reference voltage line PVSS. As a result, the current IELA flows through the light-emitting element OLED, and the light-emitting element OLED emits light. The current IELA is, for example, a current based on the voltage RDATA(n) written in the second transistor T2 + threshold voltage Vth - voltage α + voltage β (RDATA(n)+Vth-α+β). When this voltage is applied between the gate and the source between the gate electrode 622 and the first electrode 624 of the second transistor T2, a current in which the influence of the variation in the threshold voltage Vth of the second transistor T2 between the respective pixels 180 (pixel circuits 181) is canceled flows through the light-emitting element OLED, and the in-plane uniformity can be improved. Here, for example, the voltage β is a positive value and is a voltage value that changes according to the voltage RDATA(n). For example, when the voltage RDATA(n) becomes high (large), the voltage β becomes high (large), and when the voltage RDATA(n) becomes low (small), the voltage β becomes low (small). For example, the voltage β is determined so that the current value flowing through the second transistor T2 according to the gate electrode 622, the first electrode 624, and the second electrode 626 is the same as the current value flowing through the light-emitting element OLED.

[0102] On the other hand, in the present embodiment, the capacitance of the capacitive element CS of the pixel 180A disposed in the region 22A is smaller than the capacitance of the capacitive element CS of the pixel 180B disposed in the region 22B. When the capacitance of the capacitive element CS is small, the discharge in the sampling period PWR proceeds quickly, and the breakthrough of the voltage α becomes large. Therefore, the voltage held in the capacitive element CS of the pixel 180A disposed in the region 22A becomes smaller than the voltage held in the capacitive element CS of the pixel 180B disposed in the region 22B. When this voltage is applied between the gate and the source between the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows through the light-emitting element OLED of the pixel 180A disposed in the region 22A than through the light-emitting element OLED of the pixel 180B disposed in the region 22B. In this way, the phenomenon that the outermost periphery of the display region emits light more brightly at low luminance can be eliminated, and the in-plane uniformity can be further improved.

[0103] As described above, the self-emitting display device 10 is driven, image data corresponding to each pixel 180 (pixel circuit 181) is supplied to each pixel 180 (pixel circuit 181), a current corresponding to the image data is supplied to the light-emitting element OLED included in each pixel 180 (pixel circuit 181), and each light-emitting element OLED emits light with a luminance corresponding to the image data. As a result, the self-emitting display device 10 can display a desired image.

[0104] Next, with reference to FIGS. 5B, 13, and 14, an example of a driving method in which the pixel 180 (pixel circuit 181) displays black based on the voltage RDATAB included in the data signal VDATA input in one horizontal period NthHP will be described. As described above, in the low-frequency driving, the driving other than the black period PBWR is the same as the high-frequency driving. Therefore, mainly, the driving of the pixel 180 (pixel circuit 181) in the black period PBWR will be described here. Regarding the configurations identical to or similar to those in FIGS. 1 to 5A and FIGS. 6 to 12, the description here will be omitted. Note that the horizontal axis of the timing chart is time (TIME).

[0105] First, the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB will be described. In accordance with each horizontal period, an image data signal SL(m + 1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is, for example, analog data including a voltage VDL for displaying black. The voltage VDM is a voltage between the voltage VDL lower than the voltage VDH and the voltage VDH. In each horizontal period, for example, using the selection signal MUXR, the voltage VDL is selected and supplied to the image data signal line, using the selection signal MUXG, the voltage VDL is selected and supplied to the image data signal line, and using the selection signal MUXB, the voltage VDL is selected and supplied to the image data signal line. During the period when data is not selected using the selection signal MUXG, the data signal VDATA is maintained at, for example, the voltage VDM.

[0106] The driving method of pixel 180 (pixel circuit 181) during the light emission period PEM of the frame immediately before the current frame (K-1st FRAME) is the same as the driving method described with reference to FIGS. 1 to 5A and FIGS. 6 to 12. Therefore, the description here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED during the light emission period PEM of the frame immediately before the current frame (K-1st FRAME) are voltages between the voltage VDL and the voltage VDH.

[0107] Next, the driving method of pixel 180 (pixel circuit 181) during the black period PBWR that is executed following the light emission period PEM of the frame immediately before the current frame (K-1st FRAME) will be described. The black period PBWR of the current frame is a period that overlaps with a part of one horizontal period N-2nd HP, one horizontal period N-1st HP, one horizontal period Nth HP, one horizontal period N+1st HP, and a part of one horizontal period N+2nd HP.

[0108] The scan signals G(n-1), G(n), and G(n+1) are supplied with low (LO), and the light emission control signal EM(n) is supplied with high (HI). The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in the off state, and the sixth transistor T6 is in the on state.

[0109] Since the sixth transistor T6 is in the on state, the voltage RDATAB is supplied to the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Therefore, the current IRB flows from the initialization voltage line VM to the reference voltage line PVSS. The current IRB flowing through the light emitting element OLED is a current for displaying black based on the voltage RDATAB, and the light emitting element OLED hardly emits light (is not emitting light). Therefore, pixel 180 displays black.

[0110] The driving method of pixel 180 (pixel circuit 181) during the light emission period PEM of frame (KthFRAME) is the same as the driving method of pixel 180 (pixel circuit 181) during the light emission period PEM of the frame immediately preceding this frame (K - 1stFRAME). Therefore, the description here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED during the light emission period PEM of this frame (KthFRAME) are voltages between voltage VDL and voltage VDH.

[0111] During the black period PBWR of the self - emissive display device 10, the voltage RDATAB is supplied from the initialization voltage line VM to the second electrode 684 of the light emitting element OLED, whereby the self - emissive display device 10 can display black.

[0112] <2. Second Embodiment> Referring to FIG. 15, a self - emissive display device according to the second embodiment will be described. In the self - emissive display device according to the second embodiment, except that the configuration of the pixel circuit is different, it is the same as the configuration of the self - emissive display device 10 described in the first embodiment. Regarding the configuration that is the same as or similar to the configuration of the self - emissive display device described in the first embodiment, and the configuration that is the same as or similar to FIGS. 1 - 14, the description here is omitted. In this embodiment, the capacitance of pixel 180A and the capacitance of pixel 180B are different. The capacitance connected to the gate electrode 622 of the second transistor T2 of pixel 180A and the capacitance connected to the gate electrode 622 of the second transistor T2 of pixel 180B are different.

[0113] <2 - 1. Configuration of Pixel 180> Referring to FIG. 15, the outline of pixel circuit 182 will be described. FIG. 15 is a circuit diagram showing the configuration of pixel circuit 182. As an example, FIG. 15 shows the configuration of pixel circuit 182 of pixel 180 shown in FIG. 2. The configurations of pixel 180 and pixel circuit 182 are not limited to the configurations shown in FIG. 15. Regarding the configuration that is the same as or similar to FIGS. 1 - 14, the description here is omitted.

[0114] The pixel circuit 182 is a circuit for driving the pixel 180 in the same manner as the pixel circuit 181, and has the same configuration and function as the pixel circuit 181 except for the third transistor T3. In the description of the pixel circuit 182, mainly the differences from the pixel circuit 181 will be described.

[0115] As shown in FIG. 15, the pixel circuit 182 includes, in the same manner as the pixel circuit 181, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitive element CS, and a light-emitting element OLED. In the pixel circuit 182, in the same manner as the pixel circuit 181, the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors.

[0116] In the present embodiment, the capacitance of the capacitive element CS of the pixel 180A disposed in the region 22A and the capacitance of the capacitive element CS of the pixel 180B disposed in the region 22B are substantially the same. On the other hand, the capacitance between the gate and drain of the third transistor T3 of the pixel 180A disposed in the region 22A is larger than the capacitance between the gate and drain of the third transistor T3 of the pixel 180B disposed in the region 22B. The capacitance between the gate and drain of the third transistor T3 of the pixel 180A is preferably 1.1 times or more the capacitance between the gate and drain of the third transistor T3 of the pixel 180B. For example, the electrode layouts of the third transistor T3 of the pixel 180A and the third transistor T3 of the pixel 180B may be different. For example, the pixel 180A may adjust the capacitance Cgd by appropriately adjusting the area of the region where the gate electrode 632 of the third transistor T3 or the wiring connected to the gate electrode 632 overlaps with the first electrode 634 or the wiring connected to the first electrode 634. The pixel 180B may also adjust the capacitance Cgd by appropriately adjusting the area of the region where the gate electrode 632 of the third transistor T3 or the wiring connected to the gate electrode 632 overlaps with the first electrode 634 or the wiring connected to the first electrode 634. In this case, the capacitance Cgd of the pixel 180A may be larger than the capacitance Cgd of the pixel 180B.

[0117] Region 22A may include pixels 180A arranged in a plurality of rows and columns. In this case, the capacitance between the gate and drain of the transistor T3 of the pixel 180A arranged on the outermost periphery may be different from the capacitance between the gate and drain of the transistor T3 of the pixel 180A adjacent to the pixel 180B in region 22B. The capacitance between the gate and drain of the transistor T3 of the pixel 180A arranged on the outermost periphery may be larger than the capacitance between the gate and drain of the transistor T3 of the pixel 180A adjacent to the pixel 180B in region 22B. Within region 22A, from the pixel 180A arranged on the outermost periphery to the pixel 180A adjacent to the pixel 180B in region 22B, the capacitance between the gate and drain of the transistor T3 may have a negative gradient.

[0118] In this embodiment, the capacitance between the gate and drain of the transistor T3 of the pixel 180A arranged in region 22A is larger than the capacitance between the gate and drain of the transistor T3 of the pixel 180B arranged in region 22B. When the capacitance between the gate and drain of the transistor T3 is large, the breakthrough of the voltage α during the sampling period PWR becomes large. Therefore, the voltage held in the capacitive element CS of the pixel 180A arranged in region 22A becomes smaller than the voltage held in the capacitive element CS of the pixel 180B arranged in region 22B. When this voltage is applied between the gate electrode 622 and the first electrode 624 of the second transistor T2 during the light emission period PEM, a smaller current flows through the light emitting element OLED of the pixel 180A arranged in region 22A than through the light emitting element OLED of the pixel 180B arranged in region 22B. In this way, the phenomenon that the outermost periphery of the display region emits more brightly at low brightness can be eliminated, and the in-plane uniformity can be further improved.

[0119] <3. Third Embodiment> Referring to FIG. 16, a self-luminous display device according to the third embodiment will be described. In the self-luminous display device 11 according to the third embodiment, the capacitances of the pixels 180 are substantially the same, and instead, the capacitances connected to the image data signal lines 321 at the left and right ends are different from the others. Except for this, the configuration is the same as that of the self-luminous display device 10 described in the first embodiment. For the configuration that is the same as or similar to the configuration of the self-luminous display device described in the first embodiment, and for the configuration that is the same as or similar to FIGS. 1 to 15, the description here will be omitted.

[0120] <3-1. Overview of the Self-Luminous Display Device 11> Referring to FIG. 16, an overview of the self-luminous display device 11 according to the third embodiment will be described. FIG. 16 is a schematic diagram showing the configuration of the self-luminous display device 11 according to the third embodiment. The configuration of the self-luminous display device 11 shown in FIG. 16 is an example, and the configuration of the self-luminous display device 11 is not limited to the configuration shown in FIG. 16.

[0121] As shown in FIG. 16, the self-luminous display device 11 is provided with a plurality of pixels 180, a source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130. Each of the source driver circuit 110, the gate driver circuit 120, and the light emission control circuit 130 is connected to the terminal portion 150 using the connection wiring 341.

[0122] In the display area 22, a plurality of pixels 180 are arranged in a matrix. The display area 22 includes an area 22C and an area 22D. The area 22C is adjacent to the area 22D in the second direction D2 (row direction) and is arranged opposite to both the left and right ends of the display area 22. However, it is not limited to this, and the area 22C may be arranged only on one side (left or right) of the display area 22 adjacent to the area 22D in the second direction D2 (row direction). The area 22D is arranged so as to be sandwiched between the area 22C in the second direction D2 (row direction). The area 22C may include one column of pixels 180C arranged in the first direction D1 (column direction) of the outer edge of the display area 22, or may include a plurality of columns of pixels 180C. A plurality of pixels 180C arranged in the first direction D1 (column direction) of the area 22C share one image data signal line 321C. In this embodiment, since the capacitance of the pixel 180C and the capacitance of the pixel 180D are the same, when the pixel 180C and the pixel 180D are not distinguished, they are referred to as the pixel 180.

[0123] The source driver circuit 110 is provided at a position adjacent to the display area 22 in the first direction D1 (column direction). The image data signal line 321 extends from the source driver circuit 110 in the first direction D1 and is connected to a plurality of pixels 180 arranged in the first direction D1. The source driver circuit 110 includes a plurality of selection circuits 112 as in the first embodiment, is selected by an on signal supplied to the selection signal, and supplies an image data signal SL(m + 1) including a data signal VDATA supplied to the input terminal 114 to the image data signal line 321 and the pixels 180 electrically connected to the image data signal line 321.

[0124] In this embodiment, the capacitance of the capacitive element CS of the pixel 180C disposed in the region 22C and the capacitance of the capacitive element CS of the pixel 180D disposed in the region 22D are substantially the same. On the other hand, the capacitance of the image data signal line 321C connected to the pixel 180C disposed in the region 22C is larger than the capacitance of the image data signal line 321D connected to the pixel 180D disposed in the region 22D. The capacitance of the image data signal line 321C connected to the pixel 180C is preferably 1.2 times or more the capacitance of the image data signal line 321D connected to the pixel 180D. For example, the image data signal line 321C may have a dummy capacitance connected to the ground (GND). Also, the image data signal line 321D may also have a dummy capacitance connected to the ground (GND). In this case, the capacitance of the dummy capacitance of the pixel 180C may be larger than the capacitance of the dummy capacitance of the pixel 180D.

[0125] The regions 22C at both the left and right ends may each include a plurality of rows of pixels 180C. In this case, the capacitance of the image data signal line 321C connected to the pixel 180C disposed at the outermost end and the capacitance of the image data signal line 321C connected to the pixel 180C adjacent to the pixel 180D in the region 22D may be different. The capacitance of the image data signal line 321C connected to the pixel 180C disposed at the outermost end may be larger than the capacitance of the image data signal line 321C connected to the pixel 180C adjacent to the pixel 180D in the region 22D. Within the region 22C, from the image data signal line 321C connected to the pixel 180C disposed at the outermost end to the image data signal line 321C connected to the pixel 180C adjacent to the pixel 180D in the region 22D, a negative gradient may be provided in the capacitance.

[0126] In this embodiment, the capacitance of the image data signal line 321C connected to the pixel 180C disposed in the region 22C is larger than the capacitance of the image data signal line 321D connected to the pixel 180D disposed in the region 22D. When the capacitance of the image data signal line 321C is large, an increase in potential due to the flow of charge of the capacitive element CS into the image data signal line 321C during the sampling period PWR can be suppressed. Therefore, the voltage held in the capacitive element CS of the pixel 180C disposed in the region 22C sharing the image data signal line 321C is smaller than the voltage held in the capacitive element CS of the pixel 180D disposed in the region 22D sharing the image data signal line 321D. When this voltage is applied between the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows through the light-emitting element OLED of the pixel 180C disposed in the region 22C than through the light-emitting element OLED of the pixel 180D disposed in the region 22D. In this way, the phenomenon that the outermost ends of the display area emit light more brightly at low luminance can be eliminated, and the in-plane uniformity can be further improved.

[0127] <4. Fourth Embodiment> Referring to FIG. 17, a self-emissive display device according to the fourth embodiment will be described. In the self-emissive display device 11 according to the fourth embodiment, the capacitances of the pixels 180 are substantially the same, and the configuration is the same as that of the self-emissive display device 10 described in the first embodiment, except that the capacitances connected to the image data signal lines 321 at the left and right ends are different from those of the others. In the self-emissive display device 11 according to the fourth embodiment, the capacitances connected to the image data signal lines 321 are substantially the same, and the configuration is the same as that of the self-emissive display device 11 described in the third embodiment, except that the configuration of the source driver circuit is different. The description of the configurations that are the same as or similar to the configurations of the self-emissive display devices described in the first and third embodiments, and the configurations that are the same as or similar to FIGS. 1 to 16 will be omitted here.

[0128] <4-1. Outline of the Self-Emissive Display Device 11> Referring to FIG. 17, the outline of the self-emitting display device 11 according to the fourth embodiment will be described. FIG. 17 is a schematic diagram showing the configuration of the source driver circuit 111 according to the fourth embodiment. The configuration of the source driver circuit 111 shown in FIG. 17 is an example, and the configuration of the source driver circuit 111 is not limited to the configuration shown in FIG. 17.

[0129] As shown in FIG. 16, the self-emitting display device 11 is provided with a plurality of pixels 180, a source driver circuit 111, a gate driver circuit 120, and a light emission control circuit 130. Each of the source driver circuit 111, the gate driver circuit 120, and the light emission control circuit 130 is connected to the terminal portion 150 using the connection wiring 341.

[0130] In the display area 22, a plurality of pixels 180 are arranged in a matrix. The display area 22 includes an area 22C and an area 22D. The area 22C is adjacent to the area 22D in the second direction D2 (row direction) and is arranged to face both the left and right ends of the display area 22. However, it is not limited thereto, and the area 22C may be arranged adjacent to the area 22D in the second direction D2 (row direction) and only on one side (left or right) of the display area 22. The area 22D is arranged to be sandwiched between the areas 22C in the second direction D2 (row direction). The area 22C may include one column of pixels 180C arranged in the first direction D1 (column direction) of the outer edge of the display area 22, or may include a plurality of columns of pixels 180C. The plurality of pixels 180C arranged in the first direction D1 (column direction) of the area 22C share one image data signal line 321C. In this embodiment, since the capacitance of the pixel 180C and the capacitance of the pixel 180D are the same, when the pixel 180C and the pixel 180D are not distinguished, they are referred to as the pixel 180.

[0131] Similar to the self-emitting display device 11 according to the third embodiment, the source driver circuit 111 is provided at a position adjacent to the display area 22 in the first direction D1 (column direction). The image data signal line 321 extends from the source driver circuit 111 in the first direction D1 and is connected to a plurality of pixels 180 arranged in the first direction D1. The source driver circuit 111 includes a plurality of selection circuits 112 as in the first embodiment, and is selected by an on signal supplied to the selection signal, and supplies the image data signal SL(m+1) including the data signal VDATA supplied to the input terminal 114 to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. A plurality of pixels 180C arranged in the first direction D1 (column direction) of the region 22C share one selection circuit 112C.

[0132] In the present embodiment, the capacitance of the capacitive element CS of the pixel 180C arranged in the region 22C and the capacitance of the capacitive element CS of the pixel 180D arranged in the region 22D are substantially the same. The capacitance of the image data signal line 321C connected to the pixel 180C arranged in the region 22C and the capacitance of the image data signal line 321D connected to the pixel 180D arranged in the region 22D are substantially the same. On the other hand, the capacitance of the selection circuit 112C connected to the image data signal line 321C is larger than the capacitance of the selection circuit 112D connected to the image data signal line 321D. The capacitance of the selection circuit 112C connected to the image data signal line 321C is preferably 1.1 times or more the capacitance of the selection circuit 112D connected to the image data signal line 321D. For example, the electrode layouts of the selection circuit 112C connected to the image data signal line 321C and the selection circuit 112D connected to the image data signal line 321D may be different. For example, the capacitance Cgd(c) may be adjusted by appropriately adjusting the area of the region where the gate electrode of the selection circuit 112C or the wiring connected to the gate electrode overlaps with the drain electrode or the wiring connected to the drain electrode. The capacitance Cgd(d) may be adjusted by appropriately adjusting the area of the region where the gate electrode of the selection circuit 112D or the wiring connected to the gate electrode overlaps with the drain electrode or the wiring connected to the drain electrode. In this case, the capacitance Cgd(c) of the selection circuit 112C may be larger than the capacitance Cgd(d) of the selection circuit 112D.

[0133] As in the example shown in FIG. 17, the regions 22C at both the left and right ends may each include a plurality of columns of pixels 180C. In the present embodiment, the capacitance of the selection circuit 112C connected to the three columns of image data signal lines 321C of R, G, and B for each unit of the data signal VDATA1 supplied from the IC chip 170 is uniformly increased. However, the present invention is not limited to this, and the capacitance of the selection circuit 112C connected to the pixel 180C arranged at the outermost end via the image data signal line 321C may be different from the capacitance of the selection circuit 112C connected to the pixel 180C adjacent to the pixel 180D in the region 22D via the image data signal line 321C. The capacitance of the selection circuit 112C connected to the pixel 180C arranged at the outermost end via the image data signal line 321C may be larger than the capacitance of the selection circuit 112C connected to the pixel 180C adjacent to the pixel 180D in the region 22D via the image data signal line 321C. Within the region 22C, from the selection circuit 112C connected to the pixel 180C arranged at the outermost end via the image data signal line 321C to the selection circuit 112C connected to the pixel 180C adjacent to the pixel 180D in the region 22D via the image data signal line 321C, a negative gradient may be provided in the capacitance. On the other hand, only the capacitance of the selection circuit 112C connected to the one-column image data signal lines 321C (SL(1) and SL(m + 3)) at both the left and right ends may be increased.

[0134] In this embodiment, the capacitance of the selection circuit 112C connected to the pixel 180C disposed in the region 22C via the image data signal line 321C is larger than the capacitance of the selection circuit 112D connected to the pixel 180D disposed in the region 22D via the image data signal line 321D. When the capacitance of the selection circuit 112C is large, the potential drop of the image data signal line 321C due to the capacitive coupling between the gate and drain when the selection circuit 112C is turned off becomes large, and the voltage RDATA(n) applied to the pixel 180C during the sampling period PWR becomes small. Therefore, the voltage held in the capacitive element CS of the pixel 180C disposed in the region 22C sharing the selection circuit 112C becomes smaller than the voltage held in the capacitive element CS of the pixel 180D disposed in the region 22D sharing the selection circuit 112D. When this voltage is applied between the gate-source of the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows through the light-emitting element OLED of the pixel 180C disposed in the region 22C than through the light-emitting element OLED of the pixel 180D disposed in the region 22D. In this way, the phenomenon that the outermost end of the display area emits more brightly at low brightness can be eliminated, and the in-plane uniformity can be further improved.

[0135] <5. Fifth Embodiment> Referring to FIGS. 18 and 19, a self-emissive display device according to the fifth embodiment will be described. In the self-emissive display device 12 according to the fifth embodiment, the capacitances of the pixels 180 are substantially the same, and the configuration is the same as that of the self-emissive display device 10 described in the first embodiment, except that the driving methods of the upper and lower end pixels 180 (pixel circuits) by the scanning signal are different from those of the others. The description of the configuration that is the same as or similar to the configuration of the self-emissive display device described in the first embodiment, and the configuration that is the same as or similar to FIGS. 1 to 17 will be omitted here.

[0136] <5-1. Outline of the Self-Emissive Display Device 12> Referring to FIG. 18, the outline of the self-emitting display device 12 according to the fifth embodiment will be described. FIG. 18 is a schematic diagram showing the configuration of the self-emitting display device 12 according to the fifth embodiment. The configuration of the self-emitting display device 12 shown in FIG. 18 is an example, and the configuration of the self-emitting display device 12 is not limited to the configuration shown in FIG. 18.

[0137] As shown in FIG. 18, the self-emitting display device 12 is provided with a plurality of pixels 180, a source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130. Each of the source driver circuit 110, the gate driver circuit 120, and the light emission control circuit 130 is connected to the terminal portion 150 using the connection wiring 341.

[0138] In the display area 22, a plurality of pixels 180 are arranged in a matrix. The display area 22 includes an area 22E and an area 22F. The area 22E is adjacent to the area 22F in the first direction D1 (column direction) and is arranged to face both the upper and lower ends of the display area 22. The area 22F is arranged to be sandwiched between the area 22E in the first direction D1 (column direction). The area 22E may include one row of pixels 180E arranged in the second direction D2 (row direction) on the outer edge of the display area 22, or may include a plurality of rows of pixels 180E. In this embodiment, since the capacitance of the pixel 180E is the same as the capacitance of the pixel 180F, when the pixel 180E and the pixel 180F are not distinguished, they are referred to as pixels 180.

[0139] Similar to the self-emitting display device 10 according to the first embodiment, the gate driver circuit 120 is provided at a position adjacent to the display region 22 in the second direction D2 (row direction). The scanning signal lines 329, 330, 331, and 332 extend from the gate driver circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. The gate driver circuit 120 includes a plurality of shift registers (for example, shift registers 121, 122, and 123) as in the first embodiment, and based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, different timing scanning signals (for example, scanning signal G(n - 1), scanning signal G(n), scanning signal G(n + 1)) are sequentially supplied to the pixels 180 electrically connected to each of the scanning signal lines 329, 330, 331, and 332.

[0140] <5-2. Driving Method of Self-Emitting Display Device 12> Referring to FIG. 19, a driving method of the self-emitting display device 12 according to the fifth embodiment will be described. FIG. 19 is a schematic diagram showing a timing chart of the self-emitting display device 12 according to the fifth embodiment. In this embodiment, the sampling period PWR(1) of the pixel 180E is different from the sampling period PWR(2) of the pixel 180F. The sampling period PWR(1) of the pixel 180E is longer than the sampling period PWR(2) of the pixel 180F. That is, the time during which the scanning signal G(2) and the scanning signal G(3) supplied to the pixel 180E overlap may be longer than the time during which the scanning signal G(3) and the scanning signal G(4) supplied to the pixel 180F overlap. For example, the timing at which the scanning signal G(2) turns off may be late, as long as it is before the timing at which the scanning signal G(4) turns on. The pulse width during which the scanning signal G(2) is on may be longer than that of other scanning signals G. The timing at which the scanning signal G(3) turns on may be early, as long as it is after the timing at which the scanning signal G(1) turns off. The pulse width during which the scanning signal G(3) is on may be longer than that of other scanning signals G. Here, the driving method of the pixel 180E arranged in the uppermost region 22E has been described. With a similar driving method, the pixel 180E arranged in the lowermost region 22E can be driven.

[0141] As shown in FIG. 18, in the present embodiment, the regions 22E at the upper and lower ends each include one row of pixels 180E. However, the present invention is not limited to this, and the regions 22E at the upper and lower ends may each include a plurality of rows of pixels 180E. In this case, the sampling period PWR of the pixel 180E arranged at the outermost end may be different from the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. The sampling period PWR of the pixel 180E arranged at the outermost end may be longer than the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. Within the region 22E, there may be a negative gradient from the sampling period PWR of the pixel 180E arranged at the outermost end to the sampling period PWR of the pixel 180E adjacent to the pixel 180F in the region 22F.

[0142] In the present embodiment, the sampling period PWR of the pixel 180E arranged in the region 22E is longer than the sampling period PWR of the pixel 180F arranged in the region 22F. When the sampling period PWR is long, the discharge in the sampling period PWR proceeds faster. Therefore, the voltage held in the capacitive element CS of the pixel 180E arranged in the region 22E becomes smaller than the voltage held in the capacitive element CS of the pixel 180F arranged in the region 22F. When this voltage is applied between the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows through the light-emitting element OLED of the pixel 180E arranged in the region 22E than through the light-emitting element OLED of the pixel 180F arranged in the region 22F. In this way, the phenomenon that the outermost end of the display region emits more brightly at low luminance can be eliminated, and the in-plane uniformity can be further improved. Further, the driving method of the self-luminous display device according to the present embodiment can be applied to the self-luminous display device according to the third embodiment or the fourth embodiment. By applying it to these self-luminous display devices, the phenomenon that the outermost periphery of the display region emits more brightly can be eliminated, and the in-plane uniformity can be further improved.

[0143] <6. Sixth Embodiment> Referring to FIG. 20, a self-luminous display device according to the sixth embodiment will be described. In the self-luminous display device 12 according to the sixth embodiment, the capacitances of the pixels 180 are substantially the same, and the configuration is the same as that of the self-luminous display device 10 described in the first embodiment, except that the driving methods of the upper and lower end pixels 180 (pixel circuits) by the scanning signal are different. In the self-luminous display device 12 according to the sixth embodiment, the sampling period PWR is substantially the same, and the driving method of the pixel 180 (pixel circuit) is the same as that described in the fifth embodiment, except that the driving voltages of the pixels 180 (pixel circuits) are different. Regarding the configurations that are the same as or similar to the configurations of the self-luminous display devices described in the first and fifth embodiments, and the configurations that are the same as or similar to FIGS. 1 to 19, the description here will be omitted.

[0144] <6-1. Driving Method of Self-Luminous Display Device 12> Referring to FIG. 20, the driving method of the self-luminous display device 12 according to the sixth embodiment will be described. FIG. 20 is a schematic diagram showing the timing chart of the self-luminous display device 12 according to the sixth embodiment. In this embodiment, the High voltage of the sampling period PWR(1) of the pixel 180E is different from the High voltage of the sampling period PWR(2) of the pixel 180F. The High voltage of the sampling period PWR(1) of the pixel 180E is greater than the High voltage of the sampling period PWR(2) of the pixel 180F. That is, the voltages of the scanning signal G(2) and the scanning signal G(3) during the period when the scanning signal G(2) and the scanning signal G(3) supplied to the pixel 180E overlap may be greater than the voltages of the scanning signal G(3) and the scanning signal G(4) supplied to the pixel 180F during the period when the scanning signal G(3) and the scanning signal G(4) supplied to the pixel 180F overlap. For example, over-drive may be applied to the voltages of the scanning signal G(2) and the scanning signal G(3) during the period when the scanning signal G(2) and the scanning signal G(3) supplied to the pixel 180E overlap to increase the voltage. Here, the driving method of the pixel 180E arranged in the uppermost region 22E has been described. With the same driving method, the pixel 180E arranged in the lowermost region 22E can be driven.

[0145] As shown in FIG. 18, in the present embodiment, the upper and lower end regions 22E each include one row of pixels 180E. However, it is not limited to this, and the upper and lower end regions 22E may each include a plurality of rows of pixels 180E. In this case, the voltage of the sampling period PWR of the pixel 180E arranged at the outermost end may be different from the voltage of the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. The voltage of the sampling period PWR of the pixel 180E arranged at the outermost end may be greater than the voltage of the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. Within the region 22E, it may have a negative gradient from the voltage of the sampling period PWR of the pixel 180E arranged at the outermost end to the voltage of the sampling period PWR of the pixel 180E adjacent to the pixel 180F in the region 22F.

[0146] In the present embodiment, the voltage during the sampling period PWR of the pixel 180E disposed in the region 22E is greater than the voltage during the sampling period PWR of the pixel 180F disposed in the region 22F. When the voltage during the sampling period PWR is high, the voltage between the gate and drain (gate electrode 632 and first electrode 634) of the third transistor T3 when the third transistor T3 is in the off state causes the voltage of the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitive element CS to decrease (drop through). Therefore, the voltage held in the capacitive element CS of the pixel 180E disposed in the region 22E becomes smaller than the voltage held in the capacitive element CS of the pixel 180F disposed in the region 22F. When this voltage is applied between the gate and source between the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows through the light-emitting element OLED of the pixel 180E disposed in the region 22E than through the light-emitting element OLED of the pixel 180F disposed in the region 22F. In this way, the phenomenon that the outermost edge of the display region emits light more brightly at low luminance can be eliminated, and the in-plane uniformity can be further improved. Further, the driving method of the self-emission type display device according to the present embodiment can be applied to the self-emission type display device according to the third or fourth embodiment. By applying this to these self-emission type display devices, the phenomenon that the outermost periphery of the display region emits light more brightly can be eliminated, and the in-plane uniformity can be further improved.

[0147] <7. Seventh Embodiment> With reference to FIGS. 21 to 34, an example of a manufacturing method, electrical characteristics, and pixel circuit of the semiconductor device 40 used in the self-emission type display device according to the seventh embodiment will be described. FIGS. 21 and 22 are a cross-sectional view and a plan view showing an outline of the semiconductor device 40 used in the self-emission type display device according to an embodiment of the present invention. FIG. 23 is a sequence diagram showing a manufacturing method of the semiconductor device 40. FIGS. 24 to 32 are cross-sectional views showing a manufacturing method of the semiconductor device 40. FIG. 33 is a graph showing an example of the electrical characteristics of the semiconductor device 40 and an example of the electrical characteristics of a semiconductor device of a comparative example. FIG. 34 is a schematic diagram showing a configuration of a pixel circuit using the semiconductor device 40. Descriptions of configurations identical or similar to those in FIGS. 1 to 20 are omitted here.

[0148] In the description of the seventh embodiment, the direction from the substrate toward the oxide semiconductor layer is referred to as up or upward, and the direction from the oxide semiconductor layer toward the substrate is referred to as down or downward. Further, in the description of the seventh embodiment, for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical positions are reversed. The expression "oxide semiconductor layer on the substrate" merely explains the vertical relationship between the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. The expressions "upward" or "downward" mean the stacking order in a structure in which a plurality of layers are stacked. For example, when referring to a pixel electrode above a transistor, in a plan view, the positional relationship between the transistor and the pixel electrode may be a non-overlapping positional relationship. On the other hand, when referring to a pixel electrode directly above the transistor in the vertical direction, in a plan view, it means a positional relationship in which the transistor and the pixel electrode overlap.

[0149] <7-1. Configuration of Semiconductor Device 40> As shown in FIG. 21, the semiconductor device 40 is provided above the substrate 400. The semiconductor device 40 includes a gate electrode 405, gate insulating layers 410 and 420, a metal oxide layer 430, an oxide semiconductor layer 440, a gate insulating layer 450, a gate electrode 460, insulating layers 470 and 480, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as a source-drain electrode 200.

[0150] The gate electrode 405 is provided on the substrate 400. The gate insulating layer 410 and the gate insulating layer 420 are provided on the substrate 400 and the gate electrode 405. The metal oxide layer 430 is provided on the gate insulating layer 420. The metal oxide layer 430 is in contact with the gate insulating layer 420. The oxide semiconductor layer 440 is provided on the metal oxide layer 430. The oxide semiconductor layer 440 is in contact with the metal oxide layer 430. Of the main surfaces of the oxide semiconductor layer 440, the surface in contact with the metal oxide layer 430 is referred to as a lower surface 442. The ends of the metal oxide layer 430 and the ends of the oxide semiconductor layer 440 substantially coincide.

[0151] In the seventh embodiment, a semiconductor layer or an oxide semiconductor layer is not provided between the metal oxide layer 430 and the substrate 400.

[0152] In the seventh embodiment, a configuration in which the metal oxide layer 430 is in contact with the gate insulating layer 420 and the oxide semiconductor layer 440 is in contact with the metal oxide layer 430 is illustrated, but the present invention is not limited to this configuration. Another layer may be provided between the gate insulating layer 420 and the metal oxide layer 430. Another layer may be provided between the metal oxide layer 430 and the oxide semiconductor layer 440.

[0153] In FIG. 21, the side wall of the metal oxide layer 430 and the side wall of the oxide semiconductor layer 440 are arranged in a straight line, but the present invention is not limited to this configuration. The angle of the side wall of the metal oxide layer 430 with respect to the main surface of the substrate 400 may be different from the angle of the side wall of the oxide semiconductor layer 440. The cross-sectional shape of the side wall of at least one of the metal oxide layer 430 and the oxide semiconductor layer 440 may be curved.

[0154] The gate electrode 460 faces the oxide semiconductor layer 440. The gate insulating layer 450 is provided between the oxide semiconductor layer 440 and the gate electrode 460. The gate insulating layer 450 is in contact with the oxide semiconductor layer 440. Among the main surfaces of the oxide semiconductor layer 440, the surface in contact with the gate insulating layer 450 is referred to as the upper surface 441. The surface between the upper surface 441 and the lower surface 442 is referred to as the side surface 443. The insulating layers 470 and 480 are provided on the gate insulating layer 450 and the gate electrode 460. The insulating layers 470 and 480 are provided with openings 471 and 473 that reach the oxide semiconductor layer 440. The source electrode 201 is provided inside the opening 471. The source electrode 201 is in contact with the oxide semiconductor layer 440 at the bottom of the opening 471. The drain electrode 203 is provided inside the opening 473. The drain electrode 203 is in contact with the oxide semiconductor layer 440 at the bottom of the opening 473.

[0155] The gate electrode 405 functions as the bottom gate of the semiconductor device 40 and as a light-shielding film for the oxide semiconductor layer 440. The gate insulating layer 410 functions as a barrier film that shields impurities diffusing from the substrate 400 toward the oxide semiconductor layer 440. The gate insulating layers 410 and 420 function as gate insulating layers for the bottom gate. The metal oxide layer 430 is a layer containing a metal oxide mainly composed of aluminum and functions as a gas barrier film that shields gases such as oxygen and hydrogen.

[0156] The oxide semiconductor layer 440 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is the region directly below the gate electrode 460 in the oxide semiconductor layer 440. The source region S is a region in the oxide semiconductor layer 440 that does not overlap with the gate electrode 460 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region in the oxide semiconductor layer 440 that does not overlap with the gate electrode 460 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 440 in the channel region CH has physical properties of a semiconductor. The oxide semiconductor layer 440 in the source region S and the drain region D has physical properties of a conductor.

[0157] The gate electrode 460 functions as the top gate of the semiconductor device 40 and as a light-shielding film for the oxide semiconductor layer 440. The gate insulating layer 450 functions as a gate insulating layer for the top gate and has a function of releasing oxygen by heat treatment in the manufacturing process. The insulating layers 470 and 480 insulate the gate electrode 460 from the source / drain electrodes 200 and have a function of reducing the parasitic capacitance between them. The operation of the semiconductor device 40 is mainly controlled by the voltage supplied to the gate electrode 460. An auxiliary voltage is supplied to the gate electrode 405. However, when the gate electrode 405 is simply used as a light-shielding film, no specific voltage needs to be supplied to the gate electrode 405, and it may be floating. That is, the gate electrode 405 may simply be called a "light-shielding film".

[0158] In the fourth embodiment, as the semiconductor device 40, a configuration in which a dual-gate transistor having gate electrodes provided both above and below the oxide semiconductor layer is used is exemplified, but the present invention is not limited to this configuration. For example, as the semiconductor device 40, a bottom-gate transistor having a gate electrode provided only below the oxide semiconductor layer or a top-gate transistor having a gate electrode provided only above the oxide semiconductor layer may be used. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0159] As shown in FIG. 22, in a plan view, the planar pattern of the metal oxide layer 430 is substantially the same as the planar pattern of the oxide semiconductor layer 440. Referring to FIGS. 21 and 22, the lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430. In particular, in the fourth embodiment, the entire lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430. In the D1 direction, the width of the gate electrode 405 is larger than the width of the gate electrode 460. The D1 direction is the direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the semiconductor device 40. Specifically, the length in the D1 direction of the region (channel region CH) where the oxide semiconductor layer 440 and the gate electrode 460 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0160] In the fourth embodiment, the configuration in which the entire lower surface 442 of the oxide semiconductor layer 440 is covered with the metal oxide layer 430 is illustrated, but the present invention is not limited to this configuration. For example, a part of the lower surface 442 of the oxide semiconductor layer 440 may not be in contact with the metal oxide layer 430. For example, the entire lower surface 442 of the oxide semiconductor layer 440 in the channel region CH may be covered with the metal oxide layer 430, and all or part of the lower surface 442 of the oxide semiconductor layer 440 in the source region S and the drain region D may not be covered with the metal oxide layer 430. That is, all or part of the lower surface 442 of the oxide semiconductor layer 440 in the source region S and the drain region D may not be in contact with the metal oxide layer 430. However, in the above configuration, a part of the lower surface 442 of the oxide semiconductor layer 440 in the channel region CH is not covered with the metal oxide layer 430, and the other part of the lower surface 442 may be in contact with the metal oxide layer 430.

[0161] In the fourth embodiment, the configuration in which the gate insulating layer 450 is formed over the entire surface and openings 471 and 473 are provided in the gate insulating layer 450 is illustrated, but the present invention is not limited to this configuration. The gate insulating layer 450 may be patterned into a shape different from the shape in which the openings 471 and 473 are provided. For example, the gate insulating layer 450 may be patterned so as to expose all or part of the oxide semiconductor layer 440 in the source region S and the drain region D. That is, the gate insulating layer 450 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 440 and the insulating layer 470 may be in contact with each other in these regions.

[0162] In FIG. 22, a configuration in which the source / drain electrode 200 does not overlap the gate electrode 405 and the gate electrode 460 in a plan view is illustrated, but the present invention is not limited to this configuration. For example, in a plan view, the source / drain electrode 200 may overlap at least one of the gate electrode 405 and the gate electrode 460. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0163] <7-2. Materials of Members of Semiconductor Device 40> As the substrate 400, a rigid substrate having translucency, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 400 needs to have flexibility, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate, is used as the substrate 400. When a substrate containing a resin is used as the substrate 400, impurities may be introduced into the above resin in order to improve the heat resistance of the substrate 400. In particular, when the semiconductor device 40 is used in a top emission type self-luminous display device, since the substrate 400 does not need to be transparent, impurities that deteriorate the transparency of the substrate 400 may be used.

[0164] As the gate electrodes 405, 460, and the source / drain electrodes 200, a general metal material is used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. As the gate electrodes 405, 460, and the source / drain electrodes 200, the above materials may be used in a single layer or in a stacked layer.

[0165] As the gate insulating layers 410, 420 and the insulating layers 470, 480, a general insulating material is used. For example, as these insulating layers, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers are used.

[0166] As the gate insulating layer 450, an insulating layer containing oxygen among the above-described insulating layers is used. For example, as the gate insulating layer 450, an inorganic insulating layer such as silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxynitride (AlO x N y ) is used.

[0167] As the gate insulating layer 420, an insulating layer having a function of releasing oxygen by heat treatment is used. The temperature of the heat treatment in which the gate insulating layer 420 releases oxygen is, for example, 600°C or lower, 500°C or lower, 450°C or lower, or 400°C or lower. That is, the gate insulating layer 420 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 40 when a glass substrate is used as the substrate 400, for example.

[0168] As the gate insulating layer 450, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 450 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 450 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 450 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layer 450 and the insulating layer 480, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 450 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 480. For example, as the gate insulating layer 450, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0169] The above SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio (x > y) less than that of oxygen (O). SiNx O y and AlN x O y is a silicon compound and an aluminum compound containing oxygen in a ratio less than that of nitrogen (x > y).

[0170] As the metal oxide layer 430 and the metal oxide layer 490 used in the manufacturing process as described later, a metal oxide mainly composed of aluminum is used. For example, as the metal oxide layer 430 (or the metal oxide layer 490), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers are used. The "metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer 430 (or the metal oxide layer 490) is 1% or more of the entire metal oxide layer 430 (or the metal oxide layer 490). The ratio of aluminum contained in the metal oxide layer 430 (or the metal oxide layer 490) may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 430. The above ratio may be a mass ratio or a weight ratio.

[0171] As the oxide semiconductor layer 440, a metal oxide having semiconductor characteristics can be used 。

[0172] The oxide semiconductor layer 440 may be amorphous or crystalline. Further, the oxide semiconductor layer 440 may be a mixed phase of amorphous and crystal 。Knot A crystalline oxide semiconductor is less likely to form oxygen vacancies than an amorphous oxide semiconductor 。

[0173] <7-3. Problems newly recognized in the process leading to the present invention > HalfIn the conductor device 40, in the heat treatment process of the manufacturing process, hydrogen is released from the layers (for example, gate insulating layers 410 and 420) provided closer to the substrate 400 side than the oxide semiconductor layer 440, and when this hydrogen reaches the oxide semiconductor layer 440, oxygen deficiency occurs in the oxide semiconductor layer 440. The occurrence of this oxygen deficiency is more prominent as the pattern size of the oxide semiconductor layer 440 is larger. In order to suppress the occurrence of such oxygen deficiency, it is necessary to suppress the reach of hydrogen to the lower surface 442 of the oxide semiconductor layer 440. The above content is the first problem.

[0174] Apart from the above problems, there is a second problem shown below. The upper surface 441 of the oxide semiconductor layer 440 is affected by the processes (for example, patterning process or etching process) after the oxide semiconductor layer 440 is formed. On the other hand, the lower surface 442 of the oxide semiconductor layer 440 (the surface on the substrate 400 side of the oxide semiconductor layer 440) is not affected by the above such influence.

[0175] Therefore, the oxygen deficiency formed on the upper surface 441 of the oxide semiconductor layer 440 is more than the oxygen deficiency formed on the lower surface 442 of the oxide semiconductor layer 440. That is, the oxygen deficiency in the oxide semiconductor layer 440 does not exist uniformly in the thickness direction of the oxide semiconductor layer 440, but exists in a non-uniform distribution in the thickness direction of the oxide semiconductor layer 440. Specifically, the oxygen deficiency in the oxide semiconductor layer 440 is less on the lower surface 442 side of the oxide semiconductor layer 440 and more on the upper surface 441 side of the oxide semiconductor layer 440.

[0176] When an oxygen supply process is uniformly performed on the oxide semiconductor layer 440 having the oxygen deficiency distribution as described above, if an amount of oxygen necessary for repairing the oxygen deficiency formed on the upper surface 441 side of the oxide semiconductor layer 440 is supplied, oxygen is excessively supplied to the lower surface 442 side of the oxide semiconductor layer 440. As a result, on the lower surface 442 side, defect levels different from oxygen deficiency are formed by the excessive oxygen, and phenomena such as characteristic variations in the reliability test or a decrease in the field-effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface 441 side of the oxide semiconductor layer 440 while suppressing the oxygen supply to the lower surface 442 side of the oxide semiconductor layer 440.

[0177] The above problems are problems newly recognized in the process leading to the present invention and are not problems conventionally recognized. In the conventional configuration and manufacturing method, even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer, there is a trade-off relationship between the initial characteristics and the reliability test in that characteristic variations occur due to the reliability test. However, with the configuration according to the fourth embodiment, the above problems are solved, and good initial characteristics and reliability test results of the semiconductor device 40 can be obtained.

[0178] <7-4. Manufacturing Method of Semiconductor Device 40> The manufacturing method of the semiconductor device 40 will be described with reference to FIGS. 23 to 32. Here, an example of the manufacturing method of the semiconductor device 40 in which aluminum oxide is used as the metal oxide layers 430 and 490 will be described.

[0179] As shown in FIGS. 23 and 24, a gate electrode 405 is formed as a bottom gate on a substrate 400, and gate insulating layers 410 and 420 are formed on the gate electrode 405 ("Bottom GI / GE formation" in step S2001 of FIG. 23). As the gate insulating layer 410, for example, silicon nitride is formed. As the gate insulating layer 420, for example, silicon oxide is formed. The gate insulating layers 410 and 420 are formed by a CVD (Chemical Vapor Deposition) method. One or both of the gate insulating layers 410 and 420 may be referred to as the "first insulating layer".

[0180] By using silicon nitride as the gate insulating layer 410, the gate insulating layer 410 can block impurities that diffuse, for example, from the substrate 400 side toward the oxide semiconductor layer 440. The silicon oxide used as the gate insulating layer 420 is a silicon oxide having a physical property of releasing oxygen by heat treatment.

[0181] As shown in FIGS. 23 and 24, a metal oxide layer 430 and an oxide semiconductor layer 440 are formed on the gate insulating layer 420 ("OS / AlOx film formation" in step S2002 of FIG. 23). Regarding this step, it may be called that the gate insulating layers 410 and 420 are formed on the substrate 400 and the metal oxide layer 430 is formed on the gate insulating layers 410 and 420. Or, it may be the case that the metal oxide layer 430 is formed on the substrate 400 and the oxide semiconductor layer 440 is formed on the metal oxide layer 430. Specifically, the oxide semiconductor layer 440 is formed so as to be in contact with the metal oxide layer 430. The metal oxide layer 430 and the oxide semiconductor layer 440 are formed by a sputtering method or an atomic layer deposition method (ALD: Atomic Layer Deposition).

[0182] The thickness of the metal oxide layer 430 is, for example, 1 nm or more and 100 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 30 nm or less, or 1 nm or more and 10 nm or less. In the fourth embodiment, aluminum oxide is used as the metal oxide layer 430. Aluminum oxide has a high barrier property against gases. In the fourth embodiment, the aluminum oxide used as the metal oxide layer 430 blocks hydrogen and oxygen released from the gate insulating layer 420 and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 440.

[0183] The thickness of the oxide semiconductor layer 440 is, for example, 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. 。

[0184] S When the oxide semiconductor layer 440 is formed by a patterning method, the oxide semiconductor layer 440 is formed while controlling the temperature of the object to be film-formed (the substrate 400 and the structure formed thereon).

[0185] When film formation is performed on the object to be film-formed by a sputtering method, ions generated in the plasma and atoms rebounded by the sputtering target collide with the object to be film-formed, so the temperature of the object to be film-formed rises with the film formation process. 。Upper In order to control the temperature of the object to be film-formed as described above, for example, film formation can be performed while cooling the object to be film-formed. For example, the object to be film-formed can be cooled from the surface opposite to the surface to be film-formed (hereinafter referred to as the "film formation temperature") so that the temperature of the surface to be film-formed (surface) of the object to be film-formed becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. 。

[0186] As shown in FIGS. 23 and 26, a pattern of the oxide semiconductor layer 440 is formed (``OS pattern formation'' in step S2003 of FIG. 23). Although not shown, a resist mask is formed on the oxide semiconductor layer 440, and the oxide semiconductor layer 440 is etched using the resist mask. As the etching of the oxide semiconductor layer 440, wet etching may be used, or dry etching may be used. As the wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0187] After the pattern formation of the oxide semiconductor layer 440, heat treatment (OS annealing) is performed on the oxide semiconductor layer 440 (``OS annealing'' in step S2004 of FIG. 23) 。

[0188] As shown in FIGS. 23 and 27, a pattern of the metal oxide layer 430 is formed (``AlO x pattern formation'' in step S2005 of FIG. 23) 。Gold As the etching of the metal oxide layer 430, wet etching may be used, or dry etching may be used 。

[0189] As shown in FIGS. 23 and 28, a gate insulating layer 450 is formed on the oxide semiconductor layer 440 (``GI formation'' in step S2006 of FIG. 23). For example, silicon oxide is formed as the gate insulating layer 450. The gate insulating layer 450 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above as the gate insulating layer 450, the gate insulating layer 450 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 450 is, for example, 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less. After forming the gate insulating layer 450, a process of implanting oxygen into a part of the gate insulating layer 450 may be performed. The gate insulating layer 450 may be referred to as the ``second insulating layer''. A metal oxide layer 490 is formed on the gate insulating layer 450 (``AlOx film formation'' in step S2007 of FIG. 23). The metal oxide layer 490 is formed by a sputtering method. By forming the metal oxide layer 490, oxygen is implanted into the gate insulating layer 450.

[0190] The thickness of the metal oxide layer 490 is, for example, 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less. In the fourth embodiment, aluminum oxide is used as the metal oxide layer 490. Aluminum oxide has a high barrier property against gas. In the fourth embodiment, the aluminum oxide used as the metal oxide layer 490 suppresses the outward diffusion of the oxygen implanted into the gate insulating layer 450 during the film formation of the metal oxide layer 490.

[0191] For example, when the metal oxide layer 490 is formed by a sputtering method, the process gas used in sputtering remains in the film of the metal oxide layer 490. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 490. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 490.

[0192] A gate insulating layer 450 is formed over the oxide semiconductor layer 440, and a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 440 in a state where a metal oxide layer 490 is formed over the gate insulating layer 450 (the "oxidation annealing" in step S2008 of FIG. 23). In other words, a heat treatment (oxidation annealing) is performed on the metal oxide layer 430 and the oxide semiconductor layer 440 patterned as described above. In the process from when the oxide semiconductor layer 440 is formed until the gate insulating layer 450 is formed over the oxide semiconductor layer 440, many oxygen deficiencies occur on the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440. By the above oxidation annealing, oxygen released from the gate insulating layers 420 and 450 is supplied to the oxide semiconductor layer 440, and the oxygen deficiencies are repaired.

[0193] By oxidation annealing, oxygen released from the gate insulating layer 420 is blocked by the metal oxide layer 430, so it is difficult for oxygen to be supplied to the lower surface 442 of the oxide semiconductor layer 440. Oxygen released from the gate insulating layer 420 diffuses from a region where the metal oxide layer 430 is not formed to the gate insulating layer 450 provided over the gate insulating layer 420, and reaches the oxide semiconductor layer 440 through the gate insulating layer 450. As a result, oxygen released from the gate insulating layer 420 is difficult to be supplied to the lower surface 442 of the oxide semiconductor layer 440, and is mainly supplied to the side surface 443 and the upper surface 441 of the oxide semiconductor layer 440. Further, by oxidation annealing, oxygen released from the gate insulating layer 450 is supplied to the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440. By the above oxidation annealing, hydrogen may be released from the gate insulating layers 410 and 420, but the hydrogen is blocked by the metal oxide layer 430.

[0194] As described above, by the oxidation annealing step, it is possible to supply oxygen to the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440 where the amount of oxygen deficiency is large, while suppressing the supply of oxygen to the lower surface 442 of the oxide semiconductor layer 440 where the amount of oxygen deficiency is small.

[0195] Similarly, in the above-described oxidation annealing, oxygen implanted into the gate insulating layer 450 is blocked by the metal oxide layer 490, so that release into the atmosphere is suppressed. Therefore, by the oxidation annealing, the oxygen is efficiently supplied to the oxide semiconductor layer 440, and oxygen deficiency is repaired.

[0196] As shown in FIGS. 23 and 29, after the oxidation annealing, the metal oxide layer 490 is etched (removed) ("AlOx removal" in step S2009 of FIG. 23). As the etching of the metal oxide layer 490, wet etching may be used, or dry etching may be used. As the wet etching, for example, diluted hydrofluoric acid (DHF) is used. By the etching, the metal oxide layer 490 formed over the entire surface is removed. In other words, the removal of the metal oxide layer 490 is performed without using a mask. Further in other words, by the etching, all of the metal oxide layers 490 in the region overlapping the oxide semiconductor layer 440 formed in a certain pattern are removed at least in plan view.

[0197] As shown in FIGS. 23 and 30, a gate electrode 460 is formed over the gate insulating layer 450 ("GE formation" in step S2010 of FIG. 23). The gate electrode 460 is formed by a sputtering method or an atomic layer deposition method and patterned through a photolithography process. As described above, the gate electrode 460 is formed to be in contact with the gate insulating layer 450 exposed by the removal of the metal oxide layer 490.

[0198] With the gate electrode 460 patterned, the source region S and the drain region D of the oxide semiconductor layer 440 are made to have lower resistance (the "SD lower resistance" in step S2011 of FIG. 23). Specifically, impurities are implanted into the oxide semiconductor layer 440 from the gate electrode 460 side through the gate insulating layer 450 by ion implantation. By ion implantation, for example, argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 440. Oxygen vacancies are formed in the oxide semiconductor layer 440 by ion implantation, thereby reducing the resistance of the oxide semiconductor layer 440. Since the gate electrode 460 is provided above the oxide semiconductor layer 440 that functions as the channel region CH of the semiconductor device 40, no impurities are implanted into the oxide semiconductor layer 440 of the channel region CH.

[0199] As shown in FIGS. 23 and 31, insulating layers 470 and 480 are formed as interlayer films on the gate insulating layer 450 and the gate electrode 460 (the "interlayer film formation" in step S2012 of FIG. 23). The insulating layers 470 and 480 are formed by CVD. For example, silicon nitride is formed as the insulating layer 470, and silicon oxide is formed as the insulating layer 480. The materials used for the insulating layers 470 and 480 are not limited to the above. The thickness of the insulating layer 470 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 480 is 50 nm or more and 500 nm or less.

[0200] As shown in FIGS. 23 and 32, openings 471 and 473 are formed in the gate insulating layer 450 and the insulating layers 470 and 480 (the "contact opening" in step S2013 of FIG. 23). The oxide semiconductor layer 440 of the source region S is exposed by the opening 471. The oxide semiconductor layer 440 of the drain region D is exposed by the opening 473. By forming the source / drain electrode 200 on the oxide semiconductor layer 440 exposed by the openings 471 and 473 and on the insulating layer 480 (the "SD formation" in step S2044 of FIG. 23), the semiconductor device 40 shown in FIG. 23 is completed. 。

[0201] <7-5. Configuration of Pixel 180> Referring to FIG. 33, the pixel circuit 183 according to the seventh embodiment will be described. The semiconductor device 40 is used for the channel region CH of the second transistor OT2 in the pixel circuit shown in FIG. 33. The second transistor OT2 is a transistor called a so-called driving transistor. The channel region CH of the second transistor OT2 according to the seventh embodiment is formed using the oxide semiconductor layer 440, while the channel region of the second transistor TR according to the first embodiment is formed using, for example, a low-temperature poly-silicon layer (LTPS layer) or an oxide semiconductor layer having characteristics different from those of the oxide semiconductor layer 440.

[0202] Note that the pixel circuit according to the fourth embodiment shown in FIG. 33 is a circuit in which the second transistor T2 of the pixel circuit 181 according to the first embodiment described with reference to FIG. 4 is replaced with the second transistor OT2 formed using the semiconductor device 40. The configuration and functions of the pixel circuit according to the seventh embodiment other than the second transistor OT2 are the same as those of the pixel circuit 181 according to the first embodiment described with reference to FIG. 4. Therefore, the description here is omitted. Note that the channel regions of transistors other than the second transistor OT2 (the first transistor T1, the third transistor T3 to the seventh transistor T7) are formed using, for example, a low-temperature poly-silicon layer (LTPS layer), but are not limited to this configuration. The semiconductor device 40 may be used for the channel region CH of the third transistor T3 in the pixel circuit shown in FIG. 33.

[0203] Each of the above-described embodiments or a part of each embodiment as an embodiment of the present invention can be implemented in appropriate combination as long as they do not contradict each other.

[0204] Even if there are other operational effects different from the operational effects brought about by the aspects of the above-described embodiments, those that are obvious from the description in this specification or can be easily predicted by those skilled in the art are naturally considered to be brought about by the present invention.

Description of Reference Numerals

[0205] 10 Self-luminous display device, 22 Display area, 24 Peripheral area, 26 Terminal area, 40 Semiconductor device, 100 Array substrate, 110 Source driver circuit, 112 Selection circuit, 114 Input terminal, 116 Output terminal, 118 Switch, 120 Gate driver circuit, 121 Shift register, 130 Light emission control circuit, 131 Shift register, 150 Terminal section, 160 Flexible printed circuit board, 170 Chip, 180 Pixel, 181 Pixel circuit, 200 Source-drain electrode, 201 Source electrode, 203 Drain electrode, 321 Image data signal line, 329 - 332 Scanning signal lines, 334 - 337 Light emission control signal lines, 341 Connection wiring, 400 Substrate, 405 Gate electrode, 410 Gate insulating layer, 420 Gate insulating layer, 430 Metal oxide layer, 440 Oxide semiconductor layer, 450 Gate insulating layer, 460 Gate electrode, 470 Insulating layer, 480 Insulating layer, 490 Metal oxide layer

Claims

1. a substrate having a display area; a first pixel arranged in a first region on the outer edge of the display region, and a second pixel arranged in a second region surrounded by the first region, Each of the first pixel and the second pixel is a first transistor (T1) controlled by a second control signal (Scan2, G(n+1)) obtained by shifting a first control signal (Scan1, G(n)), and electrically connected between an image data signal line (321) and a first node (N1); a second transistor (T2, a drive transistor) electrically connected between the first node and a second node (N2); a first capacitance element electrically connected to a gate electrode of the second transistor; a third transistor (T3) electrically connected between the second node and the gate electrode of the second transistor, the third transistor (T3) being controlled to supply a threshold voltage of the second transistor to the gate electrode of the second transistor and the first capacitance element using the first control signal obtained by shifting a third control signal (Scan3, G(n-1)); a seventh transistor (T7) electrically connected to the second node, the gate electrode of the second transistor, and the first capacitance element, the seventh transistor being controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitance element using the third control signal; A self-luminous display device (10), in which the capacitance of a capacitance section connected to the gate electrode of the second transistor of the first pixel is different from the capacitance of a capacitance section connected to the gate electrode of the second transistor of the second pixel.

2. 2. The self-luminous display device according to claim 1, further comprising a control circuit that sequentially shifts and outputs the third control signal, the first control signal, and the second control signal.

3. A light emitting element (OLED) electrically connected to a reference voltage line (PVSS) to which a reference voltage (VSSEL) is supplied; a fourth transistor (T4) controlled by a fourth control signal (EM2, ES) and electrically connected between a drive power supply line (PVDD) to which a drive voltage is supplied and the second node; a fifth transistor (T5) controlled by the fourth control signal (EM2, ES) and electrically connected to the light emitting element and the first node; a sixth transistor (T6) electrically connected to the light emitting element and controlled to supply an initialization voltage to the light emitting element, a terminal of the fifth transistor connected to the light emitting element, and the first capacitance element; 3. The self-luminous display device according to claim 2, further comprising a light emission control circuit (130) that controls a timing for supplying the fourth control signal to the fourth transistor and the fifth transistor.

4. the capacitance portion is the first capacitance element, 4. The self-luminous display device according to claim 3, wherein a capacitance of the first capacitance element of the first pixel is smaller than a capacitance of the first capacitance element of the second pixel.

5. the capacitance portion is the third transistor, 4. The self-luminous display device according to claim 3, wherein a capacitance between the gate and drain of the third transistor of the first pixel is larger than a capacitance between the gate and drain of the third transistor of the second pixel.

6. the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor are n-channel type field effect transistors, and the fourth transistor and the fifth transistor are p-channel type field effect transistors; the sixth transistor is controlled using the fourth control signal; 6. The self-luminous display device according to claim 4.

7. the light emission control circuit supplies an ON signal to the fourth control signal; the control circuit supplies an on signal to the third control signal, supplies an on signal to the first control signal, supplies an off signal to the second control signal, and supplies the reset voltage to the second node, the gate electrode, and the first capacitive element; 7. The self-luminous display device according to claim 6.

8. the light emission control circuit supplies an ON signal to the fourth control signal; the control circuit supplies an OFF signal to the third control signal, supplies an ON signal to the first control signal, supplies an ON signal to the second control signal, and supplies image data signals from the image data signal line to the first node, the second node, and the gate electrode; 7. The self-luminous display device according to claim 6.

9. the light emission control circuit supplies an off signal to the fourth control signal, the control circuit supplies an OFF signal to the third control signal, supplies an OFF signal to the first control signal, supplies an OFF signal to the second control signal, and supplies an image data signal from the image data signal line to the first node and the light emitting element; 7. The self-luminous display device according to claim 6.

10. a channel region of each of the fourth transistor, the fifth transistor, and the sixth transistor includes low temperature polysilicon; a channel region of the second transistor includes an oxide semiconductor; 7. The self-luminous display device according to claim 6.

11. a substrate having a display area; a third pixel arranged in a third region including one end of the display region; and a fourth pixel arranged in a fourth region adjacent to the third region, Each of the third pixel and the fourth pixel is a first transistor controlled by a second control signal obtained by shifting a first control signal, the first transistor being electrically connected between an image data signal line and a first node; a second transistor electrically connected between the first node and a second node; a first capacitance element electrically connected to a gate electrode of the second transistor; a third transistor, which is controlled to supply a threshold voltage of the second transistor to a gate electrode of the second transistor and the first capacitive element by using the first control signal obtained by shifting a third control signal, and is electrically connected between the second node and the gate electrode of the second transistor; a seventh transistor that is controlled to supply a reset voltage to the second node, a gate electrode of the second transistor, and the first capacitance element using the third control signal, and is electrically connected to the second node; A self-luminous display device, wherein a capacitance of a capacitive section connected to the image data signal line connected to the third pixel is different from a capacitance of a capacitive section connected to the image data signal line connected to the fourth pixel.

12. a fifth pixel disposed in a fifth region including one end of the display region and the other end opposite the one end of the display region; The fifth pixel is a first transistor controlled by a second control signal obtained by shifting a first control signal, the first transistor being electrically connected between an image data signal line and a first node; a second transistor electrically connected between the first node and a second node; a first capacitance element electrically connected to a gate electrode of the second transistor; a third transistor, which is controlled to supply a threshold voltage of the second transistor to a gate electrode of the second transistor and the first capacitive element by using the first control signal obtained by shifting a third control signal, and is electrically connected between the second node and the gate electrode of the second transistor; a seventh transistor that is controlled to supply a reset voltage to the second node, a gate electrode of the second transistor, and the first capacitance element using the third control signal, and is electrically connected to the second node; The self-luminous display device according to claim 11 , wherein a capacitance of a capacitance section connected to the image data signal line connected to the fifth pixel is different from a capacitance of a capacitance section connected to the image data signal line connected to the fourth pixel.

13. 13. The self-luminous display device according to claim 12, wherein a capacitance of a capacitance section connected to the image data signal line connected to the third pixel is the same as a capacitance of a capacitance section connected to the image data signal line connected to the fifth pixel.

14. a light emitting element electrically connected to a reference voltage line to which a reference voltage is supplied; a fourth transistor controlled by a fourth control signal and electrically connected between a drive power supply line to which a drive voltage is supplied and the second node; a fifth transistor controlled by the fourth control signal and electrically connected to the light emitting element and the first node; a sixth transistor electrically connected to the light emitting element and controlled to supply an initialization voltage to the light emitting element, a terminal of the fifth transistor connected to the light emitting element, and the first capacitance element; a light emission control circuit that controls a timing at which the fourth control signal is supplied to the fourth transistor and the fifth transistor, The self-luminous display device according to claim 13 , wherein the third control signal, the first control signal, and the second control signal are sequentially shifted and output.

15. the capacitance portion is a second capacitance element connected to the image data signal line, 15. The self-luminous display device according to claim 14, wherein a capacitance of the second capacitance element connected to the image data signal line of the third pixel is larger than a capacitance of the second capacitance element connected to the image data signal line of the fourth pixel.

16. the capacitance section is a selection circuit connected to the image data signal line, 15. The self-luminous display device according to claim 14, wherein a capacitance between the gate and drain of the selection circuit connected to the image data signal line of the third pixel is larger than a capacitance between the gate and drain of the selection circuit connected to the image data signal line of the fourth pixel.

17. The third pixels are arranged in a plurality of the third regions and share at least one of the image data signal lines; The self-luminous display device according to claim 15 , wherein a plurality of the fourth pixels are arranged in the fourth region and share at least one of the image data signal lines.

18. the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor are n-channel type field effect transistors, and the fourth transistor and the fifth transistor are p-channel type field effect transistors; the sixth transistor is controlled using the fourth control signal; The self-luminous display device according to claim 17.

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