Mother substrate for display devices and method for manufacturing display device

Abstract

To provide a mother board for display devices and a method for manufacturing the display device with which it is possible to improve the accuracy of inspecting adjacent shorting.SOLUTION: A mother substrate for display devices according to one embodiment comprises: a plurality of inspection pads disposed for inspecting a plurality of touch electrodes included in a touch panel to see if two mutually adjacent touch electrodes among these are shorted; a first high resistance wiring for connecting the plurality of inspection pads to each other; a first cut line which is set in order to cut out multiple display devices from the mother substrate for display devices; and a second cut line which is set along the outer shape of a single display device. The first high resistance wiring is laid so as to cross the first cut line and is cut off along the first cut line before inspection is carried out using the plurality of inspection pads. The plurality of inspection pads are connected to each other by the first high resistance wiring on the occasion of inspection.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] An embodiment of the present invention relates to a mother substrate for a display device and a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. The display elements include a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] A display device may be equipped with a touch panel that detects user operations on a display area. In manufacturing such a display device with a touch panel, it is necessary to inspect whether two adjacent electrodes among a plurality of electrodes that constitute the touch panel are short-circuited. This inspection is called adjacent short inspection, and a technology to improve the accuracy of this inspection is required. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-159003 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a motherboard for a display device and a method for manufacturing a display device, which are capable of improving the accuracy of an adjacent short circuit inspection. [Means for solving the problem]

[0006] In one embodiment of the display device mother substrate, a plurality of display devices are formed, each including a display panel having a display area for displaying an image, and a touch panel having a plurality of touch electrodes overlapping the display area. The display device mother substrate includes a plurality of test pads provided for each display device in order to test whether two adjacent touch electrodes among the plurality of touch electrodes are shorted, a first high resistance wiring connecting the plurality of test pads to each other, a first cut line set for cutting out a plurality of display devices from the display device mother substrate, and a second cut line set along the outer shape of a single display device. Each of the plurality of test pads is disposed between the first cut line and the second cut line, and is electrically connected to the corresponding touch electrode for the test. The first high resistance wiring is disposed so as to straddle the first cut line, and is cut along the first cut line before the test using the plurality of test pads. The plurality of test pads are not connected to each other by the first high resistance wiring during the test.

[0007] A method for manufacturing a display device according to one embodiment is a method for manufacturing a single display device from a mother substrate for a display device on which a plurality of display devices are formed, each of which includes a display panel having a display area for displaying an image and a touch panel having a plurality of touch electrodes overlapping the display area, the mother substrate for a display device being provided with a first cut line and a second cut line, a plurality of test pads arranged between the first cut line and the second cut line and provided for each of the display devices, and a first high resistance wiring connecting the plurality of test pads to each other. The method for manufacturing a display device includes cutting the mother substrate for a display device along the first cut line set to cross the first high resistance wiring, cutting out a plurality of display devices from the mother substrate for a display device, inspecting whether two adjacent touch electrodes among the plurality of touch electrodes are shorted using the plurality of test pads, and cutting the plurality of display devices along the second cut line after the inspection to form an outer shape of a single display device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view showing a schematic configuration example of a display device according to an embodiment. [Diagram 2] FIG. 2 is a plan view showing a schematic configuration example of the touch panel according to the embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing a schematic configuration example of the display device according to the embodiment. [Figure 4] FIG. 4 is a plan view for explaining an example of a configuration for inspecting adjacent short circuits in a touch panel. [Diagram 5] FIG. 5 is a plan view for explaining an example of a configuration for inspecting adjacent short circuits in the touch panel according to the embodiment. [Figure 6] FIG. 6 is a plan view showing a schematic configuration example of a mother substrate for a display device according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing a schematic configuration example of the display device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. In addition, the disclosure is merely an example, and the invention is not limited to the contents described in the following embodiments. Modifications that a person skilled in the art can easily conceive are naturally included in the scope of the disclosure. In order to make the explanation clearer, the size, shape, etc. of each part may be changed from the actual embodiment and shown diagrammatically. In multiple drawings, corresponding elements may be given the same reference numerals, and detailed explanations may be omitted.

[0010] In the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction, the direction along the Y-axis is called the second direction, and the direction along the Z-axis is called the third direction. The third direction Z is a normal direction to a plane that includes the first direction X and the second direction Y. Moreover, viewing various elements parallel to the third direction Z is called planar view.

[0011] The display device according to the present embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, wearable terminals, etc. The display device according to the present embodiment is a display device with a touch panel that has a touch panel capable of detecting a user's operation on the display area.

[0012] 1 is a perspective view showing an example of a schematic configuration of a display device DSP according to this embodiment. The display device DSP includes a display panel PNL, a touch panel TP, a first wiring board FPC1, and a second wiring board FPC2. The display panel PNL includes a first board SUB1. The display panel PNL has a display area DA that displays an image, and a peripheral area PA that surrounds the display area DA.

[0013] The display panel PNL has a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y in a display area DA. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0016] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The first substrate SUB1 has a mounting area MA. A first wiring substrate FPC1 and a second wiring substrate FPC2 are arranged in the mounting area MA. A display controller CT1 that executes control related to image display is provided on the first wiring substrate FPC1.

[0018] The touch panel TP is disposed so as to be superimposed on the display area DA of the display panel PNL. The touch panel TP has a plurality of touch electrodes, the details of which will be described later. These touch electrodes are electrically connected to the second wiring board FPC2. The second wiring board FPC2 is provided with a detection controller CT2 that executes control related to touch detection.

[0019] The display controller CT1 and the detection controller CT2 are configured, for example, by ICs. Although the display controller CT1 and the detection controller CT2 are mounted on separate wiring boards in FIG. 1, these controllers CT1 and CT2 may be mounted on the same wiring board.

[0020] Fig. 2 is a plan view showing an example of a schematic configuration of a touch panel TP according to this embodiment. As shown in Fig. 2, the touch panel TP has a plurality of touch electrodes TX. In the example of Fig. 2, 16 touch electrodes TX1 to TX16 (4 rows x 4 columns) are arranged in a matrix. Of the touch electrodes TX1 to TX16, touch electrodes TX1 to TX8 are located in the left half of the figure, and touch electrodes TX9 to TX16 are located in the right half of the figure.

[0021] 2, the touch electrode TX1 is arranged adjacent to the touch electrodes TX2 and TX16 along the first direction X. The touch electrode TX1 is arranged adjacent to the touch electrode TX3 along the second direction Y.

[0022] The touch electrode TX2 is arranged adjacent to the touch electrode TX1 along the first direction X. The touch electrode TX2 is arranged adjacent to the touch electrode TX4 along the second direction Y.

[0023] The touch electrode TX3 is arranged adjacent to the touch electrodes TX4 and TX14 along the first direction X. The touch electrode TX3 is arranged adjacent to the touch electrodes TX1 and TX5 along the second direction Y.

[0024] The touch electrode TX4 is arranged adjacent to the touch electrode TX3 along the first direction X. The touch electrode TX4 is arranged adjacent to the touch electrodes TX2 and TX6 along the second direction Y.

[0025] The touch electrode TX5 is arranged adjacent to the touch electrodes TX6 and TX12 along the first direction X. The touch electrode TX5 is arranged adjacent to the touch electrodes TX3 and TX7 along the second direction Y.

[0026] The touch electrode TX6 is arranged adjacent to the touch electrode TX5 along the first direction X. The touch electrode TX6 is arranged adjacent to the touch electrodes TX4 and TX8 along the second direction Y.

[0027] The touch electrode TX7 is arranged adjacent to the touch electrodes TX8 and TX10 along the first direction X. The touch electrode TX7 is arranged adjacent to the touch electrode TX5 along the second direction Y.

[0028] The touch electrode TX8 is arranged adjacent to the touch electrode TX7 along the first direction X. The touch electrode TX8 is arranged adjacent to the touch electrode TX6 along the second direction Y.

[0029] The touch electrode TX9 is arranged adjacent to the touch electrode TX10 along the first direction X. The touch electrode TX9 is arranged adjacent to the touch electrode TX11 along the second direction Y.

[0030] The touch electrode TX10 is arranged adjacent to the touch electrodes TX7 and TX9 along the first direction X. The touch electrode TX10 is arranged adjacent to the touch electrode TX12 along the second direction Y.

[0031] The touch electrode TX11 is arranged adjacent to the touch electrode TX12 along the first direction X. The touch electrode TX11 is arranged adjacent to the touch electrodes TX9 and TX13 along the second direction Y.

[0032] The touch electrode TX12 is arranged adjacent to the touch electrodes TX5 and TX11 along the first direction X. The touch electrode TX12 is arranged adjacent to the touch electrodes TX10 and TX14 along the second direction Y.

[0033] The touch electrode TX13 is arranged adjacent to the touch electrode TX14 along the first direction X. The touch electrode TX13 is arranged adjacent to the touch electrodes TX11 and TX15 along the second direction Y.

[0034] The touch electrode TX14 is arranged adjacent to the touch electrodes TX3 and TX13 along the first direction X. The touch electrode TX14 is arranged adjacent to the touch electrodes TX12 and TX16 along the second direction Y.

[0035] The touch electrode TX15 is arranged adjacent to the touch electrode TX16 along the first direction X. The touch electrode TX15 is arranged adjacent to the touch electrode TX13 along the second direction Y.

[0036] The touch electrode TX16 is arranged adjacent to the touch electrodes TX1 and TX15 along the first direction X. The touch electrode TX16 is arranged adjacent to the touch electrode TX14 along the second direction Y. It should be noted that the number and arrangement of the touch electrodes TX are not limited to this example.

[0037] Lead wires LL1 to LL16 are connected to the touch electrodes TX1 to TX16, respectively. The lead wires LL1 to LL16 are electrically connected to the second wiring board FPC2 (detection controller CT2) via a connection part TCN. More specifically, the lead wires LL1 to LL8 are electrically connected to the second wiring board FPC2 via the connection part TCN1, and the lead wires LL9 to LL16 are electrically connected to the second wiring board FPC2 via the connection part TCN2.

[0038] For example, the touch electrodes TX1 to TX8, the leads LL1 to LL8, and the connection part TCN1, and the touch electrodes TX9 to TX16, the leads LL9 to LL16, and the connection part TCN2 have a shape that is axisymmetric with respect to the center line in the first direction X.

[0039] 3 is a cross-sectional view showing an example of a schematic configuration of the display device DSP according to this embodiment. As shown in FIG. 3, the display device DSP has an insulating substrate 10. The substrate 10 may be glass or a flexible resin film. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in FIG. 1.

[0040] The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11. Pixel electrodes PE1, PE2, and PE3 are disposed on the organic insulating layer 12. Although not shown in the cross section of FIG. 3, the pixel electrodes PE1, PE2, and PE3 are each connected to a pixel circuit 1 included in the circuit layer 11 through a contact hole formed in the organic insulating layer 12.

[0041] A bank BNK is disposed on the organic insulating layer 12 and the pixel electrodes PE1, PE2, and PE3. The bank BNK has a pixel opening AP1 that exposes a part of the pixel electrode PE1, a pixel opening AP2 that exposes a part of the pixel electrode PE2, and a pixel opening AP3 that exposes a part of the pixel electrode PE3. Ends of the pixel electrodes PE1, PE2, and PE3 are covered by the bank BNK.

[0042] An organic layer OR1 is disposed on the pixel electrode PE1. The organic layer OR1 covers the pixel electrode PE1 through a pixel opening AP1. An organic layer OR2 is disposed on the pixel electrode PE2. The organic layer OR2 covers the pixel electrode PE2 through a pixel opening AP2. An organic layer OR3 is disposed on the pixel electrode PE3. The organic layer OR3 covers the pixel electrode PE3 through a pixel opening AP3.

[0043] A common electrode CE is disposed on the bank BNK and the organic layers OR1, OR2, and OR3. The common electrode CE is disposed across a plurality of pixels PX (sub-pixels SP) and faces the pixel electrodes PE1, PE2, and PE3.

[0044] The pixel electrode PE1, the organic layer OR1, and the common electrode CE that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The pixel electrode PE2, the organic layer OR2, and the common electrode CE that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The pixel electrode PE3, the organic layer OR3, and the common electrode CE that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The pixel electrodes PE1, PE2, and PE3 may be referred to as lower electrodes, and the common electrode CE may be referred to as an upper electrode.

[0045] The common electrode CE is covered with a sealing layer 13. The sealing layer 13 is covered with a resin layer 14. The resin layer 14 is covered with a sealing layer 15. A touch electrode TX and a lead wire LL connected to the touch electrode TX are disposed on the sealing layer 15. The touch electrode TX and the lead wire LL are formed of the same material and by the same manufacturing process.

[0046] The touch electrode TX is covered with a resin layer 16. An optical adhesive OCA is disposed on the resin layer 16. The optical adhesive OCA bonds the resin layer 16 to a polarizing plate POL disposed thereon.

[0047] The organic insulating layer 12 is made of an organic insulating material. The bank BNK and the resin layers 14 and 16 are made of a resin material (organic insulating material) such as an epoxy resin or an acrylic resin. The sealing layers 13 and 15 are made of a material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al 2 O 3 ) and other inorganic insulating materials.

[0048] The pixel electrodes PE1, PE2, and PE3 each have a reflective layer made of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0049] The organic layers OR1, OR2, and OR3 each have a stacked structure of, for example, a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The organic layers OR1, OR2, and OR3 may have a so-called tandem structure including a plurality of light emitting layers.

[0050] The common electrode CE is formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0051] A pixel voltage is supplied to the pixel electrodes PE1, PE2, and PE3 through the pixel circuits 1 included in the sub-pixels SP1, SP2, and SP3, respectively. A common voltage is supplied to the common electrode CE.

[0052] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. For example, when a potential difference is formed between the pixel electrode PE1 and the common electrode CE, the light-emitting layer of the organic layer OR1 emits light in the red wavelength region. When a potential difference is formed between the pixel electrode PE2 and the common electrode CE, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the pixel electrode PE3 and the common electrode CE, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength region.

[0053] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0054] In manufacturing a display device DSP with a touch panel TP as shown in Figures 1 to 3, it is necessary to inspect whether two adjacent touch electrodes TX are short-circuited. This inspection is called an adjacent short inspection, and can be performed, for example, by the configuration shown in Figure 4.

[0055] FIG. 4 is a plan view for explaining an example of a configuration for inspecting adjacent short circuits in the touch panel TP. Lead wires LL1-LL8 drawn from the touch electrodes TX1-TX8 are connected to the connection part TCN1 arranged in the mounting area MA. Also, as shown in Fig. 4, wirings L1-L8 electrically connected to the touch electrodes TX1-TX8 via the lead wires LL1-LL8 and connected to the test pads PD1-PD8 are connected to the connection part TCN1. Furthermore, as shown in Fig. 4, a ring-shaped ground wiring LG and a wiring L17 electrically connected to the ground wiring LG and connected to the ground pad PDG1 are connected to the connection part TCN1.

[0056] As shown in FIG. 4, the test pad PD1 corresponding to the touch electrode TX1 and the test pad PD5 corresponding to the touch electrode TX5 are integrally formed as one test pad PD1_5. In addition, the wiring L1 electrically connected to the touch electrode TX1 and the wiring L5 electrically connected to the touch electrode TX5 are bundled and connected to the test pad PD1_5. In this way, by integrally forming a plurality of test pads PD corresponding to a plurality of non-adjacent touch electrodes TX and bundling a plurality of wirings L electrically connected to these plurality of touch electrodes TX and connecting them to the test pad PD, it is possible to reduce the number of test pads PD required for the adjacent short inspection without overlooking adjacent shorts in the touch panel TP. Since the time required for the adjacent short inspection increases in proportion to the number of test pads PD, it is possible to shorten the time required for the adjacent short inspection by reducing the number of test pads PD.

[0057] Similarly, the test pad PD2 corresponding to the touch electrode TX2 and the test pad PD6 corresponding to the touch electrode TX6 are integrally formed as one test pad PD2_6. The wiring L2 electrically connected to the touch electrode TX2 and the wiring L6 electrically connected to the touch electrode TX6 are bundled and connected to the test pad PD2_6.

[0058] The test pad PD3 corresponding to the touch electrode TX3 and the test pad PD7 corresponding to the touch electrode TX7 are integrally formed as one test pad PD3_7. The wiring L3 electrically connected to the touch electrode TX3 and the wiring L7 electrically connected to the touch electrode TX7 are bundled and connected to the test pad PD3_7.

[0059] The test pad PD4 corresponding to the touch electrode TX4 and the test pad PD8 corresponding to the touch electrode TX8 are integrally formed as one test pad PD4_8. The wiring L4 electrically connected to the touch electrode TX4 and the wiring L8 electrically connected to the touch electrode TX8 are bundled and connected to the test pad PD4_8.

[0060] The test pads PD1_5, PD2_6, PD3_7, PD4_8 and the ground pad PDG1 are connected to each other by a ring-shaped high resistance wiring LR1 (first high resistance wiring) called a short ring. By providing such a ring-shaped high resistance wiring LR1, it is possible to prevent the display device DSP (display panel PNL) from being destroyed by static electricity caused by peeling electrification generated in the process of manufacturing the display device DSP.

[0061] Although the configuration of the left half of the figure has been described above, the configuration of the right half of the figure is similar. More specifically, lead wires LL9-LL16 drawn from the touch electrodes TX9-TX16 are connected to the connection part TCN2 arranged in the mounting area MA. Also, as shown in Fig. 4, the connection part TCN2 is connected to wirings L9-L16 electrically connected to the touch electrodes TX9-TX16 via the lead wires LL9-LL16, and the wirings L9-L16 connected to the test pads PD9-PD16. Also, as shown in Fig. 4, the connection part TCN2 is connected to a ring-shaped ground wiring LG and a wiring L18 electrically connected to the ground wiring LG and connected to the ground pad PDG2.

[0062] The test pad PD9 corresponding to the touch electrode TX9 and the test pad PD13 corresponding to the touch electrode TX13 are integrally formed as one test pad PD9_13. In addition, the wiring L9 electrically connected to the touch electrode TX9 and the wiring L13 electrically connected to the touch electrode TX13 are bundled together and connected to the test pad PD9_13.

[0063] The test pad PD10 corresponding to the touch electrode TX10 and the test pad PD14 corresponding to the touch electrode TX14 are integrally formed as one test pad PD10_14. The wiring L10 electrically connected to the touch electrode TX10 and the wiring L14 electrically connected to the touch electrode TX14 are bundled together and connected to the test pad PD10_14.

[0064] The test pad PD11 corresponding to the touch electrode TX11 and the test pad PD15 corresponding to the touch electrode TX15 are integrally formed as one test pad PD11_15. The wiring L11 electrically connected to the touch electrode TX11 and the wiring L15 electrically connected to the touch electrode TX15 are bundled together and connected to the test pad PD11_15.

[0065] The test pad PD12 corresponding to the touch electrode TX12 and the test pad PD16 corresponding to the touch electrode TX16 are integrally formed as one test pad PD12_16. The wiring L12 electrically connected to the touch electrode TX12 and the wiring L16 electrically connected to the touch electrode TX16 are bundled together and connected to the test pad PD12_16.

[0066] The test pads PD9_13, PD10_14, PD11_15, and PD12_16 and the ground pad PDG2 are connected to each other by a circular high resistance wiring LR2 (first high resistance wiring) provided as a countermeasure against static electricity.

[0067] As shown in Fig. 4, the test pads PD1_5, PD2_6, PD3_7, PD4_8, PD9_13, PD10_14, PD11_15, PD12_16, the ground pads PDG1, PDG2, and the high resistance wirings LR1, LR2 are all arranged between the first cut line CL1 and the second cut line CL2. The first cut line CL1 is a cutting line set for cutting out a plurality of display devices DSPs from a display device mother substrate on which a large number of display devices DSPs are formed. The second cut line CL2 is a cutting line set along the outer shape of a single display device DSP.

[0068] The adjacent short circuit inspection is performed after cutting the display device motherboard along the first cut line CL1 and cutting out a plurality of display devices DSP from the display device motherboard. When the adjacent short circuit inspection in the touch panel TP is completed, the display device DSP is cut along the second cut line CL2 and its shape is adjusted to the outer shape of the final product. That is, the inspection pads PD1_5, PD2_6, PD3_7, PD4_8, PD9_13, PD10_14, PD11_15, PD12_16, the ground pads PDG1, PDG2, and the high resistance wirings LR1, LR2 arranged between the first cut line CL1 and the second cut line CL2 are all cut off from the display device DSP and do not remain in the final product. This makes it possible to realize a narrow frame of the display device DSP because it is not necessary to provide spaces in the display device DSP for arranging the inspection pads PD, the ground pads PDG, and the high resistance wirings LR for static electricity countermeasures.

[0069] However, the configuration shown in FIG. 4 has the following problems. For example, in order to inspect adjacent shorts between the touch electrodes TX1 and TX2 and adjacent shorts between the touch electrodes TX5 and TX6, a voltage V1 is applied to the inspection pad PD1_5, and a voltage V2 (≠V1) is applied to the inspection pad PD2_6. As a result, when a predetermined resistance value is detected between the inspection pads PD1_5 and PD2_6, it is determined that a resistance value that should not be detected under normal circumstances is detected, and a short circuit is detected between the touch electrodes TX1 and TX2 or between the touch electrodes TX5 and TX6. However, in the configuration shown in FIG. 4, since the inspection pads PD1_5 and PD2_6 are connected to each other by the high resistance wiring LR1 provided for the above-mentioned static electricity countermeasure, depending on the detected resistance value, it may be difficult to determine whether the resistance value is a resistance value caused by a short between the touch electrodes TX1 and TX2 or between the touch electrodes TX5 and TX6, or a resistance value of the high resistance wiring LR1. In other words, there is a possibility that adjacent shorts in the touch panel TP cannot be accurately detected.

[0070] Furthermore, the configuration shown in FIG. 4 has the following problems even in inspections other than the above-mentioned adjacent short inspection. For example, the continuity test of the annular ground wiring LG is performed by contacting the ground pads PDG1 and PDG2 with probes. However, the probes that contact the ground pads PDG1 and PDG2 may be misaligned, and at least one of the probes may not contact the ground pads PDG1 and PDG2. In this case, the ground pads PDG1 and PDG2 are not electrically connected, and an infinite resistance value is detected as a result of the continuity test. On the other hand, when the ground wiring LG is disconnected, the ground pads PDG1 and PDG2 are not electrically connected, and an infinite resistance value is detected as a result of the continuity test. In other words, in the configuration shown in FIG. 4, when an infinite resistance value is detected in the continuity test of the annular ground wiring LG, it is impossible to determine whether the resistance value is due to poor contact of the probes or due to a disconnection of the ground wiring LG.

[0071] Therefore, if an infinite resistance value is detected as a result of the continuity test of the ring-shaped ground wiring LG, multiple attempts are made to contact the ground pads PDG1 and PDG2 with the probe, and if an infinite resistance value is detected in both attempts, a break in the ground wiring LG is detected. However, this method has a problem in that it takes time and effort because multiple attempts are required to determine whether the infinite resistance value detected as a result of the continuity test is a resistance value caused by poor contact of the probe or a resistance value caused by a break in the ground wiring LG. In this embodiment, therefore, a configuration capable of solving the various problems described above will be described.

[0072] FIG. 5 is a plan view showing an example of a configuration for inspecting adjacent short circuits in the touch panel TP according to the present embodiment. 5, the configuration according to this embodiment differs from the configuration shown in Fig. 4 in that the high resistance wiring LR1 connecting the test pads PD1_5, PD2_6, PD3_7, PD4_8 and the ground pad PDG1 to each other, and the high resistance wiring LR2 connecting the test pads PD9_13, PD10_14, PD11_15, PD12_16 and the ground pad PDG2 to each other are provided so as to straddle the first cut line CL1. In other words, the configuration according to this embodiment differs from the configuration shown in Fig. 4 in that the first cut line CL1 is set so as to cross the high resistance wirings LR1 and LR2.

[0073] 5, the configuration according to this embodiment differs from the configuration shown in FIG. 4 in that a high resistance wiring LR3 (second high resistance wiring) that connects the ground wiring LG and wirings L17, L18 electrically connected to the ground pads PDG1, PDG2 is provided between the first cut line CL1 and the second cut line CL2. Note that the resistance value of the high resistance wiring LR3 is desirably larger than the resistance value of the ground wiring LG, and preferably has a difference of two or more digits. For example, when the resistance value of the ground wiring LG is 3 kΩ, the resistance value of the high resistance wiring LR3 is desirably 300 kΩ or the like.

[0074] As described above, the adjacent short circuit inspection is performed after cutting the display device motherboard along the first cut line CL1 and cutting out a plurality of display devices DSP from the display device motherboard. Therefore, in the configuration shown in FIG. 5, the high resistance wiring LR1 is cut along the first cut line CL1 before the adjacent short circuit inspection, and the inspection pads PD1_5, PD2_6, PD3_7, and PD4_8 and the ground pad PDG1 are not connected to each other by the high resistance wiring LR1 during the adjacent short circuit inspection. Similarly, the high resistance wiring LR2 is also cut along the first cut line CL1 before the adjacent short circuit inspection, and the inspection pads PD9_13, PD10_14, PD11_15, and PD12_16 and the ground pad PDG2 are not connected to each other by the high resistance wiring LR2 during the adjacent short circuit inspection. According to this, the high resistance wirings LR1 and LR2 can prevent the display panel PNL from being destroyed by static electricity generated in the manufacturing process of the display panel PNL, while preventing the resistance values ​​of the high resistance wirings LR1 and LR2 from being detected in the adjacent short circuit inspection. In other words, it is possible to accurately detect adjacent short circuits in the touch panel TP.

[0075] In addition, in the configuration shown in FIG. 5, as in the configuration shown in FIG. 4, when the probes in contact with the ground pads PDG1 and PDG2 are misaligned during the continuity test of the annular ground wiring LG, and at least one of the probes does not contact the ground pads PDG1 and PDG2, an infinite resistance value is detected as the result of the continuity test. On the other hand, in the configuration shown in FIG. 5, when the ground wiring LG is disconnected, the resistance value of the high resistance wiring LR3 is detected as the result of the above-mentioned continuity test. Note that when there is no contact failure between the ground pads PDG1 and PDG2 and the probes and the ground wiring LG is not disconnected, the combined resistance value of the resistance value of the ground wiring LG and the resistance value of the high resistance wiring LR3 is detected as the result of the above-mentioned continuity test. According to this, since it is possible to determine whether the ground wiring LG is disconnected or there is a contact failure between the ground pads PDG1 and PDG2 and the probes in one continuity test (and further, since it is possible to determine that the ground wiring LG is not disconnected), it is possible to reduce the time and effort required for the continuity test compared to the configuration shown in FIG. 4.

[0076] 6 is a schematic plan view of a mother substrate MB for a display device according to this embodiment. As shown in FIG. 6, a plurality of display devices DSP with touch panels TP arranged in a matrix are formed on the mother substrate MB for a display device.

[0077] The display device motherboard MB has the configuration shown in FIG. 5 for each display device DSP. More specifically, the display device motherboard MB has, for each display device DSP, a test pad PD and a ground pad PDG, high resistance wiring LR1, LR2 connecting the test pad PD and the ground pad PDG to each other, a first cut line CL1 set for cutting out a plurality of display devices DSP from the display device motherboard MB, and a second cut line CL2 set along the outer shape of a single display device DSP. Although not shown in detail in FIG. 6, the test pad PD includes test pads corresponding to the plurality of touch electrodes included in the touch panel TP. The ground pad PDG includes two ground pads corresponding to the annular ground wiring included in the touch panel TP, and the two ground pads are connected by a high resistance wiring LR3 provided separately from the high resistance wiring LR1, LR2.

[0078] At least an organic insulating layer is not disposed on the first cutline CL1 and the second cutline CL2. Although not shown in FIG. 6, verniers or marks for identifying the positions of the first cutline CL1 and the second cutline CL2 are provided near the first cutline CL1 and the second cutline CL2.

[0079] In the present embodiment described above, a configuration has been described in which the display panel PNL has one common electrode CE (upper electrode) across multiple pixels PX (sub-pixels SP), but this is not limited to this, and the display panel PNL may also be configured to have an upper electrode for each sub-pixel SP, as shown in FIG. 7.

[0080] In this case, as shown in Fig. 7, instead of the bank BNK shown in Fig. 3, a rib 5 having pixel openings AP1, AP2, AP3 and made of an inorganic material, and a partition wall 6 including a conductive lower portion 61 arranged on the rib 5 and an upper portion 62 arranged on the lower portion 61 are arranged on the organic insulating layer 12. The upper portion 62 has a width greater than that of the lower portion 61, and both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 may be referred to as an overhanging shape.

[0081] In the pixel openings AP1, AP2, and AP3, the lower electrodes LE1, LE2, and LE3 are covered with the organic layers OR1, OR2, and OR3, and the organic layers OR1, OR2, and OR3 are covered with the upper electrodes UE1, UE2, and UE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6, respectively.

[0082] Parts of the organic layers OR1, OR2, and OR3 and parts of the upper electrodes UE1, UE2, and UE3 are located on the upper portion 62 of the partition wall 6. For example, parts of the organic layer OR3 and the upper electrode UE3 are located on the upper portion 62 of the partition wall 6 located on the left side of the figure, and are separated from the organic layer OR3 and the upper electrode UE3 located below the partition wall 6. Similarly, parts of the organic layer OR2 and the upper electrode UE2 are located on the upper portion 62 of the partition wall 6 located on the right side of the figure, and are separated from the organic layer OR2 and the upper electrode UE2 located below the partition wall 6. Furthermore, parts of the organic layer OR1 and the upper electrode UE1 are located on the upper portions 62 of the partition walls 6 on both the left and right sides of the figure, and are separated from the organic layer OR1 and the upper electrode UE1 located below these partition walls 6.

[0083] A touch panel TP can also be provided on the display panel PNL with such a configuration, as shown in Fig. 7. Even in this case, by performing an adjacent short circuit test and a continuity test on the touch panel TP using the configuration shown in Fig. 5, it is possible to accurately detect adjacent short circuits on the touch panel TP and to reduce the time and effort required for the continuity test.

[0084] According to the embodiment described above, it is possible to provide a motherboard for a display device and a method for manufacturing a display device that can improve the accuracy of an adjacent short circuit inspection.

[0085] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0086] MB: mother board for display device, DSP: display device, TP: touch panel, CL1: first cut line, CL2: second cut line, PD: inspection pad, LR, LR1, LR2, LR3: high resistance wiring, TCN, TCN1, TCN2: connection part.

Claims

1. A mother substrate for a display device on which a plurality of display devices are formed, each of which includes a display panel having a display area for displaying an image and a touch panel having a plurality of touch electrodes overlapping the display area, A plurality of test pads are provided for each of the display devices in order to test whether or not two adjacent touch electrodes among the plurality of touch electrodes are short-circuited; a first high resistance wiring that connects the plurality of test pads to each other; a first cutting line for cutting out a plurality of display devices from the display device mother substrate; A second cut line is set along the outer shape of the single display device; Equipped with Each of the plurality of test pads is disposed between the first cut line and the second cut line, and is electrically connected to a corresponding touch electrode for the test; the first high resistance wiring is disposed so as to straddle the first cut line, and is cut along the first cut line before the inspection using the plurality of inspection pads; the plurality of test pads are not connected to each other by the first high resistance wiring during the test; Motherboard for display devices.

2. The touch panel has a ring-shaped ground wiring, two ground pads electrically connected to the annular ground wiring; the two ground pads are connected by a second high resistance wiring arranged between the first cut line and the second cut line; The mother substrate for a display device according to claim 1 .

3. a resistance value of the second high resistance wiring is greater than a resistance value of the annular ground wiring; The mother substrate for a display device according to claim 2 .

4. in a continuity test of the annular ground wiring, if the two ground pads are not in contact with a probe used for the continuity test, an infinite resistance value is detected as a result of the continuity test; When the annular ground wiring is broken, a resistance value of the second high resistance wiring is detected as a result of the continuity test, When the annular ground wiring is not broken, a combined resistance value of a resistance value of the annular ground wiring and a resistance value of the second high resistance wiring is detected as a result of the continuity test. The mother substrate for a display device according to claim 3 .

5. At least an organic insulating layer is not disposed on the first cut line and the second cut line.

5. The mother substrate for a display device according to claim 1.

6. The display panel includes: A lower electrode; a bank formed of an organic material, having a pixel opening overlapping the lower electrode and covering a periphery of the lower electrode; an upper electrode facing the lower electrode and disposed across a plurality of pixels arranged in a matrix in the display region; an organic layer disposed between the lower electrode and the upper electrode, the organic layer emitting light in response to a potential difference between the lower electrode and the upper electrode; The mother substrate for a display device according to claim 5 .

7. The display panel includes: A lower electrode; a rib formed of an inorganic material, the rib having a pixel opening overlapping the lower electrode and covering a periphery of the lower electrode; A partition wall disposed above the rib; an upper electrode facing the lower electrode; an organic layer disposed between the lower electrode and the upper electrode, the organic layer emitting light in response to a potential difference between the lower electrode and the upper electrode; The mother substrate for a display device according to claim 5 .

8. A method for manufacturing a display device, comprising: a mother substrate for a display device on which a plurality of display devices are formed, each of the display devices including a display panel having a display area for displaying an image, and a touch panel having a plurality of touch electrodes overlapping the display area; a first cut line and a second cut line; a plurality of test pads disposed between the first cut line and the second cut line and provided for each of the display devices; and a first high resistance wiring connecting the plurality of test pads to each other, cutting the display device mother substrate along the first cut lines set to cross the first high resistance wiring to cut out a plurality of display devices from the display device mother substrate; Inspecting whether two adjacent touch electrodes among the plurality of touch electrodes are short-circuited using the plurality of test pads; After the inspection, the plurality of display devices are cut along the second cutting lines to form an outer shape of a single display device. A method for manufacturing a display device.

9. The touch panel has a ring-shaped ground wiring, two ground pads electrically connected to the annular ground wiring; the two ground pads are connected by a second high resistance wiring arranged between the first cut line and the second cut line; The method for manufacturing a display device according to claim 8 .

10. before cutting the display devices along the second cut lines, a probe is brought into contact with the two ground pads to perform a continuity test of the annular ground wiring; The method for manufacturing a display device according to claim 9 , further comprising:

Images