Electro-optical device and electronic apparatus
Patent Information
- Application Number
- JP2023134867
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-08-22
- Publication Date
- 2025-03-07
Smart Images
Figure 2025029950000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]
[0002] 2. Description of the Related Art Electronic devices such as projectors use electro-optical devices such as liquid crystal display devices that can change optical characteristics for each pixel. One known example of such electro-optical devices is the electro-optical device described in Patent Document 1.
[0003] The liquid crystal display device described in Patent Document 1 includes a TFT (thin film transistor) substrate on which pixel electrodes are arranged in a matrix, a counter substrate on which a counter electrode is formed, and a liquid crystal layer disposed between the two substrates. The TFT substrate has a TFT including a semiconductor film, a gate insulating film, and a gate electrode, various wiring such as signal lines, and a light-shielding film. The light-shielding film can prevent light deterioration of the TFT. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] JP 2015-7806 A Summary of the Invention [Problem to be solved by the invention]
[0005] However, in this document, the TFT, the layer in which the signal lines are arranged, and the light-shielding film are arranged in this order. Therefore, the distance between the light-shielding film and the TFT becomes long due to the presence of the layer in which the signal lines are arranged. Therefore, it is difficult for the conventional light-shielding film to sufficiently suppress the incidence of light on the TFT. [Means for solving the problem]
[0006] One embodiment of the electro-optical device of the present invention comprises a substrate, a transistor having a semiconductor layer including a drain region, a source region, and a channel region located between the drain region and the source region, extending in a first direction, and a gate electrode, a scanning line electrically connected to the gate electrode, and a first light-shielding portion, wherein the substrate, the semiconductor layer, the gate electrode, and a layer in which the scanning line is provided are aligned in a second direction intersecting the first direction, and the first light-shielding portion comprises a first portion, a second portion, and a third portion, wherein the first portion is provided between the substrate and the layer in which the scanning line is provided, the second portion is provided between the semiconductor layer and the layer in which the scanning line is provided, and the third portion is provided between the gate electrode and the layer in which the scanning line is provided, and the length of the first portion in the second direction, the length of the second portion in the second direction, and the length of the third portion in the second direction are longer in this order. [Brief description of the drawings]
[0007] [Figure 1] 1 is a plan view of an electro-optical device according to an embodiment. [Diagram 2] 2 is a cross-sectional view taken along the line AA of the electro-optical device shown in FIG. [Diagram 3] 2 is an equivalent circuit diagram showing an electrical configuration of the element substrate of FIG. 1. [Figure 4] 3 is a plan view showing a part of an element substrate in the display region of FIG. 2. [Diagram 5] 5 is a cross-sectional view taken along line A1-A1 of FIG. 4. [Figure 6] 5 is a cross-sectional view taken along line A2-A2 of FIG. 4. [Figure 7] FIG. 6 is a plan view showing the transistor in FIG. 5. [Figure 8] 6 is an enlarged view of a first light-shielding portion and a second light-shielding portion in FIG. 5. [Figure 9] FIG. 2 is a plan view of a first light-shielding portion and a second light-shielding portion. [Figure 10] FIG. 2 is a plan view of a first light-shielding portion and a second light-shielding portion. [Figure 11] 11 is a cross-sectional view taken along line A3-A3 in FIG. 10. [Figure 12] 11 is a cross-sectional view taken along line A4-A4 in FIG. 10. [Figure 13] 11 is a cross-sectional view taken along line A5-A5 in FIG. 10. [Figure 14] 10A to 10C are diagrams illustrating a manufacturing process of the first light-shielding part. [Figure 15] 10A to 10C are diagrams illustrating a manufacturing process of the first light-shielding part. [Figure 16] 10A to 10C are diagrams illustrating a manufacturing process of the first light-shielding part. [Figure 17] FIG. 1 is a perspective view showing a personal computer as an example of an electronic device. [Figure 18] FIG. 1 is a plan view showing a smartphone as an example of an electronic device. [Figure 19] FIG. 1 is a schematic diagram illustrating a projector as an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0008] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that the dimensions or scale of each part in the drawings may differ from the actual dimensions, and some parts are shown diagrammatically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.
[0009] 1. Electro-optical device 1A.Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view of the electro-optical device 100 shown in FIG. 1 taken along line AA. In FIG. 1, the opposing substrate 3 is omitted. In the following description, for convenience, the X-axis, Y-axis, and Z-axis, which are orthogonal to each other, are appropriately used. In addition, one direction along the X-axis is referred to as the X1 direction, and the direction opposite to the X1 direction is referred to as the X2 direction. Similarly, one direction along the Y-axis is referred to as the Y1 direction, and the direction opposite to the Y1 direction is referred to as the Y2 direction. One direction along the Z-axis is referred to as the Z1 direction, and the direction opposite to the Z1 direction is referred to as the Z2 direction.
[0010] In addition, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α, but also the case where element α and element β are separated. Furthermore, "electrical connection" between element α and element β includes a configuration in which element α and element β are electrically connected by being directly joined to each other, as well as a configuration in which element α and element β are indirectly electrically connected via another conductor.
[0011] The electro-optical device 100 shown in Fig. 1 and Fig. 2 is a transmissive electro-optical device of an active matrix driving system. The electro-optical device 100 has an element substrate 2, a counter substrate 3, a frame-shaped seal member 4, and a liquid crystal layer 5. As shown in Fig. 2, the element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. Note that a "plan view" refers to a view from the Z1 direction or the Z2 direction in which these overlap. Also, although the shape of the electro-optical device 100 shown in Fig. 1 in a plan view is a rectangle, it may be a polygon other than a rectangle or a circle.
[0012] The element substrate 2 shown in FIG. 2 has a first substrate 21 having light-transmitting properties, a laminated body 22 having light-transmitting properties, a plurality of pixel electrodes 25 having light-transmitting properties, and a first alignment film 29 having light-transmitting properties. The first substrate 21, the laminated body 22, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in this order in the Z1 direction. Note that "light-transmitting properties" refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more. In addition, as will be described in detail later, the element substrate 2 has a light-shielding first light-shielding portion 6 and a light-shielding second light-shielding portion 7 shown in FIG. 5 and FIG. 6. Note that "light-shielding properties" refers to light-shielding properties to visible light, and preferably refers to a visible light transmittance of less than 50%, more preferably 10% or less.
[0013] The first substrate 21 corresponds to a "substrate". The first substrate 21 is a flat plate having translucency and insulation, and is composed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of insulating films having translucency. In addition, various wirings and the like are provided in the laminate 22. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The pixel electrodes 25 include, for example, a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide) and FTO (fluorine-doped tin oxide). Although not shown, the element substrate 2 has a plurality of dummy pixel electrodes surrounding the plurality of pixel electrodes 25 in a planar view. In addition, the first alignment film 29 has translucency and insulation. The first alignment film 29 aligns the liquid crystal molecules of the liquid crystal layer 5. The first alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon oxide.
[0014] The counter substrate 3 is disposed opposite the element substrate 2. The counter substrate 3 has a second substrate 31 having light-transmitting properties, an inorganic insulating layer 32 having light-transmitting properties, a common electrode 33 having light-transmitting properties, and a second alignment film 34 having light-transmitting properties. Although not shown, the counter substrate 3 has a light-shielding partition surrounding the plurality of pixel electrodes 25 in a plan view.
[0015] The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are laminated in this order in the Z2 direction. The second substrate 31 is a flat plate having translucency and insulation, and is composed of, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 has translucency and insulation, and is formed of, for example, an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode disposed with respect to the plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 has translucency and conductivity. The common electrode 33 includes, for example, a transparent conductive material, such as ITO, IZO, and FTO. The second alignment film 34 has translucency and insulation. The second alignment film 34 aligns the liquid crystal molecules of the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide, silicon oxide, or the like.
[0016] The sealing member 4 is disposed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive or the like containing various curable resins such as epoxy resin. The sealing member 4 may contain a gap material made of an inorganic material such as glass.
[0017] The liquid crystal layer 5 is disposed within a region surrounded by the element substrate 2, the counter substrate 3, and the seal member 4. The liquid crystal layer 5 is an electro-optical layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to a voltage applied to the liquid crystal layer 5.
[0018] 1, a plurality of scanning line driving circuits 11, a signal line driving circuit 12, and a plurality of external terminals 13 are arranged on the element substrate 2. Some of the plurality of external terminals 13 are connected to wiring (not shown) that is routed from the scanning line driving circuit 11 or the signal line driving circuit 12. The plurality of external terminals 13 also includes a terminal to which a constant potential Vcom is applied. The terminal is electrically connected to a common electrode 33 of the counter substrate 3 via wiring and a conductive material (not shown). Thus, the common electrode 33 is supplied with the constant potential Vcom.
[0019] The electro-optical device 100 has a display region A10 for displaying an image, and a peripheral region A20 located outside the display region A10 in a planar view. A plurality of pixels P arranged in a matrix are provided in the display region A10. A plurality of pixel electrodes 25 are arranged in a one-to-one correspondence with the plurality of pixels P. The above-mentioned common electrode 33 is provided in common to the plurality of pixels P. The peripheral region A20 surrounds the display region A10 in a planar view. A scanning line driving circuit 11 and a signal line driving circuit 12 are arranged in the peripheral region A20.
[0020] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Fig. 2, after light LL is incident on the counter substrate 3, the light is modulated while it is being emitted from the element substrate 2, thereby displaying an image. Note that the light incident on the element substrate 2 may be modulated while it is being emitted from the counter substrate 3, thereby displaying an image.
[0021] The electro-optical device 100 is also applied to a display device that performs color display, such as a personal computer and a smartphone, which will be described later. When applied to such a display device, a color filter is appropriately used for the electro-optical device 100. The electro-optical device 100 is also applied to a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light valve. In this case, the color filter is omitted for the electro-optical device 100.
[0022] 1B. Electrical configuration of element substrate 2 Fig. 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 of Fig. 1. As shown in Fig. 3, the element substrate 2 has a plurality of transistors 23, n scanning lines 241, m signal lines 242, and n constant potential lines 243. n and m are each an integer of 2 or more. The transistors 23 are arranged corresponding to each intersection of the n scanning lines 241 and the m signal lines 242. Each transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.
[0023] Each of the n scanning lines 241 extends in the X1 direction, and the n scanning lines 241 are arranged at equal intervals in the Y1 direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding transistors 23. The n scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in Fig. 1. Scanning signals G1, G2, ..., and Gn are supplied line-sequentially to the 1st to nth scanning lines 241 from the scanning line driving circuit 11.
[0024] Each of the m signal lines 242 shown in Fig. 3 extends in the Y1 direction, and the m signal lines 242 are arranged at equal intervals in the X1 direction. Each of the m signal lines 242 is electrically connected to the sources of the corresponding transistors 23. The m signal lines 242 are electrically connected to the signal line drive circuit 12 shown in Fig. 1. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m signal lines 242 from the signal line drive circuit 12.
[0025] 3 are electrically insulated from each other and arranged in a lattice pattern in plan view. An area surrounded by two adjacent scanning lines 241 and two adjacent signal lines 242 corresponds to a pixel P. A transistor 23, a pixel electrode 25, and a capacitance element 24 are provided for each pixel P. The pixel electrodes 25 are provided in a one-to-one correspondence with the transistors 23. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.
[0026] Each of the n constant potential lines 243 extends in the X1 direction, and the n constant potential lines 243 are arranged at equal intervals in the Y2 direction. The n constant potential lines 243 are electrically insulated from the n scanning lines 241 and the m signal lines 242, and are arranged at intervals from these lines. A constant potential Vcom is applied to each of the constant potential lines 243. Each of the n constant potential lines 243 is electrically connected to one of two electrodes of a corresponding capacitance element 24. Each capacitance element 24 is a capacitance element for holding the potential of a pixel electrode 25. The capacitance element 24 is provided in a one-to-one relationship with a transistor 23. The other of the two electrodes of each capacitance element 24 is electrically connected to the corresponding pixel electrode 25. Therefore, a constant potential Vcom is applied to one electrode of the capacitance element 24, and the other electrode is electrically connected to the drain of the transistor 23.
[0027] When the scanning signals G1, G2, ..., and Gn are successively activated and n scanning lines 241 are successively selected, the transistor 23 connected to the selected scanning line 241 is turned on. Then, image signals S1, S2, ..., and Sm having a magnitude corresponding to the gradation to be displayed are taken into the pixel P corresponding to the selected scanning line 241 via m signal lines 242 and applied to the pixel electrode 25. As a result, a voltage corresponding to the gradation to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the orientation of the liquid crystal molecules changes according to the applied voltage. In addition, the applied voltage is held by the capacitance element 24. Such a change in the orientation of the liquid crystal molecules modulates light, enabling gradation display.
[0028] 1C. Structure of a portion of element substrate 2 FIG. 4 shows a part of the element substrate 2 in the display region A10 of FIG. 2. As shown in FIG. 4, the display region A10 has a plurality of opening regions A11 and a light-shielding region A12. The plurality of opening regions A11 are arranged in a matrix in a plan view. The light-shielding region A12 has a frame shape in a plan view located between the plurality of opening regions A11. Each opening region A11 is an area in which a pixel electrode 25 is arranged, and is an area through which light passes. Meanwhile, a transistor 23 is arranged in the light-shielding region A12. Although not shown in FIG. 4, various wirings such as the scanning line 241, the signal line 242, and the constant potential line 243 shown in FIG. 3, and a capacitance element 24 are arranged in the light-shielding region A12.
[0029] Fig. 5 is a cross-sectional view taken along line A1-A1 in Fig. 4. Fig. 6 is a cross-sectional view taken along line A2-A2 in Fig. 4. The Y1 direction corresponds to the "first direction". The Z1 direction corresponds to the "second direction intersecting with the first direction". The X1 direction corresponds to the "third direction intersecting with the first and second directions". Moreover, a view from the Z1 direction or the Z2 direction is considered to be a planar view.
[0030] 5 and 6, the element substrate 2 has a first substrate 21, which is a "substrate", and a laminate 22. The laminate 22 has a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. The insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are laminated in this order from the first substrate 21. The insulating layers 221 to 229 are translucent and insulating. The material of each of the insulating layers 221 to 229 is, for example, an inorganic material containing silicon, such as silicon oxide and silicon oxynitride.
[0031] The laminate 22 has arranged therein a transistor 23, a scanning line 241, a signal line 242, a first light-shielding portion 6, and a second light-shielding portion 7. The laminate 22 also has arranged therein relay electrodes 244, 245, 246, 247, 248, and 249. The first substrate 21 also has arranged therein a third light-shielding portion 210.
[0032] As described above, the first substrate 21 is made of, for example, a glass substrate or a quartz substrate. The first substrate 21 has a recess H1. The recess H1 is a depression formed in the first substrate 21, and is formed for each transistor 23. The recess H1 is formed along the Y1 direction, which is the extension direction of a semiconductor layer 231 described later.
[0033] The third light-shielding portion 210 is disposed in the recess H1. The third light-shielding portion 210 is formed, for example, by using a damascene method. The third light-shielding portion 210 is provided to prevent light from entering the semiconductor layer 231 of the transistor 23. Note that the first substrate 21 does not necessarily have to have the recess H1. In this case, the third light-shielding portion 210 is disposed on a flat surface of the first substrate 21 facing the Z1 direction.
[0034] The transistor 23 is disposed on the insulating layer 221. The transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is disposed on the insulating layer 221. The gate electrode 232 is disposed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. A region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.
[0035] FIG. 7 is a plan view of the transistor 23 in FIG. 5. The transistor 23 shown in FIG. 7 has an LDD (Lightly Doped Drain) structure. The semiconductor layer 231 extends in the Y1 direction as the "first direction" in a plan view. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a low-concentration drain region 231d, and a low-concentration source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The low-concentration drain region 231d is located between the channel region 231c and the drain region 231a. The low-concentration source region 231e is located between the channel region 231c and the source region 231b. The semiconductor layer 231 is formed of, for example, polysilicon. The region other than the channel region 231c is doped with an impurity that enhances conductivity. The impurity concentration in the low-concentration drain region 231d is lower than the impurity concentration in the drain region 231a. The impurity concentration in the low-concentration source region 231e is lower than the impurity concentration in the source region 231b. For example, the transistor 23 does not need to have an LDD structure, and the low-concentration source region 231e and the low-concentration drain region 231d may be omitted.
[0036] The gate electrode 232 is formed, for example, by doping polysilicon with an impurity that enhances electrical conductivity. The gate electrode 232 may be formed using a material having electrical conductivity, such as a metal, a metal oxide, or a metal compound. The gate electrode 232 overlaps the channel region 231c of the semiconductor layer 231 in a planar view. The gate insulating film 233 is composed of a silicon oxide film formed by, for example, thermal oxidation or a CVD (chemical vapor deposition) method. The transistor 23 overlaps the third light-shielding portion 210 in a planar view.
[0037] As shown in FIG. 5 and FIG. 6, the first light shielding portion 6 and the second light shielding portion 7 are disposed in the insulating layers 222 and 223. The first light shielding portion 6 and the second light shielding portion 7 are, for example, configured of a laminate of a plurality of layers. In addition, each of the first light shielding portion 6 and the second light shielding portion 7 is formed, for example, by using a damascene method. The first light shielding portion 6 is electrically connected to the drain region 231a of the semiconductor layer 231. The second light shielding portion 7 is electrically connected to the gate electrode 232. In addition, as shown in FIG. 6, a part of the second light shielding portion 7 penetrates the insulating layer 221. The second light shielding portion 7 is electrically connected to the third light shielding portion 210. The third light shielding portion 210 functions as a back gate.
[0038] 5, a relay electrode 244 is disposed on the insulating layer 223. The relay electrode 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills a hole penetrating the insulating layers 222 and 223. Note that the relay electrode 244 and the contact 271 may be integrally formed of the same material, or may be formed of different materials.
[0039] 5, a scanning line 241, a relay electrode 245, and a relay electrode 246 are disposed on the insulating layer 224. The scanning line 241 is electrically connected to the gate electrode 232 via the second light-shielding portion 7. The relay electrode 245 is electrically connected to the first light-shielding portion 6 via a contact 272 that penetrates the insulating layer 224. The relay electrode 246 is electrically connected to the relay electrode 244 via a contact 273 that penetrates the insulating layer 224.
[0040] A relay electrode 247 and a relay electrode 248 are disposed on the insulating layer 225. The relay electrode 247 is electrically connected to the relay electrode 246 via a contact 275 that penetrates the insulating layer 225. The relay electrode 248 is electrically connected to the relay electrode 245 via a contact 274 that penetrates the insulating layer 225.
[0041] The signal line 242 is disposed on the insulating layer 226. The signal line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. Therefore, the signal line 242 is electrically connected to the source region 231b via the contact 276, the relay electrode 247, the contact 275, the relay electrode 246, the contact 273, the relay electrode 244, and the contact 271.
[0042] 6, a relay electrode 249 is disposed on the insulating layer 226. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 that penetrates the insulating layer.
[0043] The capacitance element 24 is disposed on the insulating layer 227. The capacitance element 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. The electrode 2401 is disposed on the insulating layer 227. The electrode 2402 is disposed on the insulating layer 228. The dielectric layer 2403 is disposed between the electrodes 2401 and 2402. The electrode 2401 also serves as the constant potential line 243 of FIG. 2. Also, as shown in FIG. 6, the electrode 2402 is electrically connected to the relay electrode 249 via the contact 278 that penetrates the insulating layers 227 and 228. Therefore, as shown in FIG. 5 or FIG. 6, the electrode 2402 is electrically connected to the drain region 231a via the contact 278, the relay electrode 249, the contact 277, the relay electrode 248, the contact 274, the relay electrode 245, the contact 272, and the first light-shielding portion 6.
[0044] 5, the pixel electrode 25 is disposed on the insulating layer 229. The pixel electrode 25 is electrically connected to the electrode 2402 via a contact 279 that penetrates the insulating layer 229.
[0045] Each of the aforementioned scanning line 241, signal line 242, electrode 2401, electrode 2402, relay electrodes 244, 245, 246, 247, 248, and 249 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), a metal nitride, and a metal silicide. These may be a single layer or a multilayer. For example, they are composed of a multilayer of an aluminum film and a titanium nitride film.
[0046] Each of the contacts 271 to 279 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), a metal nitride, and a metal silicide. Each of the contacts 271 to 279 may be a single layer or a multilayer. Each of the contacts 271 to 279 may be formed integrally with the electrode or wiring to which it is connected, or may be formed separately.
[0047] 5 and 6 is an example. For example, the element substrate 2 may include a capacitive element other than the capacitive element 24. Although the scanning line 241, the signal line 242, and the capacitive element 24 are arranged in this order in the Z1 direction, they do not have to be arranged in this order.
[0048] 1C. First light shielding portion 6 and second light shielding portion 7 8 is an enlarged view of the first light-shielding portion 6 and the second light-shielding portion 7 in FIG. 5. As shown in FIG. 8, the first substrate 21, the semiconductor layer 231, the gate electrode 232, and the insulating layer 225 are aligned in the Z2 direction, which is the "second direction intersecting with the first direction." The insulating layer 225 is a layer in which the scanning lines 241 are provided. In addition, the first light-shielding portion 6 and the second light-shielding portion 7 are disposed between the first substrate 21 and the insulating layer 225.
[0049] 9 and 10 are plan views of the first light-shielding portion 6 and the second light-shielding portion 7, respectively. As shown in FIG. 9, the first light-shielding portion 6 and the second light-shielding portion 7 are disposed apart from each other. The first light-shielding portion 6 is located in the Y2 direction with respect to the second light-shielding portion 7 in a plan view. The first light-shielding portion 6 overlaps with a part of the drain region 231a and the low-concentration drain region 231d of the semiconductor layer 231 in a plan view. The second light-shielding portion 7 overlaps with a part of the gate electrode 232 and a part of the channel region 231c in a plan view. The first light-shielding portion 6 and the second light-shielding portion 7 overlap with the third light-shielding portion 210 in a plan view. The second light-shielding portion 7 is located outside the first light-shielding portion 6 in a plan view.
[0050] The first light-shielding portion 6 includes a first portion 61, a second portion 62, and a third portion 63. The second light-shielding portion 7 includes two portions, a fourth portion 71, and a fifth portion 72. In Fig. 10, for ease of understanding, the first portion 61 is hatched, the second portion 62 is meshed, and the third portion 63 is dotted. Furthermore, the fourth portion 71 is hatched, and the fifth portion 72 is dotted.
[0051] As shown in FIG. 10, the first portion 61 is provided on the outer side of the second portion 62 and the third portion 63 in a plan view. Specifically, the first portion 61 includes a portion located in the X1 direction from the second portion 62 and the third portion 63 in a plan view, a portion located in the X2 direction from the second portion 62 and the third portion 63 in a plan view, and a portion located in the Y2 direction from the second portion 62. The second portion 62 is located in the Y2 direction from the third portion 63 in a plan view. As shown in FIG. 9 and FIG. 10, the first portion 61 overlaps the drain region 231a in a plan view. The second portion 62 overlaps the low-concentration drain region 231d in a plan view. The third portion 63 overlaps the gate electrode 232 in a plan view.
[0052] As shown in FIG. 10, the two fourth portions 71 are located on both sides of the fifth portion 72 in a plan view and are connected to the fifth portion 72. The fourth portion 71 includes a portion extending along the Y-axis and a portion extending along the X-axis in a plan view. The fifth portion 72 extends along the X-axis and is located between the two fourth portions 71 in a plan view. As shown in FIG. 9 and FIG. 10, the fifth portion 72 overlaps the gate electrode 232 in a plan view. Each of the two fourth portions 71 is located outside the first portion 61 in a direction along the X-axis in a plan view. In addition, the second light-shielding portion 7 and the first portion 61 surround the low-concentration drain region 231d in a plan view.
[0053] Fig. 11 is a cross-sectional view taken along the line A3-A3 in Fig. 10. Fig. 12 is a cross-sectional view taken along the line A4-A4 in Fig. 10. Fig. 13 is a cross-sectional view taken along the line A5-A5 in Fig. 10.
[0054] 11 and 12, the first light shielding portion 6 is spaced apart from the scanning line 241 and the third light shielding portion 210. The first light shielding portion 6 is not connected to either the scanning line 241 or the third light shielding portion 210. In addition, each of the second portion 62 and the third portion 63 of the first light shielding portion 6 is spaced apart from the semiconductor layer 231. In contrast, as shown in FIG. 8, the first portion 61 is directly connected to the drain region 231a of the semiconductor layer 231. Therefore, the first light shielding portion 6 is at a pixel potential.
[0055] As shown in FIGS. 11 and 13, the fourth portion 71 of the second light-shielding portion 7 is connected to the scanning line 241 and the third light-shielding portion 210. The fifth portion 72 is connected to the scanning line 241 and the gate electrode 232. Therefore, the second light-shielding portion 7 has a gate potential and is different in potential from the first light-shielding portion 6.
[0056] As described above, the first light-shielding portion 6 includes a first portion 61, a second portion 62, and a third portion 63. As shown in FIGS. 11 and 12, the first portion 61 is provided between the first substrate 21 and the insulating layer 225. Specifically, the first portion 61 extends in the Z1 direction from the insulating layer 221 to the insulating layer 224, which is a layer between the first substrate 21 and the semiconductor layer 231. Also, as shown in FIG. 12, the second portion 62 is provided between the semiconductor layer 231 and the insulating layer 225. Further, as shown in FIG. 11, the third portion 63 is provided between the gate electrode 232 and the insulating layer 225. And, as shown in FIG. 11 or FIG. 12, the length L1 of the first portion 61 in the Z1 direction, the length L2 of the second portion 62 in the Z1 direction, and the length L3 of the third portion 63 in the Z1 direction are long in this order. Therefore, the lengths L1, L2, and L3 satisfy the relationship L3 < L2 < L1.
[0057] According to the configuration of the first light-shielding portion 6, the first light-shielding portion 6 can be disposed closer to the semiconductor layer 231 than in the prior art. For this reason, the incidence of light on the semiconductor layer 231 can be suppressed more effectively than in the prior art. Therefore, it is possible to suppress the operation of the transistor 23 from becoming unstable. As a result, it is possible to suppress the occurrence of display defects such as luminance unevenness. Thus, it is possible to suppress a decrease in display quality.
[0058] As described above, the first light-shielding portion 6 is disposed between the semiconductor layer 231 and the insulating layer 225 which is the layer where the scanning line 241 is provided. In other words, no other wirings and electrodes are interposed between the first light-shielding portion 6 and the semiconductor layer 231. Therefore, the first light-shielding portion 6 can be brought close to the semiconductor layer 231. Thus, compared with the case where wirings and electrodes are interposed between the first light-shielding portion 6 and the semiconductor layer 231, the incidence of light in the Z1 direction to the semiconductor layer 231 by the first light-shielding portion 6 can be suppressed.
[0059] Also, in the first light-shielding portion 6, the first portion 61 is disposed outside the semiconductor layer 231 with respect to the X axis. Therefore, for example, the incidence of light in the X1 direction and the X2 direction of the semiconductor layer 231 can be suppressed by the first portion 61. Further, the first portion 61 has a portion disposed in the Y2 direction of the semiconductor layer 231. Therefore, the incidence of light in the Y1 direction of the semiconductor layer 231 can be suppressed by the first portion 61. Furthermore, the second portion 62 and the third portion 63 are provided in the Z1 direction with respect to the semiconductor layer 231. Therefore, the incidence of light in the Z2 direction to the semiconductor layer 231 can be suppressed. Also, since the lengths L1, L2, and L3 are in the relationship of L3 < L2 < L1, the first light-shielding portion 6 close to the semiconductor layer 231 as described above can be realized. Therefore, the incidence of light to the transistor 23 by the first light-shielding portion 6 can be suppressed more effectively than before.
[0060] In this embodiment, as shown in FIG. 9, the first light-shielding portion 6 overlaps the low-concentration drain region 231d in a plan view. Specifically, the second portion 62 overlaps the low-concentration drain region 231d in a plan view. The low-concentration drain region 231d is a region of the semiconductor layer 231 where light leakage is most likely to occur. Therefore, by overlapping the second portion 62 with the low-concentration drain region 231d in a plan view, the first light-shielding portion 6 can effectively suppress the incidence of light into the low-concentration drain region 231d. Therefore, light leakage can be effectively suppressed. In addition, no wiring or electrode is interposed between the first light-shielding portion 6 and the low-concentration drain region 231d. Therefore, the first light-shielding portion 6 can be brought close to the low-concentration drain region 231d. Therefore, the first light-shielding portion 6 can suppress the incidence of light in the Z1 direction into the low-concentration drain region 231d.
[0061] In this embodiment, the transistor 23 has an LDD structure. However, the low-concentration source region 231e and the low-concentration drain region 231d may be omitted. In this case, the semiconductor layer 231 is composed of the drain region 231a, the source region 231b, and the channel region 231c. In this case, it is preferable that the second portion 62 overlaps the junction between the drain region 231a and the source region 231b in a planar view. This junction is a region where light leakage is likely to occur. Therefore, by the second portion 62 overlapping the junction in a planar view, the first light shielding portion 6 can effectively suppress the incidence of light into the junction. Therefore, light leakage can be effectively suppressed.
[0062] Further, the first light-shielding portion 6 overlaps with the gate electrode 232 in a planar view. Specifically, the third portion 63 overlaps with a part of the gate electrode 232 in a planar view. Therefore, compared to a case where the third portion 63 does not overlap with the gate electrode 232 in a planar view, it is possible to suppress the incidence of light into the semiconductor layer 231, particularly the low-concentration drain region 231d. For example, the third portion 63 can suppress the penetration of light that has passed between the relay electrode 246 and the scanning line 241 shown in FIG. 8 into the low-concentration drain region 231d.
[0063] 8, the second portion 62 is closer to the semiconductor layer 231 in the direction along the Z-axis than the third portion 63. In other words, as shown in FIG. 8, the distance D2 between the second portion 62 and the semiconductor layer 231 is shorter than the distance D3 between the third portion 63 and the semiconductor layer 231. For this reason, the second portion 62 can be brought closer to the semiconductor layer 231 compared to a case in which the second portion 62 is farther from the semiconductor layer 231 in the direction along the Z-axis than the third portion 63. Therefore, the incidence of light into the semiconductor layer 231 can be more effectively achieved.
[0064] In particular, the surface of the second portion 62 facing the semiconductor layer 231 is preferably provided at a position between the surface of the gate electrode 232 facing the semiconductor layer 231 and the surface of the gate electrode 232 facing the scanning line 241 in the direction along the Z axis. By providing the surface of the second portion 62 facing the semiconductor layer 231 at such a position, the distance between the second portion 62 and the semiconductor layer 231 can be made very close. Furthermore, by overlapping the second portion 62 with the low concentration drain region 231d in a plan view, the second portion 62 can be made very close to the low concentration drain region 231d. In other words, the distance between the second portion 62 and the low concentration drain region 231d can be made much shorter than in the past. Therefore, it is possible to suppress the incidence of light along the Z1 direction on the semiconductor layer 231, particularly the low concentration drain region 231d. Suppressing the incidence of light along the Z1 direction is particularly effective in a form in which light is incident from the opposing substrate 3, as in this embodiment.
[0065] Moreover, the first portion 61 is directly connected to the drain region 231a. Therefore, the potential of the first light-shielding portion 6 and the potential of the drain region 231a of the semiconductor layer 231 are the same potential. Therefore, even if the first light-shielding portion 6 is brought close to the semiconductor layer 231, problems are unlikely to occur. Therefore, it is easy to bring the first light-shielding portion 6 close to the semiconductor layer 231. Since the first light-shielding portion 6 can be brought close to the semiconductor layer 231, the light-shielding property provided by the first light-shielding portion 6 can be improved compared to the conventional case.
[0066] Since the first portion 61 is directly connected to the drain region 231a, the pixel potential is applied to the first light-shielding portion 6. Therefore, the first light-shielding portion 6 is not at the gate potential. Therefore, even if the first light-shielding portion 6 is disposed close to the semiconductor layer 231, it is possible to suppress the influence of the gate potential on the semiconductor layer 231. Specifically, it is possible to suppress an increase in off-leak current caused by the gate potential approaching a region other than the channel region 231c of the semiconductor layer 231. Therefore, it is possible to suppress a decrease in display quality caused by the occurrence of black spots, etc. The off-leak current is a leakage current that flows when the transistor 23 is turned off.
[0067] 9, the second light-shielding portion 7 and the first light-shielding portion 6 surround the light-concentration drain region 231d in a plan view, which effectively suppresses the incidence of light from a direction along the XY plane into the light-concentration drain region 231d.
[0068] Further, in this embodiment, a third light-shielding portion 210, a first light-shielding portion 6, and a second light-shielding portion 7 are provided. The low-concentration drain region 231d is surrounded by the third light-shielding portion 210, the first light-shielding portion 6, and the second light-shielding portion 7. Therefore, the third light-shielding portion 210, the first light-shielding portion 6, and the second light-shielding portion 7 can particularly effectively suppress the incidence of light from all directions into the low-concentration drain region 231d. For example, the third light-shielding portion 210 suppresses the incidence of light in the Z1 direction into the low-concentration drain region 231d. The first portion 61 of the first light-shielding portion 6 and the second light-shielding portion 7 suppress the incidence of light in a direction along the XY plane into the low-concentration drain region 231d. The second portion 62 and the third portion 63 of the first light-shielding portion 6 suppress the incidence of light from the Z2 direction.
[0069] Moreover, the second light-shielding portion 7 is farther from the low-concentration drain region 231d than the first light-shielding portion 6 in the X1 direction, which is a third direction intersecting the first and second directions. Specifically, the fourth portion 71 of the second light-shielding portion 7 is located on the outer side of the first light-shielding portion 6 in the X-axis direction. As shown in FIG. 9, the fourth portion 71 of the second light-shielding portion 7 is separated from the low-concentration drain region 231d by a distance D1 in the X1 direction. In contrast, the first light-shielding portion 6 overlaps with the low-concentration drain region 231d in a plan view. Therefore, the position of the first light-shielding portion 6 in the X1 direction includes a portion equal to the position of the low-concentration drain region 231d in the X1 direction. In this way, the fourth portion 71 of the second light-shielding portion 7 is located on the outer side of the first light-shielding portion 6 in the X-axis direction, so that the influence of the gate potential on the low-concentration drain region 231d can be suppressed compared to the case where the fourth portion 71 of the second light-shielding portion 7 is located on the inner side of the first light-shielding portion 6 in the X-axis direction. Therefore, an increase in the off-leak current can be suppressed.
[0070] As shown in FIG. 13, the second light-shielding portion 7 is connected to the gate electrode 232. Therefore, the second light-shielding portion 7 can be used as a contact that connects the scanning line 241 and the gate electrode 232. Therefore, it is not necessary to separately form the second light-shielding portion 7. Moreover, by connecting the second light-shielding portion 7 to the third light-shielding portion 210, the third light-shielding portion 210 can be used as a back gate. In addition, by connecting the second light-shielding portion 7 to the third light-shielding portion 210, the second light-shielding portion 7 can suppress the incidence of light in the Y2 direction into the low-concentration drain region 231d.
[0071] Examples of the materials of the first light-shielding portion 6 and the second light-shielding portion 7 include metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), metal nitrides, and metal silicides. Among these, it is preferable that the first light-shielding portion 6 and the second light-shielding portion 7 contain tungsten. Among various metals, tungsten has excellent heat resistance, and its OD (Optical Density) value is unlikely to decrease even by heat treatment during manufacturing. Therefore, by including tungsten in the first light-shielding portion 6 and the second light-shielding portion 7, the first light-shielding portion 6 and the second light-shielding portion 7 can particularly effectively prevent light from entering the semiconductor layer 231. In addition, the first light-shielding portion 6 and the second light-shielding portion 7 may be the same as each other or different from each other.
[0072] 8, the first light-shielding portion 6 is disposed in a through hole formed in the insulating layer 223. The through hole includes a first recess R1, a second recess R2, and a third recess R3. The second recess R2 is formed at the bottom of the third recess R3. The first recess R1 is formed at the bottom of the second recess R2. For example, the first light-shielding portion 6 is formed as follows.
[0073] 14, 15, and 16 are diagrams showing a manufacturing process of the first light-shielding portion 6. In FIGS. 14 to 16, the second light-shielding portion 7 is omitted. As shown in FIG. 14, first, a part of the first portion 61 is disposed in the first recess R1. Next, as shown in FIG. 15, a part of the remainder of the first portion 61 and a part of the second portion 62 are formed in the second recess R2. Thereafter, as shown in FIG. 16, the remainder of the first portion 61, the remainder of the second portion 62, and the third portion 63 are formed in the third recess R3. Note that the manufacturing method of the first light-shielding portion 6 is not limited to the above and may be any method.
[0074] 2. Variations The above-described embodiment may be modified in various ways. Specific modified aspects that may be applied to the above-described embodiment are illustrated below. Two or more aspects selected from the following examples may be combined as appropriate to the extent that they are not mutually contradictory.
[0075] In each of the above-described embodiments, the electro-optical device 100 is an active matrix type, but the driving method of the electro-optical device 100 is not limited to this, and may be, for example, a passive matrix type or the like.
[0076] The driving method of the "electro-optical device" is not limited to the vertical electric field method, but may be a horizontal electric field method. The horizontal electric field method may be, for example, an IPS (In Plane Switching) mode. The vertical electric field method may be, for example, a TN (Twisted Nematic) mode, a VA (Vertical Alignment), a PVA mode, or an OCB (Optically Compensated Bend) mode.
[0077] In the above description, the second light shielding portion 7 is connected to the third light shielding portion 210, but it does not have to be connected. Also, the second light shielding portion 7 may be omitted.
[0078] 2.Electronic equipment The electro-optical device 100 can be used in various electronic devices.
[0079] 17 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 has an electro-optical device 100 that displays various images, a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.
[0080] 18 is a plan view showing a smartphone 3000 as an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to an operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.
[0081] 19 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-plate projector. The electro-optical device 1r is an electro-optical device 100 corresponding to a red display color, the electro-optical device 1g is an electro-optical device 100 corresponding to a green display color, and the electro-optical device 1b is an electro-optical device 100 corresponding to a blue display color. That is, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.
[0082] The illumination optical system 4001 supplies a red component r of light emitted from an illumination device 4002, which is a light source, to an electro-optical device 1r, a green component g to an electro-optical device 1g, and a blue component b to an electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 according to a display image. The projection optical system 4003 combines the light emitted from each of the electro-optical devices 1r, 1g, and 1b and projects the combined light onto a projection surface 4004.
[0083] The above electronic device includes the electro-optical device 100 and the control unit 2003, 3002, or 4005. The electro-optical device 100 has excellent light blocking properties due to the first light blocking portion 6 of the semiconductor layer 231, so that the operation of the transistor 23 is prevented from becoming unstable. This reduces the risk of display defects. Therefore, by including the electro-optical device 100, the display quality of the personal computer 2000, the smartphone 3000, or the projection display device 4000 can be improved.
[0084] Note that electronic devices to which the electro-optical device of the present invention can be applied are not limited to the exemplified devices, and examples thereof include PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation devices, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS (Point of Sale) terminals, etc. Furthermore, examples of electronic devices to which the present invention can be applied include printers, scanners, copiers, video players, and devices equipped with touch panels, etc.
[0085] Although the present invention has been described based on the preferred embodiment, the present invention is not limited to the above-mentioned embodiment. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-mentioned embodiment, and any configuration can be added.
[0086] In the above description, a liquid crystal display device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to an image sensor, etc. [Explanation of symbols]
[0087] Reference Signs List 1b...electro-optical device, 1g...electro-optical device, 1r...electro-optical device, 2...element substrate, 3...opposite substrate, 4...sealing member, 5...liquid crystal layer, 6...first light-shielding portion, 7...second light-shielding portion, 11...scanning line driving circuit, 12...signal line driving circuit, 13...external terminal, 21...first substrate, 22...laminated body, 23...transistor, 24...capacitive element, 25...pixel electrode, 29...first alignment film, 31...second substrate, 32...inorganic insulating layer, 33...common electrode, 34...second alignment film, 61...first portion, 62...second portion, 63...third portion, 71 ...fourth portion, 72...fifth portion, 100...electro-optical device, 210...third light-shielding portion, 221...insulating layer, 222...insulating layer, 223...insulating layer, 224...insulating layer, 225...insulating layer, 226...insulating layer, 227...insulating layer, 228...insulating layer, 229...insulating layer, 231...semiconductor layer, 231a...drain region, 231b...source region, 231c...channel region, 231d...low-concentration drain region, 231e...low-concentration source region, 232...gate electrode, 233...gate insulating film, 241...scanning line, 242...signal line, 243... constant potential line, 244... relay electrode, 245... relay electrode, 246... relay electrode, 247... relay electrode, 248... relay electrode, 249... relay electrode, 271... contact, 272... contact, 273... contact, 274... contact, 275... contact, 276... contact, 277... contact, 278... contact, 279... contact, 2000... personal computer, 2001... power switch, 2002... keyboard, 2003... control unit, 2010... main body, 2 401...electrode, 2402...electrode, 2403...dielectric layer, 3000...smartphone, 3001...operation button, 3002...control unit, 4000...projection type display device, 4001...illumination optical system, 4002...illumination device, 4003...projection optical system, 4004...projection surface, 4005...control unit, A10...display area, A11...opening area, A12...light-shielding area, A20...peripheral area, H1...recess, LL...light, P...pixel, R1...first recess, R2...second recess, R3...third recess, L1...length, L2...length, L3...length.
Claims
1. A substrate; a transistor including a semiconductor layer extending in a first direction, the semiconductor layer including a drain region, a source region, and a channel region located between the drain region and the source region, and a gate electrode; a scanning line electrically connected to the gate electrode; A first light-shielding portion, the substrate, the semiconductor layer, the gate electrode, and the layer in which the scanning line is provided are aligned in a second direction intersecting the first direction, the first light-shielding portion includes a first portion, a second portion, and a third portion; the first portion is provided between the substrate and a layer on which the scan lines are provided, the second portion is provided between the semiconductor layer and a layer on which the scanning line is provided, the third portion is provided between the gate electrode and a layer in which the scanning line is provided, a length of the first portion in the second direction, a length of the second portion in the second direction, and a length of the third portion in the second direction are longer in this order; Electro-optical device.
2. The semiconductor layer further includes a low-concentration drain region located between the drain region and the channel region in a plan view, The second portion overlaps with the lightly doped drain region in a plan view.
2. The electro-optical device according to claim 1.
3. the second portion is closer to the semiconductor layer in the second direction than the third portion; 2. The electro-optical device according to claim 1.
4. The first portion is connected to the drain region.
2. The electro-optical device according to claim 1.
5. the third portion overlaps with the gate electrode in a plan view; 2. The electro-optical device according to claim 1.
6. Further, a second light-shielding portion is provided, the second light-shielding portion being spaced apart from the first light-shielding portion. the second light-shielding portion and the first light-shielding portion surround the lightly doped drain region in a plan view; 3. The electro-optical device according to claim 2.
7. Further, a second light-shielding portion is provided, the second light-shielding portion being spaced apart from the first light-shielding portion. The second light shielding portion is connected to the gate electrode.
2. The electro-optical device according to claim 1.
8. Further, a second light-shielding portion is provided, the second light-shielding portion being spaced apart from the first light-shielding portion. the second light-shielding portion is farther from the lightly doped drain region than the first light-shielding portion is in a third direction intersecting the first direction and the second direction; 3. The electro-optical device according to claim 2.
9. Further, a second light-shielding portion is provided, the second light-shielding portion being spaced apart from the first light-shielding portion. The second light blocking portion is Two fourth portions that are spaced apart from each other and include a portion that extends in the first direction; and a fifth portion located between the two fourth portions in a plan view and extending in a third direction intersecting the first direction and the second direction; 3. The electro-optical device according to claim 2.
10. The electro-optical device according to claim 1 , and a control unit for controlling an operation of the electro-optical device.
Citation Information
Patent Citations
Liquid crystal display device
JP2015007806A