Data processing apparatus and data processing method

Abstract

To provide a data processing apparatus and a data processing method which can save CPU resources and can adjust a range of cache prefetching.SOLUTION: A data processing apparatus has a data reading unit for reading data stored in a cache memory accompanied by a sharing memory. The data reading unit carries out cache prefetching by reading data stored in the cache memory if access time required for reading data stored in the cache memory exceeds a threshold value, thereby determining a range of cache prefetching based on the access time.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a technique for increasing the speed of data communication between a plurality of operating systems (OS). [Background technology]

[0002] There is known a computer system that uses a hypervisor to run multiple virtual OSs on a single computer. As a method of data communication between programs running on each virtual OS, a data communication method using a shared memory that can be accessed from each OS is known (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-143120 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a system where multiple operating systems run simultaneously, a method of using shared memory is used as a method of data communication between programs running on each operating system. The problem with this method is that cache misses cause delays in data access.

[0005] In Patent Document 1, the shared memory is periodically monitored, and when an update of the shared data in the shared memory is confirmed, the shared data is received. The technology disclosed in Patent Document 1 has two problems. The first problem is that even if there is no update of the shared data, the shared memory is periodically monitored for data updates, which requires the allocation of time resources of the CPU (Central Processing Unit). The second problem is that the range of cache prefetch cannot be adjusted.

[0006] The present disclosure has been made to solve such problems, and aims to provide a data processing device and a data processing method that are capable of saving CPU resources and adjusting the range of cache prefetching. [Means for solving the problem]

[0007] In order to solve the above problems, the data processing device disclosed herein includes a data reading unit that reads data stored in a cache memory associated with a shared memory, and when the access time required to read the data stored in the cache memory exceeds a threshold value, the data reading unit performs cache prefetching by reading the data stored in the cache memory and determines the range of cache prefetching based on the access time. Effect of the Invention

[0008] According to the present disclosure, it is possible to conserve CPU resources and adjust the range of cache prefetching. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of a configuration of an entire system including a data processing device according to a first embodiment. [Diagram 2] 1 is a block diagram showing an example of a configuration of a data processing device according to a first embodiment. [Diagram 3] 4 is a flowchart showing an example of the operation of the data processing device according to the first embodiment. [Figure 4] 4 is a flowchart showing an example of the operation of the data processing device according to the first embodiment. [Diagram 5] 4 is a flowchart showing an example of the operation of the data processing device according to the first embodiment. [Figure 6] 4 is a flowchart showing an example of the operation of the data processing device according to the first embodiment. [Figure 7]11 is a flowchart showing an example of the operation of the data processing device according to the second embodiment. [Figure 8] 13 is a flowchart showing an example of the operation of the data processing device according to the third embodiment. [Figure 9] 13 is a flowchart showing an example of the operation of the data processing device according to the fourth embodiment. [Figure 10] 13 is a flowchart showing an example of the operation of the data processing device according to the fifth embodiment. [Figure 11] 23 is a flowchart showing an example of the operation of the data processing device according to the sixth embodiment. [Figure 12] 13 is a flowchart showing an example of the operation of the data processing device according to the seventh embodiment. [Figure 13] 20 is a flowchart showing an example of the operation of the data processing device according to the eighth embodiment. [Figure 14] 13 is a flowchart showing an example of the operation of the data processing device according to the ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Embodiment 1> FIG. 1 is a diagram showing an example of the overall configuration of a system including a data processing device according to the first embodiment.

[0011] In the system shown in Figure 1, multiple OSs (first OS, second OS, ..., and mth OS) run simultaneously and independently on a single piece of hardware. Multiple programs run simultaneously in each OS. For example, in the first OS, the tenth program, the eleventh program, ..., and the 1ith program run simultaneously. When data communication is performed between programs running on different OSs, data is exchanged using a shared memory provided in the hardware as a medium.

[0012] Fig. 2 is a block diagram showing an example of the configuration of a data processing device, and shows how data is exchanged between programs running on different OSs. For simplicity's sake, Fig. 2 shows two OSs running on the hardware: a first OS 101 and a second OS 201. The program running on the first OS 101 is shown as a first program 102, and the program running on the second OS 201 is shown as a second program 202.

[0013] The first program 102 has the functions of a data reading unit 103 and a data writing unit 105, and the data reading unit 103 includes the function of a data reading time measurement unit 104. The second program 202 has the functions of a data reading unit 203 and a data writing unit 205, and the data reading unit 203 includes the function of a data reading time measurement unit 204. The data processing device corresponds to a device that executes the first program 102. Therefore, the data processing device includes the data reading unit 103 and the data writing unit 105.

[0014] The hardware 301 is provided with a shared memory 302. The shared memory 302 is accompanied by a cache memory 303.

[0015] When data is transmitted from the first program 102 to the second program 202, the data is written from the data writing unit 105 of the first program 102 to the shared memory 302. The data written to the shared memory 302 is written through to the cache memory 303. In the second program 202, which is the data receiving side, the data reading unit 203 reads the data from the cache memory 303.

[0016] When data is read, the cache memory 303 stores the read data in the cache memory 303. Data stored in the cache memory 303 that has not been read is removed from the cache memory 303 according to a least recently used algorithm. If the data has been removed from the cache memory 303, the data reading unit 203 of the second program 202 reads the data from the shared memory 302. The data reading unit 203 can read data more quickly by reading data from the cache memory 303 than by reading data from the shared memory 302.

[0017] The present disclosure is an improvement over the processing of the data reading unit 103 of the first program 102 and the data reading unit 203 of the second program 202. In the following, the processing of the data reading unit 103 will be described as a representative, but the processing of the data reading unit 203 is similar.

[0018] FIG. 3 is a flow chart showing an example of the operation of the data processing device, and shows an overview of the processing program of the data reading unit 103.

[0019] In step S301, the data reading unit 103 secures memory space for the shared memory 302. The data reading unit 103 aligns the address value of the shared memory 302 to the page boundary of the virtual memory. Specifically, the data reading unit 103 takes a logical AND between the inverted value of "0xFFFFF" and the address value of the shared memory 302, and masks the lowest 20 bits with 0.

[0020] In step S302, the data reader 103 sequentially accesses the shared memory 302. Details of the process in step S302 will be described with reference to FIG.

[0021] Fig. 4 is a flowchart showing details of the process of step S302 in Fig. 3. The process in Fig. 4 is roughly divided into three processes. In the first process, cache memory 303 is randomly accessed to disable the function of cache memory 303. In the second process, cache memory 303 is refreshed. In the last process, cache memory 303 is accessed and the processing time (access time) during the access is measured.

[0022] 4 includes measuring the processing time, the data reader 103 performs loop processing in steps S401 and S410. Note that the number of loops may be a number sufficient for acquiring the processing time.

[0023] In step S 402 , the data reading unit 103 generates an integer random number within the range of the size of the cache memory 303 .

[0024] In step S403, the data reading unit 103 randomly accesses the cache memory 303 toward the location indicated by the generated random number. By the data reading unit 103 randomly accessing the cache memory 303, the cache function of the cache memory 303 is disabled.

[0025] In step S404, the data reader 103 verifies the effect of cache prefetch. There are multiple methods for the process in step S404, which will be described later.

[0026] In steps S405 to S409, the data reading unit 103 accesses the cache memory 303. A method for calculating the address of the access destination and accessing the calculated address will be described below.

[0027] In step S405, the data reading unit 103 multiplies the loop counter of step S401 by the number of cache lines. By multiplying the loop counter by the number of cache lines, it is possible to avoid reading the cache memory 303 redundantly.

[0028] In step S406, the data reading unit 103 performs a modulus operation on the value calculated in step S405 and the size of the cache memory 303. By performing the process of step S407, it is possible to point to an address in the cache memory 303 even if the loop counter in step S401 exceeds the size of the cache memory 303.

[0029] In step S407, the data read time measurement unit 104 starts measuring the access time taken by the data reading unit 103 to access the cache memory 303. In this disclosure, the CPU counter number is measured using the inline assembler of the target CPU.

[0030] In step S408, the data reading unit 103 accesses the address of the cache memory 303 calculated in step S406.

[0031] In step S409, the data reading time measurement unit 104 ends the measurement of the access time, and measures the CPU counter number when the data reading unit 103 ends its access to the cache memory 303. Then, the data reading time measurement unit 104 calculates the access time taken by the data reading unit 103 to access the cache memory 303 using the difference between the CPU counter number measured in step S407 and the CPU counter number measured in step S409.

[0032] Fig. 5 is a flowchart showing the details of step S404 in Fig. 4. The purpose of the processing in Fig. 5 is to load data onto the cache memory 303.

[0033] In steps S501 and S503, the data reading unit 103 performs a loop process of step S502 until the entire cache memory 303 has been accessed.

[0034] In step S 502 , the data reading unit 103 accesses the cache memory 303 .

[0035] If the process of Fig. 5 is performed for each loop of steps S401 to S410 in Fig. 4, the process of Fig. 5 (the process of step S404) will be performed even if the data has not been removed from the cache memory 303, resulting in unnecessary processing. The process of Fig. 6 solves this problem. The process of Fig. 6 uses the access times to the cache memory 303 measured in steps S407 and S409.

[0036] In step S601, the data reader 103 compares the access time with a threshold value. If the access time exceeds the threshold value, the process proceeds to step S602. On the other hand, if the access time is equal to or less than the threshold value, the operation of FIG. 6 ends.

[0037] In step S602, the data reading unit 103 determines the range of cache prefetch. As an example, the data reading unit 103 determines the range of cache prefetch as the product of the cache line size and the access time. However, the range of cache prefetch is not limited to this.

[0038] The processing in steps S603 to S605 is similar to the processing in steps S501 to S503 in FIG.

[0039] <Advantages of the First Embodiment> Conventionally, cache prefetching has been performed periodically, but in the first embodiment, it is determined whether or not to perform cache prefetching depending on the access time to the cache memory 303. When performing cache prefetching, the range of cache prefetching can be adjusted. This makes it possible to save CPU resources. In addition, by using the access time to the cache memory 303 when determining whether or not to perform cache prefetching, it is not necessary to use a performance counter that requires a privileged mode.

[0040] <Embodiment 2> 6 described in the first embodiment, the data reading unit 103 accesses all of the cache memory 303. The second embodiment is characterized in that the number of loops from step S602 to step S604 in FIG. 6 is reduced, thereby shortening the processing time of step S404 in FIG. 4.

[0041] Fig. 7 is a flowchart showing an example of the operation of the data processing device according to the second embodiment, and is an alternative process to that shown in Fig. 6. Note that, although the process of data reading unit 103 will be described below, data reading unit 203 also performs the same process.

[0042] In step S701, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold. If the access time exceeds the threshold, the process proceeds to step S702. On the other hand, if the access time is equal to or less than the threshold, the operation of FIG. 7 is terminated.

[0043] In step S 702 , the data reading unit 103 obtains a random number within the range of the size of the cache memory 303 .

[0044] In step S703, the data reading unit 103 obtains a random number within the range of the difference between the size of the cache memory 303 and the range of the random numbers obtained in step S702.

[0045] In step S704, the data reading unit 103 adds the range of random numbers acquired in step S703 to the range of random numbers acquired in step S702.

[0046] By performing the processes in steps S702 to S704, the range to be accessed within the range of the cache memory 303 can be determined randomly.

[0047] In steps S705 and S707, the data reading unit 103 performs a loop process for the process of step S706 within the range obtained in step S704.

[0048] In step S706, the data reading unit 103 accesses the cache memory 303 indicated by the loop counter, and performs cache prefetch.

[0049] <Advantages of the second embodiment> According to the second embodiment, the range of cache prefetching is limited to a certain extent, thereby making it possible to reduce the time required for cache prefetching. Also, by reducing the time required for cache prefetching, it is possible to save CPU resources.

[0050] <Embodiment 3> 6 described in the first embodiment has been described with respect to the case where the data reading unit 103 accesses the entire cache memory 303. In the third embodiment, in order to shorten the processing time of step S404 in Fig. 4, the range of access to the cache memory 303 is divided into several sections, and the number of loops of steps S602 to S604 in Fig. 6 is reduced.

[0051] Fig. 8 is a flowchart showing an example of the operation of the data processing device according to the third embodiment, and is an alternative process to that shown in Fig. 6. Note that, although the process of data reading unit 103 will be described below, data reading unit 203 also performs the same process.

[0052] In step S801, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a first threshold. If the access time exceeds the first threshold, the process proceeds to step S802. On the other hand, if the access time is equal to or less than the first threshold, the process proceeds to step S805.

[0053] In steps S802 and S804, the data reading unit 103 performs a loop process of step S803 until the entire first range from the beginning of the cache memory 303 to the first address is accessed.

[0054] In step S 803 , the data reading unit 103 accesses the cache memory 303 .

[0055] In step S805, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a second threshold. If the access time exceeds the second threshold, the process proceeds to step S806. On the other hand, if the access time is equal to or less than the second threshold, the process proceeds to step S809.

[0056] In steps S806 and S808, the data reading unit 103 performs the loop process of step S807 until the entire second range from the first address to the second address in the cache memory 303 is accessed.

[0057] In step S 807 , the data reading unit 103 accesses the cache memory 303 .

[0058] In step S809, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a third threshold. If the access time exceeds the third threshold, the process proceeds to step S810. On the other hand, if the access time is equal to or less than the third threshold, the data reading unit 103 determines that it is not necessary to refresh the cache memory 303, and ends the operation of FIG.

[0059] In steps S810 and S812, the data reading unit 103 performs a loop process of the process of step S811 until the entire third range from the second address to the third address in the cache memory 303 is accessed.

[0060] In step S 811 , the data reading unit 103 accesses the cache memory 303 .

[0061] <Advantages of the Third Embodiment> According to the third embodiment, the range of cache prefetching is limited to a certain extent, thereby making it possible to reduce the time required for cache prefetching. Also, by reducing the time required for cache prefetching, it is possible to save CPU resources.

[0062] <Fourth embodiment> The fourth embodiment is characterized in that the threshold value for determining whether or not to execute step S404 in FIG. 4 is dynamically changed.

[0063] Fig. 9 is a flowchart showing an example of the operation of the data processing device according to the fourth embodiment, which is an alternative process to Fig. 6. Fig. 9 uses the access time to the cache memory 303 measured in steps S407 and S409 in Fig. 4. Note that, although the process of the data reading unit 103 will be described below, the process of the data reading unit 203 is similar.

[0064] In step S901, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with the maximum threshold value. If the access time exceeds the maximum threshold value, the process proceeds to step S902. On the other hand, if the access time is equal to or less than the maximum threshold value, the process proceeds to step S903.

[0065] In step S902, the data reader 103 updates the maximum value of the threshold.

[0066] In step S903, the data reader 103 compares the access time with the maximum threshold value. If the access time exceeds the maximum threshold value, the process proceeds to step S904. On the other hand, if the access time is equal to or less than the maximum threshold value, the operation of FIG. 9 ends.

[0067] In step S904, the data reading unit 103 determines the range of cache prefetch.

[0068] In steps S905 and S907, the data reading unit 103 performs the loop process of step S906 until all of the cache memory 303 has been accessed.

[0069] In step S 906 , the data reading unit 103 accesses the cache memory 303 .

[0070] <Advantages of the Fourth Embodiment> According to the fourth embodiment, the threshold value for determining whether or not to perform a cache prefetch is dynamically determined, so that the timing of the cache prefetch can be determined in accordance with the characteristics of the target CPU.

[0071] <Fifth Preferred Embodiment> The fifth embodiment is characterized in that the threshold value for determining whether or not to execute step S404 in FIG. 4 is dynamically changed.

[0072] Fig. 10 is a flowchart showing an example of the operation of the data processing device according to the fifth embodiment, which is an alternative process to Fig. 6. Fig. 10 uses the access time to the cache memory 303 measured in steps S407 and S409 in Fig. 4. Note that, although the process of the data reading unit 103 will be described below, the process of the data reading unit 203 is similar.

[0073] In step S1001, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold. If the access time exceeds the threshold, the process proceeds to step S1002. On the other hand, if the access time is equal to or less than the threshold, the process proceeds to step S1003.

[0074] In step S1002, the data reader 103 doubles the threshold value.

[0075] In step S1003, the data reader 103 halves the threshold value.

[0076] In step S1004, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold. The threshold at this time is the threshold after being updated in step S1002 or step S1003. If the access time exceeds the threshold, the process proceeds to step S1005. On the other hand, if the access time is equal to or less than the threshold, the operation of FIG. 10 is terminated.

[0077] In step S1005, the data reading unit 103 determines the range of cache prefetch.

[0078] In steps S1006 and S1008, the data reading unit 103 performs the loop process of step S1007 until the entire cache memory 303 has been accessed.

[0079] In step S 1007 , the data reading unit 103 accesses the cache memory 303 .

[0080] <Advantages of the Fifth Embodiment> According to the fifth embodiment, the threshold for determining whether or not to perform a cache prefetch is dynamically determined, so that the timing of the cache prefetch can be determined in accordance with the characteristics of the target CPU.

[0081] <Sixth embodiment> The sixth embodiment is characterized in that the threshold value for determining whether or not to execute step S404 in FIG. 4 is dynamically changed.

[0082] Fig. 11 is a flowchart showing an example of the operation of the data processing device according to the sixth embodiment, which is an alternative process to Fig. 6. Fig. 11 uses the access time to the cache memory 303 measured in steps S407 and S409 in Fig. 4. Note that, although the process of the data reading unit 103 will be described below, the process of the data reading unit 203 is similar.

[0083] In step S1101, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold value. If the access time exceeds the threshold value, the process proceeds to step S1102. On the other hand, if the access time is equal to or less than the threshold value, the process proceeds to step S1103.

[0084] In step S1102, the data reading unit 103 increases the threshold by α, where α is a number greater than 0. That is, every time the data reading unit 103 determines in step S1101 that the access time exceeds the threshold, it increases the threshold by α at equal intervals.

[0085] In step S1103, the data reading unit 103 reduces the threshold by β, where β is a number greater than 0. α and β may be the same or different. That is, each time the data reading unit 103 determines in step S1101 that the access time is equal to or less than the threshold, it reduces the threshold by β at equal intervals.

[0086] In step S1104, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold. The threshold at this time is the threshold after being updated in step S1102 or step S1103. If the access time exceeds the threshold, the process proceeds to step S1105. On the other hand, if the access time is equal to or less than the threshold, the operation of FIG. 11 ends.

[0087] In step S1105, the data reading unit 103 determines the range of cache prefetch.

[0088] In steps S1106 and S1108, the data reading unit 103 performs the loop process of step S1107 until all of the cache memory 303 has been accessed.

[0089] In step S 1107 , the data reading unit 103 accesses the cache memory 303 .

[0090] <Advantages of the Sixth Embodiment> According to the sixth embodiment, the threshold value for determining whether or not to perform a cache prefetch is dynamically determined, so that the timing of the cache prefetch can be determined in accordance with the characteristics of the target CPU.

[0091] <Embodiment 7> The seventh embodiment is characterized in that a process is carried out in which data that is removed from the cache memory 303 is read with priority.

[0092] Fig. 12 is a flowchart showing an example of the operation of the data processing device according to the seventh embodiment, and is a process replacing that shown in Fig. 6. Fig. 12 uses the access time to the cache memory 303 measured in steps S407 and S409 in Fig. 4. Note that, although the process of the data reading unit 103 will be described below, the process of the data reading unit 203 is similar.

[0093] In step S1201, the data reader 103 determines whether the number of refreshes of the cache memory 303 meets a predetermined fixed value. If the number of refreshes meets the fixed value, the process proceeds to step S1202. On the other hand, if the number of refreshes does not meet the fixed value, the process proceeds to step S1207.

[0094] In steps S1202 and S1206, the data reading unit 103 performs a loop process of steps S1203 to S1205 until the entire cache memory 303 has been accessed.

[0095] In step S1203, the data reading time measurement unit 104 starts measuring the access time taken by the data reading unit 103 to access the cache memory 303. In this disclosure, the CPU counter number is measured using the inline assembler of the target CPU.

[0096] In step S 1204 , the data reading unit 103 accesses the cache memory 303 .

[0097] In step S1205, the data reading time measurement unit 104 ends the measurement of the access time, and measures the CPU counter number when the data reading unit 103 ends its access to the cache memory 303. Then, the data reading time measurement unit 104 calculates the access time taken by the data reading unit 103 to access the cache memory 303 using the difference between the CPU counter number measured in step S1203 and the CPU counter number measured in step S1205.

[0098] In steps S1207 and S1209, the data reading unit 103 performs a loop process of the process of step S1208 the number of times equal to the number of times indicated by the array counter.

[0099] In step S1208, the data reading unit 103 accesses the cache memory 303 indicated by the address stored in the array.

[0100] In step S1210, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold value. If the access time exceeds the threshold value, the process proceeds to step S1211. On the other hand, if the access time is equal to or less than the threshold value, the operation of FIG. 12 ends.

[0101] In step S1211, the data reading unit 103 stores the address of the cache memory 303 in the array.

[0102] In step S1212, data reading unit 103 increments a counter indicating the number of elements in the array.

[0103] <Advantages of the Seventh Embodiment> According to the seventh embodiment, when the access time to the cache memory 303 exceeds a threshold, the address is stored in an array, and only the addresses of the stored array are cache prefetched. That is, the range of cache prefetching is partial. This makes it unnecessary to perform cache prefetching for the entire cache memory 303, and therefore it is possible to reduce the processing time (time required for cache prefetching) of step S404 in FIG. 4. Also, by reducing the time required for cache prefetching, it is possible to save CPU resources.

[0104] <Embodiment 8> The eighth embodiment is characterized in that the read range of the cache memory 303 (the cache prefetch range) is dynamically determined.

[0105] Fig. 13 is a flowchart showing an example of the operation of the data processing device according to the eighth embodiment, and is a process replacing that of Fig. 6. Fig. 13 uses the access time to the cache memory 303 measured in steps S407 and S409 in Fig. 4. Note that, although the process of the data reading unit 103 will be described below, the process of the data reading unit 203 is similar.

[0106] In step S1301, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold. If the access time exceeds the threshold, the process proceeds to step S1302. On the other hand, if the access time is equal to or less than the threshold, the process proceeds to step S1303.

[0107] In step S1302, the data reading unit 103 doubles the read range of the cache memory 303.

[0108] In step S1303, the data reading unit 103 halves the read range of the cache memory 303.

[0109] In step S1304, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold. If the access time exceeds the threshold, the process proceeds to step S1305. On the other hand, if the access time is equal to or less than the threshold, the operation of FIG. 13 ends.

[0110] In steps S1305 and S1307, the data reading unit 103 performs the loop process of step S1306 until the entire read range of the cache memory 303 is accessed.

[0111] In step S 1306 , the data reading unit 103 accesses the cache memory 303 .

[0112] <Advantages of the Eighth Embodiment> According to the eighth embodiment, the time required for cache prefetching can be reduced by dynamically determining the range of cache prefetching. Also, by reducing the time required for cache prefetching, CPU resources can be saved.

[0113] <Embodiment 9> The ninth embodiment is characterized in that the read range of the cache memory 303 (the cache prefetch range) is dynamically determined.

[0114] Fig. 14 is a flowchart showing an example of the operation of the data processing device according to the ninth embodiment, and is a process replacing that of Fig. 6. Fig. 14 uses the access time to the cache memory 303 measured in steps S407 and S409 in Fig. 4. Note that, although the process of the data reading unit 103 will be described below, the process of the data reading unit 203 is similar.

[0115] In step S1401, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold value. If the access time exceeds the threshold value, the process proceeds to step S1402. On the other hand, if the access time is equal to or less than the threshold value, the process proceeds to step S1403.

[0116] In step S1402, the data reading unit 103 increases the read range of the cache memory 303 by a predetermined amount. That is, every time the data reading unit 103 determines in step S1401 that the access time exceeds the threshold, it increases the read range by a predetermined amount at equal intervals.

[0117] In step S1403, the data reading unit 103 reduces the read range of the cache memory 303 by a predetermined amount. That is, the data reading unit 103 reduces the read range by a predetermined amount at equal intervals each time it is determined in step S1401 that the access time is equal to or less than the threshold.

[0118] It should be noted that the predetermined amount in step S1402 and the predetermined amount in step S1403 may be the same or different.

[0119] In step S1404, the data reading unit 103 compares the access time to the cache memory 303 measured in steps S407 and S409 with a threshold value. If the access time exceeds the threshold value, the process proceeds to step S1405. On the other hand, if the access time is equal to or less than the threshold value, the operation of FIG. 14 ends.

[0120] In steps S1405 and S1407, the data reading unit 103 performs the loop process of step S1406 until the entire read range of the cache memory 303 is accessed.

[0121] In step S 1406 , the data reading unit 103 accesses the cache memory 303 .

[0122] <Effects of the 9th embodiment> According to the ninth embodiment, the time required for cache prefetching can be reduced by dynamically determining the range of cache prefetching. Also, by reducing the time required for cache prefetching, CPU resources can be saved.

[0123] Within the scope of the present disclosure, the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0124] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0125] (Appendix 1) a data reading unit for reading data stored in a cache memory associated with the shared memory; A data processing device in which, when an access time required to read data stored in the cache memory exceeds a threshold value, the data reading unit performs cache prefetch by reading the data stored in the cache memory, and determines the range of the cache prefetch based on the access time. (Appendix 2) 2. The data processing device according to claim 1, wherein the data reading unit determines a part of the cache memory as the cache prefetch range and randomly determines the range. (Appendix 3) A plurality of the thresholds are set, 2. The data processing device according to claim 1, wherein the data reading unit determines a portion of the cache memory corresponding to each of the thresholds as the cache prefetch range. (Appendix 4) 2. The data processing device according to claim 1, wherein the data reading unit updates the threshold when the access time exceeds the threshold. (Appendix 5) 2. The data processing device according to claim 1, wherein the data reading unit increases the threshold when the access time exceeds the threshold, and decreases the threshold when the access time is equal to or less than the threshold. (Appendix 6) 2. The data processing device according to claim 1, wherein the data reading unit performs the cache prefetch on an address when the access time exceeds the threshold. (Appendix 7) 2. The data processing device according to claim 1, wherein the data reading unit increases the range of the cache prefetch when the access time exceeds the threshold, and decreases the range of the cache prefetch when the access time is equal to or less than the threshold. (Appendix 8) A data processing method, comprising: when an access time required to read data stored in a cache memory associated with a shared memory exceeds a threshold value, performing a cache prefetch by reading the data stored in the cache memory; and determining a range of the cache prefetch based on the access time. (Appendix 9) 9. The data processing method according to claim 8, wherein a portion of the cache memory is set as the cache prefetch range, and the range is determined randomly. (Appendix 10) A plurality of the thresholds are set, 9. The data processing method according to claim 8, further comprising determining a portion of the cache memory corresponding to each of the thresholds as the cache prefetch range. (Appendix 11) 9. The data processing method of claim 8, further comprising updating the threshold if the access time exceeds the threshold. (Appendix 12) 9. The data processing method of claim 8, further comprising increasing the threshold if the access time exceeds the threshold, and decreasing the threshold if the access time is less than or equal to the threshold. (Appendix 13) 9. The data processing method according to claim 8, further comprising: performing the cache prefetch on an address when the access time exceeds the threshold. (Appendix 14) The data processing method of claim 8, further comprising increasing the range of the cache prefetch when the access time exceeds the threshold, and decreasing the range of the cache prefetch when the access time is equal to or less than the threshold. [Explanation of symbols]

[0126] 101 first OS, 102 first program, 103 data reading unit, 104 data reading time measurement unit, 105 data writing unit, 201 second OS, 202 second program, 203 data reading unit, 204 data reading time measurement unit, 205 data writing unit, 301 hardware, 302 shared memory, 303 cache memory.

Claims

1. a data reading unit for reading data stored in a cache memory associated with the shared memory; A data processing device in which, when an access time required to read data stored in the cache memory exceeds a threshold value, the data reading unit performs cache prefetch by reading the data stored in the cache memory, and determines the range of the cache prefetch based on the access time.

2. 2. The data processing device according to claim 1, wherein said data reading section randomly determines a part of said cache memory as a range of said cache prefetch.

3. A plurality of the thresholds are set, The data processing device according to claim 1 , wherein the data reading section determines a portion of the cache memory corresponding to each of the threshold values ​​as the cache prefetch range.

4. The data processing device according to claim 1 , wherein the data reading unit updates the threshold value when the access time exceeds the threshold value.

5. The data processing device according to claim 1 , wherein the data reading unit increases the threshold when the access time exceeds the threshold, and decreases the threshold when the access time is equal to or less than the threshold.

6. The data processing device according to claim 1 , wherein the data reading unit performs the cache prefetch on an address when the access time exceeds the threshold value.

7. 2 . The data processing device according to claim 1 , wherein the data reading unit increases the range of the cache prefetch when the access time exceeds the threshold, and decreases the range of the cache prefetch when the access time is equal to or less than the threshold.

8. A data processing method, comprising: when an access time required to read data stored in a cache memory associated with a shared memory exceeds a threshold value, performing a cache prefetch by reading the data stored in the cache memory; and determining a range of the cache prefetch based on the access time.

9. 9. The data processing method according to claim 8, wherein a part of said cache memory is set as a range of said cache prefetch, and said range is determined randomly.

10. A plurality of the thresholds are set, 9. The data processing method according to claim 8, further comprising determining a portion of said cache memory corresponding to each of said threshold values ​​as said cache prefetch range.

11. The data processing method according to claim 8 , further comprising updating the threshold value when the access time exceeds the threshold value.

12. The data processing method according to claim 8 , further comprising increasing the threshold value when the access time exceeds the threshold value, and decreasing the threshold value when the access time is equal to or less than the threshold value.

13. The data processing method according to claim 8 , wherein the cache prefetch is performed on an address when the access time exceeds the threshold value.

14. The data processing method according to claim 8 , further comprising: increasing a range of the cache prefetch when the access time exceeds the threshold; and decreasing a range of the cache prefetch when the access time is equal to or less than the threshold.

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