Battery cluster control

Abstract

To provide a battery cluster controller.SOLUTION: According to some embodiments, a battery cluster controller includes a serial interface configured to receive waveform data and a rank over a serial communication bus, a processor configured to generate a switching parameter based on the rank and the waveform data, and a modulation unit configured with the switching parameter to generate a bridge configuration signal to control a bridge for selectively connecting a battery element to an output terminal to generate a first component of a waveform.SELECTED DRAWING: None

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent No. 63 / 536,326, filed September 1, 2023, which is incorporated by reference in its entirety. [Background technology]

[0002] Battery-powered systems, such as electric vehicles, use direct current (DC) battery modules to store power. Some loads in the system may require alternating current (AC) power. Inverters and voltage regulators may be provided to convert the voltage level of the power source, or to convert from a DC power source to an AC power source or from an AC power source to a DC power source. Summary of the Invention [Means for solving the problem]

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] According to some embodiments, a method includes connecting a first cluster controller of a first battery cluster to a serial communication bus; connecting a second cluster controller of a second battery cluster to the serial communication bus; receiving waveform data and a first rank at the first cluster controller from the serial communication bus; receiving waveform data and a second rank at the second cluster controller from the serial communication bus; receiving a waveform start signal at the first cluster controller and the second cluster controller from the serial communication bus; and in response to receiving the waveform start signal, controlling at the first cluster controller a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the waveform data and the first rank to generate a first component of the waveform; and controlling at the second cluster controller a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to an output terminal based on the waveform data and the second rank to generate a second component of the waveform.

[0005] According to some embodiments, the battery cluster controller comprises a serial interface configured to receive waveform data and rank via a serial communication bus, a processor configured to generate switching parameters based on the rank and the waveform data, and a modulation unit configured with the switching parameters to generate bridge configuration signals for controlling a bridge to selectively connect battery elements to an output terminal to generate a first component of the waveform.

[0006] According to some embodiments, a system includes an output terminal; a serial communication bus; a first battery cluster, the first battery element; a first bridge, the first bridge configured to selectively connect the first battery element to the output terminal based on a state of the first bridge; and a first cluster controller connected to the first bridge and the serial communication bus, the first cluster controller configured to receive waveform data and a first rank from the serial communication bus, receive a waveform start signal from the serial communication bus, and control the first bridge to connect the first battery element to the output terminal based on the waveform data and the first rank to generate a first component of the waveform. a first battery cluster comprising: a second battery cluster comprising a second battery element; a second bridge configured to selectively connect the second battery element to an output terminal based on a state of the second bridge; and a second cluster controller connected to the second bridge and to a serial communication bus, the second cluster controller configured to receive waveform data and a second rank from the serial communication bus, receive a waveform start signal from the serial communication bus, and control the second bridge to connect the second battery element to the output terminal based on the waveform data and the second rank to generate a second component of the waveform.

[0007] According to some embodiments, the system includes means for connecting a first cluster controller of a first battery cluster to a serial communication bus; means for connecting a second cluster controller of a second battery cluster to the serial communication bus; means for receiving waveform data and a first rank at the first cluster controller from the serial communication bus; means for receiving waveform data and a second rank at the second cluster controller from the serial communication bus; means for receiving a waveform start signal at the first cluster controller and the second cluster controller from the serial communication bus; and in response to receiving the waveform start signal, means for controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the waveform data and the first rank to generate a first component of the waveform; and means for controlling a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to an output terminal based on the waveform data and the second rank to generate a second component of the waveform.

[0008] To the accomplishment of the foregoing and related ends, the following description and the annexed drawings set forth certain illustrative aspects and implementations, which are indicative of but a few of the various ways in which the one or more aspects may be employed. Other aspects, advantages and novel features of the present disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a battery system, according to some embodiments. [Diagram 2] FIG. 2 is a schematic diagram of a cluster controller in a battery system, according to some embodiments. [Diagram 3] 4 is a waveform diagram illustrating an output waveform generated by a battery system according to some embodiments. [Figure 4]1 is a diagram illustrating switching behavior for a battery cluster as a function of rank to generate an output waveform according to some embodiments. [Diagram 5] FIG. 1 is a flow diagram of a method for generating a waveform in a battery system, according to some embodiments. [Figure 6] FIG. 1 illustrates an exemplary embodiment of a computer-readable medium, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The claimed subject matter will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it may be apparent that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of the claimed subject matter.

[0011] Equivalent or similar elements, or elements having equivalent or similar functions, are indicated by equivalent or similar reference numerals in the following description. Note that, in the drawings, identical or functionally equivalent elements are designated by the same reference numerals, and therefore, duplicated descriptions of elements designated by the same reference numerals may be omitted. Therefore, descriptions provided for elements having the same or similar reference numerals can be mutually exchanged.

[0012] In this regard, directional terms such as "top," "bottom," "below," "above," "front," "behind," "back," "leading," "trailing," and the like, may be used with reference to the orientation of the figures being described. Because some of the embodiments can be positioned in several different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Therefore, the following detailed description is not to be taken in a limiting sense.

[0013] When an element is referred to as being "connected" or "coupled" to another element, it will be understood that it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted similarly (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.).

[0014] In the embodiments described herein or shown in the drawings, any direct electrical connection or coupling, i.e., any connection or coupling without additional intervening elements, may be implemented by an indirect connection or coupling, i.e., a connection or coupling with one or more additional intervening elements, or vice versa, so long as the general purpose of the connection or coupling, for example, to transmit a particular type of signal or transmit a particular type of information, is essentially maintained. Features from different embodiments may be combined to form further embodiments. For example, variations or modifications described with respect to one of the embodiments may be applicable to other embodiments, unless otherwise indicated.

[0015] The term "substantially" may be used herein to account for small manufacturing tolerances (e.g., within 5%) that may be accepted in the industry without departing from the aspects of the embodiments described herein.

[0016] 1 is a schematic diagram of a battery system 100 according to some embodiments. In some embodiments, the battery system 100 comprises battery clusters 102, individually referred to as battery clusters 102A, 102B, 102N-1, 102N, a power management integrated circuit (PMIC) 104 connected to a power supply voltage (e.g., 12V) and a ground reference (e.g., chassis ground), a host processor 106 connected to the PMIC 104 to receive a low voltage (LV) power source, and a serial transceiver 108 connected between the host processor 106 and the battery clusters 102. The battery system 100 may be implemented in an electric vehicle, and the battery clusters 102 may provide power to a load 110, such as an electric motor for moving the electric vehicle or other auxiliary loads in the electric vehicle. The battery system 100 is connected to the load 110 by a high-side output relay 112 and a low-side output relay 114 at output terminals 112T, 114T. Battery clusters 102 are subdivided and separately controlled elements of the main battery.

[0017] In some embodiments, each battery cluster 102 comprises a cluster controller 116, a battery element 118, an H-bridge 120 for selectively connecting the battery element 118 to the output relays 112 and 114, and an H-bridge driver 122 for controlling the state of the H-bridge 120. In some embodiments, the cluster controller 116 is implemented using a Programmable System-on-Chip (PSoC®) hardware with programmable analog sub-blocks that can be configured to control the battery cluster 102 based on instructions from the host processor 106. The PSoC® may include encryption hardware to provide security features. The cluster controller 116 may include a processing unit 124 including a microcontroller and non-volatile memory (or some other type of memory), and an analog front end 126. In some embodiments, the analog front end 126 provides an interface for sensing characteristics of the battery elements 118, such as temperature, voltage, or other parameters. In some embodiments, the host processor 106 uses a Controller Area Network (CAN) protocol to communicate with external domain controllers and a Universal Asynchronous Receiver-Transmitter (UART) protocol to communicate with the serial transceiver 108. The serial transceiver 108 may implement an Isolated UART Protocol (ISO-UART) protocol to communicate with a corresponding serial interface 202 (see FIG. 2) in the cluster controller 116. In some embodiments, the cluster controller 116 sends messages to the H-bridge driver 122 using a Serial Peripheral Interface (SPI) or Inter-Integrated Circuit (I2C) protocol.

[0018] The H-bridge 120 comprises a set of switches that determine how the battery element 118 is connected to the output relays 112 and 114. In some embodiments, the state of the H-bridge 120 is controlled by the host processor 106 by sending status messages to the cluster controller 116. In some embodiments, the functionality for controlling the state of the H-bridge 120 is split between the host processor 106 and the cluster controller 116. The H-bridge 120 can be configured by an H-bridge driver 122 to isolate the battery element 118 from the output relays 112 and 114, to connect the battery element 118 to the output relays 112 and 114 with positive polarity, or to connect the battery element 118 to the output relays 112 and 114 with negative polarity.

[0019] The number of battery clusters 102 may vary. The battery system 100 in Figure 1 shows an arrangement for one phase of a three-phase system. Additional battery clusters 102 are provided for each phase (e.g., 16 / phase*3 phases=48 battery clusters).

[0020] In some embodiments, the cluster controller 116 is connected to a serial communication bus 108B implemented by the serial transceiver 108. The cluster controllers 116 are daisy-chained, and the cluster controller 116 forwards the message to the next cluster controller 116 in the daisy chain until all cluster controllers 116 have received the message. In some embodiments, the serial communication bus 108B is configured in a ring topology where a message for the host processor 106 is forwarded to the cluster controller 116 of the last battery cluster 102N in the daisy chain and then forwarded to the serial transceiver 108. For example, a ring topology message is sent in a counterclockwise direction from the cluster controller 116 of the battery cluster 102A to the cluster controller 116 of the battery cluster 102N. A message originating from one of the cluster controllers 116 is sent in the same direction to the serial transceiver 108 for forwarding to the host processor 106.

[0021] In some embodiments, the serial communication bus 108B supports automatic addressing. During system initialization, the serial transceiver 108 identifies the cluster controllers 116 of the battery clusters 102 and assigns an address, such as a ring position, to each cluster controller 116. Initially, after power-up or interface timeout, each cluster controller 116 has an address of "0", and a first bus address is assigned to the cluster controller 116 of the first battery cluster 102A in response to receiving a wake-up message from the serial transceiver 108. The cluster controller 116 of the first battery cluster 102A forwards the wake-up message to the cluster controller 116 of the second battery cluster 102B, which results in the cluster controller 116 of the second battery cluster 102B being assigned an address. The message forwarding and address assignment continues until all of the cluster controllers 116 of the battery clusters 102 have been assigned addresses. The serial transceiver 108 may also communicate the configuration of the serial communications bus 108B and the attached cluster controller 116 to the host processor 106.

[0022] On the serial communication bus 108B, the serial transceiver 108 provides isolation between the host processor 106 and the battery clusters 102, which are in different voltage domains. If the host processor 106 communicates in parallel with the cluster controllers 116 of the battery clusters 102, each connection between the host processor 106 and the cluster controllers 116 requires 16 isolation circuits times 3 phases for a total of 48 isolation circuits. Furthermore, parallel addressing does not support automatic addressing and requires production programming to address the battery clusters 102. The use of a serial topology reduces bill of materials costs, reduces footprint, and reduces programming complexity.

[0023] The battery cluster 102 may be controlled to generate a time-varying waveform at the output terminals 112T or 114T to supply power to the load 110. For example, the state of the H-bridge 120 for the battery cluster 102 may be controlled to generate an AC waveform, such as a sinusoidal signal, at the output terminals 112T or 114T. Controlling the battery cluster 102 in this manner eliminates the need for a separate inverter between the battery system 100 and the load 110 to generate the AC waveform.

[0024] In some embodiments, the processing overhead for generating the waveform is shared by the host processor 106 and the cluster controller 116. The host processor 106 communicates waveform parameters such as rank, frequency (Fsine), cluster voltage (Vcluster), and amplitude (Vmax) to the cluster controller 116 and signals the start of waveform generation. Based on the waveform parameters, each cluster controller 116 calculates the switching time of its associated battery cluster 102 and controls the H-bridge driver 122 to configure the H-bridge 120 to contribute to the waveform. However, because each cluster controller 116 independently controls the switching for the battery cluster 102, the clocks of the cluster controllers 116 need to be synchronized. The host processor 106 controls the clock synchronization process to align the clocks of the cluster controllers 116.

[0025] 2 is a schematic diagram of a cluster controller 116 in the battery system 100, according to some embodiments. In some embodiments, each cluster controller 116 includes a physical layer (PHY) 200 for implementing signaling in a serial protocol (e.g., ISO-UART), a CPU 201, a serial interface 202 for extracting data per the serial protocol, trigger multiplexers (MUX) 204 and 205, and pulse width modulation (PWM) units 206 and 208 configured to generate bridge configuration signals ARM1 and ARM2 to control the H-bridge driver 122 to set the state of the H-bridge 120. In some embodiments, asserting ARM1 while deasserting the ARM2 signal controls the H-bridge driver 122 to connect the battery element 118 in positive polarity, and asserting ARM2 while deasserting the ARM2 signal controls the H-bridge driver 122 to connect the battery element 118 in negative polarity. Deasserting both ARM1 and ARM2 disconnects the battery element 118. Trigger multiplexers 204 and 205 are part of a larger family of programmable multiplexers that allow the routing of trigger signals from any source to a destination peripheral device.

[0026] The cluster controller 116 achieves clock synchronization using an internal mail oscillator (IMO) clock 212 and a counter 214. The IMO clock 212 has a trim register 212R for storing configurable trim parameters that trim the transitions of the IMO clock 212, for example, in a positive or negative direction, to achieve synchronization. In one example, the frequency of the IMO clock 212 is 48 MHz with a trim step size of 15 kHz, resulting in a trim accuracy of 0.03%. To facilitate synchronization, the host processor 106 sends synchronization signals including a start signal and a stop signal. A predetermined time interval between the start signal and the stop signal is converted to an ideal count value based on the frequency of the IMO clock 212, communicated by the host processor 106 to the cluster controller 116, and stored in the register 216. The cluster controller starts the counter 214 in response to receiving the start signal from the host processor 106. The cluster controller stops the counter 214 in response to receiving the stop signal from the host processor 106. The CPU 201 calculates the difference between the actual count of the start and stop signals recorded in counter 214 and the ideal count value in register 216. The frequency error is

number

number

[0027] In some embodiments, the cluster controller 116 stores the waveform parameters (Rank, Fsine, Vcluster, Vmax) sent by the host processor 106 in waveform registers 210. The CPU 201 calculates the switch times and PWM settings based on the waveform parameters and configures the PWMs 206 and 208. Although two CPUs 201 are shown in FIG. 1 to illustrate the calculations performed for synchronization and the calculations performed for switching, these calculations can be performed by the same physical processing unit or by more than two processing units.

[0028] 3 is a waveform diagram illustrating an output waveform 300 generated by the battery system 100, according to some embodiments. In some embodiments, the output waveform 300 may be an approximation of a sinusoidal signal. In an example having 16 battery clusters 102, the cluster voltage Vcluster is 30V and the maximum voltage Vmax is 480V. Each battery cluster 102 switches in or out once for each quarter period of the waveform for a total of 64 transitions. The numbers above the output waveform 300 represent the stage number of the switching scheme (e.g., 64 stages for one period of the output waveform 300), and the numbers below the output waveform 300 represent the rank of the battery cluster 102 switching in the current time interval.

[0029] In some embodiments, the rank does not correspond to the device number or position of the cluster controller 116 on the serial communication bus 108B. For example, the battery clusters 102 may not be sequentially switched. The rank represents the relative position of the cluster controller 116 in the switching scheme for generating the output waveform 300. The host processor 106 may assign the initial rank based on the load balancing of the battery clusters 102. After the initial rank assignment, each cluster controller 116 may follow a predefined rank sequence stored in a portion of the non-volatile memory 218 of the cluster controller 116. Thus, the rank may change over time to provide load balancing because each rank does not remain switched in or out for the same time interval. The host processor may change the initial rank and restart the rank sequence to address secondary or tertiary balancing issues.

[0030] To generate the output waveform 300, each cluster controller 116 calculates its switching behavior and configures the PWMs 206 and 208 according to its assigned rank. When the ranks change for load balancing based on the assignment from the host processor 106 or based on the rank sequence in the non-volatile memory 218, the cluster controllers 116 update the switching behavior. In the output waveform 300, switching occurs more frequently in the zero crossing regions. The minimum step time for switching for a system with NumCluster=16 and Fsine=1kHz is:

number

[0031] 4 is a diagram 400 illustrating switching behavior for a battery cluster 102 as a function of rank to generate an output waveform 300, according to some embodiments. Diagram 400 includes a switch position table 402, a voltage table 404, a switch time table 406, and a counter value table 408.

[0032] Each cluster has four switch positions per period of the output waveform 300. For a sine wave, the first half period is positive and the second half period is negative. Each battery cluster 102 switches four times, namely Ph1: switch on positive, Ph2: switch off, Ph3: switch on negative, and Ph4: switch off. The switching events are programmed into the PWM 206 to control the ARM1 signal and into the PWM 208 to control the ARM2 signal. The switch position of a given battery cluster 102 is determined based on its assigned rank as shown in the switch position table 402 as follows: Switch position = [Ph1: rank, Ph2: ([NumCluster 2+1] - rank), Ph3: ([NumCluster 2] + rank), Ph4: ([NumCluster 4+1] - rank)]

[0033] The voltage at each switch position is calculated based on the position and the voltage Vcluster of each battery cluster 102 as shown in the voltage table 404 as follows:

number

[0034] The switch time for each switch position is calculated based on the frequency Fsine, Tsine=1 / Fsine, the maximum sine voltage Vmax, and the voltage Vsine at the particular switch position as shown in switch time table 406, as follows:

number

[0035] The PWM units 206, 208 use counters to control the transition times. The counter values ​​for a cycle of the output waveform 300 can range from 0 to 200 as shown in table 408 as an example, with each counter step having a length of 5 μs for a 1 kHz sine wave. The counter value at each switch position can be calculated based on the time Tswitch and the counter time step Tcounter step (e.g., 5 μs) as shown in table 408 as follows:

number

[0036] The host processor 106 sends the waveform parameters (Rank, Fsine, Vcluster, Vmax) of the output waveform 300 to the cluster controller 116. The cluster controller 116 stores the waveform parameters in the waveform registers 210. The CPU 201 calculates the switch times and PWM settings and configures the switching behavior in the PWMs 206, 208. The host processor 106 sends a start waveform signal to the cluster controller 116. The switching behavior of the battery clusters 102 is synchronized based on the trim parameters in the IMO clock 212.

[0037] 5 is a flow diagram of a method 500 for generating an output waveform 300 in a battery system 100, according to some embodiments. At 502, a first cluster controller 116 of a first battery cluster 102 is connected to a serial communication bus 108B. At 504, a second cluster controller 116 of a second battery cluster 102 is connected to the serial communication bus 108B. At 506, waveform data and a first rank are received from the serial communication bus 108B at the first cluster controller 116. At 508, waveform data and a second rank are received from the serial communication bus 108B at the second cluster controller 116. At 510, a waveform start signal is received from the serial communication bus 108B at the first cluster controller 116 and the second cluster controller 116. In some embodiments, a start / stop synchronization signal may be sent before the waveform start signal. At 512, in response to receiving the waveform start signal, the first cluster controller 116 controls the first bridge 120 in the first battery cluster 102 to connect a first battery terminal of the first battery cluster 102 to the output terminal 112T or 114T based on the waveform data and the first rank to generate a first component of the output waveform 300. At 514, in response to receiving the waveform start signal, the second cluster controller 116 controls the second bridge 120 of the second battery cluster 102 to connect a second battery terminal of the second battery cluster 102 to the output terminal 112T or 114T based on the waveform data and the second rank to generate a second component of the output waveform 300.

[0038] FIG. 6 illustrates an exemplary embodiment 600 of a computer-readable medium 602, according to some embodiments. One or more embodiments include a computer-readable medium including processor-executable instructions configured to perform one or more of the techniques presented herein. The embodiment 600 comprises a non-transitory computer-readable medium 602 (e.g., a CD-R, a DVD-R, a flash drive, a platter of a hard disk drive, etc.) having computer-readable data 604 encoded thereon. The computer-readable data 604 includes a set of processor-executable computer instructions 606 that, when executed by a computing device 608 including a reader 610 for reading the processor-executable computer instructions 606 and a processor 612 for executing the processor-executable computer instructions 606, are configured to facilitate operation according to one or more of the principles described herein. In some embodiments, the processor-executable computer instructions 606, when executed, are configured to facilitate execution of a method 614, such as at least some of the methods described above. In some embodiments, the processor-executable computer instructions 606, when executed, are configured to facilitate implementation of a system, such as at least some of the systems described above. Many such computer-readable media configured to operate in accordance with the techniques presented herein may be devised by those of skill in the art.

[0039] Controlling the battery clusters 102 by determining switching parameters in the cluster controller 116 based on the assigned rank and waveform data reduces traffic on the serial communication bus 108S and reduces the processing load on the host processor 106. This approach reduces hardware costs, reduces isolated communication power consumption due to reduced traffic, and provides programming flexibility for adding future features.

[0040] According to some embodiments, a method includes connecting a first cluster controller of a first battery cluster to a serial communication bus; connecting a second cluster controller of a second battery cluster to the serial communication bus; receiving waveform data and a first rank at the first cluster controller from the serial communication bus; receiving waveform data and a second rank at the second cluster controller from the serial communication bus; receiving a waveform start signal at the first cluster controller and the second cluster controller from the serial communication bus; and in response to receiving the waveform start signal, controlling at the first cluster controller a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the waveform data and the first rank to generate a first component of the waveform; and controlling at the second cluster controller a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to an output terminal based on the waveform data and the second rank to generate a second component of the waveform.

[0041] According to some embodiments, the method includes receiving a synchronization message at a first cluster controller and adjusting a trim parameter of a clock unit in the first cluster controller based on the synchronization message to generate a clock signal based on the trim parameter, and controlling a first bridge of a first battery cluster in the first cluster controller includes controlling the first bridge based on the clock signal after adjusting the trim parameter.

[0042] According to some embodiments, receiving the synchronization message includes receiving a start message and receiving a stop message, and adjusting a trim parameter of the clock unit includes starting a counter coupled to receive the clock signal in response to receiving the start message, stopping the counter in response to receiving the stop message to generate a measurement count, determining a frequency error based on the measurement count and an ideal count for the synchronization message, and adjusting the trim parameter based on the frequency error.

[0043] According to some embodiments, in the first cluster controller, controlling the first bridge of the first battery cluster includes generating switching parameters based on the first rank and waveform data, and configuring a modulation unit configured to control the first bridge based on the switching parameters.

[0044] According to some embodiments, generating the switching parameters includes determining a switch position for the first bridge based on the first rank, determining a waveform voltage based on the switch position and a cluster voltage of the first battery cluster, and determining a switch time for the switch position based on the waveform voltage and the waveform data, where the switching parameters include the switch time.

[0045] According to some embodiments, generating the switching parameter includes determining a count value based on the switch time, the switching parameter including the count value.

[0046] According to some embodiments, connecting the first cluster controller to the serial communication bus and connecting the second cluster controller to the serial communication bus includes connecting the first cluster controller and the second cluster controller to the serial communication bus in a ring topology.

[0047] According to some embodiments, connecting the first cluster controller to the serial communication bus includes automatically assigning an address to the first cluster controller according to a protocol of the serial communication bus.

[0048] According to some embodiments, the method includes modifying a first rank in a first cluster controller according to a rank sequence to generate a modified first rank, controlling a first bridge in the first cluster controller based on the modified first rank, modifying a second rank in a second cluster controller according to the rank sequence to generate a modified second rank, and controlling a second bridge in the second cluster controller based on the modified second rank.

[0049] According to some embodiments, the battery cluster controller comprises a serial interface configured to receive waveform data and rank via a serial communication bus, a processor configured to generate switching parameters based on the rank and the waveform data, and a modulation unit configured with the switching parameters to generate bridge configuration signals for controlling a bridge to selectively connect battery elements to an output terminal to generate a first component of the waveform.

[0050] According to some embodiments, the battery cluster controller comprises a clock unit coupled to the modulation unit and configured to generate a clock signal based on the trim parameter, and the processor is configured to receive a synchronization message and adjust the trim parameter based on the synchronization message.

[0051] According to some embodiments, the battery cluster controller comprises a counter connected to the clock unit, the synchronization message includes a start message and a stop message, and the processor is configured to start the counter in response to receiving the start message and stop the counter in response to receiving the stop message to generate a measurement count, determine a frequency error based on the measurement count and an ideal count relative to the synchronization message, and adjust a trim parameter based on the frequency error.

[0052] According to some embodiments, the processor is configured to generate the switching parameters by determining a switch position for the bridge based on the rank, determining a waveform voltage based on the switch position and a cluster voltage of the battery cluster, determining a switch time for the switch position based on the waveform voltage and the waveform data, and configuring the switching parameters based on the switch time.

[0053] According to some embodiments, the processor is configured to generate the switching parameters by determining a count value based on the switch time and configuring the switching parameters based on the count value.

[0054] According to some embodiments, the serial interface is configured to receive an address that is automatically assigned to the battery cluster controller according to a protocol of the serial communication bus.

[0055] According to some embodiments, the processor is configured to modify the rank according to the rank sequence to generate a modified rank, and to update a switching parameter in the modulation unit based on the modified rank.

[0056] According to some embodiments, a system includes an output terminal; a serial communication bus; a first battery cluster, the first battery element; a first bridge, the first bridge configured to selectively connect the first battery element to the output terminal based on a state of the first bridge; and a first cluster controller connected to the first bridge and the serial communication bus, the first cluster controller configured to receive waveform data and a first rank from the serial communication bus, receive a waveform start signal from the serial communication bus, and control the first bridge to connect the first battery element to the output terminal based on the waveform data and the first rank to generate a first component of the waveform. a first battery cluster comprising: a second battery cluster comprising a second battery element; a second bridge configured to selectively connect the second battery element to an output terminal based on a state of the second bridge; and a second cluster controller connected to the second bridge and to a serial communication bus, the second cluster controller configured to receive waveform data and a second rank from the serial communication bus, receive a waveform start signal from the serial communication bus, and control the second bridge to connect the second battery element to the output terminal based on the waveform data and the second rank to generate a second component of the waveform.

[0057] According to some embodiments, the first cluster controller comprises a clock unit configured to generate a clock signal based on a trim parameter, a processor configured to generate switching parameters based on rank and waveform data, and a modulation unit configured with the switching parameters to generate a bridge configuration signal for controlling the first bridge based on the clock signal, wherein the processor is configured to receive a synchronization message and adjust the trim parameter based on the synchronization message.

[0058] According to some embodiments, the first cluster controller comprises a counter connected to the clock unit, the synchronization message includes a start message and a stop message, and the processor is configured to start the counter in response to receiving the start message and stop the counter in response to receiving the stop message to generate a measurement count, determine a frequency error based on the measurement count and an ideal count relative to the synchronization message, and adjust a trim parameter based on the frequency error.

[0059] According to some embodiments, the first cluster controller comprises a processor configured to generate switching parameters based on the rank and the waveform data, and a modulation unit configured with the switching parameters to generate a bridge configuration signal for controlling the first bridge, wherein the processor is configured to generate the switching parameters by determining a switch position for the first bridge based on the first rank, determining a waveform voltage based on the switch position and a cluster voltage of the first battery cluster, determining a switch time for the switch position based on the waveform voltage and the waveform data, and configuring the switching parameters based on the switch time.

[0060] Various operations of the embodiments are provided herein. The order in which some or all of the operations are described should not be construed as implying that these operations are necessarily order dependent. Alternative orderings will be understood with the benefit of this specification. Furthermore, it will be understood that not all operations are necessarily present in each embodiment provided herein. It will also be understood that not all operations are required in some embodiments.

[0061] Any aspect or design described herein as "example" or the like should not be construed as necessarily advantageous over other aspects or designs. Rather, use of the word "example" is intended to present one possible aspect and / or implementation that may be associated with the technology presented herein. Such an example is not intended to be necessary or limiting of such technology. Various embodiments of such technology may include such an example alone or in combination with other features, and / or may modify and / or omit the illustrated example.

[0062] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the appended claims subject matter is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least a portion of the claims.

[0063] As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or." Furthermore, "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless otherwise specified or unless the singular form is clearly intended from the context. Also, at least one of A and B, etc. generally means A or B or both A and B. Furthermore, to the extent that "includes," "having," "has," "with," or variations thereof are used, such terms are intended to be as inclusive as the term "comprising." Also, unless otherwise specified, "first," "second," etc. are not intended to imply any temporal or spatial aspects, ordering, or the like. Rather, such terms are merely used as identifiers, names, or the like of features, elements, items, and the like. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0064] Also, although the present disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art based on reading and understanding the present specification and the accompanying drawings. The present disclosure includes all such modifications and modifications, and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond to any components that perform the specified function of the described components (e.g., functionally equivalent), even if they are not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the present disclosure shown herein, unless otherwise indicated. Furthermore, although certain features of the present disclosure may be disclosed with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments as may be desired and advantageous for any given or specific application. Furthermore, to the extent the terms "include," "having," "has," "with," or variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in the same manner as the term "comprising."

[0065] Although the subject matter has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present disclosure, will be apparent to those skilled in the art upon reference to the description. Accordingly, the appended claims are intended to cover such modifications or embodiments.

Claims

1. connecting a first cluster controller of a first battery cluster to a serial communication bus; connecting a second cluster controller of a second battery cluster to the serial communication bus; receiving waveform data and a first rank at the first cluster controller from the serial communication bus; receiving the waveform data and a second rank at the second cluster controller from the serial communication bus; receiving a waveform start signal from the serial communication bus at the first cluster controller and the second cluster controller; In response to receiving the waveform start signal, controlling, in the first cluster controller, a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the waveform data and the first rank to generate a first component of a waveform; controlling, in the second cluster controller, a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the waveform data and the second rank to generate a second component of the waveform; The method includes:

2. The method comprises: receiving a synchronization message at the first cluster controller; adjusting the trim parameters of a clock unit at the first cluster controller based on the synchronization message to generate a clock signal based on the trim parameters; Including, In the first cluster controller, controlling the first bridge of the first battery cluster includes controlling the first bridge based on the clock signal after adjusting the trim parameter. The method of claim 1.

3. Receiving the synchronization message includes: Receiving an initiation message; receiving a stop message; Including, Adjusting the trim parameters of the clock unit includes: starting a counter coupled to receive the clock signal in response to receiving the start message; stopping the counter in response to receiving the stop message to generate a measurement count; determining a frequency error based on the measured count and an ideal count for the synchronization message; adjusting the trim parameters based on the frequency error; and Including, The method of claim 2.

4. Controlling the first bridge of the first battery cluster in the first cluster controller includes: generating switching parameters based on the first rank and the waveform data; configuring a modulation unit configured to control the first bridge based on the switching parameter; Including, The method of claim 1.

5. Generating the switching parameters includes: determining a switch position for the first bridge based on the first rank; determining a waveform voltage based on the switch position and a cluster voltage of the first battery cluster; determining a switch time for the switch position based on the waveform voltage and the waveform data; Including, The switching parameters include the switch time. The method according to claim 4.

6. generating the switching parameter includes determining a count value based on the switch time; The switching parameters include the count value. The method according to claim 5.

7. The coupling of the first cluster controller to the serial communication bus and the coupling of the second cluster controller to the serial communication bus include: connecting the first cluster controller and the second cluster controller to the serial communication bus in a ring topology; The method of claim 1.

8. Coupling the first cluster controller to the serial communication bus includes: automatically assigning an address to the first cluster controller according to a protocol of the serial communication bus; The method of claim 1.

9. The method comprises: modifying the first rank in the first cluster controller according to a rank sequence to generate a modified first rank; controlling, in the first cluster controller, the first bridge based on the modified first rank; modifying the second rank in the second cluster controller according to the rank sequence to generate a modified second rank; controlling, in the second cluster controller, the second bridge based on the modified second rank; Including, The method of claim 1.

10. a serial interface configured to receive the waveform data and the rank via a serial communication bus; a processor configured to generate switching parameters based on the rank and the waveform data; a modulation unit configured using the switching parameters to generate bridge configuration signals for controlling a bridge to selectively connect battery elements to an output terminal to generate a first component of a waveform; A battery cluster controller comprising:

11. the battery cluster controller comprises a clock unit coupled to the modulation unit and configured to generate a clock signal based on a trim parameter; The processor, Receives a synchronization message, configured to adjust the trim parameters based on the synchronization message; The battery cluster controller of claim 10.

12. the battery cluster controller comprises a counter coupled to the clock unit; The synchronization messages include a start message and a stop message; The processor, Initiating the counter in response to receiving the initiation message; stopping the counter in response to receiving the stop message to generate a measurement count; determining a frequency error based on the measured count and an ideal count for the synchronization message; configured to adjust the trim parameters based on the frequency error. The battery cluster controller of claim 11.

13. The processor, determining a switch position for the bridge based on the rank; determining a waveform voltage based on the switch position and a cluster voltage of the battery cluster; determining a switch time for the switch position based on the waveform voltage and the waveform data; By configuring the switching parameters based on the switch time, configured to generate the switching parameters; The battery cluster controller of claim 12.

14. The processor, determining a count value based on the switch time; Configuring the switching parameters based on the count value configured to generate the switching parameters; The battery cluster controller of claim 13.

15. the serial interface is configured to receive an address automatically assigned to the battery cluster controller according to a protocol of the serial communication bus; The battery cluster controller of claim 10.

16. The processor, modifying the ranks according to the rank sequence to generate modified ranks; configured to update the switching parameters in the modulation unit based on the revised rank. The battery cluster controller of claim 10.

17. An output terminal; A serial communication bus; a first battery cluster; a second battery cluster; A system comprising: The first battery cluster comprises: A first battery element; a first bridge configured to selectively connect the first battery element to the output terminal based on a state of the first bridge; a first cluster controller connected to the first bridge and the serial communication bus; Equipped with The first cluster controller receiving waveform data and a first rank from the serial communication bus; receiving a waveform start signal from the serial communication bus; configured to control the first bridge to connect the first battery element to the output terminal based on the waveform data and the first rank to generate a first component of a waveform; The second battery cluster comprises: A second battery element; and a second bridge configured to selectively connect the second battery element to the output terminal based on a state of the second bridge; and a second cluster controller connected to the second bridge and the serial communication bus; Equipped with The second cluster controller receiving the waveform data and a second rank from the serial communication bus; receiving the waveform start signal from the serial communication bus; and controlling the second bridge to connect the second battery element to the output terminal based on the waveform data and the second rank to generate a second component of the waveform. system.

18. The first cluster controller a clock unit configured to generate a clock signal based on the trim parameters; a processor configured to generate switching parameters based on the rank and the waveform data; a modulation unit configured with the switching parameters to generate a bridge configuration signal for controlling the first bridge based on the clock signal; Equipped with The processor, Receives a synchronization message, configured to adjust the trim parameters based on the synchronization message; 20. The system of claim 17.

19. the first cluster controller comprises a counter connected to the clock unit; The synchronization messages include a start message and a stop message; The processor, Initiating the counter in response to receiving the initiation message; stopping the counter in response to receiving the stop message to generate a measurement count; determining a frequency error based on the measured count and an ideal count for the synchronization message; configured to adjust the trim parameters based on the frequency error.

20. The system of claim 18.

20. The first cluster controller a processor configured to generate switching parameters based on the rank and the waveform data; a modulation unit configured with the switching parameters to generate a bridge configuration signal for controlling the first bridge; Equipped with The processor, determining a switch position for the first bridge based on the first rank; determining a waveform voltage based on the switch position and a cluster voltage of the first battery cluster; determining a switch time for the switch position based on the waveform voltage and the waveform data; By configuring the switching parameters based on the switch time, configured to generate the switching parameters; 20. The system of claim 17.

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