Solid state imaging element, imaging device, and method for controlling solid state imaging element

Abstract

To shorten an AD (Analog to Digital) conversion time while suppressing increase in power consumption in a solid state imaging element for performing AD conversion.SOLUTION: A solid state imaging element includes a constant current source, a control transistor, and a body bias control unit. In the solid state imaging element, the constant current source is connected to a vertical signal line. The control transistor lowers potential of the vertical signal line in accordance with a predetermined control signal. The body bias control unit controls body bias of the control transistor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present technology relates to a solid-state imaging element, and more particularly to a solid-state imaging element having vertical signal lines wired therein, an imaging device, and a method for controlling the solid-state imaging element. [Background technology]

[0002] In recent years, there has been a trend toward a demand for solid-state imaging devices with high frame rates that can smoothly represent the movement of a subject. To meet this demand, for example, a solid-state imaging device has been proposed in which a control transistor that lowers the potential of a vertical signal line when transferring charges within a pixel is added to each column (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-022259 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, the potential of the vertical signal line is lowered during the transfer of the electric charge, thereby shortening the AD (Analog to Digital) conversion time. However, in the above-mentioned conventional technology, the settling time until the potential of the vertical signal line converges may vary due to PVT (Process, Voltage, Temperature) variations. For this reason, it is necessary to provide a sufficient margin to the pulse width of the pulse signal to the control transistor in consideration of the variation in the settling time, and as a result, it becomes difficult to further shorten the AD (Analog to Digital) conversion time. If the adjustment accuracy of the pulse width is increased, the margin can be reduced, but a highly accurate clock signal is required to achieve this, and power consumption increases. In addition, if the current value of the constant current source connected to the vertical signal line is increased, the settling time can be shortened, but power consumption also increases in this case. Thus, in the above-mentioned solid-state imaging element, it is difficult to shorten the AD conversion time while suppressing an increase in power consumption.

[0005] This technology was developed in light of these circumstances, and aims to shorten the AD conversion time in solid-state imaging elements that perform AD conversion while suppressing increases in power consumption. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a solid-state imaging device including a constant current source connected to a vertical signal line, a control transistor for lowering the potential of the vertical signal line in accordance with a predetermined control signal, and a body bias control unit for controlling the body bias of the control transistor, and a control method thereof, which has the effect of shortening the AD conversion time.

[0007] In addition, in the first aspect, the control transistor may further include a replica transistor having the same characteristics as the control transistor, and the body bias control unit may include a current monitor unit that measures a value of a current flowing through the replica transistor as a measured value, a comparison unit that compares the measured value with a predetermined reference current value and outputs a comparison result, and a body bias generation unit that generates the body bias based on the comparison result, thereby providing an effect of suppressing fluctuations in settling time caused by PVT variations.

[0008] In addition, in the first aspect, the body bias control unit may include a register that holds a predetermined setting value, and a body bias generation unit that generates the body bias based on the setting value, thereby providing an effect of suppressing fluctuations in settling time caused by process variations.

[0009] In the first aspect, the semiconductor substrate on which the control transistor is formed may be a silicon on insulator (SOI) substrate, thereby providing an effect of expanding the adjustment range of the body bias.

[0010] In addition, in the first aspect, the constant current source may be formed in a first well of a semiconductor substrate, and the control transistor may be formed in a second well of the semiconductor substrate, thereby providing an effect of isolating the wells.

[0011] In the first aspect, the body bias control unit may further control a body bias of the constant current source, thereby suppressing a fluctuation in a current value of the constant current source caused by a PVT variation.

[0012] In addition, in the first aspect, the body bias control unit may control the body biases of the constant current source and the control transistor to the same potential, and the constant current source and the control transistor may be formed in a predetermined well of a semiconductor substrate, thereby reducing the mounting area of ​​the constant current source and the control transistor.

[0013] In addition, in the first aspect, the pixel may further include a photoelectric conversion element, a transfer transistor for transferring charges from the photoelectric conversion element to a floating diffusion layer in accordance with a predetermined transfer signal, a reset transistor for initializing the floating diffusion layer in accordance with a predetermined reset signal, a selection transistor for opening and closing a path between a power supply voltage and the vertical signal line in accordance with a predetermined selection signal, and an amplification transistor for amplifying the potential of the floating diffusion layer and supplying it to the vertical signal line, thereby producing an effect of generating image data.

[0014] A second aspect of the present technology is an imaging device including a constant current source connected to a vertical signal line, a control transistor for lowering a potential of the vertical signal line in accordance with a predetermined control signal, a body bias control unit for controlling a body bias of the control transistor, and a signal processing unit for processing a pixel signal of the potential, thereby shortening an AD conversion time of the imaging device. [Brief description of the drawings]

[0015] [Figure 1] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. [Diagram 2] 1 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology. [Diagram 3] 1 is a circuit diagram showing a configuration example of a pixel and a load MOS circuit according to a first embodiment of the present technology. [Figure 4] 2 is a block diagram showing a configuration example of a body bias control unit according to a first embodiment of the present technology. FIG. [Diagram 5]2 is a block diagram showing a configuration example of a column signal processing unit according to the first embodiment of the present technology. FIG. [Figure 6] 4 is a timing chart showing an example of a method for driving a pixel according to the first embodiment of the present technology. [Figure 7] 4 is a graph showing an example of input characteristics of a control transistor in the first embodiment of the present technology. [Figure 8] 11 is a timing chart showing a potential fluctuation in a comparative example in which the control transistor has a low ability to extract electric charge. [Figure 9] 11 is a timing chart showing a potential fluctuation in a comparative example in which a control transistor has a high charge extraction capability. [Figure 10] 13 is an example of a timing chart showing potential fluctuations in a comparative example and the first embodiment of the present technology. [Figure 11] 1 is a cross-sectional view showing a configuration example of a semiconductor substrate according to a first embodiment of the present technology. [Figure 12] 11 is a cross-sectional view showing a configuration example of a semiconductor substrate according to a second embodiment of the present technology. FIG. [Figure 13] 13 is a circuit diagram showing a configuration example of a load MOS circuit according to a third embodiment of the present technology. FIG. [Figure 14] 13 is a cross-sectional view showing a configuration example of a semiconductor substrate according to a third embodiment of the present technology. FIG. [Figure 15] 13 is a block diagram showing a configuration example of a body bias control unit according to a fourth embodiment of the present technology. FIG. [Figure 16] 1 is a block diagram showing a schematic configuration example of a vehicle control system; [Figure 17] FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example of controlling the body bias of a control transistor) 2. Second embodiment (example in which the body bias of the control transistor is controlled and an insulating film is formed under the channel) 3. Third embodiment (example of controlling body bias of control transistor and constant current source) 4. Fourth embodiment (example of controlling body bias of control transistor according to setting value of register) 5. Application examples for mobile objects

[0017] <1. First embodiment> [Example of imaging device configuration] 1 is a block diagram showing an example of a configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. The imaging device 100 may be a digital camera or an electronic device having an imaging function (such as a smartphone or a personal computer).

[0018] The optical unit 110 collects light from a subject and guides it to the solid-state imaging element 200. The solid-state imaging element 200 generates image data by photoelectric conversion. The solid-state imaging element 200 generates the image data and supplies it to the DSP circuit 120 via a signal line 209.

[0019] The DSP circuit 120 executes a predetermined signal processing on the image data and outputs the processed image data to a frame memory 160 or the like via a bus 150.

[0020] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0021] The bus 150 is a common path for the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170 and the power supply unit 180 to exchange data with one another.

[0022] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display unit 130, and the like.

[0023] [Example of the configuration of a solid-state imaging element] 2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a vertical drive circuit 210, a timing control section 220, a digital to analog converter (DAC) 230, and a pixel array section 240. The solid-state imaging element 200 further includes a load metal-oxide-semiconductor (MOS) circuit 260, a column signal processing section 280, a horizontal scanning circuit 290, and a body bias control section 300. In the pixel array section 240, a plurality of pixels 250 are arranged in a two-dimensional lattice pattern.

[0024] The circuits and elements in the solid-state imaging device 200 are arranged, for example, on a single semiconductor substrate. Note that the circuits and the like in the solid-state imaging device 200 may also be distributed and arranged on a plurality of stacked semiconductor substrates.

[0025] The vertical drive circuit 210 sequentially selects and drives rows in the pixel array section 240 .

[0026] The timing control section 220 controls the operation timing of the vertical drive circuit 210, the DAC 230, the load MOS circuit 260, the column signal processing section 280, and the horizontal scanning circuit 290 in synchronization with the vertical synchronization signal VSYNC.

[0027] The DAC 230 generates a sawtooth ramp signal and supplies it to the column signal processing unit 280 .

[0028] The pixels 250 generate analog signals as pixel signals by photoelectric conversion under the control of the vertical drive circuit 210. The pixels 250 in each column output pixel signals to the column signal processing unit 280 via vertical signal lines.

[0029] In the load MOS circuit 260, a constant current source (not shown) is arranged for each vertical signal line.

[0030] The column signal processing unit 280 performs AD conversion and CDS (Correlated Double Sampling) processing on pixel signals for each column of the pixels 250. The column signal processing unit 280 outputs the processed digital signal to the DSP circuit 120 under the control of the horizontal scanning circuit 290. The column signal processing unit 280 is an example of a signal processing unit described in the claims.

[0031] The horizontal scanning circuit 290 controls the column signal processing unit 280 to output digital signals in sequence.

[0032] The body bias control unit 300 controls the body bias of the transistors in the load MOS circuit 260 .

[0033] [Example of pixel and load MOS circuit configuration] 3 is a circuit diagram showing a configuration example of a pixel 250 and a load MOS circuit 260 according to the first embodiment of the present technology. A vertical signal line 259 is wired to the pixel array section 240 for each column of the pixels 250. The pixel 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, a selection transistor 255, and an amplification transistor 256. For example, an nMOS (n-channel MOS) transistor is used as each transistor in the pixel 250.

[0034] The photoelectric conversion element 251 photoelectrically converts incident light to generate electric charges. The transfer transistor 252 transfers electric charges from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with a transfer signal TG from the vertical drive circuit 210. The reset transistor 253 initializes the floating diffusion layer 254 in accordance with a reset signal RST from the vertical drive circuit 210. The floating diffusion layer 254 generates an electric potential according to the amount of accumulated electric charges.

[0035] The selection transistor 255 opens and closes a path between a power supply voltage VDD and a vertical signal line 259 in accordance with a selection signal VSEL from the vertical drive circuit 210. The amplification transistor 256 amplifies the potential of the floating diffusion layer 254 and supplies it as a pixel signal to the vertical signal line 259. Note that the circuit configuration of the pixel 250 is not limited to the one exemplified in the figure, as long as it can generate a pixel signal.

[0036] The load MOS circuit 260 includes a plurality of constant current sources 261, a plurality of control transistors 262, and a replica circuit 270. The constant current sources 261 and the control transistors 262 are arranged for each column. For example, an nMOS transistor is used as the control transistor.

[0037] The constant current source 261 supplies a constant current. This constant current source 261 is connected to the vertical signal line 259 of the corresponding column. A connection node between the constant current source 261 and the vertical signal line 259 is connected to the column signal processing unit 280. A signal of the potential of this connection node is supplied to the column signal processing unit 280 as a pixel signal Vin. As the constant current source 261, for example, a MOS transistor (such as an nMOS transistor) having a constant bias voltage applied to its gate is used.

[0038] The control transistor 262 lowers the potential of the vertical signal line 259 in accordance with an enable signal PDEN from the timing control unit 220. For example, the enable signal PDEN is set to a high level when the function of lowering the potential is enabled, and is set to a low level when the function is disabled. The control transistor 262 and the constant current source 261 are connected in parallel between the vertical signal line 259 and a ground node. The enable signal PDEN is input to the gate of the control transistor 262. The body bias control unit 300 described above generates a body bias VB, which is a bias for a semiconductor substrate on which the control transistor 262 is formed, and supplies the body bias VB to the substrate. The enable signal PDEN is an example of a control signal described in the claims.

[0039] The replica circuit 270 includes a resistor 271 and a replica transistor 272. The value of the resistor 271 is set to, for example, a resistance value of the pixel 250 when it receives incident light of a predetermined brightness. The replica transistor 272 is a transistor having various characteristics (such as input characteristics) identical to those of the control transistor 262. The body bias control unit 300 also supplies a body bias VB to the replica transistor 272.

[0040] [Example of the body bias control unit configuration] 4 is a block diagram showing an example of a configuration of the body bias control unit 300 according to the first embodiment of the present technology. The body bias control unit 300 includes a current monitor circuit 310, a comparison circuit 320, and a body bias generation unit 330.

[0041] The current monitor circuit 310 measures the value of the current flowing through the resistor 271 and the replica transistor 272. The current monitor circuit 310 measures the current when the enable signal PDEN is at a high level (i.e., enabled) and supplies the value to the comparison circuit 320 as a measured value Im.

[0042] The comparison circuit 320 compares the measured value Im with a reference value Iref, which is a value of a predetermined reference current. The comparison circuit 320 supplies the comparison result to the body bias generation section 330.

[0043] The body bias generating section 330 generates a body bias VB based on the comparison result of the comparison circuit 320. The body bias generating section 330 is realized by a charge pump circuit or the like.

[0044] When the measured value Im is greater than the reference value Iref, the body bias generating unit 330 generates a body bias VB higher than 0 volts (V). On the other hand, when the measured value Im is smaller than the reference value Iref, the body bias generating unit 330 generates a body bias VB lower than 0 volts (V). When the measured value Im is equal to the reference value Iref, the body bias generating unit 330 generates a body bias VB of 0 volts (V). In addition, the greater the difference between the measured value Im and the reference value Iref, the greater the absolute value of the body bias VB the body bias generating unit 330 increases. This control of the body bias VB causes the threshold voltage of the control transistor 262 to fluctuate. This phenomenon is called the substrate bias effect. Due to the substrate bias effect, the current flowing through the replica transistor 272 increases or decreases, and the measured value Im is adjusted to be the reference value Iref.

[0045] The generated body bias VB is supplied to the substrates (in other words, the back gates) of the control transistors 262 and the replica transistors 272 of each column.

[0046] As described above, by controlling the body bias VB based on the result of comparison between the measured value Im and the reference value Iref, it is possible to suppress fluctuations in the characteristics of the control transistor 262 due to PVT variations.

[0047] The body bias control unit 300 can measure the current and adjust the body bias at any timing. For example, the body bias is periodically adjusted while the solid-state imaging device 200 is in operation. The body bias is also adjusted while the imaging operation of the solid-state imaging device 200 is stopped. By adjusting the body bias while the imaging operation is stopped, it is possible to suppress fluctuations in the characteristics of the control transistor 262 due to process variations. Also, by adjusting the body bias during operation, it is possible to suppress fluctuations in the characteristics of the control transistor 262 due to variations in temperature and power supply voltage.

[0048] [Example of column signal processing unit configuration] 5 is a block diagram showing an example of a configuration of the column signal processing unit 280 according to the first embodiment of the present technology. The column signal processing unit 280 includes an ADC 281 and a latch circuit 284 for each column.

[0049] The ADC 281 converts an analog pixel signal Ain into a digital signal Dout. The ADC 281 includes a comparator 282 and a counter 283. Such an ADC is called a single-slope ADC. Note that instead of the single-slope ADC, a SARADC (Successive Approximation Register ADC) or the like can also be used as the ADC 281.

[0050] The comparator 282 compares the pixel signal Ain with the ramp signal RMP from the DAC 230. The comparator 282 supplies a comparison result CMP to the counter 283.

[0051] The counter 283 counts the count value over a period until the comparison result CMP is inverted. The counter 283 supplies a digital signal Dout indicating the count value to a latch circuit 284.

[0052] The timing control unit 220 controls the counter 283 to count down when the reset level is converted and to count up when the signal level is converted. Here, the reset level is the level of the pixel signal Vin when the floating diffusion layer in the pixel is initialized, and the signal level is the level of the pixel signal Vin when the charge is transferred to the floating diffusion layer. By controlling the counter to count down when the reset level is converted and to count up when the signal level is converted, it is possible to realize CDS processing for finding the difference between the reset level and the signal level. It is also possible for the ADC 281 to only count up, and for a subsequent circuit to perform CDS processing.

[0053] The latch circuit 284 holds the digital signal Dout and supplies it to the DSP circuit 120 under the control of the horizontal scanning circuit 290 .

[0054] [Example of operation of solid-state imaging device] 6 is a timing chart showing an example of a method for driving the pixel 250 according to the first embodiment of the present technology. The vertical drive circuit 210 selects rows in order and performs AD conversion on the pixel signal Vin.

[0055] When a specific row is selected, the vertical drive circuit 210 supplies a high-level selection signal VSEL to the row from timing T0 to T4. This period is called the AD conversion time dT ADC Let us assume that.

[0056] From timing T1 immediately after timing T0, over a pulse period, the vertical drive circuit 210 supplies a high-level reset signal RST to the selected row. This causes the potential of the pixel signal Vin (in other words, the potential of the vertical signal line) to drop to the reset level. The settling time from when the potential starts to drop until it converges to the reset level is dT set1Let this dT set1 The reset level is sampled from the time when the reset level is sampled until the timing T2. This period is called the sampling period dT smp1 Let us assume that.

[0057] Then, the vertical drive circuit 210 supplies a high-level transfer signal TG to the selected row for a pulse period from timing T2, and supplies a high-level enable signal PDEN for a pulse period from timing T3 immediately thereafter. This causes the potential of the pixel signal Vin (the potential of the vertical signal line) to drop according to the amount of accumulated charge and become the signal level. The settling time from when the potential starts to drop until it converges to the signal level varies depending on the brightness, but the value obtained by adding a margin for the variation to the shortest settling time is defined as dT set2 Let this dT set2 The signal level is sampled from the time when the signal level is sampled until the timing T4. smp2 Let us assume that.

[0058] As mentioned above, the AD conversion time for a row, dT ADC is dT set1 , dT smp1 , dT set2 and dT smp2 Includes.

[0059] Here, the vertical signal line is connected with an amplification transistor according to the number of rows, and thus has a parasitic capacitance. Therefore, a non-negligible settling time is required until the potential of the vertical signal line converges to the signal level after the transfer signal TG is supplied. The length of the settling time of this signal level strongly depends on the sum of the parasitic capacitances present on the vertical signal line and the current value flowing from the constant current source 261.

[0060] In the above-mentioned configuration, the more pixels there are, the more the parasitic capacitance of the vertical signal line increases, and the longer the settling time becomes. Therefore, as shown in the figure, the vertical drive circuit 210 turns on the control transistor 262 by the enable signal PDEN immediately after the transfer. This control draws charge from the parasitic capacitance, and shortens the settling time of the signal level.

[0061] However, the settling time of the signal level varies depending on the brightness as well as the PVT variation. If the body bias VB were kept constant regardless of the PVT variation, the settling time would vary due to the PVT variation in addition to the brightness. As such, a configuration in which the body bias VB is not controlled according to the PVT variation but is kept constant is assumed as a comparative example.

[0062] In the comparative example, dT is set to a value that includes a sufficiently long margin to account for the variation in settling time due to PVT variations. set2 As a result, dT set2 The AD conversion time dT ADC becomes too long.

[0063] In contrast, in the first embodiment, the body bias VB is controlled based on the comparison result between the measured value Im and the reference value Iref, so that the variation in the settling time due to the PVT variation can be suppressed. set2 By reducing the margin in ADC can be made shorter than that in the comparative example.

[0064] As will be described later, the margin can also be reduced by adjusting the pulse width of the enable signal PDEN with high precision. However, to increase the precision of the pulse width adjustment, a high-speed clock signal is required, which increases power consumption, and is therefore not preferable.

[0065] Furthermore, although the timing control section 220 supplies the pulse of the enable signal PDEN immediately after the pulse of the transfer signal TG, it is also possible to supply the pulse of the enable signal PDEN simultaneously with the pulse of the transfer signal TG.

[0066] Furthermore, when the body bias control unit 300 generates the body bias VB by a charge pump circuit, it is preferable to stop the clock signal to the charge pump circuit within the AD conversion time. While the clock signal is stopped, the body bias VB is sampled and held in the parasitic capacitance of the semiconductor substrate. This control can suppress noise from the charge pump circuit to analog circuits (such as pixels).

[0067] 7 is a graph showing an example of the input characteristics of the control transistor 262 according to the first embodiment of the present technology. The vertical axis of the graph shows the drain current Id of the control transistor 262, and the horizontal axis shows the gate-source voltage Vgs.

[0068] The dashed and dotted line indicates the reference input characteristic. The solid line indicates the input characteristic when the ability to extract charge from the parasitic capacitance is high compared to the reference. The rough dashed line indicates the input characteristic when the ability to extract charge from the parasitic capacitance is low compared to the reference. In the reference input characteristic, when the enable signal PDEN is at a high level V EN The drain current Id at this time is set as a reference value Iref.

[0069] The input characteristics of the control transistor 262 vary due to variations in PVT. EN The measured value Im of the drain current Id at this time also varies due to PVT variations.

[0070] When the measured value Im is larger than the reference value Iref, in other words, when the charge extraction capability is high (for example, the input characteristic of the solid line), the body bias control unit 300 makes the body bias VB higher than 0 volts (V). On the other hand, when the measured value Im is smaller than the reference value Iref, in other words, when the charge extraction capability is low (for example, the input characteristic of the rough dashed line), the body bias control unit 300 makes the body bias VB lower than 0 volts (V). Also, when the measured value Im is the same as the reference value Iref (that is, the input characteristic of the dashed line), the body bias control unit 300 makes the body bias VB 0 volts (V). Also, the larger the difference between the measured value Im and the reference value Iref, the larger the absolute value of the body bias control unit 300 makes the body bias VB. This control can suppress the variation in the settling time caused by the PVT variation.

[0071] 8 is a timing chart showing potential fluctuations when the charge extraction capability of the control transistor 262 in the comparative example is low. In the figure, "a" shows a timing chart when the charge extraction capability of the control transistor 262 is low and the incident light is dark. In the figure, "b" shows a timing chart when the charge extraction capability of the control transistor 262 is low and the incident light is bright.

[0072] As illustrated in FIG. 1A, the vertical drive circuit 210 supplies a high-level transfer signal TG to a selected row for a pulse period from timing T10, and then supplies a high-level enable signal PDEN for a pulse period from timing T11 immediately thereafter. This causes the potential of the pixel signal Vin (the potential of the vertical signal line) to drop according to the amount of charge accumulation and become a signal level. The time from timing T11 when the potential starts to drop to timing T12 when it converges to the signal level corresponds to the settling time.

[0073] Also, as shown in FIG. 1B, when the incident light is bright, the potential of the vertical signal line converges to the signal level at timing T13 after timing T12. That is, when the incident light is bright, the settling time is longer than when the incident light is dark.

[0074] As shown in a and b in the figure, if the charge extraction capability of the control transistor 262 is low, the settling time when it is bright is longer than when it is dark. For this reason, the dT set2 is set.

[0075] 9 is a timing chart showing potential fluctuations when the charge extraction capability of the control transistor 262 in the comparative example is high. In the figure, "a" shows a timing chart when the control transistor 262 has a high charge extraction capability and the incident light is dark. In the figure, "b" shows a timing chart when the control transistor 262 has a high charge extraction capability and the incident light is bright.

[0076] As illustrated in FIG. 13A, when the incident light is dark, the potential of the pixel signal Vin (the potential of the vertical signal line) converges to the signal level at timing T13.

[0077] On the other hand, as illustrated in FIG. 13B, when the incident light is bright, the potential of the vertical signal line converges to the signal level at timing T12, which is before timing T13.

[0078] As shown in a and b in the figure, if the control transistor 262 has a high charge extraction capability, the settling time in the dark is longer than in the light. set2 is set.

[0079] 8a and 8b and 9a and 9b, in the comparative example in which the body bias VB is not controlled, the charge extraction capability of the control transistor 262 varies due to the PVT variation. Therefore, the settling time varies due to the brightness and the PVT variation.

[0080] 10 is an example of a timing chart showing potential fluctuations in a comparative example and the first embodiment of the present technology, where a in the figure shows the timing chart of the comparative example, and b in the figure shows the timing chart of the first embodiment.

[0081] As described above, in the comparative example, the settling time varies due to brightness and PVT variation. For this reason, as illustrated in FIG. a, a pulse width including a sufficiently long margin dTm is set in the enable signal PDEN. The solid line indicates the potential variation at the longest settling time, and the dashed line indicates the potential variation at the shortest settling time. Since the pulse width is thus long, the AD conversion time is long in the comparative example.

[0082] The margin can be reduced by adjusting the pulse width of the enable signal PDEN with high precision. However, improving the accuracy of the pulse width adjustment requires a high-speed clock signal, which increases power consumption.

[0083] In contrast, in the first embodiment, the body bias control unit 300 controls the body bias VB, so that the variation in the settling time due to the PVT variation is suppressed. Therefore, as illustrated in b in the figure, the margin dTm can be reduced compared to the comparative example. This allows the AD conversion time to be shortened. In addition, since there is no need to adjust the pulse width with high precision, the increase in power consumption can be suppressed.

[0084] 11 is a cross-sectional view showing a configuration example of a semiconductor substrate 400 according to the first embodiment of the present technology. On this semiconductor substrate 400, the circuits and elements in the solid-state imaging device 200 shown in FIG.

[0085] 11, in a semiconductor substrate 400, a deep N-well 402 is formed in a P-substrate 401. + Layer 404, P - Layer 405, P -Layer 407 is formed. + Layer 404 is connected to a power supply voltage VDD which is higher than the body bias VB.

[0086] P - Layer 405 is made of P + Layer 406 and N + A source 412 and a drain 413 of the P + The layer 406 is grounded. Furthermore, a gate 411 is formed between a source 412 and a drain 413. These gate 411, source 412 and drain 413 function as the above-mentioned constant current source 261. A constant bias voltage Vb is applied to the gate 411.

[0087] Also, P - Layer 407 is P + Layer 408 and N + A source 422 and a drain 423 are formed in the P + A body bias VB is applied to the layer 408. In addition, a gate 421 is formed between a source 422 and a drain 423. The gate 421, the source 422, and the drain 423 function as the above-mentioned control transistor 262. An enable signal PDEN is input to the gate 421.

[0088] Also, adjacent N + Layer and P + An insulating layer 403 is formed between the layers. As shown in the figure, a well in which the control transistor 262 is formed is P - layer 407 and a well in which the constant current source 261 is formed, P - It is separated from the layer 405. Also, no insulating film is formed directly below the channel of the MOS transistor (the control transistor 262 and the constant current source 261), and such a structure is called a bulk structure.

[0089] In addition, P - Layer 405 is an example of a first well as defined in the claims. - Layer 407 is an example of a claimed second well.

[0090] As described above, according to the first embodiment of the present technology, the body bias control unit 300 controls the body bias of the control transistor 262, so that it is possible to suppress the fluctuation of the settling time due to the PVT variation. This makes it possible to reduce the AD conversion time while suppressing the increase in power consumption.

[0091] <2. Second embodiment> In the first embodiment described above, the control transistor 262 and the constant current source 261 are formed on the semiconductor substrate 400 having a bulk structure, but this structure may cause a lack of adjustment range of the body bias. The solid-state imaging device 200 in the second embodiment differs from the first embodiment in that it uses an SOI structure instead of a bulk structure.

[0092] 12 is a cross-sectional view showing a configuration example of a semiconductor substrate 400 according to the second embodiment of the present technology. The semiconductor substrate 400 according to the second embodiment differs from the first embodiment in that it further includes BOX (Burried Oxide) films 431 and 432.

[0093] The BOX film 431 is formed, with the gate side facing up, directly below the channel between the source 412 and the drain 413. The BOX film 432 is formed directly below the channel between the source 422 and the drain 423. A structure in which an insulating film such as a BOX film is inserted directly below the channel in this manner is called an SOI structure, and a semiconductor substrate with an SOI structure is also called an SOI substrate.

[0094] By using the semiconductor substrate 400 with the SOI structure, the parasitic capacitance is reduced, and the amount of change in the threshold voltage when the body bias VB is changed by a unit voltage is smaller than that in the case of the bulk structure. Therefore, the adjustment range of the body bias VB of the control transistor 262 can be expanded.

[0095] In this way, according to the second embodiment of the present technology, since the semiconductor substrate 400 having an SOI structure is used, the adjustment range of the body bias VB of the control transistor 262 can be expanded.

[0096] <3. Third embodiment> In the above-described second embodiment, the body bias control unit 300 supplies the body bias VB only to the control transistor 262. However, the dynamic range of the current of the constant current source 261 may also vary due to PVT variations. This body bias control unit 300 differs from the second embodiment in that it further controls the body bias of the constant current source 261.

[0097] 13 is a circuit diagram showing a configuration example of a load MOS circuit 260 according to a third embodiment of the present technology. A body bias control unit 300 according to the third embodiment supplies a body bias VB of the same potential to both the constant current source 261 and the control transistor 262 of each column, and controls the bias.

[0098] The body bias control unit 300 further controls the body bias of the constant current source 261, thereby making it possible to suppress fluctuations in the dynamic range of the current value of the constant current source 261 due to PVT variations.

[0099] 14 is a cross-sectional view showing a configuration example of a semiconductor substrate 400 according to the third embodiment of the present technology. - Of layers 405 and 407, P + Layer 405 is reduced. - Layer 407 is P + A layer 408, a gate 411, a source 412 and a drain 413 which constitute a constant current source 261, and a gate 421, a source 422 and a drain 423 which constitute a control transistor 262 are formed.

[0100] 13, the body bias control unit 300 controls the body bias of the constant current source 261 and the control transistor 262 to the same potential. With this configuration, the wells are not separated as in the second embodiment, and the constant current source 261 and the control transistor 262 are connected to the same well (P - The structure in which the wells are not separated can reduce the mounting area of ​​the constant current source 261 and the control transistor 262 compared to the case in which the wells are separated.

[0101] The body bias control unit 300 can also control the body biases of the constant current source 261 and the control transistor 262 to different potentials. In this case, separation of the wells is required.

[0102] In addition, in the figure, the semiconductor substrate 400 has an SOI structure, but it may have a bulk structure.

[0103] As described above, according to the third embodiment of the present technology, the body bias control unit 300 further controls the body bias of the constant current source 261, so that it is possible to suppress fluctuations in the dynamic range of the current value of the constant current source 261 due to PVT variations. Furthermore, by controlling the body biases of the constant current source 261 and the control transistor 262 to the same potential, it becomes unnecessary to separate the wells, and it is possible to reduce the mounting area.

[0104] <4. Fourth embodiment> In the first embodiment described above, the body bias VB is controlled based on a comparison result between the measured value Im of the current flowing through the replica transistor 272 and the reference value Iref, but there are cases where the influence of variations in the power supply voltage and temperature in the PVT is relatively small. The solid-state imaging device 200 in the fourth embodiment differs from the first embodiment in that the body bias VB is generated based on a setting value of a register.

[0105] 15 is a block diagram showing a configuration example of a body bias control unit 300 and a load MOS circuit 260 according to a fourth embodiment of the present technology. The body bias control unit 300 according to the fourth embodiment differs from the first embodiment in that it includes an OTP (One Time Programmable) memory 341 and a register 342 instead of a current monitor circuit 310 and a comparison circuit 320. Furthermore, the replica circuit 270 is not arranged in the load MOS circuit 260 according to the fourth embodiment.

[0106] A test circuit (not shown) outside the solid-state imaging device 200 measures the current flowing through the control transistor 262 in a predetermined test environment, calculates a set value based on a comparison result between the measured value Im and a reference value Iref, and stores the set value in the OTP memory 341. This set value indicates the control content of the body bias VB. The set value can also be stored in a type of non-volatile invention memory other than the OTP memory 341.

[0107] The register 342 holds the setting value read from the OTP memory 341. The register 342 supplies the setting value to the body bias generation section 330. The body bias generation section 330 generates a body bias VB in accordance with the setting value.

[0108] When the influence of variations in the power supply voltage and temperature is relatively small, the variation in the settling time due to the process variations can be suppressed by generating the body bias VB according to the setting value of the register 342. With this configuration, the replica circuit 270, the current monitor circuit 310, and the comparison circuit 320 can be eliminated.

[0109] It should be noted that the second or third embodiment can be applied to the fourth embodiment.

[0110] As described above, according to the fourth embodiment of the present technology, the body bias control unit 300 generates the body bias VB in accordance with the setting value of the register 342, so that the replica circuit 270, the current monitor circuit 310, and the comparison circuit 320 can be reduced.

[0111] <5. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0112] FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0113] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0114] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0115] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0116] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0117] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0118] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0119] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0120] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0121] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0122] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 16, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0123] FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.

[0124] In FIG. 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0125] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0126] 17 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0127] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0128] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0129] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0130] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0131] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to reduce the AD conversion time while suppressing an increase in power consumption, and therefore to increase the frame rate.

[0132] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0133] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0134] The present technology can also be configured as follows. (1) a constant current source connected to a vertical signal line; a control transistor for lowering the potential of the vertical signal line in accordance with a predetermined control signal; a body bias control unit that controls a body bias of the control transistor; A solid-state imaging device comprising: (2) further comprising a replica transistor having the same characteristics as the control transistor; The body bias control unit includes: a current monitor unit that measures a value of a current flowing through the replica transistor as a measurement value; a comparison unit that compares the measured value with a predetermined reference current value and outputs a comparison result; a body-bias generating unit that generates the body-bias based on the comparison result; Equipped The solid-state imaging device according to (1) above. (3) The body bias control unit includes: A register for holding a predetermined setting value; a body-bias generating unit that generates the body-bias based on the set value; Equipped The solid-state imaging device according to (1) above. (4) The semiconductor substrate on which the control transistor is formed is an SOI substrate. The solid-state imaging device according to any one of (1) to (3). (5) The constant current source is formed in a first well of a semiconductor substrate; The control transistor is formed in a second well of the semiconductor substrate. The solid-state imaging device according to any one of (1) to (4). (6) The body bias control unit further controls the body bias of the constant current source. The solid-state imaging device according to any one of (1) to (5). (7) the body bias control unit controls the body bias of the constant current source and the body bias of the control transistor to the same potential; The constant current source and the control transistor are formed in a predetermined well of a semiconductor substrate. The solid-state imaging device according to (6) above. (8) a photoelectric conversion element; a transfer transistor for transferring charges from the photoelectric conversion element to a floating diffusion layer in accordance with a predetermined transfer signal; a reset transistor that initializes the floating diffusion layer in accordance with a predetermined reset signal; a selection transistor that opens and closes a path between a power supply voltage and the vertical signal line in accordance with a predetermined selection signal; an amplifying transistor that amplifies the potential of the floating diffusion layer and supplies the amplified potential to the vertical signal line; The solid-state imaging device according to (1) above, further comprising: (9) a constant current source connected to the vertical signal line; a control transistor for lowering the potential of the vertical signal line in accordance with a predetermined control signal; a body bias control unit that controls a body bias of the control transistor; a signal processing unit that processes pixel signals of the potential; An imaging device comprising: (10) a step in which the control transistor reduces a potential of a vertical signal line connected to the constant current source in accordance with a predetermined control signal; a body bias control unit controls the body bias of the control transistor; A method for controlling a solid-state imaging device comprising the steps of: [Explanation of symbols]

[0135] 100 Imaging device 110 Optics Department 120 DSP circuits 130 Display section 140 Operation section 150 Bus 160 Frame Memory 170 Storage section 180 Power supply section 200 Solid-state image sensor 210 Vertical drive circuit 220 Timing control section 230 DAC 240 Pixel array section 250 pixels 251 Photoelectric conversion element 252 Transfer transistor 253 Reset Transistor 254 Floating Diffusion Layer 255 Select Transistor 256 Amplification Transistor 260 Load MOS circuit 261 Constant current source 262 Control Transistor 270 Replica Circuit 271 Resistance 272 Replica Transistor 280 Column signal processing section 281 ADC 282 Comparator 283 Counter 284 Latch Circuit 290 Horizontal scanning circuit 300 Body bias control unit 310 Current monitor circuit 320 comparison circuit 330 Body bias generator 341 OTP Memory 342 Registers 400 Semiconductor Substrates 401P board 402 Deep N-well 403 Insulating layer 404 N + layer 405, 407 P - layer 406, 408 P + layer Gates 411 and 421 422, 422 Source 423, 423 Drain 431, 432 BOX (Burried Oxide) membrane 12031 Imaging unit

Claims

1. A constant current source connected to the vertical signal line; a control transistor for lowering the potential of the vertical signal line in accordance with a predetermined control signal; a body bias control unit that controls a body bias of the control transistor; A solid-state imaging device comprising:

2. A replica transistor having the same characteristics as the control transistor is further provided. The body bias control unit includes: a current monitor unit that measures a value of a current flowing through the replica transistor as a measurement value; a comparison unit that compares the measured value with a predetermined reference current value and outputs a comparison result; a body-bias generating unit that generates the body-bias based on the comparison result; Equipped 2. The solid-state imaging device according to claim 1.

3. The body bias control unit includes: A register for holding a predetermined setting value; a body-bias generating unit that generates the body-bias based on the set value; Equipped 2. The solid-state imaging device according to claim 1.

4. The semiconductor substrate on which the control transistor is formed is a SOI (Silicon On Insulator) substrate.

2. The solid-state imaging device according to claim 1.

5. the constant current source is formed in a first well of a semiconductor substrate; The control transistor is formed in a second well of the semiconductor substrate.

2. The solid-state imaging device according to claim 1.

6. The body bias control unit further controls the body bias of the constant current source.

2. The solid-state imaging device according to claim 1.

7. the body bias control unit controls the body biases of the constant current source and the control transistor to the same potential; The constant current source and the control transistor are formed in a predetermined well of a semiconductor substrate.

7. The solid-state imaging device according to claim 6.

8. A photoelectric conversion element; a transfer transistor for transferring charges from the photoelectric conversion element to a floating diffusion layer in accordance with a predetermined transfer signal; a reset transistor that initializes the floating diffusion layer in accordance with a predetermined reset signal; a selection transistor that opens and closes a path between a power supply voltage and the vertical signal line in accordance with a predetermined selection signal; an amplifying transistor that amplifies the potential of the floating diffusion layer and supplies the amplified potential to the vertical signal line; 2. The solid-state imaging device according to claim 1, further comprising:

9. A constant current source connected to the vertical signal line; a control transistor for lowering the potential of the vertical signal line in accordance with a predetermined control signal; a body bias control unit that controls a body bias of the control transistor; a signal processing unit that processes pixel signals of the potential; An imaging device comprising:

10. a step of lowering a potential of a vertical signal line connected to a constant current source by a control transistor in accordance with a predetermined control signal; a body bias control unit controls the body bias of the control transistor; A method for controlling a solid-state imaging device comprising the steps of:

Images