Display device

Abstract

SOLUTION: A display device according to one embodiment comprises: a substrate in which a plurality of spaced pixel regions and a plurality of transmissive regions arranged between the pixel regions are defined, where each of the pixel regions includes a plurality of sub-pixels; and a plurality of signal lines that extend in a first direction on the substrate. The sub-pixels include a plurality of pixel circuits. The signal lines do not overlap the transmissive regions but overlap a region where the pixel circuits are arranged.EFFECT: Accordingly, the pixel regions and the signal lines are formed in the same region to reduce the area of an opaque region in the entire display device and enlarge the area of the transmissive regions to enable a transparent display device to materialize.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a transparent display device, and more particularly to a transparent display device using LEDs (Light Emitting Diodes). [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide variety of applications, including not only computer monitors and TVs but also personal portable devices. Research is currently underway into display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, so they are highly reliable and have a longer lifespan than LCDs and OLEDs. LEDs not only light up quickly, but also have excellent luminous efficiency, strong impact resistance, excellent stability, and can display high brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a transparent display device having high transmittance.

[0006] Another problem to be solved by the present specification is to provide a display device in which an area of ​​a transmissive region is maximized by overlapping an opaque pixel region with a plurality of wirings.

[0007] Another object of the present invention is to provide a display device in which interference between a driving transistor in a pixel region and a plurality of data lines is minimized.

[0008] Another object of the present invention is to provide a display device in which fluctuations in voltage and driving current of a driving transistor due to data wiring are minimized.

[0009] Another object of the present invention is to provide a display device having improved display quality by minimizing coupling between data lines and driving transistors.

[0010] The subject of the present specification is not limited to the subject mentioned above, and other subjects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0011] A display device according to an embodiment of the present specification includes a substrate having a plurality of pixel regions, each including a plurality of sub-pixels spaced apart from each other, and a plurality of transmissive regions disposed between the pixel regions, and a plurality of signal wirings extending in a first direction on the substrate, the sub-pixels including a plurality of pixel circuits, and the plurality of signal wirings overlap a region in which the plurality of pixel circuits are disposed, without overlapping the plurality of transmissive regions. Thus, the pixel regions and the plurality of signal wirings are formed in the same region, thereby reducing the area of ​​opaque regions and increasing the area of ​​transmissive regions in the entire display device, thereby implementing a transparent display device.

[0012] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0013] The present disclosure may provide a transparent display device with improved transmittance.

[0014] In the present specification, the area of ​​the transmissive region of the display device can be maximized by overlapping opaque components of the display device.

[0015] The present invention can minimize voltage fluctuations of the driving transistor caused by coupling between the data wiring and the driving transistor, and the resulting driving current fluctuations.

[0016] The present invention can minimize crosstalk and luminance changes caused by coupling between data wiring and driving transistors.

[0017] The effects of the present specification are not limited to the above-mentioned examples, and various other effects are included in the present specification. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a schematic diagram illustrating a configuration of a display device according to an embodiment of the present specification. [Figure 2a] 1 is a partial cross-sectional view of a display device according to an embodiment of the present specification. [Figure 2b] FIG. 1 is a perspective view of a tiling display device according to an embodiment of the present specification. [Diagram 3] 1 is a schematic enlarged plan view of a display area of ​​a display device according to an embodiment of the present specification. [Figure 4] FIG. 2 is an enlarged plan view of a display area of ​​a display device according to an embodiment of the present specification. [Diagram 5] FIG. 2 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present specification. [Figure 6] 13 shows a simulation result of measuring a crosstalk level depending on an insulating layer thickness. [Figure 7] FIG. 13 is an enlarged plan view of a display device according to another embodiment of the present specification. [Figure 8] FIG. 11 is a cross-sectional view of a subpixel of a display device according to another embodiment of the present specification. [Figure 9a] 11 is a graph showing measurements of a voltage and a driving current of a driving gate electrode according to a data voltage in a display device according to a comparative example. [Figure 9b] 11 is a graph showing a voltage and a driving current of a driving gate electrode according to a data voltage in a display device according to another embodiment of the present disclosure; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The advantages and features of the present invention, and the methods for achieving the same, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely for the purpose of making the disclosure of the present invention complete and fully conveying the scope of the invention to those skilled in the art to which the present invention pertains.

[0020] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, and the specification is not limited to the matters illustrated. The same reference symbols refer to the same components throughout the specification. In addition, in explaining this specification, if it is determined that a specific description of related known technology may unnecessarily cloud the gist of this specification, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in this specification, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the case where it includes a plural, unless otherwise expressly stated.

[0021] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0022] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., one or more other parts may be located between the two parts, so long as "immediately" or "directly" is not used.

[0023] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0024] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of this specification.

[0025] Like reference numbers refer to like elements throughout the specification.

[0026] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0027] The features of the various embodiments of this specification may be combined or combined with each other, either partially or in whole, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0028] In the following, the present specification will be described with reference to the drawings.

[0029] 1 is a schematic diagram of a display device according to an embodiment of the present specification, in which only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are shown among various components of a display device 100 for ease of explanation.

[0030] Referring to FIG. 1, a display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD for supplying various signals to the display panel PN, and a timing controller TC for controlling the gate driver GD and the data driver DD.

[0031] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided from a timing controller TC. Although one gate driver GD is shown to be disposed at a distance from one side of the display panel PN in FIG. 1, the number and arrangement of the gate driver GD are not limited thereto.

[0032] The data driver DD supplies data voltages to the data lines DL according to the data control signals and image data provided by the timing controller TC. The data driver DD converts the image data into data voltages using a reference gamma voltage and supplies the converted data voltages to the data lines DL.

[0033] The timing controller TC aligns externally input image data and supplies it to the data driver DD. The timing controller TC can generate gate control signals and data control signals using externally input synchronous signals, such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronous signal. The timing controller TC can then supply the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0034] The display panel PN is a component for displaying an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL cross each other in the display panel PN, and a plurality of sub-pixels SP may be formed at the intersections of the scan lines SL and the data lines DL.

[0035] A display area AA and a non-display area NA can be defined in the display panel PN.

[0036] The display area AA is an area where an image is displayed on the display device 100. A plurality of sub-pixels SP constituting a plurality of pixels PX and a pixel circuit for driving the plurality of sub-pixels SP may be arranged in the display area AA. The plurality of sub-pixels SP are the minimum unit constituting the display area AA, and n sub-pixels SP may form one pixel PX. A thin film transistor or the like for driving a plurality of light-emitting elements 120 may be arranged in each of the plurality of sub-pixels SP. The plurality of light-emitting elements 120 may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting element 120 may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0037] In the display area AA, a plurality of signal lines are arranged to transmit various signals to the sub-pixels SP. For example, the signal lines may include a plurality of data lines DL to supply data voltages to the sub-pixels SP, and a plurality of scan lines SL to supply scan signals to the sub-pixels SP. The scan lines SL may extend in one direction from the display area AA to be connected to the sub-pixels SP, and the data lines DL may extend in a direction different from the one direction from the display area AA to be connected to the sub-pixels SP. In addition, low potential power lines, high potential power lines, etc. may be further arranged in the display area AA, but are not limited thereto.

[0038] The non-display area NA is an area where no image is displayed, and may be defined as an area extending from the display area AA. Link wiring and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, driving ICs such as gate driver ICs and data driver ICs, etc. may be arranged in the non-display area NA.

[0039] Meanwhile, the non-display area NA may be located on the rear surface of the display panel PN, ie, on a surface without sub-pixels SP, or may be omitted, and is not limited to that shown in the drawings.

[0040] Meanwhile, drivers such as the gate driver GD, the data driver DD, and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be implemented in the non-display area NA in a GIP (Gate In Panel) manner, or in the display area AA between a plurality of sub-pixels SP in a GIA (Gate In Active area) manner.

[0041] For example, the data driver DD and the timing controller TC may be formed on a separate flexible film and printed circuit board, and the data driver DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0042] As another example, when the gate driver GD is mounted in the display area AA in the GIA manner, and a side wiring SRL is formed to connect the signal wiring on the front side of the display panel PN to the pad electrode on the rear side of the display panel PN, and a flexible film and a printed circuit board are bonded to the rear side of the display panel PN, the non-display area NA on the front side of the display panel PN can be minimized. Therefore, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN in the above manner, it may be possible to implement a zero bezel in which there is substantially no bezel, and a more detailed description will be given with reference to Figures 2a and 2b.

[0043] Figure 2a is a partial cross-sectional view of a display device according to an embodiment of the present disclosure, and Figure 2b is a perspective view of a tiling display device according to an embodiment of the present disclosure.

[0044] A plurality of pad electrodes for transmitting various signals to the sub-pixels SP are arranged in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 for transmitting signals to the sub-pixels SP is arranged in the non-display area NA on the front side of the display panel PN, and a second pad electrode PAD2 electrically connected to driving components such as a flexible film and a printed circuit board is arranged in the non-display area NA on the rear side of the display panel PN.

[0045] In this case, although not shown in the drawing, various signal lines connected to multiple sub-pixels SP, such as scan lines SL and data lines DL, may extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0046] Also, side wirings SRL are arranged along the side surfaces of the display panel PN. The side wirings SRL can electrically connect a first pad electrode PAD1 on the front surface of the display panel PN to a second pad electrode PAD2 on the rear surface of the display panel PN. Thus, signals from driving components on the rear surface of the display panel PN can be transmitted to the sub-pixels SP through the second pad electrode PAD2, the side wirings SRL and the first pad electrode PAD1. Therefore, by arranging the driving components on the rear surface of the display panel PN and forming a signal transmission path between the front and rear surfaces of the display panel PN, the area of ​​the non-display region NA on the front surface of the display panel PN can be minimized.

[0047] 2b, a tiled display device TD having a large screen can be implemented by connecting a plurality of display devices 100. In this case, as shown in FIG 2a, when the tiled display device TD is implemented using the display device 100 with a minimized bezel, a seam area between the display devices 100 where no image is displayed can be minimized, thereby improving display quality.

[0048] For example, one pixel PX may include a plurality of sub-pixels SP, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another adjacent display device 100 may be implemented as the same as a distance D1 between pixels PX within one display device 100. Therefore, the distance between pixels PX may be configured to be constant between display devices 100, thereby minimizing seam regions.

[0049] However, FIG. 2a and FIG. 2b are merely illustrative, and the display device 100 according to an embodiment of the present specification may be a general display device having a bezel, and is not limited thereto.

[0050] In the following, the display panel PN of the display device 100 according to an embodiment of the present specification will be described in more detail with reference to FIGS.

[0051] FIG 3 is a schematic enlarged plan view of a pixel PX portion in a display region of a display device according to an embodiment of the present specification. FIG 4 is an enlarged plan view of a display region of a display device according to an embodiment of the present specification. FIG 5 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present specification. FIG 6 is a simulation result of measuring a crosstalk level according to a thickness of an insulating layer. For convenience of explanation, FIG 3 shows only a scan line SL and a data line DL among the multiple lines, and shows only one pixel area UPA among the multiple pixel areas UPA and multiple transmissive areas TA surrounding the one pixel area UPA.

[0052] 3, the display area AA is provided with a pixel area UPA in which the pixel PX is formed and a transmissive area TA surrounding the pixel area UPA. The pixel PX in the display area AA is provided with a pixel circuit including a driving element and a light-emitting element 120 driven by the pixel circuit, so that the pixel areas UPA in which the pixel PX is formed may be substantially opaque areas, and the transmissive areas TA in which the pixel PX is not formed may be substantially transparent areas. In this case, the pixel area UPA defined as the area in which the pixel PX is formed may also be defined as a light-emitting area since it is an area in which light emitted by the light-emitting element 120 is displayed. The pixel area UPA defined as the area in which the pixel PX is formed may also be defined as a circuit area since it is an area in which a pixel circuit including a driving element is formed.

[0053] A plurality of pixel areas UPA are formed in the display area AA. The plurality of pixel areas UPA are areas in which driving elements and light emitting elements 120 are arranged to display an image. The plurality of pixel areas UPA may be arranged spaced apart from each other with a plurality of transmissive areas TA therebetween. For example, the plurality of pixel areas UPA may be arranged in a plurality of rows and a plurality of columns.

[0054] A plurality of sub-pixels SP are arranged in each of the plurality of pixel regions UPA. Each of the plurality of sub-pixels SP includes a light-emitting element 120 and a pixel circuit and can independently emit light. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit light of different hues. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel, but is not limited thereto.

[0055] In the following description, it is assumed that one pixel PX includes two first sub-pixels SP1, two second sub-pixels SP2, and two third sub-pixels SP3, i.e., two red sub-pixels, two green sub-pixels, and two blue sub-pixels; however, the configuration of the pixel PX is not limited to this.

[0056] Meanwhile, the pair of first sub-pixels SP1, the pair of second sub-pixels SP2, and the pair of third sub-pixels SP3 may be used as a main sub-pixel SP and a redundancy sub-pixel SP. For example, one of the pair of first sub-pixels SP1, one of the pair of second sub-pixels SP2, and one of the pair of third sub-pixels SP3 may be a main sub-pixel SP that is basically used when driving the display device 100. When displaying an image, the main sub-pixel SP may be preferentially used. The remaining of the pair of first sub-pixels SP1, the remaining of the pair of second sub-pixels SP2, and the remaining of the pair of third sub-pixels SP3 may be a redundancy sub-pixel SP, and the redundancy sub-pixel SP may be used instead when the main sub-pixel SP is defective.

[0057] The main subpixels SP may be arranged in the same order as the redundancy subpixels SP. For example, the subpixels SP constituting the main subpixels SP may be arranged in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, and the subpixels SP constituting the redundancy subpixels SP may also be arranged in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0058] However, the pair of first sub-pixels SP1, the pair of second sub-pixels SP2, and the pair of third sub-pixels SP3 are not limited to main sub-pixels SP and redundancy sub-pixels SP, and all of them may always be used when driving the display device 100, and the arrangement order of the sub-pixels SP is also not limited to this.

[0059] The pixel area UPA may overlap with the wirings extending in the column direction, for example, the data wiring DL and the reference wiring RL. The pixel area UPA may be formed in an area where a plurality of opaque wirings are arranged, so that the area of ​​the transmissive area TA may be secured in the entire display area AA. Specifically, the pixel area UPA where the plurality of sub-pixels SP are arranged may be a substantially opaque area with low transmittance due to the configuration of the pixel circuits and the light emitting elements 120 arranged in the plurality of sub-pixels SP. Thus, the plurality of sub-pixels SP of the pixel area UPA may be arranged to overlap with the opaque wirings extending in the column direction, for example, the data wiring DL, the reference wiring RL, the low potential power supply wiring VSS, and the high potential power supply wiring VDD. Therefore, the plurality of sub-pixels SP of the pixel area UPA may be arranged to overlap with the plurality of wirings, so that the area of ​​the opaque area may be reduced in the entire display area AA, and the area of ​​the transmissive area TA may be secured to the maximum.

[0060] The sub-pixels SP arranged in one pixel region UPA may be either rectangular or L-shaped. For example, one first sub-pixel SP1, one second sub-pixel SP2, and one third sub-pixel SP3 may be arranged on one side of the scan line SL, and one first sub-pixel SP1, one second sub-pixel SP2, and one third sub-pixel SP3 may be arranged on the other side of the scan line SL. On each of the one and other sides of the scan line SL, the first sub-pixel SP1 may be arranged in a rectangular region, and the second sub-pixel SP2 may be arranged in an L-shaped region surrounding two adjacent sides of the first sub-pixel SP1. And the third sub-pixel SP3 may be arranged in an L-shaped region surrounding an outer portion of the L-shaped second sub-pixel SP2. Thus, one pixel region UPA composed of the rectangular first sub-pixel SP1 and the L-shaped second and third sub-pixels SP2 and SP3 may be formed in a rectangular shape.

[0061] The plurality of transmissive regions TA are regions in the display area AA excluding the region in which the plurality of wirings and the plurality of pixel regions UPA are arranged, and have a relatively high transmittance. Light is transmitted through the transmissive regions TA, allowing the background located at the rear of the display device 100 to be seen from the front of the display device 100. The plurality of transmissive regions TA may be arranged spaced apart with the plurality of wirings and the plurality of pixel regions UPA therebetween. The plurality of transmissive regions TA may be arranged to surround the plurality of pixel regions UPA. Thus, the display device 100 according to an embodiment of the present specification may be embodied as a transparent display device 100 including the plurality of transmissive regions TA.

[0062] 3 to 5, each of the sub-pixels SP includes a pixel circuit and one or more light emitting elements 120. The pixel circuit includes a plurality of transistors T1, T2, DT and a storage capacitor Cst, and can supply a driving current to the light emitting element 120. For example, the pixel circuit can include a first transistor T1, a second transistor T2, a driving transistor DT and a storage capacitor Cst. The sub-pixels SP arranged in one pixel area UPA can be connected to a scan line SL, a plurality of data lines DL, a reference line RL, a high potential power line VDD and a low potential power line VSS to receive various signals.

[0063] First, the substrate 110 is a component for supporting various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. The substrate 110 may also be made of a material including a polymer or plastic and having flexibility.

[0064] A light blocking layer LS is disposed in each of the sub-pixels SP on the substrate 110. The light blocking layer LS blocks light incident on a driving active layer DACT of the driving transistor DT, which will be described later, under the substrate 110. The light blocking layer LS blocks light incident on the driving active layer DACT of the driving transistor DT, thereby minimizing leakage current.

[0065] A buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be composed of, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, and is not limited thereto.

[0066] On the buffer layer 111, a driving transistor DT, a first transistor T1, and a second transistor T2 are disposed in each of the sub-pixels SP.

[0067] The driving transistor DT, the first transistor T1, and the second transistor T2 of each of the sub-pixels SP may be a P-type thin film transistor or an N-type thin film transistor. For example, in a P-type thin film transistor, holes move from a source electrode to a drain electrode, so that a current may flow from the source electrode to the drain electrode. In an N-type thin film transistor, electrons move from a source electrode to a drain electrode, so that a current may flow from the drain electrode to the source electrode. In the following description, it is assumed that the driving transistor DT, the first transistor T1, and the second transistor T2 are P-type thin film transistors in which a current flows from a source electrode to a drain electrode, but the present invention is not limited thereto.

[0068] First, a driving transistor DT is disposed in each of the sub-pixels SP on the buffer layer 111. The driving transistor DT is a transistor for controlling a driving current supplied to the light-emitting element 120. In one pixel region UPA, the driving transistors DT of each of the sub-pixels SP may be disposed in a row along the column direction. The driving transistors DT of the sub-pixels SP may be disposed in a row overlapping an area in which the reference line RL and the data line DL are disposed.

[0069] The driving transistor DT includes a driving active layer DACT, a driving gate electrode DGE, a driving source electrode DSE, and a driving drain electrode DDE.

[0070] The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0071] A gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer for insulating the driving active layer DACT and the driving gate electrode DGE, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0072] A driving gate electrode DGE is disposed on the gate insulating layer 112. The driving gate electrode DGE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, and may be formed in a single or multiple layers.

[0073] A first interlayer insulating layer 113a is disposed on the driving gate electrode DGE. A contact hole is formed in the first interlayer insulating layer 113a for connecting the driving source electrode DSE to the driving active layer DACT. The first interlayer insulating layer 113a is an insulating layer for protecting the structure below the first interlayer insulating layer 113a, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0074] A driving source electrode DSE is disposed on the first interlayer insulating layer 113a. The driving source electrode DSE is electrically connected to the driving active layer DACT through a contact hole formed in the first interlayer insulating layer 113a. The driving source electrode DSE may be electrically connected to the second transistor T2. The driving source electrode DSE may be formed of a single or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0075] A second interlayer insulating layer 113b is disposed on the driving source electrode DSE. The second interlayer insulating layer 113b is an insulating layer for protecting the structure below the second interlayer insulating layer 113b, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0076] A first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer for protecting the structure below the first passivation layer 114a, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0077] A driving drain electrode DDE is disposed on the first passivation layer 114a. The driving drain electrode DDE is electrically connected to the driving active layer DACT through contact holes formed in the first passivation layer 114a, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b. The driving drain electrode DDE may be electrically connected to the low potential power wiring VSS through the contact hole formed in the first passivation layer 114a. The driving drain electrode DDE may be formed in a single layer or multiple layers using a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0078] Next, a first transistor T1 is disposed in each of the sub-pixels SP on the buffer layer 111. The first transistor T1 is a transistor that transmits a data voltage Vdata to a gate electrode of the driving transistor DT, and may be referred to as a switching transistor. In this case, in one pixel area UPA, the first transistors T1 of the sub-pixels SP may be arranged in a row in the row direction so as to overlap the scan line SL and a protruding portion of the scan line SL.

[0079] Specifically, the scan line SL may extend in a row direction on the gate insulating layer 112 and be disposed across a plurality of pixel regions UPA. In this case, the scan line SL may include portions protruding on both sides of the scan line SL toward a plurality of sub-pixels SP in a region overlapping with a plurality of pixel regions UPA. The portions protruding on one side of the scan line SL may include a portion extending in the column direction and a portion extending in the row direction from an end of the portion extending in the column direction. The scan line SL may further include a protruding portion protruding from the scan line SL and at least a portion of the protruding portion extending in the row direction. That is, the protruding portion protruding from one side of the scan line SL may be formed in an "L" shape. And, the portion protruding from the other side of the scan line SL may include a portion extending in the column direction.

[0080] The first transistors T1 of the sub-pixels SP on one side of the scan line SL may be arranged in a row along a portion of the protruding portion of the scan line SL that extends in the row direction. The first transistors T1 of the sub-pixels SP on the other side of the scan line SL may be arranged in a row along the scan line SL that extends in the row direction. Thus, the first transistors T1 on one side of the scan line SL may be arranged in a row along the row direction on the protruding portion of the scan line SL, and the first transistors T1 on the other side of the scan line SL may be arranged in a row along the row direction on the scan line SL. As the scan line SL is formed separately in two branches in one pixel region UPA, the first transistor T1 of the main sub-pixel SP and the first transistor T1 of the redundancy sub-pixel SP can be easily formed separately. Thus, the main sub-pixel SP and the redundancy sub-pixel SP may be connected to different first transistors T1 and driven.

[0081] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0082] A first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0083] A first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 may be electrically connected to the scan line SL. For example, the first gate electrode GE1 may be integrated with the scan line SL. The first gate electrode GE1 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, and may be formed in a single or multiple layers, but is not limited thereto.

[0084] The first drain electrode DE1 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The first drain electrode DE1 is electrically connected to the first active layer ACT1 through a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. The first drain electrode DE1 may be electrically connected to the second gate electrode GE2 of the second transistor T2 through the contact hole of the first interlayer insulating layer 113a. The first drain electrode DE1 may be formed of a single or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0085] A first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 is electrically connected to the first active layer ACT1 through contact holes in the first passivation layer 114a, the second interlayer insulating layer 113b, and the first interlayer insulating layer 113a. The first source electrode SE1 may be electrically connected to the data line DL. For example, the first source electrode SE1 may be integrated with the data line DL. The first source electrode SE1 may be formed in a single or multiple layers using a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0086] Next, a second transistor T2 is disposed in each of the subpixels SP on the buffer layer 111. The second transistor T2 is a transistor for compensating for the threshold voltage of the driving transistor DT, and may be referred to as a sensing transistor. The second transistors T2 of the subpixels SP may be disposed in a row along a portion of the protruding portion of the scan line SL that extends in the column direction. For example, the second transistors T2 of the subpixels SP on one side of the scan line SL may be disposed corresponding to the portion of the protruding portion of the scan line SL that extends in the column direction, and the second transistors T2 of the subpixels SP on the other side of the scan line SL may be disposed corresponding to the protruding portion of the scan line SL. Thus, the second transistors T2 disposed in one pixel region UPA may be disposed in a row along the column direction.

[0087] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0088] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0089] In this case, the second active layers ACT2 of the subpixels SP adjacent to each other may be connected to each other. For example, the second active layers ACT2 of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 arranged on one side of the scan line SL may extend in the column direction and be connected to each other and may be connected to the second drain electrode DE2 arranged in the first subpixel SP1. The second active layers ACT2 of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 arranged on the other side of the scan line SL may also extend in the column direction and be connected to each other and may be connected to the second drain electrode DE2 arranged in the first subpixel SP1. That is, the connection portion connecting the channel region of the second active layer ACT2 of the subpixels SP to the reference line RL is made of a transparent material of the second active layer ACT2 instead of an opaque conductive material, and the transmittance may be improved at the outermost edge of the pixel region UPA. In addition, a connection portion connecting the channel region of the second active layer ACT2 of the plurality of subpixels SP to the reference line RL is made of the material of the second active layer ACT2, so that a contact hole can be eliminated, and the structure of the pixel area UPA can be simplified.

[0090] The second gate electrode GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate electrode GE2 may be electrically connected to the scan line SL. For example, the second gate electrode GE2 may be integrated with and electrically connected to a protruding portion of the scan line SL. The second gate electrode GE2 may be formed of a single or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0091] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 through a contact hole in the first interlayer insulating layer 113a and the gate insulating layer 112. The second source electrode SE2 may be integrated with the driving source electrode DSE and electrically connected to the driving source electrode DSE. The second source electrode SE2 may be formed of a single or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0092] The second drain electrode DE2 is disposed between the first passivation layer 114a and the second passivation layer 114b. The second drain electrode DE2 is electrically connected to the second active layer ACT2 through a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain electrode DE2 may be integrated with the reference line RL and electrically connected to the reference line RL. The second drain electrode DE2 may be formed of a single or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0093] Next, a storage capacitor Cst is disposed on the gate insulating layer 112. The storage capacitor Cst stores a potential difference between the driving gate electrode DGE and the driving source electrode DSE of the driving transistor DT while the light emitting device 120 emits light, thereby allowing a constant driving current to be supplied to the light emitting device 120. The storage capacitor Cst includes a first capacitor electrode C1 electrically connected to the driving gate electrode DGE and a second capacitor electrode C2 electrically connected to the driving source electrode DSE, and can maintain a constant voltage between the driving gate electrode DGE and the driving source electrode DSE.

[0094] Specifically, a first capacitor electrode C1 is disposed on the gate insulating layer 112. The first capacitor electrode C1 may be integrated with the driving gate electrode DGE. A second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 may be disposed to overlap with the first interlayer insulating layer 113a sandwiched therebetween. In this case, the second capacitor electrode C2 may be integrated with the driving source electrode DSE. The first capacitor electrode C1 and the second capacitor electrode C2 may be formed of a single or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0095] Next, the auxiliary electrode AE ​​is disposed on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode for electrically connecting the driving source electrode DSE and the first reflective electrode RE1. The driving source electrode DSE and the first reflective electrode RE1 may be electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE ​​may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, and may be formed in a single or multiple layers.

[0096] A low potential power supply line VSS is disposed on the second interlayer insulating layer 113b. The low potential power supply line VSS may be disposed along the column direction and overlap a plurality of pixel areas UPA. The low potential power supply line VSS may be electrically connected to the driving drain electrode DDE. The low potential power supply line VSS may be formed of a single layer or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0097] A reference line RL is disposed on the first passivation layer 114a. The reference line RL may be disposed along the column direction and overlap a plurality of pixel regions UPA. The reference line RL may be disposed adjacent to the protruding portion of the scan line SL and may be electrically connected to a plurality of second transistors T2 disposed on the protruding portion of the scan line SL. The reference line RL may be formed of a single layer or multiple layers of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0098] A plurality of data lines DL are disposed on the first passivation layer 114a. The plurality of data lines DL may extend in a column direction and overlap a plurality of pixel regions UPA. The plurality of data lines DL may include a data line DL connected to the first transistors T1 of the plurality of first sub-pixels SP1, a data line DL connected to the first transistors T1 of the plurality of second sub-pixels SP2, and a data line DL connected to the first transistors T1 of the plurality of third sub-pixels SP3.

[0099] Next, a second passivation layer 114b is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114b is an insulating layer for protecting the components below the second passivation layer 114b, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0100] A first planarization layer 115a is disposed on the second passivation layer 114b. The first planarization layer 115a may planarize the upper portion of the substrate 110 on which the plurality of transistors and the storage capacitor Cst are disposed. The first planarization layer 115a may be configured as a single layer or multiple layers and may be made of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0101] Meanwhile, although not shown in the drawing, a further passivation layer may be disposed on the first planarization layer 115a. For example, a passivation layer made of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx) may be formed on the first planarization layer 115a to protect the structure below the passivation layer.

[0102] Next, a plurality of first reflective electrodes RE1 are disposed on the first planarization layer 115a. The plurality of first reflective electrodes RE1 are disposed in the plurality of sub-pixels SP, and electrically connect the driving transistor DT and the light emitting element 120, and can reflect light emitted from the light emitting element 120 to the outside of the display device 100. The plurality of first reflective electrodes RE1 may be disposed adjacent to the driving source electrode DSE in the plurality of sub-pixels SP. The plurality of first reflective electrodes RE1 may be made of an opaque conductive material having high reflective efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0103] A second reflective electrode RE2, which is a high-potential power supply line VDD, is disposed on the first planarization layer 115a. The second reflective electrode RE2 and the high-potential power supply line VDD are integrated to supply a high-potential power supply voltage to the light emitting element 120 and reflect light emitted from the light emitting element 120 to the outside of the display device 100. The second reflective electrodes RE2 of the sub-pixels SP may be connected to each other and integrated. The second reflective electrode RE2 and the high-potential power supply line VDD may extend in the column direction and be disposed so as to overlap the light emitting element 120. The second reflective electrode RE2 and the high-potential power supply line VDD may be disposed so as to overlap the data lines DL, the reference lines RL, and the low-potential power supply line VSS. The second reflective electrode RE2 and the high-potential power supply line VDD may be made of an opaque conductive material having high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but are not limited thereto.

[0104] A third passivation layer 114c is disposed on the plurality of first reflective electrodes RE1 and second reflective electrodes RE2. The third passivation layer 114c is an insulating layer for protecting the structure below the third passivation layer 114c, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0105] An adhesive layer AD is disposed on the third passivation layer 114c. The adhesive layer AD is formed on the front surface of the substrate 110, and can fix the light emitting element 120 disposed on the adhesive layer AD. The adhesive layer AD can be made of a photo-curable adhesive material that can be cured by light. For example, the adhesive layer AD can be selected from any one of adhesive polymer, epoxy resist, UV resin, polyimide series, acrylate series, urethane series, and Polydimethylsiloxane (PDMS), but is not limited thereto.

[0106] A plurality of light emitting elements 120 are disposed in each of a plurality of sub-pixels SP on the adhesive layer AD. The light emitting elements 120 are elements that emit light by current and may include a red light emitting element 120R that emits red light, a green light emitting element 120G that emits green light, and a blue light emitting element 120B that emits blue light, and may implement light of various hues including white by combining these elements. For example, the light emitting elements 120 may be, but are not limited to, LEDs (Light Emitting Diodes) or micro LEDs.

[0107] A red light emitting element 120R may be arranged in the first sub-pixel SP1, a green light emitting element 120G may be arranged in the second sub-pixel SP2, and a blue light emitting element 120B may be arranged in the third sub-pixel SP3. The light emitting elements 120 arranged in one pixel region UPA may be arranged in a line along the column direction. The light emitting elements 120 may be arranged so as to overlap the second reflective electrode RE2 in each of the sub-pixels SP.

[0108] Meanwhile, when the sub-pixels SP are divided into the main sub-pixels SP and the redundancy sub-pixels SP as described above, the light emitting elements 120 may also be divided into the main light emitting elements 120 and the redundancy light emitting elements 120. For example, one of the pair of first sub-pixels SP1, one of the pair of second sub-pixels SP2, and one of the pair of third sub-pixels SP3 may be the main sub-pixels SP, and the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B arranged in the main sub-pixels SP may be the main light emitting element 120. The remaining of the pair of first sub-pixels SP1, the remaining of the pair of second sub-pixels SP2, and the remaining of the pair of third sub-pixels SP3 may be the redundancy sub-pixels SP, and the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B arranged in the redundancy sub-pixels SP may be the redundancy light emitting element 120.

[0109] Each of the plurality of light emitting elements 120 includes a first semiconductor layer 121 , a light emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 , and a sealing film 126 .

[0110] A first semiconductor layer 121 is disposed on the adhesive layer AD, and a second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with n-type and p-type impurities. The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0111] The light emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 can have a single layer or a multi-quantum well (MQW) structure and can be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0112] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on an upper surface of the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0113] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on an upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting a high potential power supply line VDD to the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0114] Next, an encapsulation film 126 is disposed to surround the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is made of an insulating material and can protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. Contact holes exposing the first electrode 124 and the second electrode 125 are formed in the encapsulation film 126, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be electrically connected to the first electrode 124 and the second electrode 125.

[0115] Meanwhile, a portion of the side of the first semiconductor layer 121 may be exposed from the sealing film 126. The light emitting element 120 manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, a portion of the sealing film 126 may be peeled off during the process of separating the light emitting element 120 from the wafer. For example, a portion of the sealing film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light emitting element 120 may be peeled off during the process of separating the light emitting element 120 from the wafer, thereby exposing a portion of the lower side of the first semiconductor layer 121 to the outside. Even if the lower portion of the light emitting element 120 is exposed from the sealing film 126, the first connecting electrode CE1 and the second connecting electrode CE2 are formed after the second planarization layer 115b and the third planarization layer 115c covering the side of the first semiconductor layer 121 are formed, so that short-circuit defects can be reduced.

[0116] Next, the second planarization layer 115b and the third planarization layer 115c are disposed on the adhesive layer AD and the light emitting element 120.

[0117] The second planarization layer 115b overlaps a portion of the side surface of the plurality of light emitting elements 120 to fix and protect the plurality of light emitting elements 120. The portion where the sealing film 126 protecting the side surface of the first semiconductor layer 121 of the light emitting element 120 is peeled off can be covered with the second planarization layer 115b. This can prevent contact and short circuit defects between the connecting electrode and the first semiconductor layer 121 later.

[0118] The third planarization layer 115c is formed to cover the second planarization layer 115b and an upper portion of the light emitting element 120. The third planarization layer 115c may have contact holes formed therein to expose the first electrode 124 and the second electrode 125 of the light emitting element 120. The first electrode 124 and the second electrode 125 of the light emitting element 120 are exposed from the third planarization layer 115c, and the third planarization layer 115c is partially disposed in the region between the first electrode 124 and the second electrode 125 to reduce short circuit defects. The second planarization layer 115b and the third planarization layer 115c may be configured as a single layer or multiple layers and may be made of, for example, a photoresist or an acrylic organic material, but are not limited thereto.

[0119] The first connecting electrode CE1 and the second connecting electrode CE2 are disposed on the third planarization layer 115c.

[0120] The first connecting electrode CE1 is an electrode that electrically connects the first electrode 124 of the light emitting element 120 to the driving transistor DT. The first connecting electrode CE1 may be electrically connected to the first electrode 124 exposed from the third planarization layer 115c, and may be electrically connected to the first reflective electrode RE1 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. Thus, the first electrode 124 and the driving source electrode DSE may be electrically connected through the first connecting electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0121] The second connecting electrode CE2 is an electrode that electrically connects the second electrode 125 of the light emitting element 120 to the high potential power wiring VDD. The second connecting electrode CE2 is electrically connected to the second electrode 125 exposed from the third planarization layer 115c, and can be electrically connected to the high potential power wiring VDD as the second reflective electrode RE2 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. Therefore, the second electrode 125 and the high potential power wiring VDD can be electrically connected through the second connecting electrode CE2.

[0122] The first connecting electrode CE1 and the second connecting electrode CE2 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0123] Meanwhile, in the drawings, the driving source electrode DSE of the driving transistor DT and the first electrode 124 of the light emitting element 120 are shown to be electrically connected, but depending on the type of the driving transistor DT and the design of the pixel circuit, the driving drain electrode DDE of the driving transistor DT and the second electrode 125 of the light emitting element 120 may be electrically connected, and is not limited thereto.

[0124] Next, a bank BB is disposed on the third planarization layer 115c, the first connecting electrode CE1, and the second connecting electrode CE2 in the pixel region UPA. The bank BB may be disposed at a certain distance from the light emitting element 120. The bank BB may be disposed at a boundary between the plurality of sub-pixels SP and may cover a portion of the first connecting electrode CE1 and the second connecting electrode CE2. The bank BB may be disposed at a distance from the transmissive region TA. The bank BB may be made of an opaque material to reduce color mixing between the plurality of sub-pixels SP, for example, but is not limited to, black resin.

[0125] A protective layer 116 is disposed on the first connecting electrode CE1, the second connecting electrode CE2, and the bank BB. The protective layer 116 is a layer for protecting the components below the protective layer 116. The protective layer 116 may be configured as a single layer or multiple layers, and may be made of, for example, benzocyclobutene, light-transmitting epoxy, photoresist, an acryl-based organic material, or an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0126] Meanwhile, in order to secure the area of ​​the transmissive region TA, the sub-pixels SP may be arranged to overlap with the wirings. In this case, some of the wirings may cause a driving current fluctuation in each of the sub-pixels SP. For example, the driving transistor DT and the storage capacitor Cst of each of the sub-pixels SP may overlap with the data wiring DL and be coupled to the data wiring DL. In this case, the voltage of the driving gate electrode DGE may fluctuate due to the data wiring DL to which a different voltage is applied for each frame. As the voltage of the driving gate electrode DGE fluctuates, the driving current flowing through the light emitting element 120 may fluctuate, and a luminance change due to crosstalk may occur, resulting in a deterioration in display quality.

[0127] Therefore, in the display device 100 according to an embodiment of the present specification, the thickness of the insulating layer disposed between the storage capacitor Cst and the driving transistor DT and the data line DL may be adjusted in consideration of the dielectric constant of the insulating layer, thereby reducing the voltage fluctuation of the driving gate electrode DGE due to the data line DL. For example, the inorganic insulating layer disposed on the substrate 110, i.e., the insulating layers such as the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113a, and the second passivation layer 114b, may be formed to a thickness of several thousand angstroms (Å). However, unlike other insulating layers, the first passivation layer 114a and the second interlayer insulating layer 113b, which are insulating layers disposed between the data line DL and the storage capacitor Cst, are formed to a thickness of at least several micrometers (μm), thereby minimizing the voltage fluctuation of the driving transistor DT due to the data line DL. Therefore, the thickness of the insulating layer between the data line DL and the storage capacitor Cst may be thicker than the thickness of the buffer layer 111, the thickness of the gate insulating layer 112, the thickness of the first interlayer insulating layer 113a, and the thickness of the second passivation layer 114b.

[0128] Referring to FIG. 6, when the width of the data line DL is 1 μm, the thickness of the insulating layer may be determined depending on the material and dielectric constant of the insulating layer disposed under the data line DL. As the thickness of the insulating layer increases, the level of brightness change due to crosstalk may be reduced. In this case, when the insulating layer is made of silicon nitride (SiNx) having a dielectric constant of about 6.69 and the target crosstalk is 2%, the thickness of the insulating layer is formed to be about 16.55 μm or more to control the level of brightness change due to crosstalk to 2% or less. When the insulating layer is made of silicon oxide (SiOx) having a dielectric constant of about 4.3 and the target crosstalk is 2%, the thickness of the insulating layer is formed to be about 10.64 μm or more to control the level of brightness change due to crosstalk to 2% or less. Therefore, when the width of the data line DL is 1 μm, the total thickness of the first passivation layer 114a and the second interlayer insulating layer 113b is formed to be at least 10.64 μm or more to minimize the voltage fluctuation of the driving transistor DT and the storage capacitor Cst connected to the driving transistor DT due to the data line DL. Also, as the width of the data line DL increases, a thicker insulating layer may be required to achieve the same level of crosstalk.

[0129] Therefore, the total thickness of the first passivation layer 114a and the second interlayer insulating layer 113b can be determined taking into consideration the width of the data line DL, the dielectric constants of the first passivation layer 114a and the second interlayer insulating layer 113b, and the target crosstalk level, and the driving current can be maintained constant while minimizing interference between the data line DL and the driving transistor DT and the storage capacitor Cst connected to the driving transistor DT.

[0130] In the display device 100 according to an embodiment of the present specification, a plurality of pixel areas UPA are disposed in an area where a plurality of wirings extending in a column direction are disposed, thereby maximizing the area of ​​the transmissive area TA. A substantially opaque pixel area UPA including a pixel circuit and a light emitting element 120 is disposed together with opaque wirings, thereby reducing the area of ​​the opaque area in the entire display area AA. Thus, by maximizing the area of ​​the transmissive area TA, the overall transmittance of the display device 100 can be improved, and a transparent display device 100 can be realized.

[0131] In the display device 100 according to an embodiment of the present specification, the voltage fluctuation of the driving transistor DT due to the data line DL can be minimized. When the data line DL and the pixel area UPA are overlapped to secure the area of ​​the transmissive region TA, the configurations of the data line DL and the pixel area UPA may be coupled to each other, causing a voltage fluctuation. For example, the data line DL may overlap the driving transistor DT and the storage capacitor Cst and be coupled to the driving transistor DT and the storage capacitor Cst, causing the voltage of the driving transistor DT and the storage capacitor Cst to fluctuate, causing a fluctuation in luminance and a deterioration in display quality. Therefore, the thickness of the insulating layer between the data line DL and the driving transistor DT and the storage capacitor Cst may be formed thick to minimize the influence of the data line DL. At this time, the thickness of the insulating layer may be determined in consideration of the dielectric constant of the insulating layer, the width of the data line DL, the target crosstalk level, and the like. Therefore, in the display device 100 according to an embodiment of the present specification, the thickness of the insulating layer between the data line DL and the driving transistor DT among the multiple insulating layers may be formed relatively thick to minimize the driving current fluctuation due to the data line DL and improve the display quality.

[0132] FIG. 7 is an enlarged plan view of a display device according to another embodiment of the present specification. FIG. 8 is a cross-sectional view of a subpixel of a display device according to another embodiment of the present specification. FIG. 9a is a graph showing measurements of a voltage and a driving current of a driving gate electrode according to a data voltage in a display device according to a comparative example. FIG. 9b is a graph showing measurements of a voltage and a driving current of a driving gate electrode according to a data voltage in a display device according to another embodiment of the present specification. The display panel PN' of FIGS. 7 and 8 is substantially the same in configuration as the display panel PN of FIGS. 1 to 5 except for the low potential power supply wiring VSS, and therefore a duplicated description will be omitted.

[0133] 7 and 8, the low potential power supply wiring VSS is disposed between the second interlayer insulating layer 113b and the first passivation layer 114a so as to overlap with the plurality of data wirings DL. The low potential power supply wiring VSS may overlap the region where the plurality of data wirings DL are disposed. The low potential power supply wiring VSS has a relatively wide width so that one low potential power supply wiring VSS and the plurality of data wirings DL may overlap. The low potential power supply wiring VSS may cover the storage capacitors Cst and the driving transistors DT of the plurality of sub-pixels SP'. Since only the low potential power supply wiring VSS is disposed between the second interlayer insulating layer 113b and the first passivation layer 114a, the low potential power supply wiring VSS may be easily formed in the remaining region except for the region where the contact holes are disposed.

[0134] The low potential power supply wiring VSS may have an opening formed therein overlapping with the contact hole. For example, the low potential power supply wiring VSS may have an opening formed therein overlapping with the contact hole connecting the first source electrode SE1 and the first active layer ACT1 and the contact hole connecting the driving drain electrode DDE and the driving active layer DACT. The first source electrode SE1 and the driving drain electrode DDE are disposed on the low potential power supply wiring VSS, and the first active layer ACT1 and the driving active layer DACT are disposed below the low potential power supply wiring VSS. Thus, by forming an opening in the low potential power supply wiring VSS, the components connected to the upper and lower parts of the low potential power supply wiring VSS may be easily connected.

[0135] The low potential power supply wiring VSS is disposed between the storage capacitor Cst and the driving transistor DT and a plurality of data lines DL, and can function as a blocking film for blocking voltage fluctuations of the driving transistor DT caused by the data lines DL. The low potential power supply wiring VSS, to which a constant voltage is applied, is disposed between the storage capacitor Cst and the driving transistor DT and the data lines DL, and can prevent coupling between the data lines DL and the storage capacitor Cst and the driving transistor DT. The low potential power supply wiring VSS is disposed to cover at least the driving gate electrode DGE of the driving transistor DT, and can protect the voltage DTG of the driving gate electrode DGE from fluctuating due to the data lines DL.

[0136] The effect of expanding and arranging the low potential power supply wiring VSS will be described below with reference to FIGS. 9a and 9b.

[0137] 9a, the display device 10 according to the comparative example has a structure in which a low potential power supply line VSS is not disposed between the data line DL and the driving transistor DT. In the display panel 10 according to the comparative example, a separate blocking film is not disposed between the data line DL and the driving transistor DT, and it can be seen that the voltage DTG of the driving gate electrode DGE fluctuates due to the voltage fluctuation of the data line DL. It can also be seen that the driving current ILED flowing through the light emitting element 120 fluctuates as the voltage DTG of the driving gate electrode DGE fluctuates. In this case, the luminance may fluctuate, degrading the display quality.

[0138] 9b, in a display panel PN' according to another embodiment of the present specification, a low potential power supply line VSS is disposed between the data line DL and the driving transistor DT, and between the data line DL and the storage capacitor Cst, functioning as a blocking film. Therefore, even if the voltage of the data line DL fluctuates, the voltage DTG of the driving gate electrode DGE and the driving current ILED can be maintained constant. Therefore, the brightness can be maintained constant, and the display quality can be improved.

[0139] In the display panel PN' according to another embodiment of the present specification, a low potential power supply line VSS is formed between the data line DL and the driving transistor DT, thereby minimizing the voltage fluctuation of the driving transistor DT due to the data line DL. The low potential power supply line VSS may be disposed under the data lines DL to cover the driving transistor DT and the storage capacitor Cst. The low potential power supply line VSS, which always maintains a constant voltage, can prevent the data lines DL from interfering with the driving transistor DT and the storage capacitor Cst. In this case, the voltage DTG and the driving current ILED of the driving gate electrode DGE can be maintained constant without forming a thick insulating layer between the data lines DL and the driving transistor DT and the storage capacitor Cst. Also, instead of forming a separate blocking film, the size of the existing low potential power supply line VSS can be expanded to correspond to the area where the data lines DL are arranged, and the low potential power supply line VSS can be used as a blocking film, thereby simplifying the manufacturing process of the display panel PN'. Therefore, in a display panel PN' according to another embodiment of this specification, the size of the low-potential power supply wiring VSS is expanded so as to overlap all of the multiple data wirings DL, thereby maintaining the driving current ILED of the sub-pixel SP' stably and constantly, thereby improving the reliability of the display panel PN'.

[0140] Meanwhile, in the past, a main light emitting element and a redundancy light emitting element were both arranged in one sub-pixel, and the main light emitting element and the redundancy light emitting element were connected in parallel to one pixel circuit. In this case, the first and second electrodes of the main light emitting element and the first and second electrodes of the redundancy light emitting element may be connected to the same node, i.e., the same electrode. In such a structure, if a short circuit occurs in the light emitting element or pixel circuit, the main light emitting element and the redundancy light emitting element, which are connected in parallel and share a specific electrode, may both be darkened, and it may be difficult to isolate and repair the defective light emitting element.

[0141] Alternatively, in the display panels PN, PN' according to various embodiments of the present specification, as described above, the sub-pixels SP, SP' may be divided into main sub-pixels SP, SP' including a main light-emitting element 120 and redundancy sub-pixels SP, SP' including a redundancy light-emitting element 120. The main light-emitting element 120 of the main sub-pixels SP, SP' and the redundancy light-emitting element 120 of the redundancy sub-pixels SP, SP' may be driven independently. That is, a pixel circuit for driving the main light-emitting element 120 and a pixel circuit for driving the redundancy light-emitting element 120 may be formed separately. For example, an "L"-shaped protruding portion may be further formed on the scan line SL extending in the row direction, and one of the first transistor T1 for driving the main light emitting element 120 and the first transistor T1 for driving the redundancy light emitting element 120 may be formed on the scan line SL, and the other may be formed on the "L"-shaped protruding portion, thereby separately forming the first transistor T1 for driving the main light emitting element 120 and the first transistor T1 for driving the redundancy light emitting element 120. Thus, by further forming a protruding portion on the scan line SL, the first transistor T1 for the main light emitting element 120 and the first transistor T1 for the redundancy light emitting element 120 may be separately formed, and the main light emitting element 120 and the redundancy light emitting element 120 may be independently driven. Therefore, in the display panels PN, PN' according to various embodiments of the present specification, the main light-emitting element 120 and the redundancy light-emitting element 120 are connected to different pixel circuits, so that a defect in a specific sub-pixel SP, SP' does not affect other sub-pixels SP, SP', and only the defective sub-pixel SP, SP' can be easily detected and repaired.

[0142] A display device according to various embodiments of the present disclosure can be described as follows.

[0143] A display device according to one embodiment of the present specification includes a substrate defining a plurality of pixel regions spaced apart from one another, each pixel region including a plurality of sub-pixels, and a plurality of transparent regions disposed between the pixel regions, and a plurality of signal wirings extending in a first direction on the substrate, the sub-pixels including a plurality of pixel circuits, and the plurality of signal wirings not overlapping the plurality of transparent regions but overlapping the region in which the plurality of pixel circuits are disposed.

[0144] According to another feature of the present specification, the pixel array further includes scan lines extending in a second direction different from the first direction across the plurality of pixel regions on the substrate, and the plurality of sub-pixels in each of the plurality of pixel regions include a first main sub-pixel, a second main sub-pixel, and a third main sub-pixel arranged on one side of the scan lines, and a first redundancy sub-pixel, a second redundancy sub-pixel, and a third redundancy sub-pixel arranged on the other side of the scan lines, wherein the first main sub-pixel and the first redundancy sub-pixel emit light of a first color, the second main sub-pixel and the second redundancy sub-pixel emit light of a second color, and the third main sub-pixel and the third redundancy sub-pixel emit light of a third color.

[0145] According to still another aspect of the present disclosure, the plurality of signal lines may include at least one of a plurality of data lines and a plurality of reference lines.

[0146] According to still another feature of the present specification, each of the plurality of sub-pixels may further include: a first transistor disposed between one of the plurality of data lines and a substrate and electrically connected to the plurality of data lines; a driving transistor disposed between one of the data lines and the substrate and electrically connected to the first transistor; a second transistor disposed between one of the data lines and the substrate and electrically connected to the driving transistor; a storage capacitor disposed between one of the data lines and the driving transistor and electrically connected to a gate electrode of the driving transistor; and a light-emitting element disposed on one of the data lines and electrically connected to the driving transistor.

[0147] According to still another feature of the present specification, in one pixel region among the plurality of pixel regions, first transistors of each of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel may be arranged in a row along a second direction that is different from the first direction, and in one pixel region among the plurality of pixel regions, first transistors of each of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel may be arranged in a row along the second direction.

[0148] According to another feature of the present specification, in one pixel region among the plurality of pixel regions, the scan line may include a protruding portion protruding from the scan line in a first direction and including at least a portion extending in a second direction, and first transistors of a first main sub-pixel, a second main sub-pixel, and a third main sub-pixel arranged on one side of the scan line may be arranged on the protruding portion of the scan line, and first transistors of a first redundancy sub-pixel, a second redundancy sub-pixel, and a third redundancy sub-pixel arranged on the other side of the scan line may be arranged on the scan line.

[0149] According to still another feature of the present specification, in one pixel region among the plurality of pixel regions, the second transistors of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel may be arranged in a row along the first direction, and in one pixel region among the plurality of pixel regions, the second transistors of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel may be arranged in a row along the first direction.

[0150] According to still another feature of the present specification, in one pixel region among the plurality of pixel regions, driving transistors of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel may be arranged in a row along the first direction, and in one pixel region among the plurality of pixel regions, driving transistors of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel may be arranged in a row along the first direction.

[0151] According to another feature of the present specification, in one pixel region among the plurality of pixel regions, light-emitting elements of a first main sub-pixel, a second main sub-pixel, and a third main sub-pixel may be arranged in a row along a first direction, and in one pixel region among the plurality of pixel regions, light-emitting elements of a first redundancy sub-pixel, a second redundancy sub-pixel, and a third redundancy sub-pixel may be arranged in a row along the first direction.

[0152] According to still another aspect of the present disclosure, a plurality of signal wirings may be disposed on the driving transistor and the storage capacitor and overlap the driving transistor and the storage capacitor.

[0153] According to another feature of the present specification, the semiconductor device may further include a buffer layer disposed between the substrate and the driving transistor, a gate insulating layer disposed on the buffer layer between the driving gate electrode and the driving active layer of the driving transistor, a first interlayer insulating layer covering the driving transistor, and one or more insulating layers covering the storage capacitor on the first interlayer insulating layer, wherein a plurality of signal wirings are disposed on the one or more insulating layers, and a thickness of the one or more insulating layers may be thicker than a thickness of the buffer layer, a thickness of the gate insulating layer, and a thickness of the first interlayer insulating layer.

[0154] According to still another feature of the present disclosure, the semiconductor device may further include a power supply wiring disposed between the storage capacitor and the plurality of signal wirings, the power supply wiring overlapping the plurality of signal wirings.

[0155] According to yet another feature of the present disclosure, the power supply wiring may include a low potential power supply wiring or a high potential power supply wiring.

[0156] According to yet another aspect of the present disclosure, the power supply wiring may overlap the drive transistor and the storage capacitor.

[0157] According to still another feature of the present specification, a driving active layer of the driving transistor and a first active layer of the first transistor are disposed under a power supply wiring, a driving drain electrode of the driving transistor and a first source electrode of the first transistor are disposed on the power supply wiring, and the low potential power supply wiring may include a plurality of openings overlapping a contact hole connecting the driving active layer and the driving drain electrode and a contact hole connecting the first active layer and the first source electrode.

[0158] According to still another feature of the present disclosure, the plurality of reference lines may be electrically coupled to the second transistor, and the plurality of reference lines may be disposed in the same layer as the plurality of data lines.

[0159] According to still another feature of the present disclosure, the plurality of reference lines may be integrally formed with a second drain electrode of the second transistor.

[0160] According to another feature of the present specification, the plurality of sub-pixels include a first sub-pixel having a rectangular shape in a plane, a second sub-pixel surrounding adjacent two of four sides of the first sub-pixel in the plane, and a third sub-pixel surrounding an outer portion of the second sub-pixel in the plane, and the first sub-pixel, the second sub-pixel, and the third sub-pixel may form a single rectangular shape.

[0161] A display device according to another embodiment of the present specification includes a substrate including a pixel region and a light-transmitting region that is more transparent than the pixel region, a driving transistor disposed in the pixel region, a power wiring disposed on the driving transistor in the pixel region, a signal wiring disposed on the power wiring in the pixel region, and a light-emitting element disposed in the pixel region and electrically connected to the driving transistor.

[0162] According to another feature of the present specification, the signal wiring may be disposed between the drive transistor and the power supply wiring on the cross section, and may overlap the drive transistor and the power supply wiring.

[0163] Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments, and various modifications can be made within the scope of the technical idea of ​​the present specification. Therefore, the embodiments disclosed in the present specification are for illustration purposes, not for limiting the technical idea of ​​the present specification, and the scope of the technical idea of ​​the present specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. A substrate including a plurality of pixel regions spaced apart from one another, each pixel region including a plurality of sub-pixels, and a plurality of transmissive regions disposed between the pixel regions; and A plurality of signal wirings extending in a first direction on the substrate, the plurality of sub-pixels include a plurality of pixel circuits, and the plurality of signal wirings do not overlap the plurality of transmissive regions but overlap a region in which the plurality of pixel circuits are arranged.

2. scan lines extending in a second direction different from the first direction across the plurality of pixel regions on the substrate; the plurality of sub-pixels in each of the plurality of pixel regions include a first main sub-pixel, a second main sub-pixel, and a third main sub-pixel arranged on one side of the scan line, and a first redundancy sub-pixel, a second redundancy sub-pixel, and a third redundancy sub-pixel arranged on the other side of the scan line; 2. The display device of claim 1, wherein the first main sub-pixel and the first redundancy sub-pixel emit light of a first hue, the second main sub-pixel and the second redundancy sub-pixel emit light of a second hue, and the third main sub-pixel and the third redundancy sub-pixel emit light of a third hue.

3. The display device according to claim 2 , wherein the plurality of signal lines include at least one of a plurality of data lines and a plurality of reference lines.

4. Each of the plurality of sub-pixels includes a first transistor disposed between one of the plurality of data lines and the substrate and electrically connected to the plurality of data lines; a driving transistor disposed between the one data line and the substrate and electrically connected to the first transistor; a second transistor disposed between the one data line and the substrate and electrically connected to the driving transistor; a storage capacitor disposed between the one data line and the driving transistor and electrically connected to a gate electrode of the driving transistor; and The display device of claim 3 , further comprising a light emitting diode disposed on the one data line and electrically connected to the driving transistor.

5. In one pixel region among the plurality of pixel regions, the first transistors of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel are arranged in a row along a second direction different from the first direction, 5. The display device of claim 4, wherein in one pixel region among the plurality of pixel regions, the first transistors of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel are arranged in a row along the second direction.

6. In the one pixel region, the scan line includes a protruding portion protruding from the scan line in the first direction and having at least a portion extending in the second direction; 6. The display device of claim 5, wherein the first transistors of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel arranged on one side of the scan line are arranged on the protruding portion of the scan line, and the first transistors of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel arranged on the other side of the scan line are arranged on the scan line.

7. In one pixel region among the plurality of pixel regions, the second transistors of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel are arranged in a row along the first direction, 5. The display device of claim 4, wherein in one pixel region among the plurality of pixel regions, the second transistors of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel are arranged in a row along the first direction.

8. In one pixel region among the plurality of pixel regions, the driving transistors of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel are arranged in a row along the first direction, 5. The display device of claim 4, wherein in one of the plurality of pixel regions, the driving transistors of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel are arranged in a row along the first direction.

9. In one pixel region among the plurality of pixel regions, the light emitting diodes of the first main sub-pixel, the second main sub-pixel, and the third main sub-pixel are arranged in a row along the first direction, 5. The display device of claim 4, wherein in one pixel region among the plurality of pixel regions, the light emitting diodes of the first redundancy sub-pixel, the second redundancy sub-pixel, and the third redundancy sub-pixel are arranged in a row along the first direction.

10. The display device according to claim 4 , wherein the signal wirings are arranged above the driving transistor and the storage capacitor and overlap the driving transistor and the storage capacitor.

11. a buffer layer disposed between the substrate and the driving transistor; a gate insulating layer disposed on the buffer layer and between the driving gate electrode of the driving transistor and a driving active layer; A first interlayer insulating layer covering the driving transistor; and one or more insulating layers covering the storage capacitor on the first interlayer insulating layer; the plurality of signal wirings are disposed on the one or more insulating layers; The display device of claim 4 , wherein a thickness of the one or more insulating layers is greater than a thickness of the buffer layer, a thickness of the gate insulating layer, and a thickness of the first interlayer insulating layer.

12. a power supply wiring disposed between the storage capacitor and the plurality of signal wirings; The display device according to claim 4 , wherein the power supply wiring overlaps the plurality of signal wirings.

13. The display device according to claim 12 , wherein the power supply wiring includes a low potential power supply wiring or a high potential power supply wiring.

14. The display device of claim 12 , wherein the power supply wiring overlaps the driving transistor and the storage capacitor.

15. a driving active layer of the driving transistor and a first active layer of the first transistor are disposed under the power supply wiring; a driving drain electrode of the driving transistor and a first source electrode of the first transistor are disposed on the power supply wiring; 14. The display device of claim 13, wherein the low potential power wiring includes a plurality of openings overlapping a contact hole connecting the driving active layer and the driving drain electrode and a contact hole connecting the first active layer and the first source electrode.

16. the plurality of reference lines are electrically connected to the second transistor; The display device according to claim 4 , wherein the plurality of reference lines are arranged in the same layer as the plurality of data lines.

17. The display device according to claim 16 , wherein the plurality of reference lines are formed integrally with a second drain electrode of the second transistor.

18. The plurality of sub-pixels include a first sub-pixel having a rectangular shape in a plan view; a second sub-pixel surrounding adjacent two of four sides of the first sub-pixel in a plan view; and a third sub-pixel surrounding an outer portion of the second sub-pixel in a plan view; The display device of claim 1 , wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel form a rectangular shape.

19. a substrate including a pixel region and a light-transmitting region that is more transparent than the pixel region; A drive transistor disposed in the pixel region. a power supply wiring arranged on the driving transistor in the pixel region; A signal wiring arranged on the power supply wiring in the pixel region; and a light emitting element disposed in the pixel region and electrically connected to the driving transistor;

20. The display device according to claim 19 , wherein, in a cross-sectional view, the signal wiring is disposed between the driving transistor and the power supply wiring and overlaps with the driving transistor and the power supply wiring.

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