Transmission scheme for SC-FDMA with two DFT-precoding stages
Patent Information
- Application Number
- JP2024231947
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2015-12-16
- Filing Date
- 2024-12-27
- Publication Date
- 2025-03-26
Smart Images
Figure 2025041953000001_ABST
Abstract
Description
[Technical field]
[0001] This application relates generally to wireless communication systems, and more particularly to Single Carrier Frequency Domain Multiple Access (SC-FDMA) systems that employ multiple DFT precoding stages. [Background technology]
[0002] The ever-increasing demand for data in cellular networks has led to the deployment of small cells providing Long Term Evolution (LTE) connectivity to a smaller number of users than those typically served by macro cells. This allows both to provide users with greater transmit / receive resource opportunities as well as to reduce the load on the macro network. The technical challenges of the small cell Radio Access Network (RAN) have been the focus of significant standardization efforts throughout 3GPP Releases 10-12. This is particularly challenging for outdoor small cell deployments due to the non-traditional locations of small cell sites, such as light poles, road signs, bus shelters, and traffic signals.
[0003] The LTE wireless access technology, also known as Evolved Universal Terrestrial Radio Access Network (E-UTRAN), has been standardized by 3GPP working groups. Orthogonal Frequency Division Multiple Access (OFDMA) and SC-FDMA schemes have been selected for the E-UTRAN downlink (DL) and uplink (UL), respectively. User Equipment (UE) is time and frequency multiplexed on the Physical Uplink Shared Channel (PUSCH) and Physical Uplink Control Channel (PUCCH), and time and frequency synchronization between UEs ensures optimal inter-cell orthogonality. The LTE air interface has been widely adopted by operators as the native 4G technology for Radio Access Networks (RANs) since it offers the best spectral efficiency and cost tradeoff of recent cellular network standards, making it a robust and proven technology. As the trend in RAN topologies is to increase cell density by adding small cells in the vicinity of traditional macro cells, the associated backhaul link density increases accordingly, and the differentiation between RAN and backhaul wireless channels decreases. Several special problems are associated with small cell sites, such as the requirement for high reliability with a packet error rate (PER) of 10-6, sparse spectrum availability, critical latency, cost, relaxed peak-to-average power ratio (PAPR), etc. Small cell sites also behave differently from the RAN in that there are no handovers, remote units do not connect and disconnect at the same rate as user equipment (UE), Non-Line-Of-Sight (NLOS) remote units (RUs) and small cell sites are not mobile.
[0004] While previous improvements in small cell topologies have provided significant improvements in data throughput, further improvements are possible. Summary of the Invention
[0005] In a first embodiment, a method of operating a wireless communication system includes receiving a first data stream, and DFT0 transforming it into a first frequency domain data stream by a Discrete Fourier Transform (DFT) having a size of N DFT0 N is a positive integer. The method further includes receiving a second data stream in parallel with the first data stream. The second data stream has a length N DFT1 is transformed into a second frequency domain data stream by a DFT having size N DFT1 is a positive integer. The first and second frequency domain data streams are mapped to respective subcarriers.
[0006] In a second embodiment, a method of operating a wireless communication system includes receiving a parallel data stream having first and second portions. The first portion is a parallel data stream of size N DFT0 The first time domain data stream is transformed into a time domain data stream by an Inverse Discrete Fourier Transform (IDFT) having N DFT0 is a positive integer. The second part is the size N DFT1 and transforming the second time domain data stream into a second time domain data stream by IDFT with N DFT1 is a positive integer.
[0007] In a third embodiment, a method of operating a wireless communications system includes encoding a serial data stream with a forward error correction (FEC) code to generate FEC encoded data, the FEC encoded data being mapped to a sequence of symbols, and out-of-phase pilot symbols being inserted into the sequence of symbols. [Brief description of the drawings]
[0008] [Figure 1] FIG. 1 is a diagram of a wireless communication system with a cellular macro site that hosts a backhaul point-to-multipoint (P2MP) hub unit (HU) that serves a remote unit (RU) that relays communications between small cells and multiple user equipments (UEs).
[0009] [Diagram 2] FIG. 1 is a diagram of a subset of frame structures.
[0010] [Diagram 3] FIG. 1 is a diagram of a conventional baseband transmitter.
[0011] [Figure 4] 1 is a table showing 50 predetermined Discrete Fourier Transform (DFT) or Inverse Discrete Fourier Transform (IDFT) sizes and their corresponding indexes.
[0012] [Figure 5A] FIG. 2 is a diagram of a baseband transmitter having two separate DFT precoding stages.
[0013] [Figure 5B] FIG. 2 is a diagram of a baseband receiver having two separate IDFT decoding stages.
[0014] [Figure 6A] 1 is a table showing predetermined DFT / IDFT sizes for a system bandwidth of 5 MHz. [Figure 6B] 1 is a table showing predetermined DFT / IDFT sizes for a system bandwidth of 10 MHz. [Figure 6C] 1 is a table showing predetermined DFT / IDFT sizes for a system bandwidth of 15 MHz. [Figure 6D] 1 is a table showing predetermined DFT / IDFT sizes for a system bandwidth of 20 MHz.
[0015] [Figure 7A] FIG. 2 is a diagram of a baseband transmitter having two separate and parallel DFT precoding stages.
[0016] [Figure 7B]FIG. 2 is a diagram of a baseband receiver having two separate and parallel IDFT decoding stages.
[0017] [Figure 8A] 1 is a diagram of a baseband transmitter with time domain phase pilot symbol insertion.
[0018] [Figure 8B] FIG. 1 is a diagram of a baseband receiver with phase noise mitigation (PNM).
[0019] [Figure 8C] FIG. 1 is a diagram of a baseband transmitter having time-domain phase pilot symbol insertion with two separate DFT precoding stages.
[0020] [Figure 8D] FIG. 1 is a diagram of a baseband transmitter with time-domain phase pilot symbol insertion and two separate and parallel DFT precoding stages.
[0021] [Figure 9A] FIG. 8B is a diagram of a phase pilot symbol generator circuit that can be used in FIG. 8A, FIG. 8C, or FIG. 8D.
[0022] [Figure 9B] FIG. 2 illustrates phase pilot symbols inserted within a 48QAM symbol. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0023] FIG. 1 illustrates a NLOS time division duplex (TDD) wireless backhaul system according to an exemplary embodiment. A cellular macro site 100 hosts a macro base station. The macro site 100 also hosts a wireless backhaul hub unit (HU). The macro site 100 is connected to small cell sites, such as small cell site 104. Each small cell site is co-located with a small cell base station and a wireless backhaul remote unit (RU). The macro site 100 communicates with the small cell sites through a point-to-multipoint (P2MP) wireless backhaul system via a backhaul link, such as backhaul link 110. The base station of the macro site 100 communicates directly with the UE 102 via the RAN link 112. However, the UE 106 communicates directly with the small cell base station of the small cell site 104 via the RAN access link 108. The RUs of the small cell site 104 communicate directly with the HUs of the macro cell site 100 via the backhaul link 110. The system is designed to maximize spectrum reuse. The backhaul link 110 design utilizes a 0.5 ms slot-based transmission time interval (TTI) to minimize latency, and 5 ms UL and DL frames for compatibility with TD-LTE. Alternative embodiments may use different frame durations and different slot-based TTIs.
[0024] FIG. 2 illustrates UL / DL frame configurations 1, 3, and 5. Each frame has a 5 ms duration, and each frame is slot-based, not subframe-based. Each frame has 10 slots (0-9). Each slot has a 0.5 ms duration. Of course, alternative embodiments may use different frame durations and different slot-based transmission time intervals (TTIs). Here, D denotes a downlink slot and U denotes an uplink slot. In each of the three UL / DL configurations, slot 3 is a special slot, denoted S. This fixed location of the special slot ensures compatibility with TD-LTE frames. It advantageously makes it possible to always find an NLOS UL / DL configuration that is 100% compatible with any 5 ms duration TD-LTE UL / DL subframe configuration. For example, this prevents NLOS backhaul DL transmissions from interfering with TD-LTE RAN UL transmissions on the access link when both operate on the same frequency. In other words, it advantageously prevents the transmitters at the macrocell site 100 of one system from interfering with the receivers of the co-located system.
[0025] FIG. 3 is a diagram of a conventional baseband transmitter. In this description, any reference to a circuit may include a circuit formed by hardware, software, or a combination of hardware and software. The baseband transmitter of FIG. 3 receives a data signal and adds a cyclic redundancy check (CRC) block. The data is then encoded or precoded by a forward error correction (FEC) encoder and scrambled by a scrambling circuit. The scrambled data is mapped to an appropriate symbol constellation and converted into a parallel data stream. A discrete Fourier transform (DFT) precoding stage converts the data into the frequency domain and applies it to a subcarrier (SC) mapping circuit along with control channel and other physical (PHY) channel data. The parallel data stream is then converted into time domain data and converted into a serial data stream. A cyclic prefix is added to the serial data stream. The resulting time slotted output data is conceptually represented on the right with time as the horizontal axis and frequency as the vertical axis. A time slot is preferably 0.5 ms in duration comprising seven SC-FDMA symbols. The first SC-FDMA symbol is a pilot signal that transmits a predetermined frequency domain signal to assist the receiver in performing channel estimation. The next six SC-FDMA symbols in time are for the data channel. The bandwidth of the time slot may be from 5 MHz to 20 MHz, including upper and lower subcarriers reserved for the control channel at each end of the frequency band. The space between the control channel and the pilot signal / data channel indicates subcarriers that are possibly not used. This may occur when a particular size of DFT is not supported. This frequently occurs when a small number of UEs or RUs are assigned to the available radio resources, reducing the spectral efficiency.
[0026] One of the problems with conventional DFT circuits is that they are necessarily limited in discrete size. This is because DFT operations are typically implemented in hardware due to high data throughput requirements. Of course, the same constraints apply to the receiver and their corresponding inverse discrete Fourier transforms (IDFTs), as detailed hereafter. Figure 4 is a table showing 50 predefined discrete Fourier transform (DFT) or inverse discrete Fourier transform (IDFT) sizes and their corresponding indexes. These predefined sizes are provided by Texas Instruments in their Keystone family of system-on-chip (SoC) products. When a single transmission link or a small number of transmission links are assigned to a large frequency band, it is possible that the entire frequency spectrum cannot be filled and some subcarriers are not used for communication. For example, an LTE 20 MHz system has 1200 subcarriers with a 15 KHz subcarrier spacing. If the control channel (Figure 3) requires 24 subcarriers, including 12 above and 12 below the data channel, then 1176 subcarriers are still available for the data channel. Although DFT index 41 (FIG. 4) is used for the data channel, 24 subcarriers (1200-24-1152=24) remain unused, so the spectral efficiency of the communication system is less than optimal.
[0027] FIG. 5A is a diagram of a baseband transmitter according to a first embodiment having two separate DFT precoding stages. The baseband transmitter of FIG. 5A receives a data signal and appends a cyclic redundancy check (CRC) block 500. The data is then encoded or precoded by a forward error correction (FEC) encoder 502 and scrambled by a scrambling circuit 504. The scrambled data is mapped 506 to an appropriate symbol constellation and converted to a parallel data stream 508. Discrete Fourier Transform (DFT) circuits 510 and 511 convert the data to a frequency domain signal and apply it to a subcarrier (SC) mapping circuit 512 along with control channel and other physical (PHY) channel data. The DFT circuit 510 uses DFT index 31 to map N DFT0 = 600. The DFT circuit 511 uses a DFT index of 30, and N DFT1 =576. Taken together, they allocate 1176 subcarriers to the data channel 530, and all available subcarriers are used. The frequency domain data is applied to a subcarrier (SC) mapping circuit 512 along with the control channel and other physical (PHY) channel data. The parallel data stream is then converted to time domain data 514 and converted to a serial data stream 516. A cyclic prefix is added 528 to the serial data stream. The resulting output data for the time slot 530 is conceptually represented to the right, with time as the horizontal axis and frequency as the vertical axis. The top of the data channel is the N DFT0 The lower part of the data channel corresponds to the N subcarriers generated by the DFT circuit 511. DFT1 5A advantageously uses parallel DFT precoding stages 510 and 511 to fully utilize the available subcarriers, thereby maximizing spectral efficiency.
[0028] 5B is a diagram of a baseband receiver with two separate IDFT stages. Data 530 is applied to the baseband receiver and the cyclic prefix (CP) is removed 540. A serial-to-parallel circuit 542 converts the data into a parallel data stream, which is applied to a Fast Fourier Transform (FFT) circuit 544. The resulting frequency domain data is applied to a subcarrier demapping and equalization circuit 546, where the individual subcarriers are preferably equalized to compensate for channel effects. The equalized data is then applied to Inverse Discrete Fourier Transform (IDFT) circuits 548 and 549. The IDFT circuit 548 is an N-th order DFT circuit corresponding to the DFT circuit 510. DFT0 The IDFT circuit 549 performs N = 600 transformations corresponding to the DFT circuit 511. DFT1 A = 576 transformation is performed on the received and equalized QAM symbols. The resulting time domain data is applied to a parallel-to-serial circuit 550. The resulting serial data stream is then applied to a symbol demapping circuit 552, where a log-likelihood ratio (LLR) calculation is performed on the received and equalized QAM symbols to provide soft decision information for each information bit to an FEC decoder (such as a turbo decoder). The resulting soft decision information is then descrambled 554 and applied to a decode circuit 556. The resulting decoded data is then applied to a cyclic redundancy check (CRC) circuit 558 to verify correct data reception.
[0029] The above examples of Figures 5A and 5B advantageously use all 1200 subcarriers of the 20 MHz bandwidth, with no unused or guard subcarriers. The data and control channel allocation sizes are specified as part of the air interface standard. Of course, other sizes of DFT and IDFT combinations are possible. For example, the DFT circuit 510 may be configured to perform N DFT0 = 1080, and the DFT circuit 511 may use a DFT index of 40 DFT1 Alternatively, the DFT circuit 510 may use a DFT index of 11 with N DFT0 = 960, and the DFT circuit 511 may use a DFT index 37 of NDFT1 = 216 DFT indices 18 may be used. However, taken together, any selected combination uses 1176 subcarriers of the data channel 530.
[0030] 6A-6D are tables showing predetermined DFT / IDFT sizes for system bandwidths of 5 MHz, 10 MHz, 15 MHz, and 20 MHz, respectively, with 300, 600, 900, and 1200 system subcarriers. The embodiment preferably uses the same table for DFT and IDFT allocations. Each row indicates a respective PHY channel category, including control channel, data channel, and unused or guard subcarrier allocations, as well as DFT0 and DFT1 sizes for the data channel. Each column shows various subcarrier allocations for the control channel with 2 or 4 physical resource blocks (PRBs). There are four different control channel allocation sizes, depending on the required amount of control information in each mode of operation. For maximum spectral efficiency, the sum of the control channel, data channel, and guard subcarriers in each column should be equal to the total number of system subcarriers for the respective system bandwidth. N DFT0 and N DFT1 The sum of N is equal to the number of subcarriers in the data channel. The two selected DFT sizes of Figures 6A-6D for the parallel DFT precoding stage advantageously provide a minimum number of unused or guard subcarriers, thereby maximizing the spectral efficiency of the system. The examples of Figures 5A and 5B above are similar to those of Figure 6D, except that the sum of N DFT0 = 600 and N DFT1 We use an allocation of N = 576. Also, in some cases, only a single DFT and a single IDFT circuit are needed. For example, for a 10 MHz bandwidth with 2 PRBs, as shown in the left column of FIG. 6B, DFT0 Only N = 576 single DFT precoding stages are needed. Also, for a 20 MHz bandwidth with 4 PRBs, as shown in the second column of Figure 6D, DFT0= 1152. Finally, although only two DFT / IDFT sizes are provided by example, three or more DFT / IDFT sizes may be allocated to utilize all available subcarriers.
[0031] 7A is a diagram of a baseband transmitter according to a second embodiment having two separate and parallel DFT precoding stages. This embodiment provides two separate data channels, each with its own respective transport block. Data channel 0 includes a CRC circuit 700 and an FEC encoder circuit 702, followed by a scrambling circuit 704. The scrambled data is symbol mapped by circuit 706 and applied to a serial-to-parallel (S / P) circuit 708. The parallel data streams are then multiplied by a 16-bit DFT precoding circuit 708 of size N as previously described. DFT0 The data is then applied to a DFT circuit 710 having a DFT of size N as previously described. Data channel 1 is formed in parallel with data channel 0 and includes a CRC circuit 701 and an FEC encoder circuit 703 followed by a scrambling circuit 705. The scrambled data is symbol mapped by circuit 707 and applied to an S / P circuit 709. The parallel data streams are then multiplied by a DFT circuit 710 having a DFT of size N as previously described. DFT1 The frequency domain data is applied to a DFT circuit 711 having a frequency domain (Fd) of 10 MHz. The frequency domain data is applied to a subcarrier (SC) mapping circuit 712 along with control channel and other physical (PHY) channel data. The parallel data streams are then converted to time domain data 714 and converted to a serial data stream 716. A cyclic prefix is added to the serial data stream 718. The resulting output data for time slot 730 is conceptually represented to the right with time as the horizontal axis and frequency as the vertical axis. The top (data channel 0) shows the N DFT0 The lower part (data channel 2) corresponds to the N subcarriers generated by the DFT circuit 711. DFT1 Corresponding to the subcarrier.
[0032] FIG. 7B is a diagram of a baseband receiver corresponding to the baseband transmitter of FIG. 7A, with two separate and parallel IDFT stages. Data 730 is applied to the baseband receiver and the cyclic prefix (CP) is removed 740. A serial-to-parallel circuit 742 converts the data into a parallel data stream, which is applied to a Fast Fourier Transform (FFT) circuit 744. The resulting frequency domain data is applied to a subcarrier demapping and equalization circuit 746, where the individual subcarriers are preferably equalized to compensate for channel effects. The equalized data is then applied to Inverse Discrete Fourier Transform (IDFT) circuits 748 and 749. The IDFT circuit 748 performs an N-th subcarrier de-mapping and equalization for data channel 0, which corresponds to the DFT circuit 710. DFT0 The IDFT circuit 749 performs the N DFT1 A conversion is performed on the received and equalized QAM symbols. The resulting time domain data is applied to parallel-to-serial circuits 750 and 751. The resulting serial data streams are each demapped by respective circuits 752 and 753. Here, a log-likelihood ratio (LLR) calculation is performed on the received and equalized QAM symbols to provide soft decision information for each information bit to an FEC decoder (such as a turbo decoder). The resulting soft decision information is then descrambled by respective circuits 754 and 755. The descrambled data streams are applied to respective decode circuits 756 and 757. A cyclic redundancy check (CRC) is performed on each data stream by respective circuits 758 and 759 to verify correct data reception.
[0033] The above examples of Figures 7A and 7B advantageously use all subcarriers in the 5 MHz to 20 MHz bandwidth without requiring additional hardware. The data and control channel allocation sizes are specified as part of the air interface standard, so no additional software is required. The embodiments of Figures 7A and 7B are also adapted to separate data channels and their respective transport blocks.
[0034] FIG. 8A is a diagram of a baseband transmitter with time-domain phase pilot symbol insertion. The baseband transmitter of FIG. 8A receives a data signal and appends a cyclic redundancy check (CRC) block 800. The data is then encoded or precoded 802 by a forward error correction (FEC) encoder and scrambled 804 by a scrambling circuit. The scrambled data is mapped 806 to an appropriate symbol constellation. A phase pilot symbol (PPS) generator 900 generates a sequence of phase pilot symbols that are inserted into the time-domain data stream by a phase pilot symbol insertion circuit 808. The phase pilot symbols can allow the receiver to estimate, track, and compensate for phase noise in the received QAM symbols. This allows significant phase noise mitigation, which is very important for higher order modulation formats, including 256QAM or higher. This is particularly advantageous in higher frequency bands, such as the 5 GHz license-free band, microwave bands, and mmWave bands. The resulting data stream with phase pilot symbols is converted to a parallel data stream 810. A discrete Fourier transform (DFT) circuit 812 converts the data to the frequency domain and applies it, along with control channel and other physical (PHY) channel data, to a subcarrier (SC) mapping circuit 814. The parallel data stream is then converted to time domain data 816 and converted to a serial data stream 818. A cyclic prefix is added to the serial data stream 820.
[0035] FIG. 8B is a diagram of a baseband receiver that may be used with the baseband transmitter of FIG. 8A. Data is applied to the baseband receiver and the cyclic prefix (CP) is removed 840. A serial-to-parallel circuit 842 converts the data into a parallel data stream that is applied to a Fast Fourier Transform (FFT) circuit 844. The resulting frequency domain data is applied to a subcarrier demapping and equalization circuit 846, where the individual subcarriers are preferably equalized to compensate for channel effects. The equalized data is then applied to an Inverse Discrete Fourier Transform (IDFT) circuit 848, which generates an N-th order DFT corresponding to the DFT circuit 810. IDFT 8, a parallel to serial conversion is performed. The resulting time domain data is applied to a parallel to serial circuit 850. The resulting serial data stream is then applied to a phase noise mitigation (PNM) circuit 552. The PNM circuit estimates and tracks the phase noise embedded in the received and equalized quadrature amplitude modulation (QAM) symbols. The PNM circuit compensates for the embedded phase noise using known phase pilot symbols 900 from the baseband transmitter. The compensated QAM data stream is then applied to a symbol demapping circuit 854. The resulting information bits are then descrambled 856 and applied to a decode circuit 858. The resulting decoded data is then applied to a cyclic redundancy check (CRC) circuit 860 to verify correct data reception.
[0036] FIG. 8C is a diagram of a baseband transmitter with time domain phase pilot symbol insertion with two separate DFT precoding stages. The precoding section (800-806) of the baseband transmitter of FIG. 8C operates as described above with reference to FIG. 8A. A phase pilot symbol (PPS) generator 900 generates a sequence of phase pilot symbols which are inserted into the time domain data stream by a phase pilot symbol insertion circuit 808. The resulting data stream with the phase pilot symbols is converted into a parallel data stream 810. Discrete Fourier Transform (DFT) circuits 812 and 813 convert the data into the frequency domain and apply it, along with the control channel and other physical (PHY) channel data, to a subcarrier (SC) mapping circuit 814. The DFT circuit 812 converts N DFT0 The DFT circuit 813 performs the N DFT1 8. The parallel data streams are then converted to time domain data 816 and then converted to a serial data stream 818. A cyclic prefix is added to the serial data stream 820.
[0037] FIG. 8D is a diagram of another embodiment of a baseband transmitter with time domain phase pilot symbol insertion and two separate and parallel DFT precoding stages. As described above with reference to FIG. 7A, this embodiment provides two separate data channels, each with its own respective transport block. Data channel 0 includes a CRC circuit 800 and an FEC encoder circuit 802, followed by a scrambling circuit 804. The scrambled data is symbol mapped by circuit 806 and applied to a phase pilot insertion circuit 808. The phase pilot insertion circuit 808 inserts phase pilot symbols from the PPS generator circuit 900 into the serial data stream. A serial-to-parallel (S / P) circuit 810 converts this into a parallel data stream of size N DFT0The data is applied to a DFT circuit 812 having a PPS generator circuit 901. Data channel 1 is formed in parallel with data channel 0 and includes a CRC circuit 801 and an FEC encoder circuit 803 followed by a scrambling circuit 805. The scrambled data is symbol mapped by circuit 807 and applied to a phase pilot insertion circuit 809 which inserts phase pilot symbols from a PPS generator circuit 901 into the serial data stream. A serial to parallel (S / P) circuit 811 converts this to a parallel data stream of size N DFT1 The resulting frequency domain data from data channels 1 and 2 is applied to a DFT circuit 813 having a DFT circuit with a DFT signal. The resulting frequency domain data from data channels 1 and 2 is applied to a subcarrier (SC) mapping circuit 814 along with the control channel and other physical (PHY) channel data. The parallel data streams are then converted to time domain data 816 and converted to a serial data stream 818. A cyclic prefix is added to the serial data stream 818.
[0038] FIG. 9A is a diagram of a phase pilot symbol (PPS) generator circuit 900 or 901 that can be used in FIG. 8A, FIG. 8C, or FIG. 8D. The PPS generator includes a pseudorandom noise (PN) generator circuit 902, which may be formed from one or more linear feedback shift registers (LFSRs) with appropriate feedback circuit elements. The PN generator circuit 902 preferably generates a pseudorandom noise (PN) sequence, such as a Gold code, that is used for the PPS symbols. The PPS generator includes a symbol mapper circuit 906 coupled to receive the PN sequence. The symbol mapper circuit 906 preferably maps two PN sequence bits to quadrature phase shift keying (QPSK) symbols to form the PPS. Of course, the symbol mapper can be adapted to map the PN sequence bits to other symbols, such as QAM symbols. The QPSK PPS is preferably generated at a higher power than the QAM data symbols to facilitate receiver phase noise mitigation under low SNR or poor channel conditions. The PPS generator also includes a seed circuit 904 coupled to receive a loading signal, the active level of which is determined by an initialization sequence c at the beginning of each radio frame. init is loaded into the generator circuit 902. In a preferred embodiment, init is expressed as follows: JPEG2025041953000002.jpg14166, where n RU is the index of a remote unit (RU) or other receiving unit as in FIG. 1, and q is the binary codeword index i DL,UL where N is the cell ID of the wireless cell. K is used to denote the stage K of the LFSR that receives the initialization seed.
[0039] 9B is a diagram showing the phase pilot symbols inserted into the 48QAM symbol. PHP The phase pilot (PHP) block is inserted with N DFT / NPHP Phase pilot symbols are inserted into the PHP block. PHP / 2-1 modulation symbol before PPS, N PHP Each PPS is inserted such that there are 1 / 2 modulation symbols after the PPS. For example, the left PHP block in Figure 9B contains 23 leading modulation symbols, one PPS, and 24 trailing modulation symbols for a total of 48 symbols. Similarly, if the last PHP block is of length N PHP,last If N PHP,last / 2-1 modulation symbol before PPS, N PHP,last The PPS is inserted such that 1 / 2 modulation symbols are after the PPS. In the example of Figure 9B, the PPS advantageously compensates for the phase noise embedded in the QAM symbol stream with only 2% overhead. PPS insertion is preferably enabled or disabled via higher layer signaling independently for each RU or receiving unit.
[0040] Variations may be made in the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the present invention. The embodiments may be implemented in software, hardware, or a combination of both.
Claims
1. 1. A method of operating a communications system, comprising: Receiving a first data stream; N ＤＦＴ０ Transforming the first data stream into a first frequency domain data stream by a Discrete Fourier Transform (DFT) having a size of N ＤＦＴ０ is a positive integer, receiving a second data stream in parallel with the first data stream; N ＤＦＴ１ transforming the second data stream into a second frequency domain data stream by a DFT having a size of N ＤＦＴ１ is a positive integer, and mapping the first and second frequency domain data streams to respective subcarriers; A method comprising:
2. 2. The method of claim 1 , Mapping the first and second frequency domain data streams to respective subcarriers along with other physical channel data.
3. 2. The method of claim 1 , converting each of the subcarriers into a time domain data stream by an inverse fast Fourier transform having an N FFT size; ＦＦＴ But, N ＤＦＴ０ and N ＤＦＴ１ A method that is greater than or equal to the sum of.
4. 4. The method of claim 3, A method comprising appending a cyclic prefix to the time domain data stream.
5. 2. The method of claim 1 , receiving an input data stream; encoding the input data stream with a forward error correction code (FEC) to generate an FEC encoded data stream; mapping the FEC encoded data stream into a plurality of data symbols; and generating said first and second data streams from said plurality of data symbols; A method comprising:
6. 5. The method of claim 4, The method of claim 1, further comprising scrambling the FEC encoded data stream prior to said mapping step.
7. 2. The method of claim 1 , N to minimize the number of unused subcarriers. ＤＦＴ０ and N ＤＦＴ１ The method of claim 1, further comprising:
8. 2. The method of claim 1 , Receiving a first input data stream; encoding the first input data stream with a first forward error correction code (FEC) to generate a first FEC encoded data stream; mapping the first FEC encoded data stream to a first plurality of data symbols; generating the first data stream from the first plurality of data symbols; receiving a second input data stream in parallel with the first input data stream; generating a second forward error correction (FEC) encoded data stream; encoding the second input data stream with FEC of 2; mapping the second FEC encoded data stream to a second plurality of data symbols; and generating the second data stream from the second plurality of data symbols; A method comprising:
9. 9. The method of claim 8, scrambling the first FEC encoded data stream prior to said step of mapping the first FEC encoded data stream; and scrambling the second FEC encoded data stream prior to said step of mapping the second FEC encoded data stream; A method comprising:
10. 1. A method of operating a communications system, comprising: receiving first and second portions of the data stream in parallel; Size N ＤＦＴ０ transforming the first portion into a first time-domain data stream by an Inverse Discrete Fourier Transform (IDFT) having N ＤＦＴ０ is a positive integer, and Size N ＤＦＴ１ transforming the second portion into a second time domain data stream by an IDFT having N ＤＦＴ１ is a positive integer, A method comprising:
11. 11. The method of claim 10, generating parallel streams of subcarriers by a Fast Fourier Transform (FFT) having size N FFT , where N FFT is a positive integer and N FFT is a positive integer; ＤＦＴ０ and N ＤＦＴ１ greater than or equal to the sum of Demapping and equalizing the subcarriers to generate the first and second portions; A method comprising:
12. 12. The method of claim 11, N FFT is N ＤＦＴ０ and N ＤＦＴ１ A method that is greater than the sum of .
13. 11. The method of claim 10, symbol demapping the first and second time domain data streams to generate a serial data stream; decoding a forward error correction code (FEC) of the serial data stream; and performing a cyclic redundancy check on the decoded serial data stream; A method comprising:
14. 14. The method of claim 13, The method comprising descrambling the serial data stream prior to said decoding step.
15. 11. The method of claim 10, removing a cyclic prefix prior to said step of receiving the first and second portions of the data stream.
16. 11. The method of claim 10, Demapping symbols of the first time domain data stream to generate a first serial data stream; decoding a forward error correction code (FEC) of the first serial data stream; performing a cyclic redundancy check on the decoded first serial data stream; Demapping symbols of the second time domain data stream to generate a second serial data stream; decoding a forward error correction code (FEC) of the second serial data stream; and performing a cyclic redundancy check on the decoded second serial data stream; A method comprising:
17. 17. The method of claim 16, descrambling the first serial data stream prior to the step of decoding the FEC of the first serial data stream; and descrambling the second serial data stream prior to said step of decoding the FEC of the second serial data stream; A method comprising:
18. 1. A method of operating a communications system, comprising: Mapping the first data stream into a first series of quadrature amplitude modulation (QAM) symbols; generating a first pseudorandom noise (PN) sequence; mapping a plurality of bits of the first PN sequence to a first phase pilot symbol; inserting said first phase pilot symbol into said first series of QAM symbols; After the step of inserting, N ＤＦＴ０ Transforming the first data stream into a first frequency domain data stream by a Discrete Fourier Transform (DFT) having a size of N ＤＦＴ０ is a positive integer, mapping the first frequency domain data stream to respective first subcarriers; and transforming each first subcarrier into a first time-domain data stream with an Inverse Discrete Fourier Transform (IDFT) having size N, where N is a positive integer; A method comprising:
19. 20. The method of claim 18, The method includes generating the first PN sequence in response to at least one of a remote unit (RU) index, a codeword index, a cell identification, and a downlink (DL) or uplink (UL) index.
20. 20. The method of claim 18, mapping the second data stream to a second series of QAM symbols; generating a second pseudorandom noise PN sequence; mapping a plurality of bits of the second PN sequence to second phase pilot symbols; inserting said second phase pilot symbol into said second series of QAM symbols; N ＤＦＴ１ transforming the second data stream into a second frequency domain data stream by a Discrete Fourier Transform (DFT) having a size of N ＤＦＴ１ is a positive integer, and mapping the second frequency domain data stream to respective second subcarriers; A method comprising: