Display device

Abstract

To provide a display device capable of improving light transmissivity.SOLUTION: A display device in an embodiment includes a base material, a plurality of first pixels disposed in a first region included in a display region on the base material, and a plurality of second pixels disposed in a second region that is different from the first region included in the display region. Each of the first pixels includes a first pixel circuit including a plurality of transistors, and a first display element driven by the first pixel circuit. Each of the second pixels includes a second pixel circuit including a plurality of transistors, and a second display element driven by the second pixel circuit. The number of transistors included in the second pixel circuit is smaller than that in the first pixel circuit.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] 2. Description of the Related Art In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use, and it is known that electronic devices such as smartphones are equipped with such display devices.

[0003] In such electronic devices, by adopting a configuration in which a camera is disposed on the back surface of the display device (display area), it is possible to expand the display area to an area overlapping with the camera.

[0004] However, in such a configuration, light must enter the camera (its imaging element) through the display device, so it is necessary to ensure sufficient light transmittance in the display device (the area of ​​the display area that overlaps with the camera). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-036290 A [Patent Document 2] JP 2019-211665 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a display device capable of improving light transmittance. [Means for solving the problem]

[0007] A display device according to an embodiment includes a substrate, a plurality of first pixels arranged in a first region included in a display region on the substrate, and a plurality of second pixels arranged in a second region different from the first region included in the display region. Each of the first pixels includes a first pixel circuit including a plurality of transistors and a first display element driven by the first pixel circuit. Each of the second pixels includes a second pixel circuit including a plurality of transistors and a second display element driven by the second pixel circuit. The number of transistors included in the second pixel circuit is smaller than the number of transistors included in the first pixel circuit. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of a plurality of sub-pixels included in a pixel. [Diagram 3] FIG. 13 is a diagram showing another example of the layout of a plurality of sub-pixels included in a pixel. [Figure 4] FIG. 3 is a schematic cross-sectional view of the display device taken along the line AA in FIG. 2. [Diagram 5] FIG. [Figure 6] FIG. 11 is a schematic cross-sectional view for explaining a display element formed by utilizing a partition wall. [Figure 7] FIG. 11 is a schematic cross-sectional view for explaining a display element formed by utilizing a partition wall. [Figure 8] FIG. 11 is a schematic cross-sectional view for explaining a display element formed by utilizing a partition wall. [Figure 9] FIG. 1 is a plan view showing a part of an electronic device in which a display device is incorporated. [Figure 10] FIG. 4 is a diagram for explaining pixel circuits arranged in the first display region. [Figure 11] FIG. 4 is a diagram for explaining pixel circuits arranged in the second display region. [Figure 12] FIG. 12 is a schematic cross-sectional view of the display device taken along line BB in FIG. [Figure 13]FIG. 2 is a diagram showing an example of a circuit configuration of a pixel circuit arranged in a first display region. [Figure 14] FIG. 4 is a diagram showing an example of a circuit configuration of a pixel circuit arranged in a second display region. [Figure 15] 15 is a diagram showing a schematic arrangement of various wirings connected to the pixel circuit shown in FIGS. 13 and 14. FIG. [Figure 16] 14 is a diagram for explaining the operation of the pixel circuit shown in FIG. 13. [Figure 17] 15 is a diagram for explaining the operation of the pixel circuit shown in FIG. 14. [Figure 18] FIG. 13 is a diagram showing another example of the circuit configuration of the pixel circuits arranged in the first display region. [Figure 19] FIG. 13 is a diagram showing another example of the circuit configuration of the pixel circuits arranged in the second display region. [Figure 20] 20 is a diagram showing a schematic arrangement of various wirings connected to the pixel circuit shown in FIGS. 18 and 19. FIG. [Figure 21] 19 is a diagram for explaining the operation of the pixel circuit shown in FIG. 18. [Figure 22] 20 is a diagram for explaining the operation of the pixel circuit shown in FIG. 19. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in terms of width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0010] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0011] The display device according to the present embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be mounted on an electronic device such as a smartphone. Note that the electronic device on which the display device according to the present embodiment is mounted may be an electronic device other than a smartphone (for example, a tablet terminal, etc.).

[0012] 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA surrounding the display area DA, on an insulating base material 10. The base material 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged (disposed) in a matrix in the first direction X and the second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the subpixels SP include a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The subpixels SP may include subpixels of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3. The subpixels SP may also include subpixels of other colors instead of any of the subpixels SP1, SP2, and SP3.

[0015] Each of the subpixels SP includes a pixel circuit and a display element driven by the pixel circuit, the details of which will be described later. The pixel circuit is composed of, for example, a plurality of transistors (switching elements constituted by thin film transistors). The display element is an organic light-emitting diode as a light-emitting element. For example, the subpixel SP1 includes a display element that emits light in the red wavelength range, the subpixel SP2 includes a display element that emits light in the green wavelength range, and the subpixel SP3 includes a display element that emits light in the blue wavelength range.

[0016] 2 shows an example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in a pixel PX. Here, the following description focuses on four pixels PX.

[0017] The sub-pixels SP1, SP2, and SP3 constituting one pixel PX are each formed in a substantially rectangular shape extending in the second direction Y, and are aligned in the first direction X. When focusing on two pixels PX aligned in the first direction X, the colors displayed in adjacent sub-pixels SP are different from each other. When focusing on two pixels PX aligned in the second direction Y, the colors displayed in adjacent sub-pixels SP are the same. The areas of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0018] FIG. 3 shows another example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in the pixel PX.

[0019] The subpixels SP1 and SP2 constituting one pixel PX are aligned in the second direction Y, the subpixels SP1 and SP3 are aligned in the first direction X, and the subpixels SP2 and SP3 are aligned in the first direction X. The subpixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and the subpixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of ​​the subpixel SP2 is larger than the area of ​​the subpixel SP1, and the area of ​​the subpixel SP3 is larger than the area of ​​the subpixel SP2. The area of ​​the subpixel SP1 may be the same as the area of ​​the subpixel SP2.

[0020] Focusing on two pixels PX aligned in the first direction X, in a region where subpixels SP1 and SP3 are alternately arranged and in a region where subpixels SP2 and SP3 are alternately arranged, the colors displayed in the subpixels SP adjacent in the first direction X are different from each other. On the other hand, focusing on two pixels PX aligned in the second direction Y, in a region where subpixels SP1 and SP2 are alternately arranged, the colors displayed in the subpixels SP adjacent in the second direction Y are different from each other. Also, in a region where multiple subpixels SP3 are aligned, the colors displayed in the subpixels SP adjacent in the second direction are the same.

[0021] Note that the outlines of the subpixels SP1, SP2, and SP3 shown in Figures 2 and 3 correspond to the outlines of the areas in which colors are displayed in the subpixels SP (i.e., the light-emitting areas), but are shown in a simplified form and do not necessarily reflect the actual shapes.

[0022] Here, although details will be described later, ribs and partition walls are arranged in the display area DA in this embodiment. The ribs have openings in the sub-pixels SP1, SP2, and SP3, respectively. The partition walls are arranged at the boundaries between adjacent sub-pixels SP and overlap with the ribs in a plan view. Specifically, the partition walls are arranged between adjacent openings (sub-pixels SP) in the first direction X and between adjacent openings (sub-pixels SP) in the second direction Y. As a result, the partition walls have a lattice shape formed so as to separate the sub-pixels SP1, SP2, and SP3 as a whole. In other words, the partition walls have openings in the sub-pixels SP1, SP2, and SP3, similar to the ribs.

[0023] Fig. 4 is a schematic cross-sectional view of the display device DSP taken along the line AA in Fig. 2. In the display device DSP, an insulating layer 11 called an undercoat layer is disposed on a light-transmitting substrate 10 such as the above-mentioned glass (on the surface on which a display element and the like are disposed).

[0024] The insulating layer 11 has a three-layered structure including, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). Note that the insulating layer 11 is not limited to a three-layered structure. The insulating layer 11 may have a layered structure of more than three layers, or may have a single-layered structure or a two-layered structure.

[0025] The circuit layer 12 is disposed on the insulating layer 11. The circuit layer 12 has pixel circuits (various circuits and wiring) that drive the display elements included in each of the subpixels SP1, SP2, and SP3 as described above. The circuit layer 12 is covered with the insulating layer 13.

[0026] The insulating layer 13 functions as a planarizing film that flattens unevenness caused by the circuit layer 12. Although not shown in Fig. 4, the insulating layer 13 is provided with a contact hole for connecting the lower electrode LE to the pixel circuit.

[0027] The lower electrodes LE (LE1, LE2, and LE3) are disposed on the insulating layer 13. The rib 5 is disposed on the insulating layer 13 and the lower electrodes LE. An end (part) of the lower electrode LE is covered by the rib 5.

[0028] The partition wall 6 has a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61 in the first direction X and the second direction Y. As a result, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 can be said to be an overhanging shape.

[0029] The organic layers OR (OR1, OR2, and OR3) and the upper electrodes UE (UE1, UE2, and UE3), together with the lower electrodes LE (LE1, LE2, and LE3), constitute a display element provided in the subpixel SP.

[0030] As shown in FIG. 4, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b spaced apart from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b spaced apart from each other. The first organic layer OR1a contacts the lower electrode LE1 through an opening AP1 (an opening in the rib 5 in the subpixel SP1) and covers a part of the rib 5. The second organic layer OR1b is located on the upper portion 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts a side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0031] As shown in FIG. 4, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b spaced apart from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b spaced apart from each other. The first organic layer OR2a contacts the lower electrode LE2 through an opening AP2 (an opening in the rib 5 in the subpixel SP2) and covers a part of the rib 5. The second organic layer OR2b is located on the upper portion 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts a side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0032] As shown in FIG. 4, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b spaced apart from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b spaced apart from each other. The first organic layer OR3a contacts the lower electrode LE3 through an opening AP3 (an opening in the rib 5 in the subpixel SP3) and covers a part of the rib 5. The second organic layer OR3b is located on the upper portion 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts a side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0033] In the example shown in FIG. 4, the subpixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 (optical path adjustment layers) for adjusting the optical properties of the light emitted from the light emitting layers of the organic layers OR1, OR2, and OR3.

[0034] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b spaced apart from each other. The first cap layer CP1a is located in the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0035] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b spaced apart from each other. The first cap layer CP2a is located in the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0036] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b spaced apart from each other. The first cap layer CP3a is located in the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0037] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers each component of the subpixel SP1, including the first cap layer CP1a, the partition wall 6, and the second cap layer CP1b. The sealing layer SE2 continuously covers each component of the subpixel SP2, including the first cap layer CP2a, the partition wall 6, and the second cap layer CP2b. The sealing layer SE3 continuously covers each component of the subpixel SP3, including the first cap layer CP3a, the partition wall 6, and the second cap layer CP3b.

[0038] 4, the second organic layer OR1b, the second upper electrode UE1b, the second cap layer CP1b, and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP2 are spaced apart from the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition 6 between the subpixels SP2 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer SE3 on the partition 6.

[0039] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15. The sealing layer 15 is further covered with a resin layer 16.

[0040] The insulating layer 13 and the resin layers 14 and 16 are made of an organic material. The rib 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are made of an inorganic material such as silicon nitride (SiNx).

[0041] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may be made of a conductive oxide such as ITO.

[0042] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE corresponds to an anode and the upper electrode UE corresponds to a cathode. When the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE corresponds to an anode and the lower electrode LE corresponds to a cathode.

[0043] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. For example, the organic layer OR has a structure in which a hole injection layer, a hole import layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order.

[0044] The cap layer CP (CP1, CP2, and CP3) is formed, for example, by a multilayer body of multiple transparent thin films. The multiple thin films may include a thin film formed of an inorganic material and a thin film formed of an organic material. Furthermore, these multiple thin films have different refractive indices. The material of the thin films constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. The cap layer CP may be omitted.

[0045] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to each of the lower electrodes LE (LE1, LE2, and LE3) through a pixel circuit included in each of the subpixels SP (SP1, SP2, and SP3).

[0046] When a potential difference is generated between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength region. When a potential difference is generated between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength region. When a potential difference is generated between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength region.

[0047] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of colors corresponding to the subpixels SP1, SP2, and SP3.

[0048] Fig. 5 is a schematic enlarged cross-sectional view of the partition wall 6. Elements other than the rib 5, the partition wall 6, the insulating layer 13, and the pair of lower electrodes LE are omitted in Fig. 5. The pair of lower electrodes LE corresponds to any one of the above-mentioned lower electrodes LE1, LE2, and LE3.

[0049] In the example shown in FIG. 5, the lower portion 61 of the partition wall 6 includes a barrier layer (bottom portion) 611 disposed on the rib 5, and a metal layer (shaft portion) 612 disposed on the barrier layer 611. The barrier layer 611 is formed of a material different from that of the metal layer 612, and is formed of a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN). The metal layer 612 is formed to be thicker than the barrier layer 611. The metal layer 612 may have a single-layer structure or a laminated structure of different metal materials. As an example, the metal layer 612 is formed of aluminum (Al), for example.

[0050] The upper portion (top portion) 62 is thinner than the lower portion 61. In the example shown in Fig. 5, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is made of, for example, titanium (Ti), and the second layer 622 is made of, for example, ITO.

[0051] 5, the width of the lower portion 61 decreases toward the upper portion 62. That is, side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the third direction Z. The upper portion 62 has an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b.

[0052] The protrusion amount D of the ends 62a and 62b from the side surfaces 61a and 61b (hereinafter referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. The protrusion amount D of the partition wall 6 in this embodiment corresponds to the distance in the width direction (first direction X or second direction Y) perpendicular to the third direction Z of the partition wall 6 between the lower ends (barrier layers 611) of the side surfaces 61a and 61b and the ends 62a and 62b.

[0053] 5, the side surface of the barrier layer 611 and the side surface of the metal layer 612 are aligned to form a flat surface without any steps, but for example, the side surface of the barrier layer 611 may be slightly recessed from the side surface of the metal layer 612 or may protrude from the side surface of the metal layer 612. Also, in FIG. 5, the side surfaces of the barrier layer 611 and the metal layer 612 (i.e., the side surfaces 61a and 61b of the lower portion 61) are inclined with respect to the third direction Z, but the side surfaces may be parallel to the third direction Z.

[0054] The structure of the partition walls 6 and the material of each portion of the partition walls 6 can be appropriately selected in consideration of, for example, the method of forming the partition walls 6, etc.

[0055] In this embodiment, the partitions 6 are formed so as to partition the sub-pixels SP in a plan view. The organic layer OR is formed by, for example, an anisotropic or directional vacuum deposition method. When an organic material for forming the organic layer OR is deposited over the entire substrate 10 with the partitions 6 arranged, the organic layer OR is hardly formed on the side surfaces of the partitions 6 because the partitions 6 have shapes as shown in Figures 4 and 5. This makes it possible to form an organic layer OR (display element) that is divided into sub-pixels SP by the partitions 6.

[0056] 6 to 8 are schematic cross-sectional views for explaining a display element formed by using the partition wall 6. Note that the base material 10, the insulating layer 11, and the circuit layer 12 are omitted in Figs. 6 to 8. Also, the subpixels SPα, SPβ, and SPγ shown in Figs. 6 to 8 correspond to any one of the subpixels SP1, SP2, and SP3.

[0057] First, in a state where the partition 6 is disposed as described above, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are sequentially formed by vapor deposition on the entire substrate 10 as shown in FIG. 6. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the subpixel SPα. The overhanging partition 6 divides the organic layer OR into a first organic layer ORa that contacts the lower electrode LE through the opening AP and a second organic layer ORb on the partition 6, the upper electrode UE into a first upper electrode UEa that covers the first organic layer ORa and a second upper electrode UEb that covers the second organic layer ORb, and the cap layer CP into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa is in contact with the lower portion 61 of the partition 6. The sealing layer SE continuously covers the first cap layer CPa, the second cap layer CPb, and the partition 6.

[0058] Next, as shown in Fig. 7, a resist R is formed on the sealing layer SE. The resist R covers the subpixel SPα. That is, the resist R is disposed directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located in the subpixel SPα. The resist R is also located directly above the portions of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the subpixel SPα and the subpixel SPβ that are closer to the subpixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0059] Furthermore, by etching using the resist R as a mask, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are removed in portions exposed from the resist R, as shown in Fig. 8. As a result, a display element including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa is formed in the subpixel SPα. Meanwhile, the lower electrode LE is exposed in the subpixels SPβ and SPγ. The above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0060] After the display element of the subpixel SPα is formed as described above, the resist R is removed, and the display elements of the subpixels SPβ and SPγ are formed in sequence in the same manner as the subpixel SPα.

[0061] By forming display elements of subpixels SP1, SP2 and SP3 as exemplified above for subpixels SPα, SPβ and SPγ, and then forming resin layer 14, sealing layer 15 and resin layer 16, the structure of the display device DSP shown in Figure 4 is realized.

[0062] Here, it is assumed that the display device DSP according to this embodiment is incorporated into an electronic device such as a smartphone together with a camera for use.

[0063] 9 is a plan view showing a part of an electronic device incorporating a display device DSP (display panel) according to this embodiment. As described above, in the display device DSP, the display area DA includes a plurality of pixels PX (sub-pixels SP1, SP2, and SP3) arranged in a matrix in the first direction X and the second direction Y. The display device DSP also has a display surface having the display area DA and a rear surface (hereinafter referred to as the rear surface of the display device DSP) facing the display surface. In an electronic device incorporating the display device DSP according to this embodiment, a camera 100 for capturing an image, for example, is disposed on the rear side of the display device DSP.

[0064] In this case, as shown in FIG. 9, in order to enlarge the display area DA in the electronic device (display device DSP) (to widen the range of the display area DA), it is possible to place the camera 100 in a position that overlaps with the display area DA (i.e., multiple pixels PX).

[0065] Here, the sub-pixels SP (SP1, SP2, and SP3) arranged in the display area DA include pixel circuits that drive display elements, and it is assumed that the pixel circuits are 7Tr1C pixel circuits consisting of, for example, seven transistors (Tr) and one storage capacitor (C). In this case, as shown in Fig. 10, the pixel circuit 200 is arranged in an area that occupies most of the sub-pixels SP1, SP2, and SP3 in a planar view, and the light transmittance of the area overlapping with the camera 100 (i.e., the area including the pixel PX) is reduced due to the influence of the pixel circuit 200, and there is a possibility that not enough light will be incident on the camera 100 (its imaging element) via the display device DSP.

[0066] In this case, for example, a configuration may be considered in which pixels PX are thinned out in the area overlapping with the camera 100. However, simply thinning out pixels PX may result in a decrease in the resolution of the area overlapping with the camera 100, which may result in a decrease in the display quality of the display device DSP.

[0067] Therefore, in this embodiment, in an area DA1 (hereinafter referred to as the first display area DA1) of the display area DA that does not overlap with the camera 100, a pixel circuit 200 (7Tr1C pixel circuit) as shown in FIG. 10 is arranged to drive the display element, whereas in an area DA2 (hereinafter referred to as the second display area DA2) of the display area DA that overlaps with the camera 100, a pixel circuit 210 (4Tr1C pixel circuit) composed of, for example, four transistors and one storage capacitor is arranged to drive the display element, as shown in FIG. 11.

[0068] In such a configuration, the pixel circuit 210 (4Tr1C pixel circuit) arranged in the second display area DA2 is simpler than the pixel circuit 200 (7Tr1C pixel circuit) arranged in the first display area DA1. Therefore, as shown in FIG. 11, in the second display area DA2, the area occupied by the pixel circuit 210 can be reduced, and a transmissive section 220 corresponding to an area with high light transmittance can be arranged.

[0069] 12 is a schematic cross-sectional view of the display device DSP taken along the line BB in FIG. 11. As shown in FIG. 12, in a region overlapping with the pixel circuit 210 (a region overlapping with an opening of the rib 5), a display element (lower electrode LE1, organic layer OR1, and upper electrode UE1), a cap layer CP1, and a sealing layer SE1 are arranged, but in the transmissive portion 220, the display element, the cap layer, and the sealing layer are not arranged in a region overlapping with the opening of the rib 5. In addition, in FIG. 12, a circuit layer 12 is arranged at a position overlapping with the transmissive portion 220, and although wiring connected to a subpixel SP arranged near the transmissive portion 220 may be arranged in the circuit layer 12, the pixel circuit 210 is not arranged. In addition, in the second display region DA2, the region overlapping with the pixel circuit 210 and the transmissive portion 220 are partitioned by the rib 5 and the partition wall 6, similarly to the subpixel SP.

[0070] According to such a transmission section 220, it is possible to realize high light transmittance without being affected by display elements or the like.

[0071] In the following, the pixel circuit 200 arranged in the first display area DA1 and the pixel circuit 210 arranged in the second display area DA2 in this embodiment will be described.

[0072] Fig. 13 shows an example of a circuit configuration of a pixel circuit 200 arranged in the first display area DA1. As shown in Fig. 13, the pixel circuit 200 is a 7Tr1C pixel circuit including seven transistors (hereinafter referred to as first to seventh transistors) Tr1 to Tr7 and one storage capacitor Cst.

[0073] In the following description, one of the source-drain terminals of each of the first to seventh transistors Tr1 to Tr7 shown in Fig. 13 is referred to as a first terminal, and the other is referred to as a second terminal. Also, one terminal of the storage capacitor Cst (a capacitive element realizing the storage capacitor Cst) shown in Fig. 13 is referred to as a first terminal, and the other terminal is referred to as a second terminal.

[0074] A first terminal of the first transistor Tr1 is connected to a first terminal of the second transistor Tr2 and a second terminal of the fifth transistor Tr5 via a node n3. The second terminal of the first transistor Tr1 is connected to a data signal line that supplies a data signal Data. The data signal Data corresponds to a signal (pixel signal) written to a pixel. The first transistor Tr1 is, for example, an n-channel transistor.

[0075] The second transistor Tr2 corresponds to a drive transistor (DRT) that supplies a current to the display element 20 included in the subpixel SP (i.e., the display element 20 driven by the pixel circuit 200). A first terminal of the second transistor Tr2 is connected to a first terminal of the first transistor Tr1 and a second terminal of the fifth transistor Tr5 via a node n3. A second terminal of the second transistor Tr2 is connected to a second terminal of the third transistor Tr3, a first terminal of the fourth transistor Tr4, and a first terminal of the seventh transistor Tr7 via a node n1. The second transistor Tr2 is, for example, an n-channel transistor.

[0076] A first terminal of the third transistor Tr3 is connected to the gate terminal of the second transistor Tr2 and the second terminal of the storage capacitor Cst via a node n2. A second terminal of the third transistor Tr3 is connected to the second terminal of the second transistor Tr2, the first terminal of the fourth transistor Tr4, and the first terminal of the seventh transistor Tr7 via a node n1. The third transistor Tr3 is, for example, an n-channel transistor.

[0077] A first terminal of the fourth transistor Tr4 is connected to a second terminal of the second transistor Tr2, a second terminal of the third transistor Tr3, and a first terminal of the seventh transistor Tr7 via a node n1. A second terminal of the fourth transistor Tr4 is connected to a power supply line that supplies a power supply voltage VDDEL. The fourth transistor Tr4 is, for example, a p-channel transistor.

[0078] A first terminal of the fifth transistor Tr5 is connected to the anode terminal of the display element 20. Also, the first terminal of the fifth transistor Tr5 is connected to a first terminal of the sixth transistor Tr6 and a first terminal of the storage capacitor Cts via a node n4. A second terminal of the fifth transistor Tr5 is connected to a first terminal of the first transistor Tr1 and a first terminal of the second transistor Tr2 via a node n3. The fifth transistor Tr5 is, for example, a p-channel transistor.

[0079] A first terminal of the sixth transistor Tr6 is connected to a first terminal of the fifth transistor Tr5, a first terminal of the storage capacitor Cst, and an anode terminal of the display element 20 via a node n4. A second terminal of the sixth transistor Tr6 is connected to a power supply line that supplies an initialization voltage Vini. The sixth transistor Tr6 is, for example, an n-channel transistor.

[0080] A first terminal of the seventh transistor Tr7 is connected to a second terminal of the second transistor Tr2, a second terminal of the third transistor Tr3, and a first terminal of the fourth transistor Tr4 via a node n1. A second terminal of the seventh transistor Tr7 is connected to a power supply line that supplies a power supply voltage VSH. The seventh transistor Tr7 is, for example, an n-channel transistor.

[0081] 13, the gate terminal of the first transistor Tr1 is connected to a gate signal line that supplies a gate signal Scan2. The gate terminal of the third transistor Tr3 is connected to a gate signal line that supplies a gate signal Scan1. The gate terminals of the fourth to sixth transistors Tr4 to Tr6 are connected to a control signal line that supplies a control signal EM. The gate terminal of the seventh transistor Tr7 is connected to a gate signal line that supplies a gate signal Scan3.

[0082] A first terminal of the storage capacitor Cst is connected, via a node n4, to a first terminal of the fifth transistor Tr5, a first terminal of the sixth transistor Tr6, and an anode terminal of the display element 20. A second terminal of the storage capacitor Cst is connected, via a node n2, to a gate terminal of the second transistor Tr2 and a first terminal of the third transistor Tr3.

[0083] The anode terminal of the display element 20 is connected to a first terminal of the fifth transistor Tr5. The anode terminal of the display element 20 is also connected to a first terminal of the sixth transistor Tr6 and a first terminal of the storage capacitor Cst via a node n4. The cathode terminal of the display element 20 is connected to a power supply line that supplies a power supply voltage VSSEL. The above-mentioned power supply voltage VDDEL corresponds to the anode voltage supplied to the display element 20, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the display element 20.

[0084] Fig. 14 shows an example of a circuit configuration of a pixel circuit 210 arranged in the second display area DA2. As shown in Fig. 14, the pixel circuit 210 is a 4Tr1C pixel circuit including four transistors (hereinafter referred to as first to fourth transistors) Tr1 to Tr4 and one storage capacitor Cst.

[0085] In the following description, one of the source-drain terminals of each of the first to fourth transistors Tr1 to Tr4 shown in Fig. 14 is referred to as a first terminal, and the other is referred to as a second terminal. Also, one terminal of the storage capacitor Cst (a capacitive element realizing the storage capacitor Cst) shown in Fig. 14 is referred to as a first terminal, and the other terminal is referred to as a second terminal.

[0086] A first terminal of the first transistor Tr1 is connected to a gate terminal of the second transistor Tr2 and a second terminal of the storage capacitor Cst via a node n1. The second terminal of the first transistor Tr1 is connected to a data signal line that supplies a data signal Data. The first transistor Tr1 is, for example, an n-channel transistor.

[0087] The second transistor Tr2 corresponds to a drive transistor (DRT) that supplies a current to a display element 20 included in the subpixel SP (i.e., the display element 20 driven by the pixel circuit 210). A first terminal of the second transistor Tr2 is connected to a first terminal of the third transistor Tr3, a first terminal of the storage capacitor Cst, and an anode terminal of the display element 20 via a node n2. A second terminal of the second transistor Tr2 is connected to a first terminal of the fourth transistor Tr4. The second transistor Tr2 is, for example, an n-channel transistor.

[0088] A first terminal of the third transistor Tr3 is connected to a first terminal of the second transistor Tr2 and an anode terminal of the display element 20 via a node n2. The first terminal of the third transistor Tr3 is also connected to a first terminal of the storage capacitor Cst. The second terminal of the third transistor Tr3 is connected to a power supply line that supplies an initialization voltage Vini. The third transistor Tr3 is, for example, an n-channel transistor.

[0089] A first terminal of the fourth transistor Tr4 is connected to a second terminal of the second transistor Tr2. A second terminal of the fourth transistor Tr4 is connected to a power supply line that supplies a power supply voltage VDDEL. The fourth transistor Tr4 is, for example, a p-channel transistor.

[0090] 14, the gate terminal of the first transistor Tr1 and the gate terminal of the third transistor Tr3 are connected to a gate signal line that supplies a gate signal Scan1, and the gate terminal of the fourth transistor Tr4 is connected to a control signal line that supplies a control signal EM.

[0091] A first terminal of the storage capacitor Cst is connected to a first terminal of the second transistor Tr2 and an anode terminal of the display element 20 via a node n2. A first terminal of the storage capacitor Cst is connected to a first terminal of the third transistor Tr3. A second terminal of the storage capacitor Cst is connected to a first terminal of the first transistor Tr1 and a gate terminal of the second transistor Tr2 via a node n1.

[0092] An anode terminal of the display element 20 is connected to a first terminal of the second transistor Tr2, a first terminal of the third transistor Tr3, and a first terminal of the storage capacitor Cst via a node n2. A cathode terminal of the display element 20 is connected to a power supply line that supplies a power supply voltage VSSEL.

[0093] As described above, the display device DSP of this embodiment comprises a substrate 10, a plurality of sub-pixels SP (first pixels) arranged in a first display area DA1 included in a display area DA on the substrate 10, and a plurality of sub-pixels SP (second pixels) arranged in a second display area DA2 included in the display area DA, and the number of transistors constituting the pixel circuit 210 (second pixel circuit) included in the sub-pixels SP arranged in the second display area DA2 is smaller than the number of transistors constituting the pixel circuit 200 (first pixel circuit) included in the sub-pixels SP arranged in the first display area DA1.

[0094] In this embodiment, the first display area DA1 is an area arranged in a position that does not overlap with the camera 100, and the second display area DA2 is an area arranged in a position that overlaps with the camera 100.

[0095] In this embodiment, with the above-mentioned configuration, the area occupied by the pixel circuit 210 per unit area of ​​the second display area DA2 can be made smaller than the area occupied by the pixel circuit 200 per unit area of ​​the first display area DA1, thereby improving the light transmittance in the second display area DA2.

[0096] Specifically, in the second display area DA2, a transmissive portion 220 can be disposed, which corresponds to an area overlapping the opening AP of the rib 5 and in which the pixel circuit 210, the display element (the lower electrode LE, the light-emitting layer OR, and the upper electrode UE), the cap layer CP, and the sealing layer SE are not formed. Since high light transmittance can be achieved in such a transmissive portion 220, the light transmittance in the second display area DA2 can be improved.

[0097] Furthermore, in this embodiment, since there is no need to thin out the pixels PX (sub-pixels SP1, SP2, and SP3), the resolution in the second display area DA2 does not decrease.

[0098] 15 is a diagram showing a schematic arrangement of various wirings connected to the pixel circuits 200 arranged in the first display area DA1 and the pixel circuits 210 arranged in the second display area DA2. Note that in FIG. 15, only data signal lines that supply data signals Data, gate signal lines that supply gate signals Scan1 to Scan3, control signal lines that supply control signals EM, and power supply lines that supply an initialization voltage Vini are shown.

[0099] 15, data signal lines supplying data signals Data are arranged side by side in the first direction X so as to extend in the second direction Y. Furthermore, gate signal lines supplying gate signals Scan1 to Scan3, control signal lines supplying control signals EM, and power supply lines supplying initialization voltages Vini are arranged side by side in the second direction Y so as to extend in the first direction X.

[0100] In this embodiment, the transmissive portion 220 is arranged in the second display area DA2 as described above, but if a large number of wirings are formed in the transmissive portion 220 (the circuit layer 12 therein), it is conceivable that the light transmittance in the transmissive portion 220 will decrease.

[0101] In contrast, for example, in pixel circuit 200 shown in FIG. 13 and pixel circuit 210 shown in FIG. 14, the gate signal line that supplies gate signal Scan1, the control signal line that supplies control signal EM, and the power supply line that supplies initialization voltage Vini are common to pixel circuits 200 and 210, so that only the gate signal lines that supply gate signals Scan2 and Scan3 need to be formed (placed) in transmissive portion 220, and it is possible to prevent the light transmittance in transmissive portion 220 from decreasing due to the influence of the wiring connected to pixel circuit 200.

[0102] In other words, in this embodiment, by implementing pixel circuits 200 and 210 so that some of the multiple wirings connected to pixel circuit 200 are connected to pixel circuit 210 (i.e., more signals are available that can be used in common), it is possible to further improve the light transmittance in the second display area DA2.

[0103] Hereinafter, the operations of the pixel circuit 200 (7Tr1C pixel circuit) shown in FIG. 13 and the pixel circuit 210 (4Tr1C pixel circuit) shown in FIG. 14 described in this embodiment will be briefly described.

[0104] The multiple transistors constituting the pixel circuits 200 and 210 include n-channel transistors and p-channel transistors, and the n-channel transistor is a switching element that is turned off (non-conductive) when a low (level) signal is supplied to its gate terminal and turned on (conductive) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switching element that is turned off (non-conductive) when a high (level) signal is supplied to its gate terminal and turned on (conductive) when a low (level) signal is supplied to the gate terminal.

[0105] First, the operation of the pixel circuit 200 shown in Fig. 13 will be described with reference to Fig. 16. Fig. 16 is a timing chart showing an example of output of gate signals Scan1 to Scan3 and control signals EM to the pixel circuits 200 (sub-pixels SP arranged in the first display area DA1) arranged in rows n-1 and n shown in Fig. 15. Here, the operation of the pixel circuit 200 arranged in row n-1 will be described.

[0106] During a period t0 shown in FIG. 16, since the control signal EM is low, the fourth transistor Tr4 and the fifth transistor Tr5 of the seven transistors included in the pixel circuit 200 are in an on state, and the sixth transistor Tr6 is in an off state.

[0107] During the period t0, the gate signals Scan1 to Scan3 are low, so that the first transistor Tr1, the third transistor Tr3 and the seventh transistor Tr7 are in the off state.

[0108] This maintains a state in which a current controlled by the gate voltage of the second transistor Tr2 (a voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED).

[0109] At the end of the period t0, the control signal EM is switched from low to high.

[0110] 16, since the control signal EM is high, the fourth transistor Tr4 and the fifth transistor Tr5 are in an off state, and the sixth transistor Tr6 is in an on state. In this case, the initialization voltage Vini is supplied to the node n4 via the sixth transistor Tr6, but since the initialization voltage Vini is set to a value that does not cause a current to flow through the display element 20, no current flows through the display element 20 during the period t1.

[0111] Furthermore, at the timing when the period t1 starts, the gate signal Scan1 is switched from low to high. Therefore, during the period t1, the third transistor Tr3 is in the ON state. Furthermore, after the period t0 ends and before the period t1 starts, the gate signal Scan3 is switched from low to high. Therefore, during the period t1, the seventh transistor Tr7 is in the ON state. As a result, the power supply voltage VSH is supplied to the gate terminal of the second transistor Tr2 via the seventh transistor Tr7 and the third transistor Tr3. In this case, the voltage VSH-Vini is applied to the storage capacitance Cst (between the first and second terminals), and the information of the previous frame is reset.

[0112] At the end of the period t1, the gate signal Scan3 is switched from high to low.

[0113] 16, the gate signal Scan2 is switched from low to high at the start of the period t2. Therefore, the first transistor Tr1 is turned on during the period t2. Also, since the gate signal Scan3 is low during the period t2, the seventh transistor Tr7 is turned off.

[0114] In this case, the gate terminal of the second transistor Tr2 is supplied with the data signal Data (corresponding voltage Vdata) and the threshold voltage Vth of the second transistor Tr2 (i.e., a voltage equivalent to Vdata+Vth) via the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3. As a result, a voltage of Vdata+Vth-Vini is applied to the storage capacitance Cst, and information regarding Vdata and Vth is written to the storage capacitance Cst.

[0115] At the end of the period t2, the gate signal Scan1 is switched from high to low.

[0116] Next, in the period t3 shown in FIG. 16, the gate signal Scan1 is low, so the third transistor Tr3 is in the off state. Also, the gate signal Scan2 is switched from high to low before the period t3 starts, so the first transistor Tr1 is in the off state. Furthermore, the control signal EM is switched from high to low at the timing when the period t3 starts. Therefore, the fourth transistor Tr4 and the fifth transistor Tr5 are in the on state, and the sixth transistor Tr6 is in the off state.

[0117] Here, if the first terminal of the second transistor Tr2 is the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n2 to node n3) of the second transistor Tr2 becomes the voltage (Vdata+Vth-Vini) of the storage capacitor Cst. In this case, the second transistor Tr2 is turned on, and a current flows from the power line (power line supplying the power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n4. As a result, the potential of the node n4 starts to rise, and when the potential exceeds the threshold value of the display element 20 (OLED), a current starts to flow to the display element 20, and the display element 20 starts to emit light. Finally, when the current Ioled flowing through the display element 20 reaches the output current Idrt provided by the second transistor Tr2 (the output current in the saturation region of the second transistor Tr2), the potential rise of the node n4 stops, and the display element 20 enters a steady light-emitting state.

[0118] Here, the voltage Vgs=Vdata+Vth-Vini between the gate terminal and the source terminal of the second transistor Tr2 is expressed by the TFT saturation formula Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 Substituting into, Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini) 2 Here, Cox is the gate capacitance per unit area, μ is the carrier mobility, W is the channel width of the second transistor Tr2, and L is the channel length of the second transistor Tr2.

[0119] This means that Idrt becomes a value that is independent of the threshold voltage Vth of the second transistor Tr2 (i.e., a current that is independent of the threshold voltage Vth of the second transistor Tr2 flows through the display element 20), and it can be seen that the effect of variations in the threshold voltage Vth on Idrt can be eliminated.

[0120] 13 (7Tr1C pixel circuit) has a function of correcting the variation in the threshold voltage Vth of the second transistor Tr2 (hereinafter, referred to as a Vth correction function). This Vth correction function is mainly realized by the first transistor Tr1 and the seventh transistor Tr7.

[0121] Note that, although the operation of the pixel circuit 200 arranged in row n-1 shown in FIG. 16 has been described here, the operation of the pixel circuit 200 arranged in row n is similar, so a detailed description thereof will be omitted here.

[0122] Next, the operation of the pixel circuit 210 shown in Fig. 14 will be described with reference to Fig. 17. Fig. 17 is a timing chart showing an example of output of the gate signal Scan1 and the control signal EM to the pixel circuit 210 (sub-pixel SP arranged in the second display area DA2) arranged in the n-1th row shown in Fig. 15.

[0123] 17, since the control signal EM is low, the fourth transistor Tr4 of the four transistors included in the pixel circuit 210 is in an on state. Also, since the gate signal Scan1 is low during the period t10, the first transistor Tr1 and the third transistor Tr3 are in an off state.

[0124] This maintains a state in which a current controlled by the gate voltage of the second transistor Tr2 (a voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED).

[0125] At the end of the period t10, the control signal EM is switched from low to high.

[0126] 17, the control signal EM is high, and therefore the fourth transistor Tr4 is in the off state. In this case, the current flowing through the display element 20 becomes zero.

[0127] Furthermore, at the start of the period t11, the gate signal Scan1 is switched from low to high, so that the first transistor Tr1 and the third transistor Tr3 are turned on during the period t11.

[0128] In this case, an initialization voltage Vini is supplied to node n2 via the third transistor Tr3, but since the initialization voltage Vini is set to a value that does not cause current to flow through the display element 20, no current flows through the display element 20 during period t11.

[0129] Furthermore, a data signal Data (corresponding voltage Vdata) is supplied to the node n1 from the data signal line via the first transistor Tr1. As a result, a voltage of Vdata-Vini is applied to the storage capacitance Cst, and information about Vdata is written to the storage capacitance Cst.

[0130] At the end of the period t11, the gate signal Scan1 is switched from high to low.

[0131] 17, the gate signal Scan1 is low, so that the first transistor Tr1 and the third transistor Tr3 are off. At the start of the period t12, the control signal EM is switched from high to low. As a result, the fourth transistor Tr4 is turned on.

[0132] Here, if the first terminal of the second transistor Tr2 is the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n1 to node n2) of the second transistor Tr2 becomes the voltage (Vdata-Vini) of the storage capacitor Cst. In this case, the second transistor Tr2 is turned on, and a current flows from a power line (power line supplying a power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n2. As a result, the potential of the node n2 starts to rise, and when the potential exceeds the threshold value of the display element 20 (OLED), a current starts to flow to the display element 20, and the display element 20 starts to emit light. Finally, when the current Ioled flowing through the display element 20 reaches the output current Idrt provided by the second transistor Tr2, the potential rise of the node n2 stops, and the display element 20 enters a steady light-emitting state.

[0133] Here, the voltage Vgs=Vdata-Vini between the gate terminal and the source terminal of the second transistor Tr2 is expressed by the TFT saturation formula Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 Substituting this, Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini-Vth) 2 It becomes.

[0134] This shows that Idrt has a value that depends on the threshold voltage Vth of the second transistor Tr2 (i.e., a current that depends on the threshold voltage Vth of the second transistor Tr2 flows through the display element 20), and that variations in the threshold voltage Vth affect Idrt.

[0135] That is, it can be said that the pixel circuit 210 (4Tr1C pixel circuit) shown in FIG. 14 does not have the above-mentioned Vth correction function, unlike the pixel circuit 200 shown in FIG.

[0136] In addition, even if the pixel circuit 200 and the pixel circuit 210 have the same data signal Data (Vdata), there is a difference in Idrt (Ioled) depending on the presence or absence of a Vth correction function, so that a luminance difference may occur between the first display area DA1 and the second display area DA2. In this case, for example, the data signal Data (Vdata signal) may be biased and corrected to eliminate the luminance difference occurring between the first display area DA1 and the second display area DA2.

[0137] 16 and 17, the pixel circuits 200 and 210 are driven by the gate signal Scan1 and the control signal EM output (supplied) at the same timing from the shared gate signal line and the control signal line. In this embodiment, by adopting a combination of the pixel circuits 200 and 210 that share some of the multiple wirings and can be driven by signals supplied at the same timing, it is possible to reduce the number of wirings arranged in the transmissive portion 220 and improve the light transmittance in the second display area DA2.

[0138] In this embodiment, the pixel circuit 200 arranged in the first display area DA1 is the 7Tr1C pixel circuit shown in Fig. 13, and the pixel circuit 210 arranged in the second display area DA2 is the 4Tr1C pixel circuit shown in Fig. 14. However, in this embodiment, in order to improve the light transmittance in the second display area DA2, it is sufficient that the pixel circuits 200 and 210 are configured such that the area occupied by the pixel circuit 210 per unit area is smaller than the area occupied by the pixel circuit 200. Specifically, it is sufficient that the pixel circuit 210 is configured with a smaller number of transistors than the pixel circuit 200, and the pixel circuits 200 and 210 are not limited to the circuit configurations shown in Figs. 13 and 14.

[0139] Hereinafter, a description will be given of other examples of the circuit configuration of the pixel circuits 200 and 210. Although the case where the driving transistor is an n-channel transistor has been described in the above-mentioned Fig. 13 and Fig. 14, a description will be given here of the case where the driving transistor is a p-channel transistor.

[0140] Fig. 18 shows another example of the circuit configuration of the pixel circuit 200 arranged in the first display area DA1. As shown in Fig. 18, the pixel circuit 200 is a 7Tr1C pixel circuit including seven transistors (hereinafter referred to as first to seventh transistors) and one storage capacitor Cst.

[0141] In the following description, one of the source-drain terminals of each of the first to seventh transistors Tr1 to Tr7 shown in Fig. 18 is referred to as a first terminal, and the other is referred to as a second terminal. In addition, one terminal of the storage capacitor Cst (a capacitive element realizing the storage capacitor Cst) shown in Fig. 18 is referred to as a first terminal, and the other terminal is referred to as a second terminal.

[0142] A first terminal of the first transistor Tr1 is connected to a second terminal of the second transistor Tr2 and a second terminal of the fourth transistor Tr3 via a node n1. A second terminal of the first transistor Tr1 is connected to a data signal line that supplies a data signal Data. The first transistor Tr1 is, for example, a p-channel transistor.

[0143] The second transistor Tr2 corresponds to a drive transistor (DRT) that supplies a current to the display element 20 included in the subpixel SP (i.e., the display element 20 driven by the pixel circuit 200). A first terminal of the second transistor Tr2 is connected to a second terminal of the third transistor Tr3 and a second terminal of the fifth transistor Tr5 via a node n3. A second terminal of the second transistor Tr2 is connected to a first terminal of the first transistor Tr1 and a second terminal of the fourth transistor Tr4 via a node n1. The second transistor Tr2 is, for example, a p-channel transistor.

[0144] A first terminal of the third transistor Tr3 is connected to the gate terminal of the second transistor Tr2, a first terminal of the seventh transistor Tr7, and a second terminal of the storage capacitor Cst via a node n2. A second terminal of the third transistor Tr3 is connected to the first terminal of the second transistor Tr2 and the second terminal of the fifth transistor Tr5 via a node n3. The third transistor Tr3 is, for example, a p-channel transistor.

[0145] A first terminal of the fourth transistor Tr4 is connected to a first terminal of the first transistor Tr1 and a second terminal of the second transistor Tr2 via a node n1. A second terminal of the fourth transistor Tr4 is connected to a first terminal of the storage capacitor Cst. In addition, a second terminal of the fourth transistor Tr4 is connected to a power supply line that supplies a power supply voltage VDDEL. The fourth transistor Tr4 is, for example, a p-channel transistor.

[0146] A first terminal of the fifth transistor Tr5 is connected to a first terminal of the sixth transistor Tr6 and an anode terminal of the display element 20 via a node n4. A second terminal of the fifth transistor Tr5 is connected to a first terminal of the second transistor Tr2 and a second terminal of the third transistor Tr3 via a node n3. The fifth transistor Tr5 is, for example, a p-channel transistor.

[0147] A first terminal of the sixth transistor Tr6 is connected to a first terminal of the fifth transistor Tr5 and an anode terminal of the display element 20 via a node n4. A second terminal of the sixth transistor Tr6 is connected to a second terminal of the seventh transistor Tr7. In addition, the second terminal of the sixth transistor Tr6 is connected to a power supply line that supplies a reset voltage Vrst. The sixth transistor Tr6 is, for example, a p-channel transistor.

[0148] A first terminal of the seventh transistor Tr7 is connected to the gate terminal of the second transistor Tr2 and the first terminal of the third transistor Tr3 via the node n2. The first terminal of the seventh transistor Tr7 is connected to the second terminal of the storage capacitor Cst. The second terminal of the seventh transistor Tr7 is connected to the second terminal of the sixth transistor Tr6. The second terminal of the seventh transistor Tr7 is connected to a power supply line that supplies a reset voltage Vrst. The seventh transistor Tr7 is, for example, a p-channel transistor.

[0149] 18, the gate terminals of the first transistor Tr1, the third transistor Tr3, and the sixth transistor Tr6 are connected to a gate signal line that supplies a gate signal Scan2. The gate terminals of the fourth transistor Tr4 and the fifth transistor Tr5 are connected to a control signal line that supplies a control signal EM. The gate terminal of the seventh transistor Tr7 is connected to a gate signal line that supplies a gate signal Scan1.

[0150] A first terminal of the storage capacitor Cst is connected to a second terminal of the fourth transistor Tr4. The first terminal of the storage capacitor Cst is connected to a power supply line that supplies a power supply voltage VDDEL. The second terminal of the storage capacitor Cst is connected to a gate terminal of the second transistor Tr2 and a first terminal of the third transistor Tr3 via a node n2. The second terminal of the storage capacitor Cst is connected to a first terminal of the seventh transistor Tr7.

[0151] The anode terminal of the display element 20 is connected to a first terminal of the fifth transistor Tr5 and a first terminal of the sixth transistor Tr6 via a node n4. The cathode terminal of the display element 20 is connected to a power supply line that supplies a power supply voltage VSSEL. The above-mentioned power supply voltage VDDEL corresponds to the anode voltage supplied to the display element 20, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the display element 20.

[0152] Fig. 19 shows another example of the circuit configuration of the pixel circuit 210 arranged in the second display area DA2. As shown in Fig. 19, the pixel circuit 210 is a 2Tr1C pixel circuit including two transistors (hereinafter referred to as first and second transistors) Tr1 and Tr2 and one storage capacitor Cst.

[0153] In the following description, one of the source-drain terminals of each of the first and second transistors Tr1 and Tr2 shown in Fig. 19 is referred to as a first terminal, and the other is referred to as a second terminal. Also, one terminal of the storage capacitor Cst (a capacitive element realizing the storage capacitor Cst) shown in Fig. 19 is referred to as a first terminal, and the other terminal is referred to as a second terminal.

[0154] A first terminal of the first transistor Tr1 is connected to a gate terminal of the second transistor Tr2 and a second terminal of the storage capacitor Cst via a node n1. The second terminal of the first transistor Tr1 is connected to a data signal line that supplies a data signal Data. The first transistor Tr1 is, for example, a p-channel transistor.

[0155] The second transistor Tr2 corresponds to a drive transistor (DRT) that supplies a current to a display element 20 included in the subpixel SP (i.e., the display element 20 driven by the pixel circuit 210). A first terminal of the second transistor Tr2 is connected to an anode terminal of the display element 20. A second terminal of the second transistor Tr2 is connected to a first terminal of the storage capacitor Cst. In addition, the second terminal of the second transistor Tr2 is connected to a power supply line that supplies a power supply voltage VDDEL. The second transistor Tr2 is, for example, a p-channel transistor.

[0156] As shown in FIG. 19, the gate terminal of the first transistor Tr1 is connected to a gate signal line that supplies a gate signal Scan2.

[0157] A first terminal of the storage capacitor Cst is connected to a second terminal of the second transistor Tr2. The first terminal of the storage capacitor Cst is also connected to a power supply line that supplies a power supply voltage VDDEL. A second terminal of the storage capacitor Cst is connected to a first terminal of the first transistor Tr1 and a gate terminal of the second transistor Tr2 via a node n1.

[0158] An anode terminal of the display element 20 is connected to a first terminal of the second transistor Tr2, and a cathode terminal of the display element 20 is connected to a power supply line that supplies a power supply voltage VSSEL.

[0159] According to the circuit configurations shown in Figures 18 and 19 described above, the number of transistors constituting the pixel circuit 210 arranged in the second display area DA2 can be made smaller than the number of transistors constituting the pixel circuit 200 arranged in the first display area DA1, and the transmissive section 220 can be arranged in the second display area DA2, thereby improving the light transmittance in the second display area DA2.

[0160] In addition, when the pixel circuit 200 shown in FIG. 18 is arranged in the first display area DA1, and the pixel circuit 210 shown in FIG. 19 is arranged in the second display area DA2, the gate signal line that supplies the gate signal Scan2 can be shared by the pixel circuits 200 and 210, as shown in FIG. 20.

[0161] Hereinafter, the operations of the pixel circuit 200 (7Tr1C pixel circuit) shown in FIG. 18 and the pixel circuit 210 (2Tr1C pixel circuit) shown in FIG. 19 will be briefly described.

[0162] First, the operation of the pixel circuit 200 shown in Fig. 18 will be described with reference to Fig. 21. Fig. 21 is a timing chart showing an example of output of gate signals Scan1, Scan2 and a control signal EM to the pixel circuit 200 (sub-pixel SP arranged in the first display region DA1) arranged in row n-1 shown in Fig. 20.

[0163] During a period t20 shown in FIG. 21, since the control signal EM is low, the fourth transistor Tr4 and the fifth transistor Tr5 of the seven transistors included in the pixel circuit 200 are in an on state.

[0164] During the period t20, the gate signals Scan1 and Scan2 are high, so that the first transistor Tr1, the third transistor Tr3, the sixth transistor Tr6 and the seventh transistor Tr7 are in the off state.

[0165] This maintains a state in which a current controlled by the gate voltage of the second transistor Tr2 (a voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED).

[0166] At the end of the period t20, the control signal EM is switched from low to high.

[0167] 21, since the control signal EM is high, the fourth transistor Tr4 and the fifth transistor Tr5 are in the off state, so that the current flowing through the display element 20 becomes zero.

[0168] At the start of the period t21, the gate signal Scan1 is switched from high to low, so that the seventh transistor Tr7 is turned on during the period t21.

[0169] In this case, the reset voltage Vrst is supplied to the gate terminal of the second transistor Tr2 via the seventh transistor Tr7, and the voltage Vrst-VDDEL is applied to the storage capacitor Cst, resetting the information of the previous frame.

[0170] At the end of the period t21, the gate signal Scan1 is switched from low to high.

[0171] 21, the gate signal Scan1 is high, so that the seventh transistor Tr7 is off. At the start of the period t22, the gate signal Scan2 is switched from high to low. As a result, the first transistor Tr1, the third transistor Tr3, and the sixth transistor Tr6 are turned on.

[0172] In this case, the data signal Data (corresponding voltage Vdata) and the threshold voltage Vth (i.e., a voltage equivalent to Vdata+Vth) of the second transistor Tr2 are supplied to the gate terminal of the second transistor Tr2 via the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3. As a result, a voltage of Vdata+Vth-VDDEL is applied to the storage capacitance Cst, and information regarding Vdata and Vth is written to the storage capacitance Cst.

[0173] Furthermore, a reset voltage Vrst is supplied to node n4 (the anode terminal of the display element 20) via a sixth transistor Tr6, thereby resetting the anode.

[0174] At the end of the period t22, the gate signal Scan2 is switched from low to high.

[0175] Next, in a period t23 shown in Fig. 21, the gate signal Scan2 is high, so that the first transistor Tr1, the third transistor Tr3, and the sixth transistor Tr6 are in an off state. Also, at the timing when the period t23 starts, the control signal EM is switched from high to low. Therefore, the fourth transistor Tr4 and the fifth transistor Tr5 are in an on state.

[0176] Here, if the second terminal of the second transistor Tr2 is the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n1 to node n2) of the second transistor Tr2 becomes the voltage (Vdata+Vth-VDDEL) of the storage capacitor Cst. In this case, the second transistor Tr2 is turned on, and a current flows from the power line (power line supplying the power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n4. As a result, the potential of the node n4 starts to rise, and when the potential exceeds the threshold value of the display element 20 (OLED), a current starts to flow to the display element 20, and the display element 20 starts to emit light. Finally, when the current Ioled flowing through the display element 20 reaches the output current Idrt provided by the second transistor Tr2 (the output current in the saturation region of the second transistor Tr2), the potential rise of the node n4 stops, and the display element 20 enters a steady light-emitting state.

[0177] Here, the voltage Vgs between the gate terminal and the source terminal of the second transistor Tr2 is expressed as Vdata+Vth-VDDEL, which is the TFT saturation formula Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth). 2 Substituting this, Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-VDDEL) 2 It becomes.

[0178] This means that Idrt becomes a value that is independent of the threshold voltage Vth of the second transistor Tr2 (i.e., a current that is independent of the threshold voltage Vth of the second transistor Tr2 flows through the display element 20), and it can be seen that the effect of variations in the threshold voltage Vth on Idrt can be eliminated.

[0179] That is, it can be said that the pixel circuit 200 (7Tr1C pixel circuit) shown in FIG. 18 has a function of correcting the variation in the threshold voltage Vth of the second transistor Tr2 (Vth correction function).

[0180] Next, the operation of the pixel circuit 210 shown in Fig. 19 will be described with reference to Fig. 22. Fig. 22 is a timing chart showing an example of output of the gate signal Scan2 to the pixel circuit 210 (sub-pixel SP arranged in the second display area DA2) arranged in the n-1th row shown in Fig. 20.

[0181] During a period t30 shown in FIG. 22, since the gate signal Scan2 is high, the first transistor Tr1 of the two transistors included in the pixel circuit 210 is in an off state.

[0182] This maintains a state in which a current controlled by the gate voltage of the second transistor Tr2 (a voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED).

[0183] Next, the gate signal Scan2 is switched from high to low at the start of a period t31 shown in Fig. 22. As a result, the first transistor Tr1 is turned on during the period t31.

[0184] In this case, the node n1 is supplied with a data signal Data (corresponding voltage Vdata) from the data signal line via the first transistor Tr1. As a result, if the second terminal of the second transistor Tr2 is the source terminal, a voltage of Vdata-VDDEL is applied to the storage capacitor Cst (between the gate terminal and source terminal of the second transistor Tr2), and information about Vdata is written to the storage capacitor Cst.

[0185] At the end of the period t31, the gate signal Scan1 is switched from low to high.

[0186] Next, in a period t32 shown in FIG. 22, the gate signal Scan2 is high, and therefore the first transistor Tr1 is in an off state. In this case, the voltage Vgs between the gate terminal and the source terminal of the second transistor Tr2 becomes the voltage (Vdata-VDDEL) of the storage capacitor Cst. In this case, the second transistor Tr2 is turned on, and a current flows from a power supply line (power supply line that supplies the power supply voltage VDDEL) connected to the second terminal (source terminal) of the second transistor Tr2 toward the anode terminal of the display element 20. Accordingly, the potential of the node between the first terminal (drain terminal) of the second transistor Tr2 and the anode terminal of the display element 20 starts to rise, and when the potential exceeds the threshold value of the display element 20 (OLED), a current starts to flow through the display element 20, and the display element 20 starts to emit light. Finally, when the current Ioled flowing through the display element 20 reaches the output current Idrt provided by the second transistor Tr2, the potential rise at the node between the first terminal (drain terminal) of the second transistor Tr2 and the anode terminal of the display element 20 stops, and the display element 20 enters a steady light-emitting state.

[0187] Here, the voltage Vgs between the gate terminal and the source terminal of the second transistor Tr2 = Vdata-VDDEL is expressed by the TFT saturation formula Idrt = 1 / 2Cox * μ * W / L * (Vgs-Vth) 2 Substituting this, Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-VDDEL-Vth) 2 It becomes.

[0188] This shows that Idrt has a value that depends on the threshold voltage Vth of the second transistor Tr2 (i.e., a current that depends on the threshold voltage Vth of the second transistor Tr2 flows through the display element 20), and that variations in the threshold voltage Vth affect Idrt.

[0189] That is, it can be said that the pixel circuit 210 (2Tr1C pixel circuit) shown in FIG. 19 does not have the above-mentioned Vth correction function, unlike the pixel circuit 200 shown in FIG.

[0190] 21 and 22, the pixel circuits 200 and 210 are driven by the gate signal Scan2 output (supplied) at the same timing from a shared gate signal line. This means that even with the combination of the pixel circuit 200 shown in Fig. 18 and the pixel circuit 210 shown in Fig. 19, it is possible to improve the light transmittance in the second display area DA2.

[0191] In this embodiment, it is assumed that the camera 100 (the imaging element of the camera 100) is disposed on the back of the display device DSP, but this embodiment can be applied to a case where a sensor including a light receiving element that converts incident light into an electrical signal or a device including the sensor is disposed on the back of the display device DSP. In other words, the DSP according to this embodiment only needs to be configured to improve the light transmittance in a predetermined area of ​​the display area DA, and is not limited to being disposed on the back of the display device DSP.

[0192] All display devices that can be implemented by those skilled in the art through appropriate design modifications based on the display devices described above as the embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0193] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0194] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0195] DSP...display device, DA...display area, DA1...first display area, DA2...second display area, NDA...non-display area, PX...pixel, SP, SP1, SP2, SP3...sub-pixel, AP, AP1, AP2, AP3...opening, LE, LE1, LE2, LE3...lower electrode, UE, UE1, UE2, UE3...upper electrode, OR, OR1, OR2, OR3...organic layer, SE, SE1, SE2, SE3...sealing layer, Tr1 to Tr7...transistor, Cst...storage capacitance, 5...rib, 6...partition, 10...substrate, 11...insulating layer, 12...circuit layer, 13...insulating layer, 14...resin layer, 15...sealing layer, 16...resin layer, 20...display element, 61...lower part, 62...upper part, 200, 210...pixel circuit.

Claims

1. A substrate; A plurality of first pixels arranged in a first region included in a display region on the substrate; a plurality of second pixels arranged in a second region different from a first region included in the display region; Equipped with Each of the first pixels includes a first pixel circuit including a plurality of transistors and a first display element driven by the first pixel circuit; Each of the second pixels includes a second pixel circuit including a plurality of transistors and a second display element driven by the second pixel circuit; The number of transistors constituting the second pixel circuit is smaller than the number of transistors constituting the first pixel circuit. Display device.

2. The display device according to claim 1 , wherein the second region is disposed at a position overlapping a light receiving element that receives light through the display device.

3. the first pixel circuit includes a transistor for achieving a function of correcting a variation in a threshold voltage of a drive transistor that supplies a current to the first display element, among a plurality of transistors constituting the first pixel circuit; The second pixel circuit does not include a transistor for realizing a function of correcting a variation in a threshold voltage of a drive transistor that supplies a current to the second display element, among a plurality of transistors constituting the second pixel circuit. The display device according to claim 1.

4. The display device according to claim 1 , wherein a part of a plurality of wirings connected to the first pixel circuit is connected to the second pixel circuit.

5. 2 . The display device according to claim 1 , wherein an area of ​​the region occupied by the second pixel circuit per unit area of ​​the second region is smaller than an area of ​​the region occupied by the first pixel circuit per unit area of ​​the first region.

6. Ribs and Bulkhead and Further comprising: The first and second display elements each include a lower electrode, an organic layer, and an upper electrode; the lower electrode is disposed on the substrate; the rib has an opening overlapping the lower electrode, The partition has a lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion, the organic layer is in contact with the lower electrode through the opening; The upper electrode is disposed over the organic layer. The display device according to claim 1.

7. a cap layer disposed on the upper electrode; a sealing layer disposed on the cap layer; The display device according to claim 6 , further comprising:

8. The display device according to claim 7 , wherein the second region includes an area overlapping an opening of the rib, and in which the second pixel circuit, the second display element, the cap layer, and the sealing layer are not formed.

9. A substrate; A plurality of first pixels arranged in a first region included in a display region on the substrate; a plurality of second pixels arranged in a second region different from a first region included in the display region; Equipped with Each of the plurality of first pixels includes a first display element and a first pixel circuit that drives the first display element; Each of the second pixels includes a second display element and a second pixel circuit that drives the second display element; The area of ​​the region occupied by the second pixel circuit per unit area of ​​the second region is smaller than the area of ​​the region occupied by the first pixel circuit per unit area of ​​the first region. Display device.

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