Circuit device, electro-optical device and electronic apparatus

Abstract

To provide a circuit device, etc., capable of shortening the time required for a voltage, with which an amplifier circuit drives a capacitive load, to be settled to a target voltage.SOLUTION: A circuit device 100 includes an amplifier circuit 150 and a voltage output circuit 110. An output terminal of the amplifier circuit 150 is connected to an inverted input terminal. The amplifier circuit 150 outputs a drive voltage VQ to a capacitive load 1. The voltage output circuit 110 outputs an output voltage VAI corresponding to a D / A conversion voltage of input data DI to a non-inverted input terminal of the amplifier circuit 150. When the drive voltage VQ overshoots the D / A conversion voltage by changing the input data DI in a positive direction, the voltage output circuit 110 makes the output voltage VAI into a voltage higher than the D / A conversion voltage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device, an electro-optical device, an electronic device, and the like. [Background technology]

[0002] Patent Document 1 discloses a display driver that performs assist driving of an output line of a D / A conversion circuit. The display driver includes a D / A conversion circuit, an assist circuit, and an amplifier circuit. The assist circuit has a capacitor group and a drive circuit that outputs a drive signal group to one end of a plurality of capacitors included in the capacitor group. The amplifier circuit outputs a signal to an electro-optical panel based on a voltage applied to the output line. Before the D / A conversion circuit applies a drive voltage based on a video signal, the assist circuit initializes a potential applied to the output line of the D / A conversion circuit, and applies a voltage close to the video signal to the output line by capacitive driving. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-33095 Summary of the Invention [Problem to be solved by the invention]

[0004] The amplifier circuit controls the output voltage of the output node based on feedback from the output node. Therefore, the amplifier circuit tries to lower the output voltage when the output voltage becomes higher than the target voltage, and tries to raise the output voltage when the output voltage becomes lower than the target voltage. This causes a problem that ringing occurs in the output voltage, and it takes a long time for the output voltage to converge to the target voltage. When the amplifier circuit drives a capacitive load, the ringing prevents charge transfer to the capacitance before the capacitance of the capacitive load is charged to the target voltage, and it takes a long time for the output voltage to converge to the target voltage. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device that includes an amplifier circuit having an output terminal connected to an inverting input terminal and outputting a drive voltage to a capacitive load, and a voltage output circuit that outputs an output voltage corresponding to a D / A conversion voltage of input data to a non-inverting input terminal of the amplifier circuit, wherein the voltage output circuit makes the output voltage higher than the D / A conversion voltage when the input data changes in the positive direction and the drive voltage overshoots the D / A conversion voltage.

[0006] Another aspect of the present disclosure relates to an electro-optical device including the above-mentioned circuit device and an electro-optical panel.

[0007] Yet another aspect of the present disclosure relates to an electronic device including the above circuit device. [Brief description of the drawings]

[0008] [Figure 1] 1 shows a first configuration example of a circuit device. [Diagram 2] 6 shows an example of a signal waveform when overdriving according to the present embodiment is not performed. [Diagram 3] 4 shows an example of a signal waveform in the present embodiment. [Figure 4] 2 shows a second configuration example of a circuit device. [Diagram 5] 13 is a detailed configuration example of an amplifier circuit in the second configuration example of the circuit device. [Figure 6] 6 shows example signal waveforms in a second configuration example of the circuit device. [Figure 7] 11 is a flow chart showing a process flow performed by an arithmetic circuit in a second configuration example of the circuit device. [Figure 8] 6A and 6B show timing charts and details of calculations performed by a calculation circuit in a second configuration example of the circuit device. [Figure 9] FIG. 4 is a diagram for explaining overdrive timing. [Figure 10] 3 shows a third configuration example of a circuit device. [Figure 11] 13 shows an example of signal waveforms in a third example configuration of a circuit device. [Figure 12]13 is a flow chart showing a process flow performed by an arithmetic circuit in a third configuration example of a circuit device. [Figure 13] 13A and 13B show timing charts and details of calculations performed by a calculation circuit in a third configuration example of the circuit device. [Figure 14] 4 shows a fourth configuration example of a circuit device. [Figure 15] 1 shows an example of the configuration of an electro-optical device. [Figure 16] 13 is a detailed configuration example of a circuit device as a driver. [Figure 17] Example of electronic device configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0010] 1. First configuration example 1 shows a first configuration example of a circuit device. The circuit device 100 includes a voltage output circuit 110 and an amplifier circuit 150. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0011] The circuit device 100 drives a capacitive load 1 connected to an output node NVQ. The capacitive load 1 includes a resistor RP and a capacitor CP connected in series between the output node NVQ and a ground node or the like. The resistor RP is a parasitic resistance of a wiring, or a resistor or the like as a circuit element. The capacitor CP is a parasitic capacitance of a wiring, or a capacitor or the like as a circuit element. The capacitive load 1 may be either inside or outside the circuit device 100. As an example, the circuit device 100 is a driver that drives a data line of an electro-optical panel. For example, the input resistance of the electro-optical panel corresponds to the resistor RP, and the parasitic capacitance of the data line and the pixel capacitance correspond to the capacitance CP.

[0012] The amplifier circuit 150 is an operational amplifier configured as a voltage follower circuit. That is, the inverting input terminal of the amplifier circuit 150 is connected to the output terminal, the output terminal is connected to the output node NVQ, and the non-inverting input terminal is connected to the output node NVAI of the voltage output circuit 110.

[0013] The voltage output circuit 110 outputs an output voltage VAI corresponding to a D / A converted voltage of the input data DI to an output node NVAI. The voltage output circuit 110 basically performs D / A conversion on the input data DI and outputs the result as the output voltage VAI, but temporarily overdrives the output voltage VAI at a given timing.

[0014] The operation of the circuit device 100 will be described below using examples of signal waveforms. First, for comparison, an example of signal waveforms when the overdrive of this embodiment is not performed will be described using Fig. 2. As shown in Fig. 2, the value of the input data DI changes at time ta. Here, an example is shown in which the input data DI changes in a direction that increases the output voltage VAI of the voltage output circuit 110.

[0015] The output voltage VAI of the voltage output circuit 110 starts to change from time ta and gradually approaches the target voltage corresponding to the input data DI. The amplifier circuit 150 increases the drive voltage VQ in response to the increase in the output voltage VAI of the voltage output circuit 110. The amplifier circuit 150 changes the output in response to the voltage difference of the differential input, so that the drive voltage VQ increases slightly after the increase in the output voltage VAI of the voltage output circuit 110. When the output voltage VAI of the voltage output circuit 110 approaches the target voltage and the increase becomes gentle, the drive voltage VQ exceeds the output voltage VAI of the voltage output circuit 110 and overshoots. When the voltage difference of the differential input becomes greater than a certain level due to the overshoot, the drive voltage VQ is lowered in response. As a result, the drive voltage VQ falls below the output voltage VAI of the voltage output circuit 110 and undershoots. Such repeated overshooting and undershooting is called ringing, and the ringing converges and the drive voltage VQ converges to the target voltage.

[0016] The driving voltage VQ charges the capacitance CP via the resistance RP of the capacitive load 1. As a result, as the driving voltage VQ converges to the target voltage, the voltage VP of the capacitance CP also converges to the target voltage. The speed of this convergence is usually about the time constant determined by the resistance RP and the capacitance CP. One method for speeding up the convergence time of the voltage VP is to temporarily make the driving voltage VQ higher than the target voltage, thereby accelerating the charging of the capacitance CP. Ringing overshoot can accelerate the charging of the capacitance CP, but undershoot acts in a direction that hinders the charging of the capacitance CP, lowering the voltage VP of the capacitance CP. In other words, ringing slows down the convergence to the target voltage.

[0017] 3 is an example of a signal waveform in this embodiment. The voltage output circuit 110 overdrives the output voltage VAI at time tb after time ta. That is, the voltage output circuit 110 makes the output voltage VAI higher than the D / A converted voltage of the input data DI at time tb. Time tb is when the drive voltage VQ first overshoots. Time tb may be any time within the overshoot period from immediately after the drive voltage VQ first overshoots to immediately before it first turns to undershoot in FIG. 2. As an example, time tb is near the peak of the first overshoot, but is not limited to this.

[0018] After overdriving the output voltage VAI at time tb, the voltage output circuit 110 returns the output voltage VAI to the D / A converted voltage of the input data DI. This return may be done in various ways, such as gradually or stepwise. The interval between times ta and tb can be set arbitrarily. For example, it is set in a register or non-volatile memory (not shown). The interval between times ta and tb may be determined in advance by circuit simulation, sample evaluation, or the like.

[0019] According to this embodiment, when the drive voltage VQ overshoots, the voltage output circuit 110 temporarily overdrives the output voltage VAI, thereby reducing the voltage difference of the differential inputs of the amplifier circuit 150. This makes it possible to eliminate or reduce the undershoot that occurs after the overshoot. The overshoot of the drive voltage VQ accelerates the charging of the capacitance CP of the capacitive load 1, and the subsequent undershoot does not interfere with the charging, or the charging is prevented or reduced, so that the capacitive load 1 can be driven at high speed.

[0020] When the input data DI changes in a direction that decreases the output voltage VAI of the voltage output circuit 110, the drive voltage VQ first undershoots. At this time, overdriving means making the output voltage VAI lower than the D / A conversion voltage of the input data DI. That is, the voltage output circuit 110 makes the output voltage VAI lower than the D / A conversion voltage of the input data DI at time tb, and then returns the output voltage VAI to the D / A conversion voltage of the input data DI.

[0021] In this embodiment, the circuit device 100 includes an amplifier circuit 150 and a voltage output circuit 110. An output terminal of the amplifier circuit 150 is connected to an inverting input terminal. The amplifier circuit 150 outputs a drive voltage VQ to a capacitive load 1. The voltage output circuit 110 outputs an output voltage VAI corresponding to a D / A conversion voltage of input data DI to a non-inverting input terminal of the amplifier circuit 150. When the input data DI changes in the positive direction, causing the drive voltage VQ to overshoot the D / A conversion voltage, the voltage output circuit 110 makes the output voltage VAI a voltage higher than the D / A conversion voltage.

[0022] According to this embodiment, when the drive voltage VQ overshoots the D / A converted voltage of the input data DI, the voltage output circuit 110 can temporarily overdrive the output voltage VAI in a direction to increase it. This reduces the voltage difference of the differential inputs of the amplifier circuit 150, so that the undershoot after the overshoot can be eliminated or reduced. When the input data DI changes in the positive direction, the charging of the capacitive load 1 is hindered if an undershoot occurs, but according to this embodiment, the undershoot is eliminated or reduced, so that the capacitive load 1 can be driven at high speed.

[0023] Furthermore, in this embodiment, the voltage output circuit 110 makes the output voltage VAI a voltage higher than the D / A conversion voltage, and then returns it to the D / A conversion voltage.

[0024] According to this embodiment, the output voltage VAI input to the non-inverting input terminal of the amplifier circuit 150 is overdriven and then returns to the D / A converted voltage of the input data DI. This causes the drive voltage VQ to converge to a target voltage corresponding to the input data DI.

[0025] Furthermore, in this embodiment, the voltage output circuit 110 changes the output voltage VAI with a delay from the timing at which the input data DI changes.

[0026] 2 and 3, when the input data DI changes, the output voltage VAI starts to change, and when the change in the output voltage VAI becomes gentler, the drive voltage VQ exceeds the output voltage VAI and overshoots. By changing the output voltage VAI with a delay from the timing of the change in the input data DI, the voltage output circuit 110 can overdrive the output voltage VAI when the drive voltage VQ overshoots.

[0027] Furthermore, in this embodiment, when the input data DI changes in the negative direction and the drive voltage VQ undershoots the D / A conversion voltage, the voltage output circuit 110 sets the output voltage VAI to a voltage lower than the D / A conversion voltage.

[0028] According to this embodiment, when the drive voltage VQ undershoots the D / A converted voltage of the input data DI, the voltage output circuit 110 can temporarily overdrive the output voltage VAI in a direction lowering it. This reduces the voltage difference of the differential inputs of the amplifier circuit 150, so that the overshoot after the undershoot can be eliminated or reduced. When the input data DI changes in the negative direction, the overshoot of the drive voltage VQ prevents the charging of the capacitive load 1, but according to this embodiment, the overshoot is eliminated or reduced, so that the capacitive load 1 can be driven at high speed.

[0029] 2. Second configuration example Fig. 4 shows a second configuration example of a circuit device. The circuit device 100 includes a voltage output circuit 110 and an amplifier circuit 150. The following mainly describes the parts that differ from Fig. 1.

[0030] The voltage output circuit 110 includes a D / A conversion circuit 120, an overdrive circuit 140, a resistor 131, and a capacitor 132. The voltage output circuit 110 has a first output node NVAI1 and a second output node NVAI2, which correspond to the output node NVAI in FIG.

[0031] The D / A conversion circuit 120 performs D / A conversion on the input data DI and outputs the result as a D / A conversion voltage VAI1 to a first output node NVAI1. The D / A conversion circuit 120 includes, for example, a ladder resistor circuit that generates a plurality of voltages corresponding to each value of the input data DI, and a selection circuit that selects a voltage corresponding to the input data DI from the plurality of voltages. The voltage selected by the selection circuit is output as the D / A conversion voltage VAI1. However, the configuration of the D / A conversion circuit 120 is not limited to this.

[0032] One end of the resistor 131 is connected to the first output node NVAI1, and the other end is connected to the second output node NVAI2. One end of the capacitor 132 is connected to the second output node NVAI2, and the other end is connected to the first node NV. Input data DI is input to the overdrive circuit 140, and the output of the overdrive circuit 140 is connected to the first node NV.

[0033] The amplifier circuit 150 has a first non-inverting input terminal indicated by "+1" and a second non-inverting input terminal indicated by "+2." The first non-inverting input terminal is connected to the first output node NVAI1, and the second non-inverting input terminal is connected to the second output node NVAI2. By using such two non-inverting input terminals, the input voltage of the non-inverting side of the amplifier circuit 150 becomes a voltage between the D / A converted voltage VAI1 of the first output node NVAI1 and the voltage VAI2 of the second output node NVAI2.

[0034] The overdrive circuit 140 changes the voltage VAI2 of the second output node NVAI2 by driving the first node NV based on the difference between the current input data DI and the previous input data DI. The previous input data DI is the input data DI immediately before the current input data DI among the input data DI input in time series. By the overdrive circuit 140 driving the first node NV, the input voltage of the non-inverting side of the amplifier circuit 150 changes from the D / A conversion voltage VAI1, that is, the input voltage of the non-inverting side of the amplifier circuit 150 is overdriven.

[0035] The overdrive circuit 140 includes overdrive capacitors CV1 to CV5, an overdrive drive circuit 141, and an arithmetic circuit 142. The number of overdrive capacitors is not limited to 5 and may be m, where m is an integer of 2 or more.

[0036] The arithmetic circuit 142 obtains overdrive data DV[4:0] from the input data DI. Specifically, the arithmetic circuit 142 obtains overdrive data DV[4:0] based on the difference between the current input data DI and the previous input data DI. The number of bits of the overdrive data is not limited to 5 and may be m.

[0037] One end of the overdrive capacitor CVq is connected to the first node NV. q=1, 2, . . . , 5. The capacitance value is CVq=CV1×2 (q-1)The overdrive driving circuit 141 outputs the overdrive voltage VVq to the other end of the overdrive capacitor CVq based on the bit DV[q-1]. When DV[q-1] is at a low level, VVq is a low-potential power supply voltage, and when DV[q-1] is at a high level, VVq is a high-potential power supply voltage. The overdrive driving circuit 141 includes, for example, a buffer circuit that buffers the bit DV[q-1] and outputs it as the overdrive voltage VVq. The overdrive driving circuit 141 changes the overdrive voltages VV1 to VV5 based on the overdrive data DV[4:0], so that charges are supplied from the overdrive capacitors CV1 to CV5 to the first node NV, or charges are discharged from the first node NV to the overdrive capacitors CV1 to CV5. This changes the voltage VAI2 of the second output node NVAI2.

[0038] 5 is a detailed configuration example of an amplifier circuit in the second configuration example of the circuit device. The amplifier circuit 150 includes P-type transistors TP1 to TP3 and N-type transistors TN1 to TN5. Note that (+1) indicates a first non-inverting input terminal, (+2) indicates a second non-inverting input terminal, (-) indicates an inverting input terminal, and (OUT) indicates an output terminal. VDD indicates a high potential side power supply voltage, and VSS indicates a low potential side power supply voltage.

[0039] P-type transistors TP1 and TP2 form a current mirror circuit and serve as the load for the differential pair. N-type transistors TN1 and TN2 are the transistors on the non-inverting input side of the differential pair, and N-type transistor TN3 is the transistor on the inverting input side of the differential pair. The gate of N-type transistor TN1 is connected to the first non-inverting input terminal, and the gate of N-type transistor TN2 is connected to the second non-inverting input terminal. N-type transistor TN4 is the current source for the differential pair, and a bias voltage VREF is input to its gate. P-type transistor TP3 is the transistor in the output stage, and the output voltage of the differential pair is input to its gate. N-type transistor TN5 is the current source for the output stage, and a bias voltage VREF is input to its gate.

[0040] FIG. 6 shows an example of signal waveforms in the second configuration example of the circuit device. The arithmetic circuit 142 changes the value of the overdrive data DV[4:0] at time tb after the drive voltage VQ first overshoots. As a result, the voltage VAI2 becomes higher than the D / A conversion voltage VAI1. The voltage VAI2 at this time is also called an overdrive voltage. Since the second output node NVAI2 is connected to the first output node NVAI1 via the resistor 131, the voltage VAI2 gradually decreases and converges to the D / A conversion voltage VAI1. The time constant at which the overdrive converges is determined by the resistance value of the resistor 131, the capacitance value of the capacitor 132, and the capacitance values ​​of the overdrive capacitors CV1 to CV5. By setting this time constant to be approximately the same as the time constant of the capacitive load 1, the time at which the drive voltage VQ, which has become higher than the target voltage, decreases to the target voltage and the time at which the overdrive converges to the target voltage can be approximately the same. This makes it possible to eliminate or reduce undershoot in the drive voltage VQ, and to speed up the drive time of the capacitive load 1.

[0041] When the input data DI changes in a direction in which the D / A conversion voltage VAI1 decreases, the drive voltage VQ first undershoots. At this time, the arithmetic circuit 142 changes the value of the overdrive data DV[4:0] so that the voltage VAI2 becomes lower than the D / A conversion voltage VAI1 at time tb.

[0042] 7 is a flow chart of a process performed by the arithmetic circuit in the second configuration example of the circuit device. In step S1, the arithmetic circuit 142 acquires input data DI. In step S2, the arithmetic circuit 142 acquires the previous input data DI stored in a memory, a register, or the like. In step S3, the arithmetic circuit 142 calculates the difference between the input data DI acquired in step S1 and the previous input data DI acquired in step S2.

[0043] In step S4, a calculation coefficient is obtained by referring to a calculation coefficient lookup table based on the difference. The calculation coefficient lookup table is a table that outputs a calculation coefficient for an input difference. The calculation coefficient lookup table is stored in, for example, a memory or a register, and may be externally settable via an interface circuit (not shown). A constant calculation coefficient may be used regardless of the difference. In step S5, the calculation circuit 142 multiplies the difference by the calculation coefficient. When the calculation coefficient is, for example, 1 / 2, the difference may be divided by 2 to substantially realize the multiplication of the calculation coefficient.

[0044] In step S6, the arithmetic circuit 142 acquires the previous overdrive data DV[4:0] stored in a memory or a register. In step S7, the arithmetic circuit 142 obtains the current overdrive data DV[4:0] by adding the multiplication result of step S5 to the previous overdrive data DV[4:0]. If the difference is negative, the multiplication result of step S5 is negative. At this time, the addition of the multiplication result may be substantially realized by subtracting the absolute value of the multiplication result from the previous overdrive data DV[4:0]. In step S8, the arithmetic circuit 142 outputs the overdrive data DV[4:0] obtained in step S7.

[0045] 8 shows the contents and timing chart of the calculation performed by the calculation circuit in the second configuration example of the circuit device. DATA0, DATA1, and DATA2 are input in time series to the calculation circuit 142 as input data DI. Here, the initial value of the overdrive data DV[4:0] is set to 0, but the initial value is not limited to 0.

[0046] When DATA1 is input, the arithmetic circuit 142 calculates DV[4:0]=(DATA1-DATA0)×α. (DATA1-DATA0) is the difference between the current input data DI and the previous input data. α is an arithmetic coefficient obtained from the arithmetic coefficient lookup table. Let (DATA1-DATA0)×α=OF1. The arithmetic circuit 142 changes the overdrive data DV[4:0] with a delay from the timing when the input data DI changes from DATA0 to DATA1.

[0047] When DATA2 is input, the calculation circuit 142 calculates DV[4:0]=OF1+(DATA2-DATA1)×α. OF1 is the previous overdrive data DV[4:0]. (DATA2-DATA1) is the difference between the current input data DI and the previous input data. α is the calculation coefficient acquired from the calculation coefficient lookup table. Similar calculations are performed thereafter. The calculation circuit 142 changes the overdrive data DV[4:0] with a delay from the timing when the input data DI changes from DATA1 to DATA2. At this time, the change timing of DV[4:0] when (DATA2-DATA1) is large is later than the change timing of DV[4:0] when (DATA2-DATA1) is small.

[0048] Fig. 9 is a diagram for explaining the timing of overdrive, showing an example of a signal waveform when the difference between the previous input data DI and the current input data is changed.

[0049] Line LA indicates the timing at which the drive voltage VQ overshoots the D / A conversion voltage VAI1. As shown by line LA, the greater the difference in the input data DI, the later the timing of the overshoot. For this reason, the arithmetic circuit 142 delays the timing of the overdrive as the difference in the input data DI increases. Specifically, the times at which the overdrive data DV[4:0] is changed when the difference in the input data DI is a first value to a fourth value are set to tb1, tb2, tb3, and tb4. When the first value<second value<third value<fourth value, tb1 <tb2<tb3<tb4である。

[0050] For example, the arithmetic circuit 142 determines the time tb by referring to a timing setting lookup table. The timing setting lookup table is a table that receives the difference between the previous input data DI and the current input data and outputs the time tb. The timing setting lookup table is stored in, for example, a memory or a register, and may be externally set via an interface circuit (not shown).

[0051] In this embodiment, the voltage output circuit 110 changes the time from the timing of change in the input data DI to the timing of change in the output voltage VAI, depending on the difference between the previous input data DI and the current input data DI.

[0052] 8 and 9, the greater the difference between the previous input data DI and the current input data DI, the later the timing at which the drive voltage VQ overshoots the D / A converted voltage of the input data DI. According to this embodiment, the voltage output circuit 110 changes the change timing of the output voltage VAI in accordance with the difference, thereby making it possible to overdrive the output voltage VAI when the drive voltage VQ overshoots.

[0053] In this embodiment, the amplifier circuit 150 has a first non-inverting input terminal and a second non-inverting input terminal as the non-inverting input terminal. The voltage output circuit 110 includes a D / A conversion circuit 120, a resistor 131, a capacitor 132, and an overdrive circuit 140. The D / A conversion circuit 120 performs D / A conversion on the input data DI and outputs a D / A conversion voltage VAI1 to the first non-inverting input terminal. The resistor 131 is provided between an output node NVAI1 of the D / A conversion circuit 120 and the second non-inverting input terminal. The capacitor 132 is provided between the second non-inverting input terminal and the first node NV. The overdrive circuit 140 drives the first node NV based on the input data DI to set the voltage of the second non-inverting input terminal to an overdrive voltage higher than the D / A conversion voltage VAI1.

[0054] According to this embodiment, the overdrive circuit 140 drives the first node NV based on the input data DI, thereby changing the voltage VAI2 of the second non-inverting input terminal of the amplifier circuit 150 via the capacitor 132. As a result, the voltage on the non-inverting input side of the amplifier circuit 150 is overdriven. Since the resistor 131 is provided between the output node NVAI1 and the second non-inverting input terminal of the D / A conversion circuit 120, the overdriven voltage VAI2 of the second non-inverting input terminal gradually returns to the D / A conversion voltage of the input data DI.

[0055] In this embodiment, the overdrive circuit 140 includes an arithmetic circuit 142, first to m-th overdrive capacitors CV1 to CVm, and an overdrive drive circuit 141. The arithmetic circuit 142 calculates overdrive data DV[4:0] corresponding to the overdrive voltage based on the input data DI. One ends of the first to m-th overdrive capacitors CV1 to CVm are connected to a first node NV. The overdrive drive circuit 141 drives the other ends of the first to m-th overdrive capacitors CV1 to CVm based on the overdrive data DV[4:0].

[0056] According to this embodiment, the overdrive driving circuit 141 drives the other ends of the first to m-th overdrive capacitors CV1 to CVm, thereby changing the voltage VAI2 of the second non-inverting input terminal of the amplifier circuit 150 via the first to m-th overdrive capacitors CV1 to CVm and the capacitor 132. This causes the voltage of the non-inverting input side of the amplifier circuit 150 to be overdriven. Also, the arithmetic circuit 142 calculates the overdrive data DV[4:0], thereby making it possible to change the overdrive voltage.

[0057] Moreover, in this embodiment, the arithmetic circuit 142 multiplies the difference between the previous input data DI and the current input data DI by a coefficient, and outputs the overdrive data DV[4:0] using the result of the multiplication.

[0058] According to this embodiment, the overdrive data DV[4:0] is calculated according to the difference between the previous input data DI and the current input data DI, so that the voltage output circuit 110 can output an overdrive voltage according to the difference.

[0059] Furthermore, in this embodiment, the arithmetic circuit 142 multiplies the difference by a coefficient that varies depending on the difference.

[0060] According to this embodiment, the arithmetic circuit 142 multiplies the difference by a coefficient that varies depending on the difference, thereby making it possible to generate an appropriate overdrive voltage for the overshoot of the drive voltage VQ.

[0061] 3.Third configuration example 10 shows a third configuration example of a circuit device. The circuit device 100 includes a voltage output circuit 110 and an amplifier circuit 150. Below, differences from Fig. 1 will be mainly described. The voltage output circuit 110 includes a D / A conversion circuit 180 and an arithmetic circuit 170.

[0062] The arithmetic circuit 170 outputs output data DQ based on the input data DI. The arithmetic circuit 170 basically outputs the output data DQ of the same value as the input data DI, but changes the output data DQ from the input data DI at a given timing. After that, the arithmetic circuit 170 returns the output data DQ to the input data DI. For example, the arithmetic circuit 170 returns the output data DQ to the input data DI stepwise, gradually, or directly.

[0063] The D / A conversion circuit 180 performs D / A conversion on the output data DQ and outputs the result as an output voltage VAI to an output node NVAI. The D / A conversion circuit 180 includes, for example, a ladder resistor circuit that generates a plurality of voltages corresponding to each value of the output data DQ, and a selection circuit that selects a voltage corresponding to the output data DQ from the plurality of voltages. The voltage selected by the selection circuit is output as the output voltage VAI. However, the configuration of the D / A conversion circuit 180 is not limited to this.

[0064] 11 shows an example of signal waveforms in the third configuration example of the circuit device. An example in which the arithmetic circuit 170 changes the output data DQ stepwise will be described below.

[0065] The arithmetic circuit 170 outputs output data DQ having the same value as the input data DI from time ta to time tb. Time b is the time after the drive voltage VQ first overshoots. The arithmetic circuit 170 changes the output data DQ to a value larger than the input data DI at time tb. This output data DQ is also called the first output data. As a result, the output voltage VAI of the D / A conversion circuit 180 becomes higher than the D / A conversion voltage of the input data DI. The arithmetic circuit 170 gradually lowers the output data DQ at times tc and td after time tb. This output data DQ is also called the second output data and the third output data. The arithmetic circuit 170 makes the output data DQ the same value as the input data DI at time te after time td. As a result, the output voltage VAI of the D / A conversion circuit 180 returns to the D / A conversion voltage of the input data DI. By setting the time from when the output voltage VAI rises until it returns to the D / A converted voltage of the input data DI to approximately the same as the time constant of the capacitive load 1, the time it takes for the drive voltage VQ, which has become higher than the target voltage, to fall to the target voltage and the time it takes for the overdrive to converge to the target voltage can be made approximately the same. This makes it possible to eliminate or reduce undershoot in the drive voltage VQ, and to speed up the drive time of the capacitive load 1.

[0066] When the input data DI changes in a direction that decreases the D / A conversion voltage of the input data DI, the drive voltage VQ first undershoots. At this time, the arithmetic circuit 170 changes the output data DQ to a value smaller than the input data DI at time tb. After that, the arithmetic circuit 170 gradually increases the output data DQ to the input data DI.

[0067] 12 is a flow of processing performed by the arithmetic circuit in the third configuration example of the circuit device. In step S21, the arithmetic circuit 170 acquires input data DI. In step S22, the arithmetic circuit 170 acquires the previous input data DI held in a memory, a register, or the like. In step S23, the arithmetic circuit 170 calculates the difference between the input data DI acquired in step S21 and the previous input data DI acquired in step S22.

[0068] In step S24, a calculation coefficient is obtained by referring to a calculation coefficient lookup table based on the difference. The calculation coefficient lookup table is a table that outputs a calculation coefficient for an input difference. The calculation coefficient lookup table is stored in, for example, a memory or a register, and may be externally set via an interface circuit (not shown). Note that a constant value of the calculation coefficient may be used regardless of the difference.

[0069] In step S25, the arithmetic circuit 170 generates a shift timing for changing the value of the output data DQ. The shift timing corresponds to, for example, times tb, tc, td, and te in FIG. 11. In step S26, the arithmetic circuit 170 shifts the arithmetic coefficient at each shift timing. The arithmetic coefficient acquired in step S24 is set as β. As an example, the arithmetic circuit 170 performs calculations using β×1, β×1 / 2, and β×1 / 4 as coefficients at times tb, tc, and td. This corresponds to shifting β to the LSB side by one bit at a time. The arithmetic circuit 170 performs calculations using β×0 as a coefficient at time te. Note that the method for changing the coefficient is not limited to the above shift calculation, and it is sufficient if the coefficient is made smaller in stages.

[0070] In step S27, the arithmetic circuit 170 multiplies the difference obtained in step S23 by the coefficient obtained in step S26. Note that when the coefficient is, for example, 1 / 2, the multiplication by the coefficient may be substantially realized by dividing the difference by 2.

[0071] In step S28, the arithmetic circuit 170 obtains output data DQ by adding the multiplication result of step S27 to the input data DI obtained in step S21. If the difference is negative, the multiplication result of step S27 is negative. At this time, the addition of the multiplication result may be substantially realized by subtracting the absolute value of the multiplication result from the input data DI. In step S29, the arithmetic circuit 170 outputs the output data DQ obtained in step S28.

[0072] 13 is a timing chart and the contents of the calculation performed by the calculation circuit in the third configuration example of the circuit device. DATA0, DATA1, and DATA2 are input to the calculation circuit 170 in time series as input data DI.

[0073] When DATA1 is input to the arithmetic circuit 170, it outputs DATA1 as output data DQ. After that, the arithmetic circuit 170 outputs the output data DQ shown in (1), (2), and (3). The coefficient by which the difference (DATA1-DATA0) is multiplied is shifted to 0.125, 0.125 / 2=0.0625, and 0.125 / 4=0.0312. After that, the arithmetic circuit 170 sets the output data DQ to DATA1. The same applies when DATA2 is input to the arithmetic circuit 170, and the equations for the output data DQ are shown in (4), (5), and (6).

[0074] 8 and 9, the greater the difference in the input data DI, the later the timing of the overshoot. Therefore, the arithmetic circuit 170 delays the time tb at which the overdrive starts as the difference in the input data DI increases. Accordingly, the times tc, td, and te also become later.

[0075] In this embodiment, the voltage output circuit 110 includes an arithmetic circuit 170 and a D / A conversion circuit 180. The arithmetic circuit 170 calculates output data DQ based on input data DI. The D / A conversion circuit 180 outputs an output voltage VAI by D / A converting the output data DQ. The arithmetic circuit 170 changes the output data DQ from the input data DI to first output data for making the output voltage VAI a voltage higher than the D / A conversion voltage of the input data DI.

[0076] According to this embodiment, the arithmetic circuit 170 changes the output data DQ from the input data DI to the first output data, so that the output voltage VAI of the D / A conversion circuit 180 becomes a voltage higher than the D / A conversion voltage of the input data DI. As a result, the voltage VAI input to the non-inverting input terminal of the amplifier circuit 150 is overdriven.

[0077] Furthermore, in this embodiment, after changing the output data DQ to the first output data, the arithmetic circuit 170 returns the output data DQ to the input data DI.

[0078] According to this embodiment, the overdriven voltage VAI of the second non-inverting input terminal returns to the D / A converted voltage of the input data DI.

[0079] Moreover, in this embodiment, the arithmetic circuit 170 multiplies the difference between the previous input data DI and the current input data DI by a coefficient, and outputs the first output data using the result of the multiplication.

[0080] According to this embodiment, the first output data is calculated according to the difference between the previous input data DI and the current input data DI, so that the D / A conversion circuit 180 can output an overdrive voltage according to the difference.

[0081] Furthermore, in this embodiment, the arithmetic circuit 170 multiplies the difference by a coefficient that varies depending on the difference.

[0082] According to this embodiment, the arithmetic circuit 170 multiplies the difference by a coefficient that varies depending on the difference, thereby making it possible to generate an appropriate overdrive voltage for the overshoot of the drive voltage VQ.

[0083] 4. Fourth Configuration Example Fig. 14 shows a fourth configuration example of the circuit device. The circuit device 100 includes a voltage output circuit 110, an amplifier circuit 150, and a capacitance driving circuit 160. The same reference numerals are used for components already described, and the description of these components will be omitted. Fig. 14 shows an example in which the capacitance driving circuit 160 is added to the first configuration example of the circuit device 100, but the capacitance driving circuit 160 may be added to the second and third configuration examples.

[0084] The capacitive driving circuit 160 drives the capacitive load 1 by capacitive driving. The capacitive driving circuit 160 includes a capacitor circuit 10 and a capacitor driving circuit 20.

[0085] The capacitor circuit 10 includes first to n-th capacitors C1 to Cn. The capacitor driving circuit 20 includes first to n-th driving circuits DR1 to DRn. An example where n=11 will be described below, but n may be any integer equal to or greater than 2.

[0086] One end of the capacitor Ci is connected to the output node NVQ, and the other end is connected to the capacitor driving node NDRi. i is an integer equal to or greater than 1 and equal to or less than n=11. The capacitors C1 to C11 have binary-weighted capacitance values. Specifically, the capacitance value of the capacitor Ci is 2 (i-1) ×C1.

[0087] The number of bits of the input data is n=11, which is denoted as DI[10:0]. The i-th bit DI[i-1] of the input data DI[10:0] is input to the input node of the driving circuit DRi. The driving circuit DRi outputs a first voltage level to the capacitor driving node NDRi when the bit DI[i-1] is at a first logic level, and outputs a second voltage level to the capacitor driving node NDRi when the bit DI[i-1] is at a second logic level. For example, the first logic level is a low level, the second logic level is a high level, the first voltage level is a low potential side power supply voltage, and the second voltage level is a high potential side power supply voltage. The driving circuit DRi is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the driving circuit DRi, and a buffer circuit that buffers the output of the level shifter.

[0088] When the drive circuits DR1 to DR11 drive the capacitors C1 to C11, charge redistribution occurs between the capacitors C1 to C11 and the capacitance CP of the capacitive load 1. As a result, a drive voltage VQ corresponding to the input data DI[10:0] is output to the output node NVQ.

[0089] It is assumed that the sum of the capacitance values ​​of the capacitors C1 to C11 is Ctot = C1 + C2 + ··· + C11. As an example, it is assumed that the output amplitude of the amplifier circuit 150 is 10V and the high potential side power supply voltage is 15V. In this case, the capacitance values ​​of the capacitors C1 to C11 are set so that Ctot / CP = 2. The amplitude of the drive voltage VQ by capacitive driving is 15V × {Ctot / (Ctot + CP)} = 10V, and the amplitude of the capacitive driving and the output amplitude of the amplifier circuit 150 are the same.

[0090] By providing the capacitive driving circuit 160, it is possible to change the driving voltage VQ at high speed by charge redistribution, and to drive the capacitive load 1 at high speed. However, since the charge is supplied at a speed much faster than the time constant of the capacitive load 1, the ringing of the driving voltage VQ may become large, and the driving time of the capacitive load 1 may become long. Even in such a case, the driving time of the capacitive load 1 can be shortened by the voltage output circuit 110 overdriving the output voltage VAI at the first overshoot or first undershoot.

[0091] 5. Electro-optical devices An example in which the circuit device 100 is used as a driver for an electro-optical device will be described below. FIG. 15 shows an example of the configuration of an electro-optical device. An electro-optical device 400 includes the circuit device 100 and an electro-optical panel 200. An electro-optical device 400 using a demultiplex drive method will be described below as an example, but is not limited to this, and for example, the electro-optical device 400 may be using a phase expansion drive method. Also, an example in which the demultiplex number is 8 will be described below, but the demultiplex number may be p, where p is an integer equal to or greater than 2.

[0092] The circuit device 100 includes a control circuit 40, output circuits DD1 to DDk, output terminals TQ1 to TQk, and control signal output terminals SQ1 to SQ8, where k is an integer equal to or greater than 2. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0093] The electro-optical panel 200 includes input terminals TI1 to TIk, signal supply lines SL1 to SLk, demultiplexers DM1 to DMk, data lines DL11 to DL18, DL21 to DL28, ..., DLk1 to DLk8, and control signal input terminals SI1 to SI8. The electro-optical panel 200 is an active matrix type liquid crystal display panel, an EL display panel using self-luminous elements, or the like. EL is an abbreviation for Electro-Luminescence.

[0094] The control circuit 40 outputs grayscale data as input data to the output circuit DD1. The output circuit DD1 converts the grayscale data into a data voltage and outputs the data voltage to the output terminal TQ1. The output terminal TQ1 is connected to the input terminal TI1, and the input terminal TI1 is connected to a signal supply line SL1. The same applies to the output circuits DD2 to DDk, the output terminals TQ2 to TQk, the input terminals TI2 to TIk, and the signal supply lines SL2 to SLk.

[0095] The demultiplexer DM1 includes switches SW11 to SW18. Each switch is, for example, a TFT. TFT is an abbreviation for Thin Film Transistor. One end of the switch SW11 is connected to a signal supply line SL1, and the other end is connected to a data line DL11. The switch SW11 is controlled to be turned on or off by a control signal S1. Similarly, one end of the switches SW12 to SW18 is connected to a signal supply line SL1, and the other end is connected to data lines DL12 to DL18. The switches SW12 to SW18 are controlled to be turned on or off by control signals S2 to S8. The same is true for the demultiplexers DM2 to DMk, the switches SW21 to SW28, . . . , SWk1 to SWk8, and the data lines DL21 to DL28, . . . , DLk1 to DLk8. The number of switches and the number of data lines in each demultiplexer may be p, which is the same as the number of demultiplexes.

[0096] Although not shown in FIG. 15, the electro-optical panel 200 has a plurality of pixels arranged in a matrix. One data line and one scanning line are connected to one pixel. The scanning lines are selected by a scanning line driving circuit (not shown). The scanning line driving circuit may be included in the circuit device 100 or may be provided outside the circuit device 100.

[0097] Demultiplex driving will be explained using the output circuit DD1 as an example. In one horizontal scanning period, the switches SW11, SW12, ..., SW18 are sequentially turned on. When the switch SW11 is on, the output circuit DD1 writes a data voltage to the pixels connected to the data line DL11. Similarly, when the switches SW12, ..., SW18 are on, the output circuit DD1 writes a data voltage to the pixels connected to the data lines DL12, ..., DL1k.

[0098] Fig. 16 shows a detailed configuration example of a circuit device as a driver. Fig. 16 shows an output circuit DDj, which is any one of the output circuits DD1 to DDk, and a control circuit 40. j is an integer between 1 and k. The output circuit DDj includes a voltage output circuit 110, an amplifier circuit 150, and a capacitance driving circuit 160. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48. Note that, although an example in which the fourth configuration example of the circuit device is used as the output circuit DDj is shown here, the first to third configuration examples may be used as the output circuit DDj.

[0099] The interface circuit 44 performs interface processing between the circuit device 100 and the display controller 300 that controls the circuit device 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is, for example, an image interface circuit of the LVDS type, the parallel RGB type, or the display port type. LVDS is an abbreviation of Low Voltage Differential Signaling.

[0100] The processing circuit 42 outputs the input data DI[10:0] as grayscale data to the voltage output circuit 110 and the capacitive driving circuit 160 based on the grayscale data GD[9:0]. As an example, the common voltage is 7.5V, the voltage range of the positive polarity drive is 7.5V to 12.5V, and the voltage range of the negative polarity drive is 7.5V to 2.5V. In this case, DI[10:0]=000h corresponds to 2.5V, DI[10:0]=400h corresponds to 7.5V, and DI[10:0]=4FFh corresponds to 12.5V. In addition, when the polarity is not inverted, the grayscale data GD[9:0] may be output as it is to the voltage output circuit 110 and the capacitive driving circuit 160.

[0101] The register circuit 48 stores setting data that sets the time tb at which overdrive starts. For example, the display controller 300 writes the setting data to the register circuit 48 via the interface circuit 44. Alternatively, the circuit device 100 may include a non-volatile memory (not shown) that stores the setting data in advance, and the setting data may be loaded from the non-volatile memory to the register circuit 48. The processing circuit 42 controls the timing of overdrive by the voltage output circuit 110 based on the setting data read from the register circuit 48.

[0102] 17 shows an example of the configuration of an electronic device including a circuit device as a driver. As the electronic device of this embodiment, various electronic devices equipped with a display device can be assumed. For example, the electronic device is a projector, a television device, an information processing device, a portable information terminal, a car navigation system, a portable game terminal, or the like.

[0103] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a circuit device 100 and an electro-optical panel 200.

[0104] The user interface unit 330 is an interface unit that accepts various operations from a user. For example, it is composed of a button, a mouse, a keyboard, or a touch panel attached to the electro-optical panel 200. The data interface unit 340 is an interface unit that inputs and outputs image data or control data. For example, it is a wired communication interface such as a USB, or a wireless communication interface such as a wireless LAN. The storage unit 320 stores image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as a working memory for the processing device 310 or the display controller 300. The processing device 310 performs control processing of each part of the electronic device and various data processing. The processing device 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing of the circuit device 100. For example, the display controller 300 converts image data transferred from the data interface unit 340 or the storage unit 320 into a format that can be accepted by the circuit device 100, and outputs the converted image data to the circuit device 100. The circuit device 100 drives the electro-optical panel 200 based on image data transferred from the display controller 300 .

[0105] The circuit device is not limited to a driver, and the electronic device in which the circuit device is incorporated is not limited to the above. In other words, the electronic device may include a device equivalent to a capacitive load and the circuit device 100 that drives it.

[0106] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the circuit device, control circuit, output circuit, electro-optical panel, electro-optical device, electronic device, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0107] 1...capacitive load, 10...capacitor circuit, 20...capacitor driving circuit, 40...control circuit, 42...processing circuit, 44...interface circuit, 48...register circuit, 100...circuit device, 110...voltage output circuit, 120...D / A conversion circuit, 131...resistor, 132...capacitor, 140...overdrive circuit, 141...overdrive driving circuit, 142...arithmetic circuit, 150...amplifier circuit, 160...capacitive driving circuit, 170...arithmetic circuit, 180...D / A conversion circuit, 200...electro-optical panel, 300...display controller, 310...processing device, 320...storage unit, 330...user interface unit, 340...data interface unit, 400...electro-optical device, 500...electronic device, CV1 to CV5...capacitor for overdrive, DI...input data, DQ...output data, DV[4:0]...data for overdrive, NV...first node, VQ...driving voltage

Claims

1. an amplifier circuit having an output terminal connected to an inverting input terminal and outputting a drive voltage to a capacitive load; a voltage output circuit that outputs an output voltage corresponding to a D / A converted voltage of input data to a non-inverting input terminal of the amplifier circuit; Including, The voltage output circuit includes: A circuit device characterized in that, when the input data changes in a positive direction, causing the drive voltage to overshoot the D / A conversion voltage, the output voltage is made higher than the D / A conversion voltage.

2. 2. The circuit device according to claim 1, The circuit device according to claim 1, wherein the voltage output circuit makes the output voltage higher than the D / A conversion voltage and then returns the output voltage to the D / A conversion voltage.

3. 2. The circuit device according to claim 1, The circuit device according to claim 1, wherein the voltage output circuit changes the output voltage with a delay from a timing at which the input data changes.

4. 4. The circuit device according to claim 3, The circuit device according to claim 1, wherein the voltage output circuit changes a time period from a change in the input data to a change in the output voltage in accordance with a difference between previous input data and current input data.

5. 2. The circuit device according to claim 1, The voltage output circuit includes: A circuit device characterized in that, when the input data changes in a negative direction, causing the drive voltage to undershoot the D / A conversion voltage, the output voltage is made lower than the D / A conversion voltage.

6. 2. The circuit device according to claim 1, The amplifier circuit includes: The non-inverting input terminal includes a first non-inverting input terminal and a second non-inverting input terminal, The voltage output circuit includes: a D / A conversion circuit that performs D / A conversion on the input data and outputs the D / A converted voltage to the first non-inverting input terminal; a resistor provided between an output node of the D / A conversion circuit and the second non-inverting input terminal; a capacitor provided between the second non-inverting input terminal and a first node; an overdrive circuit that drives the first node based on the input data to set a voltage of the second non-inverting input terminal to an overdrive voltage higher than the D / A conversion voltage; A circuit device comprising:

7. 7. A circuit device according to claim 6, The overdrive circuit includes: an arithmetic circuit for calculating overdrive data corresponding to the overdrive voltage based on the input data; first to m-th overdrive capacitors, one end of which is connected to the first node; an overdrive driving circuit for driving the other ends of the first to m-th overdrive capacitors based on the overdrive data; A circuit device comprising:

8. 8. The circuit arrangement according to claim 7, The arithmetic circuit includes: A circuit device comprising: a circuit for multiplying a difference between previous input data and current input data by a coefficient; and outputting the overdrive data using a result of the multiplication.

9. 9. A circuit arrangement according to claim 8, The arithmetic circuit includes: A circuit device comprising: a circuit for multiplying the difference by the coefficient, which varies depending on the difference.

10. 2. The circuit device according to claim 1, The voltage output circuit includes: an arithmetic circuit that calculates output data based on the input data; a D / A conversion circuit that performs D / A conversion on the output data to output the output voltage; Including, The arithmetic circuit includes: A circuit device which changes said output data from said input data to first output data for making said output voltage a voltage higher than said D / A converted voltage of said input data.

11. 11. A circuit arrangement according to claim 10, The arithmetic circuit includes: A circuit device, comprising: a first output data input section that outputs the first output data to the first circuit; a second output data input section that outputs the first output data to the first circuit;

12. 11. A circuit arrangement according to claim 10, The arithmetic circuit includes: A circuit device comprising: a first input data unit that multiplies a difference between previous input data and current input data by a coefficient; and a result of the multiplication is used to output the first output data.

13. 13. A circuit arrangement according to claim 12, The arithmetic circuit includes: A circuit device comprising: a circuit for multiplying the difference by the coefficient, which varies depending on the difference.

14. 2. The circuit device according to claim 1, the input data is gradation data, The circuit device is characterized in that the amplifier circuit drives an electro-optical panel.

15. A circuit arrangement according to claim 14; The electro-optical panel; 1. An electro-optical device comprising:

16. 15. An electronic device comprising the circuit device according to claim 1.

Images