Display device

Abstract

To provide a display device in which the decrease in display quality can be suppressed.SOLUTION: A display device in an embodiment includes a base material, a plurality of pixels disposed in a display region on the base material, and data signal lines that supply data signals to the pixels. Each of the pixels includes a pixel circuit including a plurality of transistors, and a light-emitting element driven by the pixel circuit. The pixel circuit drives the light-emitting element so that light is emitted in a time divisional manner. A first transistor, among the transistors included in the pixel circuit, that is connected to the data signal line is an oxide transistor.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] 2. Description of the Related Art In recent years, display devices that use organic light-emitting diodes (OLEDs), which are light-emitting elements that function as display elements, have been put to practical use.

[0003] In such a display device, the light emitting elements are driven by pixel circuits, but depending on the circuit configuration of the pixel circuits, the display quality of the display device may be degraded. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-036290 A [Patent Document 2] JP 2019-211665 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of suppressing deterioration in display quality. [Means for solving the problem]

[0006] A display device according to an embodiment includes a substrate, a plurality of pixels arranged in a display region on the substrate, and a data signal line for supplying a data signal to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit including a plurality of transistors, and a light-emitting element driven by the pixel circuit. The pixel circuit drives the light-emitting element to emit light in a time-division manner. A first transistor of the plurality of transistors constituting the pixel circuit and connected to the data signal line is an oxide transistor. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of a plurality of sub-pixels included in a pixel. [Diagram 3] FIG. 13 is a diagram showing another example of the layout of a plurality of sub-pixels included in a pixel. [Figure 4] FIG. 3 is a schematic cross-sectional view of the display device taken along the line AA in FIG. 2. [Diagram 5] FIG. [Figure 6] FIG. 11 is a schematic cross-sectional view for explaining a light-emitting element formed by utilizing a partition wall. [Figure 7] FIG. 11 is a schematic cross-sectional view for explaining a light-emitting element formed by utilizing a partition wall. [Figure 8] FIG. 11 is a schematic cross-sectional view for explaining a light-emitting element formed by utilizing a partition wall. [Figure 9] FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel circuit. [Figure 10] A diagram showing an overview of PWM drive. [Figure 11] 4 is a diagram for explaining the operation of the pixel circuit during PWM driving. [Figure 12] 1A and 1B are diagrams for explaining the display quality of a display device to which PWM driving is applied. [Figure 13] FIG. 4 is a diagram for explaining a region where a ghost occurs. [Figure 14] FIG. 2 is a diagram showing an example of a layout of a pixel circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in terms of width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0009] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Also, viewing various elements parallel to the third direction Z is called a planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device having organic light emitting diodes (OLEDs) as display elements (light emitting elements), and is mounted on televisions, personal computers, mobile terminals, mobile phones, and the like.

[0011] 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA surrounding the display area DA, on an insulating base material 10. The base material 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged (disposed) in a matrix in the first direction X and the second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the subpixels SP include a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The subpixels SP may include subpixels of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3. The subpixels SP may also include subpixels of other colors instead of any of the subpixels SP1, SP2, and SP3.

[0014] Each of the sub-pixels SP includes a pixel circuit and a light-emitting element driven by the pixel circuit, the details of which will be described later. The pixel circuit is composed of, for example, a plurality of transistors (switching elements constituted by thin film transistors). The light-emitting element is the above-mentioned organic light-emitting diode. For example, the sub-pixel SP1 includes a light-emitting element that emits light so as to emit light in the red wavelength range, the sub-pixel SP2 includes a light-emitting element that emits light so as to emit light in the green wavelength range, and the sub-pixel SP3 includes a light-emitting element that emits light so as to emit light in the blue wavelength range.

[0015] 2 shows an example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in a pixel PX. Here, the following description focuses on four pixels PX.

[0016] The sub-pixels SP1, SP2, and SP3 constituting one pixel PX are each formed in a substantially rectangular shape extending in the second direction Y, and are aligned in the first direction X. When focusing on two pixels PX aligned in the first direction X, the colors displayed in the sub-pixels SP adjacent to each other in the first direction X are different from each other. When focusing on two pixels PX aligned in the second direction Y, the colors displayed in the sub-pixels SP adjacent to each other in the second direction Y are the same. The areas of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0017] FIG. 3 shows another example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in the pixel PX.

[0018] Subpixels SP1 and SP2 constituting one pixel PX are aligned in the second direction Y, subpixels SP1 and SP3 are aligned in the first direction X, and subpixels SP2 and SP3 are aligned in the first direction X. Subpixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and subpixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of ​​subpixel SP2 is larger than the area of ​​subpixel SP1, and the area of ​​subpixel SP3 is larger than the area of ​​subpixel SP2. The shape and area of ​​subpixel SP1 may be the same as those of subpixel SP2.

[0019] Focusing on two pixels PX aligned in the first direction X, in a region where subpixels SP1 and SP3 are alternately arranged and in a region where subpixels SP2 and SP3 are alternately arranged, the colors displayed in the subpixels SP adjacent in the first direction X are different from each other. On the other hand, focusing on two pixels PX aligned in the second direction Y, in a region where subpixels SP1 and SP2 are alternately arranged, the colors displayed in the subpixels SP adjacent in the second direction Y are different from each other. Also, in a region where multiple subpixels SP3 are aligned, the colors displayed in the subpixels SP adjacent in the second direction are the same.

[0020] Note that the outlines of the subpixels SP1, SP2, and SP3 shown in Figures 2 and 3 correspond to the outlines of the areas in which colors are displayed in the subpixels SP (i.e., the light-emitting areas), but are shown in a simplified form and do not necessarily reflect the actual shapes.

[0021] Here, although details will be described later, ribs and partition walls are arranged in the display area DA in this embodiment. The ribs have openings in the sub-pixels SP1, SP2, and SP3, respectively. The partition walls are arranged at the boundaries between adjacent sub-pixels SP and overlap with the ribs in a plan view. Specifically, the partition walls are arranged between adjacent openings (sub-pixels SP) in the first direction X and between adjacent openings (sub-pixels SP) in the second direction Y. As a result, the partition walls have a lattice shape formed so as to separate the sub-pixels SP1, SP2, and SP3 as a whole. In other words, the partition walls have openings in the sub-pixels SP1, SP2, and SP3, similar to the ribs.

[0022] Fig. 4 is a schematic cross-sectional view of the display device DSP taken along the line AA in Fig. 2. In the display device DSP, an insulating layer 11 called an undercoat layer is disposed on a light-transmitting substrate 10 such as the above-mentioned glass (on the surface on which light-emitting elements and the like are disposed).

[0023] The insulating layer 11 has a three-layered structure including, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). Note that the insulating layer 11 is not limited to a three-layered structure. The insulating layer 11 may have a layered structure of more than three layers, or may have a single-layered structure or a two-layered structure.

[0024] The circuit layer 12 is disposed on the insulating layer 11. The circuit layer 12 has pixel circuits (various circuits and wiring) that drive the light-emitting elements included in each of the subpixels SP1, SP2, and SP3 as described above. The circuit layer 12 is covered with the insulating layer 13.

[0025] The insulating layer 13 functions as a planarizing film that flattens unevenness caused by the circuit layer 12. Although not shown in Fig. 4, the insulating layer 13 is provided with a contact hole for connecting the lower electrode LE to the pixel circuit.

[0026] The lower electrodes LE (LE1, LE2, and LE3) are disposed on the insulating layer 13. The rib 5 is disposed on the insulating layer 13 and the lower electrodes LE. An end (part) of the lower electrode LE is covered by the rib 5.

[0027] The partition wall 6 has a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61 in the first direction X and the second direction Y. As a result, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 can be said to be an overhanging shape.

[0028] The organic layers OR (OR1, OR2, and OR3) and the upper electrodes UE (UE1, UE2, and UE3), together with the lower electrodes LE (LE1, LE2, and LE3), constitute a light-emitting element included in the subpixel SP.

[0029] As shown in FIG. 4, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b spaced apart from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b spaced apart from each other. The first organic layer OR1a contacts the lower electrode LE1 through an opening AP1 (an opening in the rib 5 in the subpixel SP1) and covers a part of the rib 5. The second organic layer OR1b is located on the upper portion 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts a side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0030] As shown in FIG. 4, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b spaced apart from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b spaced apart from each other. The first organic layer OR2a contacts the lower electrode LE2 through an opening AP2 (an opening in the rib 5 in the subpixel SP2) and covers a part of the rib 5. The second organic layer OR2b is located on the upper portion 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts a side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0031] As shown in FIG. 4, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b spaced apart from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b spaced apart from each other. The first organic layer OR3a contacts the lower electrode LE3 through an opening AP3 (an opening in the rib 5 in the subpixel SP3) and covers a part of the rib 5. The second organic layer OR3b is located on the upper portion 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts a side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0032] In the example shown in FIG. 4, the subpixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 (optical path adjustment layers) for adjusting the optical properties of the light emitted from the light emitting layers of the organic layers OR1, OR2, and OR3.

[0033] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b spaced apart from each other. The first cap layer CP1a is located in the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0034] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b spaced apart from each other. The first cap layer CP2a is located in the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0035] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b spaced apart from each other. The first cap layer CP3a is located in the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0036] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers each component of the subpixel SP1, including the first cap layer CP1a, the partition wall 6, and the second cap layer CP1b. The sealing layer SE2 continuously covers each component of the subpixel SP2, including the first cap layer CP2a, the partition wall 6, and the second cap layer CP2b. The sealing layer SE3 continuously covers each component of the subpixel SP3, including the first cap layer CP3a, the partition wall 6, and the second cap layer CP3b.

[0037] 4, the second organic layer OR1b, the second upper electrode UE1b, the second cap layer CP1b, and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP2 are spaced apart from the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition 6 between the subpixels SP2 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer SE3 on the partition 6.

[0038] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15. The sealing layer 15 is further covered with a resin layer 16.

[0039] The insulating layer 13 and the resin layers 14 and 16 are made of an organic material. The rib 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are made of an inorganic material such as silicon nitride (SiNx).

[0040] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may be made of a conductive oxide such as ITO.

[0041] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE corresponds to an anode and the upper electrode UE corresponds to a cathode. When the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE corresponds to an anode and the lower electrode LE corresponds to a cathode.

[0042] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. For example, the organic layer OR has a structure in which a hole injection layer, a hole import layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order.

[0043] The cap layer CP (CP1, CP2, and CP3) is formed, for example, by a multilayer body of multiple transparent thin films. The multiple thin films may include a thin film formed of an inorganic material and a thin film formed of an organic material. Furthermore, these multiple thin films have different refractive indices. The material of the thin films constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. The cap layer CP may be omitted.

[0044] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to each of the lower electrodes LE (LE1, LE2, and LE3) through a pixel circuit included in each of the subpixels SP (SP1, SP2, and SP3).

[0045] When a potential difference is generated between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength region. When a potential difference is generated between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength region. When a potential difference is generated between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength region.

[0046] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of colors corresponding to the subpixels SP1, SP2, and SP3.

[0047] Fig. 5 is a schematic enlarged cross-sectional view of the partition wall 6. Elements other than the rib 5, the partition wall 6, the insulating layer 13, and the pair of lower electrodes LE are omitted in Fig. 5. The pair of lower electrodes LE corresponds to any one of the above-mentioned lower electrodes LE1, LE2, and LE3.

[0048] In the example shown in FIG. 5, the lower portion 61 of the partition wall 6 includes a barrier layer (bottom portion) 611 disposed on the rib 5, and a metal layer (shaft portion) 612 disposed on the barrier layer 611. The barrier layer 611 is formed of a material different from that of the metal layer 612, and is formed of a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN). The metal layer 612 is formed to be thicker than the barrier layer 611. The metal layer 612 may have a single-layer structure or a laminated structure of different metal materials. As an example, the metal layer 612 is formed of aluminum (Al), for example.

[0049] The upper portion (top portion) 62 is thinner than the lower portion 61. In the example shown in Fig. 5, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is made of, for example, titanium (Ti), and the second layer 622 is made of, for example, ITO.

[0050] 5, the width of the lower portion 61 decreases toward the upper portion 62. That is, side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the third direction Z. The upper portion 62 has an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b.

[0051] The protrusion amount D of the ends 62a and 62b from the side surfaces 61a and 61b (hereinafter referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. The protrusion amount D of the partition wall 6 in this embodiment corresponds to the distance in the width direction (first direction X or second direction Y) perpendicular to the third direction Z of the partition wall 6 between the lower ends (barrier layers 611) of the side surfaces 61a and 61b and the ends 62a and 62b.

[0052] 5, the side surface of the barrier layer 611 and the side surface of the metal layer 612 are aligned to form a flat surface without any steps, but for example, the side surface of the barrier layer 611 may be slightly recessed from the side surface of the metal layer 612 or may protrude from the side surface of the metal layer 612. Also, in FIG. 5, the side surfaces of the barrier layer 611 and the metal layer 612 (i.e., the side surfaces 61a and 61b of the lower portion 61) are inclined with respect to the third direction Z, but the side surfaces may be parallel to the third direction Z.

[0053] The structure of the partition walls 6 and the material of each portion of the partition walls 6 can be appropriately selected in consideration of, for example, the method of forming the partition walls 6, etc.

[0054] Here, in this embodiment, the partition wall 6 is formed so as to partition the sub-pixels SP in a plan view. The above-mentioned organic layer OR is formed, for example, by an anisotropic or directional vacuum deposition method. When an organic material for forming the organic layer OR is deposited over the entire substrate 10 with the partition wall 6 disposed, the organic layer OR is hardly formed on the side surface of the partition wall 6 because the partition wall 6 has a shape as shown in Figures 4 and 5. This makes it possible to form an organic layer OR (light-emitting element) that is divided into sub-pixels SP by the partition wall 6.

[0055] 6 to 8 are schematic cross-sectional views for explaining a light-emitting element formed by utilizing the partition wall 6. Note that the base material 10, the insulating layer 11, and the circuit layer 12 are omitted in Figs. 6 to 8. Also, the subpixels SPα, SPβ, and SPγ shown in Figs. 6 to 8 correspond to any one of the subpixels SP1, SP2, and SP3.

[0056] First, in a state where the partition 6 is disposed as described above, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are sequentially formed by vapor deposition on the entire substrate 10 as shown in FIG. 6. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the subpixel SPα. The overhanging partition 6 divides the organic layer OR into a first organic layer ORa that contacts the lower electrode LE through the opening AP and a second organic layer ORb on the partition 6, the upper electrode UE into a first upper electrode UEa that covers the first organic layer ORa and a second upper electrode UEb that covers the second organic layer ORb, and the cap layer CP into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa is in contact with the lower portion 61 of the partition 6. The sealing layer SE continuously covers the first cap layer CPa, the partition 6, and the second cap layer CPb.

[0057] Next, as shown in Fig. 7, a resist R is formed on the sealing layer SE. The resist R covers the subpixel SPα. That is, the resist R is disposed directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located in the subpixel SPα. The resist R is also located directly above the portions of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the subpixel SPα and the subpixel SPβ that are closer to the subpixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0058] Furthermore, by etching using the resist R as a mask, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are removed in portions exposed from the resist R, as shown in Fig. 8. As a result, a light-emitting element including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa is formed in the subpixel SPα. Meanwhile, the lower electrode LE is exposed in the subpixels SPβ and SPγ. The above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0059] After the light-emitting element of the subpixel SPα is formed as described above, the resist R is removed, and the light-emitting elements of the subpixels SPβ and SPγ are formed in sequence in the same manner as the subpixel SPα.

[0060] The structure of the display device DSP shown in Figure 4 is realized by forming light-emitting elements of sub-pixels SP1, SP2, and SP3 as exemplified above for sub-pixels SPα, SPβ, and SPγ, and then forming resin layer 14, sealing layer 15, and resin layer 16.

[0061] Here, as described above, each of the sub-pixels SP includes a pixel circuit that drives a light-emitting element. An example of a circuit configuration of the pixel circuit will be described below with reference to Fig. 9. Note that the pixel circuit 100 shown in Fig. 9 is a 7Tr1C pixel circuit that includes seven transistors (hereinafter referred to as first to seventh transistors) Tr1 to Tr7 and one storage capacitor Cst.

[0062] In the following description, one of the source-drain terminals of each of the first to seventh transistors Tr1 to Tr7 shown in Fig. 9 is referred to as a first terminal, and the other is referred to as a second terminal. Also, one terminal of the storage capacitor Cst (a capacitive element realizing the storage capacitor Cst) shown in Fig. 9 is referred to as a first terminal, and the other terminal is referred to as a second terminal.

[0063] A first terminal of the first transistor Tr1 is connected to a first terminal of the second transistor Tr2 and a second terminal of the fifth transistor Tr5 via a node n3. The second terminal of the first transistor Tr1 is connected to a data signal line that supplies a data signal Data. The data signal Data corresponds to a signal (pixel signal) written to a pixel. The first transistor Tr1 is, for example, an n-channel transistor.

[0064] The second transistor Tr2 corresponds to a drive transistor (DRT) that supplies a current to the light-emitting element 20 included in the subpixel SP (i.e., the light-emitting element 20 driven by the pixel circuit 100). A first terminal of the second transistor Tr2 is connected to a first terminal of the first transistor Tr1 and a second terminal of the fifth transistor Tr5 via a node n3. A second terminal of the second transistor Tr2 is connected to a second terminal of the third transistor Tr3, a first terminal of the fourth transistor Tr4, and a first terminal of the seventh transistor Tr7 via a node n1. The second transistor Tr2 is, for example, an n-channel transistor.

[0065] A first terminal of the third transistor Tr3 is connected to the gate terminal of the second transistor Tr2 and the second terminal of the storage capacitor Cst via a node n2. A second terminal of the third transistor Tr3 is connected to the second terminal of the second transistor Tr2, the first terminal of the fourth transistor Tr4, and the first terminal of the seventh transistor Tr7 via a node n1. The third transistor Tr3 is, for example, an n-channel transistor.

[0066] A first terminal of the fourth transistor Tr4 is connected to a second terminal of the second transistor Tr2, a second terminal of the third transistor Tr3, and a first terminal of the seventh transistor Tr7 via a node n1. A second terminal of the fourth transistor Tr4 is connected to a power supply line that supplies a power supply voltage VDDEL. The fourth transistor Tr4 is, for example, a p-channel transistor.

[0067] A first terminal of the fifth transistor Tr5 is connected to a first terminal of the sixth transistor Tr6, a first terminal of the storage capacitor Cst, and an anode terminal of the light-emitting element 20 via a node n4. A second terminal of the fifth transistor Tr5 is connected to a first terminal of the first transistor Tr1 and a first terminal of the second transistor Tr2 via a node n3. The fifth transistor Tr5 is, for example, a p-channel transistor.

[0068] A first terminal of the sixth transistor Tr6 is connected to a first terminal of the fifth transistor Tr5, a first terminal of the storage capacitor Cst, and an anode terminal of the light-emitting element 20 via a node n4. A second terminal of the sixth transistor Tr6 is connected to a power supply line that supplies an initialization voltage Vini. The sixth transistor Tr6 is, for example, an n-channel transistor.

[0069] A first terminal of the seventh transistor Tr7 is connected to a second terminal of the second transistor Tr2, a second terminal of the third transistor Tr3, and a first terminal of the fourth transistor Tr4 via a node n1. A second terminal of the seventh transistor Tr7 is connected to a power supply line that supplies a power supply voltage VSH. The seventh transistor Tr7 is, for example, an n-channel transistor.

[0070] 9, the gate terminal of the first transistor Tr1 is connected to a gate signal line that supplies a gate signal Scan2. The gate terminal of the third transistor Tr3 is connected to a gate signal line that supplies a gate signal Scan1. The gate terminals of the fourth to sixth transistors Tr4 to Tr6 are connected to a control signal line that supplies a control signal EM. The gate terminal of the seventh transistor Tr7 is connected to a gate signal line that supplies a gate signal Scan3.

[0071] A first terminal of the storage capacitor Cst is connected, via a node n4, to a first terminal of the fifth transistor Tr5, a first terminal of the sixth transistor Tr6, and the anode terminal of the light-emitting element 20. A second terminal of the storage capacitor Cst is connected, via a node n2, to the gate terminal of the second transistor Tr2 and a first terminal of the third transistor Tr3.

[0072] The anode terminal of the light-emitting element 20 is connected to a first terminal of the fifth transistor Tr5, a first terminal of the sixth transistor Tr6, and a first terminal of the storage capacitor Cst via a node n4. The cathode terminal of the light-emitting element 20 is connected to a power supply line that supplies a power supply voltage VSSEL. The above-mentioned power supply voltage VDDEL corresponds to the anode voltage supplied to the light-emitting element 20, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the light-emitting element 20.

[0073] 9, for example, a data signal line for supplying a data signal Data, a power supply line for supplying a power supply voltage VDDEL, and a power supply line for supplying a power supply voltage VSH are arranged side by side in the first direction X so as to extend in the second direction Y. In other words, the data signal line, the power supply line for supplying the power supply voltage VDDEL, and the power supply line for supplying the power supply voltage VSH are connected to each of the sub-pixels SP (pixel circuits 100) arranged in the second direction Y. In addition, for example, the gate signal lines for supplying the gate signals Scan1 to Scan3, the control signal lines for supplying the control signals EM, and the power supply line for supplying the initialization voltage Vini are arranged side by side in the second direction Y so as to extend in the first direction X. In other words, the gate signal lines, the control signal lines, and the power supply line for supplying the initialization voltage Vini are connected to each of the sub-pixels SP (pixel circuits 100) arranged in the first direction X.

[0074] In the display device DSP, the pixel circuits 100 included in each of the plurality of subpixels SP drive the light-emitting elements 20 to display various screens (images) in the display area DA, but when the entire screen displayed in the display area DA needs to be darkened, for example, it is possible to make the light-emitting elements 20 included in each of the plurality of subpixels SP emit light at a low luminance. However, when the light-emitting elements 20 included in each of the plurality of subpixels SP emit light at a low luminance, unevenness is likely to occur on the screen.

[0075] For this reason, in the display device DSP, in order to avoid unevenness on the screen, PWM (Pulse Width Modulation) driving can be applied in which the light-emitting element 20 emits (lights) at high brightness and in a time-division manner, rather than emitting (lighting) the light-emitting element 20 at low brightness for the entire period.

[0076] Fig. 10 shows an overview of PWM driving. In Fig. 10, the vertical axis represents rows 1 to N (hereinafter referred to as rows 1 to N of the display area DA) each consisting of a plurality of pixels PX (sub-pixels SP) arranged in the display area DA, and the horizontal axis represents time. N is an integer equal to or greater than 2.

[0077] In PWM driving, a data signal Data is written to each row of the display area DA for each frame period during which one frame (image) is displayed. The data signal Data is written in the order of rows 1 to N of the display area DA.

[0078] In addition, in PWM driving, after a data signal Data is written to each row of the display area DA, the light-emitting elements 20 included in the pixels PX (sub-pixels SP) that make up each row are repeatedly illuminated (turned on and off) (i.e., the light-emitting elements 20 are illuminated and turned off in a time-division manner).

[0079] In the example shown in Figure 10, a write scan period P1 in which a data signal Data is written to each of rows 1 to N of the display area DA, first to fourth emission periods P11 to P14 in which the light-emitting element 20 is caused to emit light, and first to fourth extinction periods P21 to P24 in which the light-emitting element 20 is extinguished are arranged in one frame period, and it is shown that the emission and extinction of the light-emitting element 20 are each repeated four times in PWM drive.

[0080] Although FIG. 10 shows an example in which the light emitting element 20 is turned on and off four times, the number of times the light emitting element 20 is turned on and off may be any number other than four.

[0081] According to such PWM driving, compared to a driving method (normal driving) in which the light-emitting element 20 is made to emit light at low brightness throughout one frame period (period other than the write scanning period P1), it is easier to control the current supplied to the light-emitting element 20 via, for example, the driving transistor DRT (the second transistor Tr2 shown in FIG. 9), and unevenness on the screen displayed in the display area DA is less likely to occur.

[0082] Furthermore, since PWM driving can adjust the brightness of the screen by changing the ratio of the first to fourth light emission periods P11 to P14 in one frame period, it is possible to easily adjust the luminance without changing the data signal (video data). Furthermore, PWM driving may be used to correct unevenness (uneven image quality) that occurs in a low gradation screen (image).

[0083] Here, the operation of the pixel circuit 100 shown in Fig. 9 during PWM driving will be described with reference to Fig. 11. Fig. 11 is a timing chart showing an example of output of gate signals Scan1 to Scan3 and control signals EM to sub-pixels SP (pixel circuits 100) arranged in rows n-1 and n of rows 1 to N of the display area DA described above. Here, n is an integer equal to or greater than 2 and equal to or less than N.

[0084] Here, we will mainly explain the operation of the pixel circuit 100 in the fourth emission period P14, the fourth extinction period P24, the write scanning period P1, which are arranged in one frame period shown in Figure 10 above, and the first emission period P11, which is arranged in the next frame period.

[0085] The multiple transistors constituting the pixel circuit 100 include n-channel transistors and p-channel transistors, and the n-channel transistor is a switching element that is turned off (non-conductive) when a low (level) signal is supplied to its gate terminal and turned on (conductive) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switching element that is turned off (non-conductive) when a high (level) signal is supplied to its gate terminal and turned on (conductive) when a low (level) signal is supplied to the gate terminal.

[0086] First, in the fourth light emission period P14 shown in FIG. 11, since the control signal EM is low, the fourth transistor Tr4 and the fifth transistor Tr5 of the seven transistors included in the pixel circuit 100 are in the on state, and the sixth transistor Tr6 is in the off state.

[0087] In the fourth light emission period P14, the gate signals Scan1 to Scan3 are low, so that the first transistor Tr1, the third transistor Tr3 and the seventh transistor Tr7 are in the off state.

[0088] As a result, a current controlled by the gate voltage of the second transistor Tr2 (a voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the light-emitting element 20 (OLED), causing the light-emitting element 20 to emit light.

[0089] Next, at the start of the fourth turn-off period P24 shown in FIG. 11, the control signal EM is switched from low to high.

[0090] According to this, the fourth transistor Tr4 and the fifth transistor Tr5 are turned off, so that no current is supplied to the light emitting element 20, and the light emitting element 20 is turned off.

[0091] 11, the control signal EM is high, so that the sixth transistor Tr6 is in an on state. In this case, the initialization voltage Vini is supplied to the node n4 via the sixth transistor Tr6, but since the initialization voltage Vini is set to a value that causes no current to flow through the light-emitting element 20, no current flows through the light-emitting element 20 during the period P1a (i.e., the light-emitting element 20 does not emit light).

[0092] Furthermore, at the start of the period P1a, the gate signal Scan1 is switched from low to high. Therefore, during the period P1a, the third transistor Tr3 is in the ON state. Furthermore, at the start of the write scanning period P1, the gate signal Scan3 is switched from low to high. Therefore, during the period P1a, the seventh transistor Tr7 is in the ON state. This results in a state in which the power supply voltage VSH is supplied to the gate terminal of the second transistor Tr2 via the seventh transistor Tr7 and the third transistor Tr3. In this case, a voltage of VSH-Vini is applied to (between the first and second terminals of) the storage capacitance Cst, and the information of the previous frame is reset.

[0093] At the end of the period P1a, the gate signal Scan3 is switched from high to low.

[0094] At the start of period P1b in the write scanning period P1, the gate signal Scan2 is switched from low to high. Therefore, during period P1b, the first transistor Tr1 is turned on. During period P1b, the gate signal Scan3 is low, so the seventh transistor Tr7 is turned off.

[0095] In this case, the gate terminal of the second transistor Tr2 is supplied with the data signal Data (corresponding voltage Vdata) and the threshold voltage Vth of the second transistor Tr2 (i.e., a voltage equivalent to Vdata+Vth) via the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3. As a result, a voltage of Vdat+Vth-Vini is applied to the storage capacitance Cst, and information on Vdata and Vth is written to the storage capacitance Cst (i.e., a voltage that controls the current supplied by the second transistor Tr2 to the light-emitting element 20 is stored in the storage capacitance Cst).

[0096] At the end of the period P1b, the gate signal Scan1 is switched from high to low.

[0097] Next, in the first light-emitting period P11 shown in Fig. 11, the gate signal Scan1 is low, so the third transistor Tr3 is in the off state. Also, the gate signal Scan2 is switched from high to low before the first light-emitting period P11 starts, so the first transistor Tr1 is in the off state. Furthermore, the control signal EM is switched from high to low at the timing when the first light-emitting period P11 starts. Therefore, the fourth transistor Tr4 and the fifth transistor Tr5 are in the on state, and the sixth transistor Tr6 is in the off state.

[0098] Here, if the first terminal of the second transistor Tr2 is the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n2 to node n3) of the second transistor Tr2 becomes the voltage (Vdata+Vth-Vini) of the storage capacitor Cst. In this case, the second transistor Tr2 is turned on, and a current flows from the power line (power line supplying the power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n4. As a result, the potential of the node n4 starts to rise, and when the potential exceeds the threshold value of the light-emitting element 20 (OLED), a current starts to flow to the light-emitting element 20, and the light-emitting element 20 starts to emit light. Finally, when the current Ioled flowing through the light-emitting element 20 reaches the output current Idrt provided by the second transistor Tr2 (the output current in the saturation region of the second transistor Tr2), the potential rise of the node n4 stops, and the light-emitting element 20 enters a steady light-emitting state.

[0099] The voltage Vgs=Vdata+Vth-Vini between the gate terminal and the source terminal of the second transistor Tr2 is expressed by the TFT saturation formula Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 Substituting this, Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini) 2 Here, Cox is the gate capacitance per unit area, μ is the carrier mobility, W is the channel width of the second transistor Tr2, and L is the channel length of the second transistor Tr2.

[0100] This means that Idrt becomes a value that is independent of the threshold voltage Vth of the second transistor Tr2 (i.e., a current that is independent of the threshold voltage Vth of the second transistor Tr2 flows through the light-emitting element 20), and it can be seen that the effect of variations in the threshold voltage Vth on Idrt can be eliminated.

[0101] That is, it can be said that the pixel circuit 100 (7Tr1C pixel circuit) shown in FIG. 9 has a function of correcting the variation in the threshold voltage Vth of the second transistor Tr2 (Vth correction function).

[0102] Note that, although the operation of the pixel circuit 100 arranged in row n-1 shown in FIG. 11 has been described here, the pixel circuit 100 arranged in row n performs a similar operation such as writing the data signal Data to row n after the data signal Data is written to row n-1.

[0103] Hereinafter, a case will be considered where a screen (window) as shown in the left side of Fig. 12 is displayed in the display area DA of the display device DSP to which the above-mentioned PWM drive is applied. Note that a black belt portion 101 (a black belt-shaped image) is arranged near the center of the screen shown on the left side of Fig. 12. In this case, the n-1th row of the above-mentioned display area DA corresponds to the row displaying the black belt portion 101, and the nth row corresponds to the row displaying a portion (non-black belt portion) different from the black belt portion 101 that is located in the second direction Y from the black belt portion 101.

[0104] In the following description, for convenience, the operation of the pixel circuit 100 during the fourth emission period P14 will be referred to as the emission operation, the operation of the pixel circuit 100 during the fourth extinction period P24 will be referred to as the extinction operation, and the operation of the pixel circuit 100 during the write scanning period P1 will be referred to as the write operation.

[0105] Here, when the pixel circuits 100 arranged in the n-1th row perform a write operation, a data signal line to which the first transistors Tr1 constituting the pixel circuits 100 arranged in the n-1th row are connected is supplied with a data signal Data (corresponding black voltage) for displaying the black band portion 101. In this embodiment, the black voltage corresponds to a voltage that does not cause the light emitting element 20 to emit light (no current flows through the light emitting element 20).

[0106] Meanwhile, as described above, the first transistor Tr1 constituting the pixel circuit 100 arranged in row n is also connected to the data signal line to which the data signal Data for displaying the black band portion 101 is supplied. However, when the pixel circuit 100 arranged in row n-1 is undergoing a write operation, the pixel circuit 100 arranged in row n is in an extinguished operation, and the nodes n1 and n3 of the pixel circuit 100 arranged in row n are in a floating state.

[0107] In this manner, when the nodes n1 and n3 of the pixel circuits 100 arranged in n rows are in a floating state, if a data signal Data (i.e., black voltage) for displaying the black band portion 101 is supplied to the data signal line connected to the first transistor Tr1 constituting the pixel circuit 100 as described above, a leakage current (OFF leakage) from the node n3 side toward the data signal line side flows into the first transistor Tr1, causing potential fluctuations at the nodes n1 and n3 which are in a floating state.

[0108] The pixel circuits 100 arranged in row n perform a write operation after a turn-off operation, but the potential fluctuations occurring at the nodes n1 and n3 during the turn-off operation affect the gate voltage of the second transistor Tr2 even after the write operation (remain as a potential difference in the gate voltage). For this reason, when an attempt is made to display the screen shown in the left side of Fig. 12 in the display area DA in a display device DSP to which PWM driving is applied, a ghost is visible (occurs) in the area 102 after row n where a write operation is performed after row n-1 of the display area DA, as shown in the right side of Fig. 12.

[0109] Incidentally, since the occurrence of this ghost is caused by the data signal Data (black voltage) for displaying the black band portion 101 being supplied to the data signal line during the light-out operation (i.e., while node n1 and node n3 are in a floating state), the ghost does not occur in a display device DSP to which the above-mentioned normal driving is applied (i.e., there is no light-out period in one frame period).

[0110] As described above, the region 102 where a ghost occurs is a region made up of pixels PX (sub-pixels SP) whose data signal lines are supplied with data signals Data for displaying the black belt portions 101 during the fourth extinction period P24 arranged immediately before the write scanning period P1, as shown in Fig. 13. In other words, the region 102 where a ghost occurs is a region where at least a part of the fourth extinction period P24 overlaps with the period in which the black belt portions 101 are written.

[0111] As described above, when a screen in which the black belt portion 101 is arranged in the display area DA is displayed in the display device DSP to which PWM driving is applied, ghosting may occur, which may degrade the display quality of the display device DSP. Note that, for the sake of convenience, the explanation has been given here assuming that the black belt portion 101 (black belt-shaped image) is displayed in part of the display area DA, but ghosting may also occur in the case where belt-shaped images of other colors are displayed, which may degrade the display quality of the display device DSP.

[0112] Here, the first transistor Tr1 constituting the pixel circuit 100 is generally a polysilicon transistor using, for example, low temperature polysilicon (LTPS: Low Temperature Ply Silicon), but in this embodiment, focusing on the fact that the above-mentioned ghost occurs according to the leakage current generated in the first transistor Tr1, an oxide transistor (Oxide TFT) using an oxide semiconductor is adopted as the first transistor Tr1. Since the oxide transistor has an extremely small leakage current compared to a polysilicon transistor, even if a data signal Data (black voltage) for displaying the black band portion 101 during the above-mentioned light-off operation is supplied to the data signal line, no potential fluctuation occurs at the node n1 and the node n3 in the pixel circuit 100 arranged in the above-mentioned region 102, and the occurrence of the ghost can be suppressed.

[0113] Here, Fig. 14 shows an example of the layout of the pixel circuit 100. Fig. 14 shows, for example, each element of the pixel circuit 100 (first to seventh transistors Tr1 to Tr7, storage capacitor Cst, gate signal lines, control signal lines, data signal lines, and various power supply lines) formed in a circuit layer 12 composed of first to fifth layers.

[0114] The first layer is a layer formed below the second layer, the second layer is a layer formed below the third layer, the third layer is a layer formed below the fourth layer, and the fourth layer is a layer formed below the fifth layer. In other words, the first to fifth layers are stacked in order, with the first layer being the bottom layer and the fifth layer being the top layer.

[0115] The first layer is a layer (p-Si layer) in which a polysilicon semiconductor layer is formed, the second, fourth and fifth layers are layers (metal layers) in which electrodes constituting transistors and wiring connected to the transistors are formed, and the third layer is a layer (oxide layer) in which an oxide semiconductor layer is formed.

[0116] 14, the first transistor Tr1, which is an oxide transistor, is formed across the second to fourth layers. Here, it is assumed that the first transistor Tr1 has a dual gate structure in which an oxide semiconductor is sandwiched between a first gate electrode formed in the fourth layer (upper layer) and a second gate electrode formed in the second layer (lower layer) (i.e., the third layer).

[0117] In order to properly hold the voltage supplied to the gate terminal of the second transistor Tr2 during one frame period in the storage capacitor Cst, an oxide transistor is often used as the third transistor Tr3 connected to the node n2.

[0118] On the other hand, the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 are polysilicon transistors and are formed across the first and second layers. That is, the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 are formed in a layer below the first transistor Tr1 and the third transistor Tr3 (oxide transistor). Note that, like the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7, the storage capacitor Cst is formed across the first and second layers.

[0119] Moreover, the gate signal lines, the control signal lines, and the power supply lines for supplying the initialization voltage Vini are formed in the second layer, and the data signal lines and other power supply lines are formed in the fifth layer.

[0120] Note that the connections between the elements of the pixel circuit 100 described above are as described in FIG. 9, so detailed description thereof will be omitted here. However, as shown in FIG. 14, elements formed in different layers are connected via contact holes CH.

[0121] 14, the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 are all polysilicon transistors, but some of the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 may be oxide transistors. Specifically, for example, the second transistor Tr2, the fourth transistor Tr4, and the fifth transistor Tr5 that supply current to the light emitting element 20 may be polysilicon transistors with relatively high stability, and the remaining sixth transistor Tr6 and seventh transistor Tr7 may be oxide transistors.

[0122] It should be noted that the layout of the pixel circuit 100 shown in FIG. 14 is just an example, and the positions and orientations of the components of the pixel circuit 100 may be different from the example shown in FIG.

[0123] As described above, the display device DSP according to this embodiment includes a substrate 10, a plurality of sub-pixels SP arranged in a display area DA on the substrate 10, and a data signal line that supplies a data signal Data to each of the sub-pixels SP. Each of the sub-pixels SP includes a pixel circuit 100 composed of a plurality of transistors, and a light-emitting element 20 driven by the pixel circuit 100. The pixel circuit 100 drives the light-emitting element 20 to emit light in a time-division manner. Furthermore, of the plurality of transistors that configure the pixel circuit 100, a first transistor Tr1 connected to the data signal line is an oxide transistor.

[0124] In this embodiment, with the above-mentioned configuration, even when a screen in which a black band portion 101 or the like is arranged is displayed in the display area DA of the display device DSP to which PWM driving is applied, it is possible to suppress a deterioration in the display quality of the display device DSP (i.e., to realize good display quality without the occurrence of ghosts).

[0125] In the present embodiment, the second transistor Tr2, which supplies a current to the light-emitting element 20 among the multiple transistors constituting the pixel circuit 100, is a polysilicon transistor, thereby making it possible to supply a stable current to the light-emitting element 20. Note that in the present embodiment, it is preferable that the fourth transistor Tr4 arranged between the power supply line that supplies the power supply voltage VDDEL and the second transistor Tr2, and the fifth transistor Tr5 arranged between the light-emitting element 20 and the second transistor Tr2 are also polysilicon transistors.

[0126] Furthermore, in this embodiment, the third transistor Tr3 has a first terminal (one of the source terminal and the drain terminal) of the second transistor Tr2 connected to the first terminal of the first transistor Tr1, a first terminal (one of the source terminal and the drain terminal) connected to the gate terminal of the second transistor Tr2 and the second terminal (one terminal) of the holding capacitance Cst, and a second terminal (the other of the source terminal and the drain terminal) connected to the second terminal (the other of the source terminal and the drain terminal) of the second transistor Tr2. Since the third transistor Tr3 is an oxide transistor, the voltage supplied to the gate terminal of the second transistor Tr2 can be appropriately held in the holding capacitance Cst without being affected by leakage current.

[0127] In this embodiment, the first transistor Tr1 connected to the data signal line has been described as an oxide transistor, but the first transistor Tr1 may be any transistor configured to have a smaller leakage current than, for example, a second transistor that supplies current to the light-emitting element 20 among the multiple transistors that constitute the pixel circuit 100.

[0128] All display devices that can be implemented by those skilled in the art through appropriate design modifications based on the display devices described above as the embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0129] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0130] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0131] DSP...display device, DA...display area, NDA...non-display area, PX...pixel, SP, SP1, SP2, SP3...sub-pixel, AP, AP1, AP2, AP3...opening, LE, LE1, LE2, LE3...lower electrode, UE, UE1, UE2, UE3...upper electrode, OR, OR1, OR2, OR3...organic layer, SE, SE1, SE2, SE3...sealing layer, Tr1 to Tr7...transistor, Cst...storage capacitance, 5...rib, 6...partition, 10...substrate, 11...insulating layer, 12...circuit layer, 13...insulating layer, 14...resin layer, 15...sealing layer, 16...resin layer, 20...light-emitting element, 61...lower part, 62...upper part, 100...pixel circuit.

Claims

1. A substrate; A plurality of pixels arranged in a display region on the substrate; a data signal line for supplying a data signal to each of the plurality of pixels; Equipped with Each of the plurality of pixels includes a pixel circuit including a plurality of transistors and a light-emitting element driven by the pixel circuit; the pixel circuit drives the light emitting element to emit light in a time division manner; A first transistor connected to the data signal line among the plurality of transistors constituting the pixel circuit is an oxide transistor. Display device.

2. 2. The display device according to claim 1, wherein a second transistor that supplies a current to the light emitting element among the plurality of transistors that constitute the pixel circuit is a polysilicon transistor.

3. the pixel circuit further includes, in addition to the plurality of transistors, a storage capacitor that stores a voltage that controls a current that the second transistor supplies to the light-emitting element, a third transistor among the plurality of transistors constituting the pixel circuit is an oxide transistor; the second transistor has one of a source terminal and a drain terminal connected to one of a source terminal and a drain terminal of the first transistor; The third transistor has one of a source terminal and a drain terminal connected to a gate terminal of the second transistor and one terminal of the storage capacitor, and the other of the source terminal and drain terminal connected to the other of the source terminal and drain terminal of the second transistor. The display device according to claim 2.

4. a fourth transistor and a fifth transistor among the plurality of transistors constituting the pixel circuit are polysilicon transistors; the fourth transistor is disposed between a power supply line that supplies a power supply voltage and the second transistor; The fifth transistor is disposed between the light emitting element and the second transistor. The display device according to claim 3.

5. A substrate; A plurality of pixels arranged in a display region on the substrate; a data signal line for supplying a data signal to each of the plurality of pixels; Equipped with Each of the plurality of pixels includes a pixel circuit including a plurality of transistors and a light-emitting element driven by the pixel circuit; the pixel circuit drives the light emitting element to emit light in a time division manner; A first transistor connected to the data signal line among the plurality of transistors constituting the pixel circuit is configured to have a smaller leakage current than a second transistor that supplies a current to the light emitting element among the plurality of transistors. Display device.

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