Semiconductor device and electronic apparatus

Abstract

To provide a semiconductor device capable of generating a current signal in an improved manner.SOLUTION: A semiconductor device 1X comprises: a signal output terminal SENSE; a current signal generation circuit 13; and a voltage detection circuit 21. The current signal generation circuit 13 is configured to generate a current signal and externally output the generated current signal from the signal output terminal SENSE. The voltage detection circuit 21 is configured to be able to detect voltage of the signal output terminal SENSE. The voltage detection circuit 21 is configured to control the current signal generation circuit 13 according to the voltage of the signal output terminal SENSE.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The invention disclosed in this specification relates to a semiconductor device and an electronic device.

Background Art

[0002] Conventionally, electronic devices that generate a current detection signal indicating a current to be monitored based on the voltage drop of a sense resistor have been used in various applications (such as LED [light emitting diode] driver ICs and switching power supply ICs).

[0003] As an example of the prior art related to the above, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] There was room for further consideration regarding the generation of a current detection signal in the semiconductor device disclosed in Patent Document 1.

[0006] The semiconductor device disclosed in this specification includes a signal output terminal, a current signal generation circuit, and a voltage detection circuit. The current signal generation circuit is configured to generate a current signal and output it externally from the signal output terminal. The voltage detection circuit is configured to be able to detect the voltage of the signal output terminal. The voltage detection circuit is configured to control the current signal generation circuit according to the voltage of the signal output terminal.

[0007] The electronic device disclosed in this specification includes the semiconductor device having the above configuration in which a current signal generation circuit and a voltage detection circuit are integrated on one chip, and a current signal detection circuit configured to be able to detect a current signal.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

[0009] [Detailed Description] <Regarding the Comparative Example Electronic Device 100Y> First, the electronic device 100Y will be described as a comparative example of the electronic device 100X of the present disclosure. Next, the problems of the comparative example will be described, and then the electronic device 100X of the present disclosure will be described.

[0010] <Regarding the Electronic Device 100Y> FIG. 1 is a block diagram showing the configuration of the electronic device 100Y of the comparative example. The electronic device 100Y is an IPD [Intelligent Power Device] having an abnormality detection function. As shown in FIG. 1, the electronic device 100Y includes a semiconductor device 1Y, a current signal detection circuit 2, and an inflow restriction circuit 3Y.

[0011] The semiconductor device 1Y includes a plurality of external terminals (VBB terminal, OUT terminal, SENSE terminal, and GND terminal in terms of FIG. 1) as means for establishing electrical connection with the outside of the device. The semiconductor device 1Y receives power supply from the VBB terminal and generates an output current Io and a current signal Is. The semiconductor device 1Y outputs the output current Io from the OUT terminal and generates the current signal Is from the SENSE terminal.

[0012] The current signal detection circuit 2 is externally attached to the SENSE terminal of the semiconductor device 1Y. The current signal detection circuit 2 is configured to be able to detect the current signal Is. Specifically, it is as follows. The current signal detection circuit 2 includes a resistance circuit 4 and an MCU [Micro Controller Unit] 5. The resistance circuit 4 includes a sense resistor Rs. The sense resistor Rs is a resistance element having a predetermined resistance value.

[0013] The first end of the sense resistor Rs is connected to the SENSE terminal. The second end of the sense resistor Rs is connected to the ground terminal DGND of the signal system (digital system). At the connection node n1 between the first end of the sense resistor Rs and the SENSE terminal, a sense voltage Vs corresponding to the current signal Is and the resistance value of the sense resistor Rs is generated.

[0014] The MCU 5 is capable of detecting the sense voltage Vs. By detecting the sense voltage Vs, the MCU 5 diagnoses the state of the semiconductor device 1Y (more specifically, the state of the internal control circuit 15 and the output state of the output current Io, which will be described later).

[0015] The inflow restriction circuit 3Y is configured to restrict the current flowing from the GND terminal into the semiconductor device 1Y in a state where the semiconductor device 1Y is reversely connected (the connection destinations of the GND terminal and the VBB terminal are reversed from the state shown in FIG. 1). The inflow restriction circuit 3Y includes a resistor R1. The first end of the resistor R1 is connected to the GND terminal. The second end of the resistor R1 is connected to the ground terminal PGND. If the semiconductor device 1Y is reversely connected and the second end of the resistor R1 is connected to the power supply voltage, the resistor R1 restricts the current flowing from this power supply to the GND terminal.

[0016] <Basic Configuration of Semiconductor Device 1Y> Next, the basic configuration of the semiconductor device 1Y will be described. As shown in FIG. 1, the semiconductor device 1Y integrates an output current generation circuit 10, a drive control circuit 11, an abnormality detection circuit 12, a current signal generation circuit 13, a clamp circuit 14, an internal control circuit 15, and an electrostatic breakdown protection circuit 16y on one chip.

[0017] The output current generation circuit 10 outputs an output signal Io from the OUT terminal by functioning as a switch that conducts / blocks the current flowing from the power supply voltage VBB. The drive control circuit 11 generates a drive signal G1 and controls the outputs of the output current generation circuit 10 and the current signal generation circuit 13 (more specifically, the sense current generation circuit 17 described later).

[0018] The abnormality detection circuit 12 is configured to detect an abnormal state of a monitoring target and generate an abnormality detection signal S1 according to the detection result. The monitoring target here may be, for example, the internal control circuit 15 described later. The abnormal state may be, for example, at least one of an overvoltage state and an overheat state.

[0019] The current signal generation circuit 13 receives the inputs of the power supply voltage VBB, the drive signal G1, and the abnormality detection signal S1, generates a current signal Is, and outputs it from the SENSE terminal.

[0020] The clamp circuit 14 is configured to be able to detect the current signal Is. The clamp circuit 14 controls the output of the current signal Is so that the voltage value of the sense voltage Vs does not exceed a predetermined threshold. Specifically, when the current value of the current signal Is reaches the threshold, the clamp circuit 14 allows the current exceeding the threshold to flow to the GND terminal and maintains (clamps) the current value of the current signal Is at the threshold. In this way, the clamp circuit 14 suppresses the sense voltage at the SENSE terminal (= sense voltage Vs) from exceeding the breakdown voltage of the current signal detection circuit 2 and destroying the current signal detection circuit 2.

[0021] The internal control circuit 15 is configured to be able to execute internal control for realizing various functions of the semiconductor device 1Y. The internal control circuit 15 operates by receiving power supply via the VBB terminal. Also, the power system ground terminal PGND is input to the internal control circuit 15 via the GND terminal. The internal control circuit 15 generates an operating current Ig. The operating current Ig basically flows to the GND terminal.

[0022] The electrostatic breakdown protection circuit 16y is configured to protect the clamp circuit 14 from electrostatic breakdown. Specifically, when a large current due to static electricity flows in the semiconductor device 1Y, the electrostatic breakdown protection circuit 16y is configured to flow this large current to the GND terminal while preventing it from flowing into the clamp circuit 14. The detailed configuration of the electrostatic breakdown protection circuit 16y will be described later.

[0023] <Internal Configuration of Semiconductor Device 1Y> Next, the internal configuration of the semiconductor device 1Y will be described in detail. FIG. 2 is a block diagram showing the detailed configuration of the semiconductor device 1Y. As shown in FIG. 2, the output current generation circuit 10 includes a power transistor Tp. The power transistor Tp is an N-channel type MOSFET [Metal-Oxide-Semiconductor Field-Effect Transistor].

[0024] The drain terminal of the power transistor Tp is connected to the VBB terminal. The source terminal of the power transistor Tp is connected to the OUT terminal. The gate terminal of the power transistor Tp is input with a drive signal G1. The power transistor Tp turns on / off according to the voltage level of the drive signal G1. When the power transistor Tp is in the on state, it outputs an output current Io as a drain current.

[0025] As shown in FIGS. 1 and 2, the current signal generation circuit 13 includes a sense current generation circuit 17 and an error current generation circuit 18. The above-mentioned current signal Is includes a sense current Ics and an error current Ie. The sense current generation circuit 17 generates a sense current Ics as a part of the current signal Is. The error current generation circuit 18 generates an error current Ie as a part of the current signal Is. The details of the sense current generation circuit 17 and the error current generation circuit 18 are as follows.

[0026] The sense current generation circuit 17 is composed of a transistor T1, a transistor T2, and an operational amplifier OP1. The transistor T1 is an N-channel MOSFET. The drain terminal of the transistor T1 is connected to the VBB terminal. The source terminal of the transistor T1 is connected to the source terminal of the transistor T2. A drive signal G1 is input to the gate terminal of the transistor T1. The transistor T1 turns on / off synchronously with the power transistor Tp according to the drive signal G1. When the transistor T1 is in the on state, it generates a drain current.

[0027] The non-inverting input terminal (+) of the operational amplifier OP1 is connected to the source terminal of the power transistor Tp. The inverting input terminal (-) of the operational amplifier OP1 is connected to the source terminal of the transistor T1. The operational amplifier OP1 outputs a drive signal G3 according to the differential input (the difference value of the drain-source voltage between each of the transistors T1 and T2).

[0028] The transistor T2 is a P-channel MOSFET. The source terminal of the transistor T2 is connected to the source terminal of the transistor T1. The gate terminal of the transistor T2 is connected to the output terminal of the operational amplifier OP1. The drain of the transistor T2 is connected to the SENSE terminal. The on-resistance value of the transistor T2 is controlled according to the voltage level of the drive signal G3. Specifically, the operational amplifier OP1 controls the on-resistance value of the transistor T2 so that the source terminal of the transistor Tp (=OUT terminal) and the source terminal of the transistor T1 are at the same potential. Thereby, a sense current Ics corresponding to the output current Io is generated.

[0029] The sense current Ics depends on the output current Io. Specifically, the current value of the sense current Ics has a proportional relationship with the current value of the output current Io (more specifically, a proportional relationship according to the characteristics of each of the transistors T1, T2, and the power transistor Tp, for example, 1 / K times).

[0030] The error current generation circuit 18 is composed of transistors T3 to T5 and a current source 19. Transistor T3 is a P-channel MOSFET. Transistors T4 and T5 are N-channel MOSFETs.

[0031] The source terminal of transistor T3 is connected to the VBB terminal. The drain terminal of transistor T3 is connected to the drain terminal of transistor T4. The source terminal of transistor T4 is connected to the applied terminal of the current source 19. An abnormality detection signal S1 is input to the gate terminals of transistor T3 and transistor T4. A drive signal G2 is output from the connection node n2 between the drain terminal of transistor T3 and the drain terminal of transistor T4.

[0032] The source terminal of transistor T5 is connected to the VBB terminal. The drain terminal of transistor T5 is connected to the SENSE terminal together with the drain terminal of transistor T2. A drive signal G2 is input to the gate terminal of transistor T5. Transistor T5 turns on / off according to the voltage level of the drive signal G2.

[0033] When the abnormality detection signal S1 is at a low level (= the logic level when no abnormality is detected), transistor T3 turns on and transistor T4 turns off. At this time, the drive voltage G2 becomes high level and transistor T5 turns off. When the abnormality detection signal S1 is at a high level (= the logic level when an abnormality is detected), transistor T3 turns off and transistor T4 turns on. At this time, the drive voltage G2 becomes low level and transistor T5 turns on. When transistor T5 is in the on state, an error current Ie as a drain current flows toward the SENSE terminal.

[0034] The clamp circuit 14 is composed of a control circuit 20, a resistor R3, and a transistor T6. Transistor T6 is an N-channel MOSFET.

[0035] The input terminal of the control circuit 20 is connected to the SENSE terminal together with the first terminal of the resistor R3. The second terminal of the resistor R3 is connected to the drain terminal of the transistor T6. The source terminal of the transistor T6 is connected to the GND terminal. The control circuit 20 generates a drive signal G4 according to the current signal Is and inputs it to the gate of the transistor T6. The transistor T6 turns on / off according to the voltage level of the drive signal G4.

[0036] When the current signal Is is less than the above-mentioned threshold value, the control circuit 20 inputs a low-level drive signal G4 to the gate of the transistor T6 according to the current signal Is. Therefore, the transistor T6 is off. Thus, at this time, the current signal Is is output from the SENSE terminal without being clamped by the clamp circuit 14.

[0037] When the current signal Is reaches the threshold value, the control circuit 20 inputs a high-level drive signal G4 to the gate of the transistor T6 according to the current signal Is. As a result, the transistor T6 turns on. Therefore, a part of the current signal Is (the current exceeding the threshold value in the current signal Is) flows to the GND terminal via the clamp circuit 14. In this way, the clamp circuit 14 clamps the current signal Is so that the current value of the current signal Is does not exceed the threshold value.

[0038] The electrostatic breakdown protection circuit 16y is composed of including the transistor T7. The transistor T7 is an N-channel type MOSFET. The gate terminal of the transistor T7 is connected to the GND terminal together with its own source terminal. The drain terminal of the transistor T7 is connected to the SENSE terminal. The gate terminal and the source terminal of the transistor T7 are short-circuited and it is always in the off state.

[0039] Transistor T7 forms a parasitic diode with its back gate (source terminal) as the anode and its drain terminal as the cathode. For example, when a positive surge voltage is applied to the SENSE terminal, the parasitic diode associated with transistor T7 breaks down. Then, current is discharged in the direction from the SENSE terminal through the parasitic diode of transistor T7 towards the GND terminal. Thereby, the clamp circuit 14 can be protected from electrostatic breakdown.

[0040] <Consideration on Current Signal Detection> Incidentally, when the current signal detection circuit 2 and the semiconductor device 1Y are designed separately, a potential difference may occur between the ground terminal DGND and PND. In this case, the voltage of the GND terminal (= operating current Ig × resistance value of resistor R1) may exceed the forward voltage of transistor T7. Then, the operating current Ig is output from the SENSE terminal as part of the current signal Is via transistor T7. In this case, the current signal detection circuit 2 cannot accurately detect the current signal Is.

[0041] In particular, an electronic device 100Y as described above generally mounts an inflow restriction circuit 3Y to prevent breakdown when the semiconductor device 1Y is reverse-connected. Therefore, depending on the resistance value of the inflow restriction circuit 3Y, the possibility that the voltage of the GND terminal exceeds the forward voltage of the parasitic diode associated with transistor T7 increases.

[0042] To prevent the operating current Ig from flowing into the electrostatic breakdown protection circuit 16y, a Schottky diode can be inserted in parallel with the resistor R1 in the inflow restriction circuit 3Y (see the broken line part in the inflow restriction circuit 3Y in FIGS. 1 and 2). However, implementing such a countermeasure increases the number of components and also leads to an increase in the size of the electronic device 100Y.

[0043] Thus, when adopting a configuration such as the above-described electronic device 100Y, there is a problem that the number of components increases in order to accurately detect the current signal Is.

[0044] In response to such problems, the electronic device 100X of the present disclosure is capable of suppressing an increase in the number of components while suppressing the inability to accurately detect the current signal Is. Hereinafter, the electronic device 100X according to the present disclosure will be described in detail. Note that the semiconductor device 1X according to the embodiment of the present disclosure includes a configuration common to the semiconductor device 1Y described above. Therefore, the same reference numerals are given to the common configurations and the description thereof is omitted.

[0045] <Regarding the electronic device 100X according to the embodiment of the present disclosure> FIG. 3 is a block diagram showing the configuration of the electronic device 100X according to the present disclosure. The electronic device 100X is an IPD having a self-diagnosis function, similar to the electronic device 100Y. As shown in FIG. 3, the electronic device 100X includes a semiconductor device 1X, a current signal detection circuit 2, and an inflow restriction circuit 3X.

[0046] The semiconductor device 1X includes a plurality of external terminals (VBB terminal, OUT terminal, SENSE terminal, and GND terminal, described with reference to FIG. 3) as means for establishing electrical connection with the outside of the device. The semiconductor device 1X receives power supply from the VBB terminal and generates an output current Io and a current signal Is. The semiconductor device 1X outputs the output current Io from the OUT terminal and generates the current signal Is from the SENSE terminal.

[0047] The MCU 5 diagnoses the state of the semiconductor device 1X, that is, the state of the internal control circuit 15, by detecting the sense voltage Vs.

[0048] The inflow restriction circuit 3X is configured to restrict the current flowing from the GND terminal to the semiconductor device 1X in a state where the semiconductor device 1X is reversely connected (a state where the connection destinations of the GND terminal and the VBB terminal are reversed). Specifically, the inflow restriction circuit 3X includes a resistor R1.

[0049] <Basic configuration of the semiconductor device 1X> Next, the basic configuration of the semiconductor device 1X will be described. As shown in FIG. 3, the semiconductor device 1X integrates an output current generation circuit 10, a drive control circuit 11, an abnormality detection circuit 12, a current signal generation circuit 13, an internal control circuit 15, a voltage detection circuit 21, and an electrostatic breakdown protection circuit 16x on a single chip.

[0050] The voltage detection circuit 21 is configured to be able to detect the voltage of the SENSE terminal. The voltage detection circuit 21 controls the current signal generation circuit 13 according to the voltage of the SENSE terminal. Details of the voltage detection circuit 21 will be described later.

[0051] The electrostatic breakdown protection circuit 16x is configured to protect the semiconductor device 1X from electrostatic breakdown. Specifically, the electrostatic breakdown protection circuit 16x is configured to conduct static electricity to the GND terminal when a large current due to static electricity flows in the semiconductor device 1X. Also, if the voltage of the GND terminal becomes higher than the voltage of the SENSE terminal, the operating current Ig is configured to be restricted from flowing into the SENSE terminal. In this way, the electrostatic breakdown protection circuit 16x can shunt current in both directions (the direction from the SENSE terminal side to the GND side and the reverse direction).

[0052] The electrostatic breakdown protection circuit 16x includes transistors T7 and T17. The gate terminal of transistor T17 is connected to the SENSE terminal together with its source terminal. The drain terminal of transistor T17 is connected to the drain terminal of transistor T7.

[0053] <Internal Configuration of Voltage Detection Circuit 21> Next, the internal configuration of the semiconductor device 1X will be described in detail. FIG. 4 is a block diagram showing the detailed configuration of the semiconductor device 1X. As shown in FIG. 4, the voltage detection circuit 21 includes a detection circuit 21a, a sense current control circuit 21b, and an error current control circuit 21c.

[0054] The detection circuit 21a is configured to be able to detect the voltage of the SENSE terminal (= sense voltage Vs). The sense current control circuit 21b controls the drive signal G3 of the sense current generation circuit 17 according to the detection result of the detection circuit 21a. The error current control circuit 21c controls the drive signal G2 of the error current generation circuit 18 according to the detection result of the detection circuit 21a. That is, the voltage detection circuit 21 controls the drive signals G2 and G3 by the sense current control circuit 21b and the error current control circuit 21c, and adjusts the outputs of the sense current Ics and the error current Ie so that the current signal Is does not exceed the threshold value.

[0055] The detection circuit 21a includes transistors T8, T9, T11, T12 and a current source 22.

[0056] The transistors T8 and T9 are N-channel MOSFETs. The transistors T11 and T12 are P-channel MOSFETs. The gate terminal of the transistor T8 is connected to the SENSE terminal. The source terminal of the transistor T8 is connected to the applied terminal of the current source 22 together with the source terminal of the transistor T9. The drain terminal of the transistor T8 is connected to the source terminal of the transistor T11. The drain terminal of the transistor T9 is connected to the source terminal of the transistor T12. The voltage Vref is input to the gate terminal of the transistor T9.

[0057] The drain terminal of the transistor T11 is connected to the drain terminal of a transistor T13 to be described later. The drain terminal of the transistor T12 is connected to the VBB terminal. The enable signal EN is input to the gates of the transistors T11 and T12 respectively. Basically, the transistors T11 and T12 are turned on with a low-level enable signal EN input to their gate terminals. When the voltage detection circuit 21 is not to be functioned, a high-level enable signal EN is input to the gate terminals of the transistors T11 and T12 to turn off the transistors T11 and T12 in advance.

[0058] The sense current control circuit 21b includes a transistor T14. The transistor T14 is a P-channel MOSFET. The source terminal of the transistor T14 is connected to the VBB terminal. The drain terminal of the transistor T14 is connected to the gate terminal of the transistor T2 together with the output terminal of the operational amplifier OP1. The gate terminal of the transistor T14 is connected to the drain terminal of the transistor T11 together with the respective gate terminals of the transistors T13 and T15 described later.

[0059] The error current control circuit 21c includes transistors T13 and T15.

[0060] The source terminal of the transistor T13 is connected to the VBB terminal together with the source terminal of the transistor T15. The drain terminal of the transistor T13 is connected to its own gate terminal. The drain terminal of the transistor T15 is connected to the gate terminal of the transistor T5 together with the connection node n2.

[0061] <Regarding the operation of the voltage detection circuit 21> Next, the operation of the voltage detection circuit 21 will be described. Here, the description will be made with the function of the voltage detection circuit 21 in an effective state (the state where the transistors T11 and T12 are on).

[0062] The voltage of the SENSE terminal (= sense voltage Vs) is input to the gate terminal of the transistor T8. The transistor T8 is off when the current value of the current signal Is is less than the above-described threshold value.

[0063] At this time, the currents flowing through transistors T8 and T11 become substantially zero values. Here, the current flowing through transistor T11 is mirrored as the drain currents of transistors T14 and T15 respectively by the current mirror formed by transistors T13 to T15. As described above, since the current flowing through T11 is substantially zero, the drive signals G2 and G3 are not affected by the voltage adjustment by the voltage detection circuit 21. Therefore, the on-resistance values of transistors T2 and T5 do not vary, and the sense current Ics and the error current Ie do not vary. At this time, transistor T9 is turned on by the voltage Vref applied to the gate terminal. And, a current from the current source 22 substantially flows through transistor T9.

[0064] When the current value of the current signal Is reaches the above-described threshold value, a current I2 (a current value corresponding to the voltages V1 and Vs) starts to flow through transistors T8 and T11. Through transistor T9, a current corresponding to the current obtained by subtracting the current I2 from the current from the current source 22 flows.

[0065] The current flowing through transistor T11 is mirrored as the drain currents of transistors T14 and T15 respectively by the current mirror formed by transistors T13 to T15. The drain currents of transistors T14 and T15 pull up the drive signals G2 and G3. As a result, the on-resistance values of transistors T2 and T5 are controlled to increase, and the sense current Ics and the error current Ie decrease.

[0066] As the current value of the current signal Is increases, the current value of the current I2 flowing through transistor T11 also increases, and the current values of the drain currents of transistors T14 and T15 also increase. Thereby, the drive signals G2 and G3 are further pulled up, and the on-resistance values of transistors T2 and T5 are controlled to further increase. Therefore, the current signal Is is clamped to a predetermined threshold value.

[0067] As described above, the voltage detection circuit 21 controls the current signal generation circuit 13 so that the current signal Is does not exceed the threshold value according to the voltage of the SENSE terminal. Thereby, it is possible to suppress the voltage of the SENSE terminal from exceeding the withstand voltage of the current signal detection circuit 2 and the current signal detection circuit 2 from being destroyed.

[0068] Also, as described above, the electrostatic breakdown protection circuit 16x can shunt the current in both directions (the direction from the SENSE terminal side to the GND side and the reverse direction). Therefore, even if the voltage of the GND terminal becomes higher than the voltage of the SENSE terminal, it is possible to suppress the operating current Ig from flowing into the SENSE terminal without providing the above-described Schottky diode outside the semiconductor device 1X. Accordingly, it is possible to accurately detect the current signal Is while suppressing an increase in the number of components.

[0069] <Supplementary Note> The semiconductor device (1X) disclosed in the specification includes a signal output terminal (SENSE), a current signal generation circuit (13) configured to generate a current signal (Is) and output it externally from the signal output terminal (SENSE), and a voltage detection circuit (21) configured to be able to detect the voltage of the signal output terminal (SENSE), and the voltage detection circuit (21) is configured to control the current signal generation circuit (13) according to the voltage of the signal output terminal (SENSE) (first configuration).

[0070] Note that in the semiconductor device (1X) according to the first configuration, the voltage detection circuit (21) may be configured to control the current signal generation circuit (13) so that it does not exceed the threshold voltage according to the voltage of the signal output terminal (SENSE) (second configuration).

[0071] Also, the semiconductor device (1X) according to the first or second configuration includes a power transistor (Tp) configured to generate an output current (Io), and the current signal generation circuit (13) may be configured to generate a current signal (Is) according to the output current (Io) (third configuration).

[0072] Also, in the semiconductor device (1X) according to the third configuration, the current signal generation circuit (13) may be configured to include a first current generation circuit (17) that generates a first current (Ics) such that the current value varies depending on the output current (Io) and outputs the first current (Ics) as at least part of the current signal (Is) (fourth configuration).

[0073] Also, the semiconductor device (1X) according to the third or fourth configuration may include an abnormality detection circuit (12) configured to detect an abnormal state of a monitoring target and generate an abnormality detection signal (S1) according to the detection result, and the current signal generation circuit (13) may be configured to include a second current generation circuit (18) that generates a second current (Ie) according to the abnormality detection signal (S1) and outputs the second current (Ie) as at least part of the current signal (Is) (fifth configuration).

[0074] Also, in the semiconductor device (1X) according to the fifth configuration, the abnormality detection circuit (12) may be configured to be able to detect at least one of an overheat state and an overcurrent state of the monitoring target as an abnormal state (sixth configuration).

[0075] Also, the semiconductor device (1X) according to any one of the first to sixth configurations may include a reference voltage terminal (GND) to which a reference voltage is applied from the outside, and a current limiting circuit (16x) connected between the signal output terminal (SENSE) and the reference voltage terminal (GND) and configured to limit the flow of current from the reference voltage terminal (GND) to the signal output terminal (SENSE) when the voltage of the reference voltage terminal (GND) is higher than the voltage of the signal output terminal (SENSE) (seventh configuration).

[0076] Also, in the semiconductor device (1X) according to the seventh configuration, the reference voltage may be configured to be a ground voltage (PGND) (eighth configuration).

[0077] The electronic device disclosed in the specification may be configured to include a semiconductor device (1X) according to any one of the first to eighth configurations in which a current signal generation circuit (13) and a voltage detection circuit (21) are integrated on one chip, and a current signal detection circuit (2) configured to be able to detect a current signal (Is) (ninth configuration).

[0078] In addition, in the electronic device according to the ninth configuration, the current signal detection circuit (2) is connected outside the semiconductor device (1X) between the signal output terminal (SENSE) and the application terminal of the ground voltage (PGND), and may be configured to include a resistance circuit (4) configured to generate a voltage signal corresponding to the current signal (Is) as the voltage between both ends, and a control circuit (5) configured to be able to detect the voltage signal (tenth configuration).

[0079] The electronic device disclosed in the specification includes a semiconductor device (1X) according to the seventh configuration, and an inflow restriction circuit (3X) connected between a reference voltage terminal (GND) and an application terminal of a reference voltage. The inflow restriction circuit (3X) may be configured to restrict the current flowing from the application terminal of the reference voltage to the reference voltage terminal (GND) when the reference voltage is higher than the ground voltage (PGND) (eleventh configuration).

[0080] According to the semiconductor device of the present disclosure, it is possible to accurately detect a current detection signal while suppressing an increase in the number of components.

[0081] <Others> In addition, various technical features disclosed in this specification can be variously modified within the scope not departing from the gist of the technical creation in addition to the above embodiments. That is, the above embodiments should be considered as illustrative in all respects and not restrictive. Also, the technical scope of the present disclosure is defined by the scope of the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the scope of the claims are included.

Explanation of Reference Numerals

[0082] 1X Semiconductor device 1Y Semiconductor Device 2 Current Signal Detection Circuit 3X Inflow Limiting Circuit 3Y Inflow Limiting Circuit 4 Resistance Circuit 10 Output Current Generation Circuit 11 Drive Control Circuit 12 Abnormality Detection Circuit 13 Current Signal Generation Circuit 14 Clamp Circuit 15 Internal Control Circuit 16x Electrostatic Discharge Protection Circuit 16y Electrostatic Discharge Protection Circuit 17 Sense Current Generation Circuit 18 Error Current Generation Circuit 19 Power Supply 20 Control Circuit 21 Voltage Detection Circuit 21a Detection Circuit 21b Sense Current Control Circuit 21c Error Current Control Circuit 22 Power Supply 100X Electronic Equipment 100Y Electronic Equipment EN Enable Signal G1~G4 Drive Signals I2 Current Ics Sense Current Ie Error Current Ig Operating Current Io Output Current Is Current Signal OP1 Operational Amplifier PGND Ground Voltage R1, R3 Resistors Rs Sense Resistor S1 Abnormality Detection Signal SENSE Signal Output Terminal T1~T15 Transistors T17 Transistor Tp Power Transistor V1, Vref Voltages Vs Sense Voltage n1 Connection Node n2 Connection Node

Claims

1. A signal output terminal, a current signal generation circuit configured to generate a current signal and output it externally from the signal output terminal, a voltage detection circuit configured to be able to detect the voltage of the signal output terminal, comprising: The voltage detection circuit is a semiconductor device that controls the current signal generation circuit according to the voltage of the signal output terminal.

2. The semiconductor device according to claim 1, wherein the voltage detection circuit controls the current signal generation circuit so as not to exceed a threshold voltage according to the voltage of the signal output terminal.

3. comprising a power transistor configured to generate an output current, The semiconductor device according to claim 1, wherein the current signal generation circuit generates the current signal according to the output current.

4. The semiconductor device according to claim 3, wherein the current signal generation circuit includes a first current generation circuit that generates a first current whose current value varies depending on the output current and outputs the first current as at least part of the current signal.

5. comprising an abnormality detection circuit configured to detect an abnormal state of a monitoring target and generate an abnormality detection signal according to the detection result, The semiconductor device according to claim 3 or 4, wherein the current signal generation circuit includes a second current generation circuit configured to generate a second current according to the abnormality detection signal and output the second current as at least part of the current signal.

6. The semiconductor device according to claim 5, wherein the abnormality detection circuit can detect at least one of an overheat state and an overcurrent state of the monitoring target as the abnormal state.

7. a reference voltage terminal to which a reference voltage is applied from the outside, a current limiting circuit connected between the signal output terminal and the reference voltage terminal and configured to limit the flow of current from the reference voltage terminal to the signal output terminal when the voltage of the reference voltage terminal is higher than the voltage of the signal output terminal, The semiconductor device according to claim 1, comprising:

8. The semiconductor device according to claim 7, wherein the reference voltage is a ground voltage.

9. The semiconductor device according to claim 1, in which the current signal generation circuit and the voltage detection circuit are integrated on one chip, a current signal detection circuit configured to be able to detect the current signal, An electronic device comprising:

10. The current signal detection circuit is A resistance circuit that is connected outside the semiconductor device between the signal output terminal and the application terminal of the ground voltage and is configured to generate a voltage signal corresponding to the current signal as a voltage across both ends; A control circuit configured to be able to detect the voltage signal; The electronic device according to claim 9, comprising the above.

11. The semiconductor device according to claim 7; An inflow restriction circuit connected between the reference voltage terminal and the application terminal of the reference voltage; Comprising; The electronic device, wherein the inflow restriction circuit is configured to limit the current flowing from the application terminal of the reference voltage to the reference voltage terminal when the reference voltage is higher than the ground voltage.

Images