Method for reducing spurious of frequency synthesizer and program

Abstract

To easily suppress a signal strength of a spurious contained in an output signal of a frequency synthesizer.SOLUTION: A method containing the steps of: generating a first spurious characteristic data obtained by specifying a frequency difference between a frequency of a Mth-order spurious generated in an output signal to be output from the frequency synthesizer and a frequency of an output signal, and performing a plot; extracting a data of which the frequency difference becomes smallest in each frequency of the output signal, and generating a second spurious characteristic data; generating the plurality of second spurious characteristic data corresponded to a plurality of multipliers; generating a third spurious characteristic data by extracting a data of which the frequency difference of the output signal becomes largest; and specifying each multiplier to be connected to a DDS.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a method and a program for reducing spurs of a frequency synthesizer.

Background Art

[0002] A frequency synthesizer that switches and outputs signals of a plurality of predetermined frequencies using a direct digital synthesizer (DDS) is known (see, for example, Patent Document 1 and Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The output signal of the DDS includes spurs caused by harmonics of the frequency of the signal. Spurs may be generated in the vicinity of the frequency of the output signal of the DDS due to aliasing. In this case, even when using a narrow-band filter such as a SAW filter with a passband of about several MHz, it may be difficult to reduce the signal intensity of the spurs, which may cause performance degradation of devices operating based on the output signal.

[0005] Therefore, the present invention has been made in view of these points, and an object thereof is to easily suppress the signal intensity of spurs included in the output signal of a frequency synthesizer.

[0006] ​In a first aspect of the present invention, there is provided a method for reducing spurs of a frequency synthesizer executed by a computer, the frequency synthesizer including: a clock signal source that outputs a clock signal; a DDS that outputs a DDS signal based on the clock signal output from the clock signal source; a plurality of multipliers that multiply the frequencies of signals input at different multiplication factors; a plurality of band-pass filters respectively connected to each of the plurality of multipliers; and a first switching unit that connects the DDS and any one of the plurality of multipliers in response to a first control signal input thereto. The method for reducing spurs includes: generating first spur characteristic data by identifying and plotting a frequency difference between the frequency of the output signal output from the frequency synthesizer and the frequency of an Mth-order spur (where M is an integer of 2 or more and not more than a predetermined number) generated in the output signal due to an Mth-order harmonic of a predetermined order or lower included in the DDS signal; generating second spur characteristic data by extracting data having the smallest frequency difference for each frequency of the output signal in the first spur characteristic data; repeating the step of generating the first spur characteristic data and the step of generating the second spur characteristic data for each of the plurality of multipliers to generate a plurality of second spur characteristic data corresponding to the plurality of multipliers; generating third spur characteristic data by extracting data having the largest frequency difference for each frequency of the output signal in frequency characteristic data obtained by plotting the plurality of second spur characteristic data on the same graph; and identifying, based on the third spur characteristic data, the multiplier to be connected to the DDS corresponding to the frequency of the output signal of the frequency synthesizer among the plurality of multipliers.

[0007] In the step of identifying the multiplier, the multiplier that outputs a signal corresponding to the data showing the maximum value of the frequency difference among the third spur characteristic data may be identified as the multiplier to be connected to the DDS.

[0008] In the step of identifying the multiplier, the multiplier that outputs a signal corresponding to the data among the third spurious characteristic data whose frequency difference exceeds a predetermined detuning frequency may be identified as the multiplier connected to the DDS.

[0009] The predetermined detuning frequency may be a frequency greater than the half-value width of the pass frequency band of the plurality of band-pass filters.

[0010] The method further includes: executing the step of generating the first spurious characteristic data, the step of generating the second spurious characteristic data, and the step of generating the third spurious characteristic data for each of a plurality of predetermined clock frequencies to generate a plurality of the third spurious characteristic data; extracting, from the frequency characteristic data obtained by drawing the plurality of third spurious characteristic data on the same graph, the data having the largest frequency difference for each frequency of the output signal to generate fourth spurious characteristic data; and identifying, based on the fourth spurious characteristic data, the multiplier among the plurality of multipliers that is connected to the DDS corresponding to the frequency of the output signal of the frequency synthesizer.

[0011] In a second aspect of the present invention, there is provided a program that, when executed by a computer, causes the computer to execute the method of the first aspect.

Advantages of the Invention

[0012] According to the present invention, there is an effect that the signal strength of spurious signals included in the output signal of the frequency synthesizer can be easily suppressed.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

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Figure 4

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Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0014] <Configuration Example of Conventional Frequency Synthesizer 10> FIG. 1 shows a configuration example of a conventional frequency synthesizer 10. The frequency synthesizer 10 outputs an output signal having a set frequency from an output unit 11. The frequency synthesizer 10 includes an output unit 11, a clock signal source 20, a direct digital synthesizer (DDS) 30, a first switching unit 41, a second switching unit 42, a first narrowband filter 51, a second narrowband filter 52, a control unit 60, a storage unit 61, and an amplification circuit 70.

[0015] The clock signal source 20 outputs a clock signal. The clock signal source 20 is, for example, a clock signal source capable of outputting a clock signal with a frequency specified by the control unit 60. The clock signal source 20 outputs a clock signal with a clock frequency of, for example, about 1000 MHz to about 4000 MHz. The clock signal output by the clock signal source 20 becomes the reference clock signal of the DDS 30.

[0016] The DDS 30 outputs a DDS signal based on the clock signal output from the clock signal source 20. The DDS 30 outputs a DDS signal with a frequency indicated by the control signal received from the control unit 60. The frequency of the DDS signal is, for example, a frequency between about 500 MHz and about 3000 MHz. Since the operation of the DDS 30 to output a DDS signal is known, the description is omitted here.

[0017] The DDS signal output by the DDS 30 may include spurs caused by the Nth harmonic (N is a natural number of 2 or more) of the DDS signal. Such higher-order spurs are generated when the Nth harmonic is folded back at the clock frequency. Therefore, the frequency at which the spurs occur changes according to the frequency of the DDS signal, the order of the harmonic, and the clock frequency. In the present embodiment, the spurs caused by the Nth harmonic of the DDS signal are referred to as Nth-order spurs or simply spurs.

[0018] The conventional frequency synthesizer 10 uses a narrowband filter to reduce such spurs. Since the DDS 30 outputs DDS signals with various frequencies according to the setting data, the frequency synthesizer 10 switches a plurality of narrowband filters corresponding to the setting data. FIG. 1 shows an example of the frequency synthesizer 10 capable of switching two narrowband filters.

[0019] The first switching unit 41 and the second switching unit 42 switch the narrowband filter to be connected to the DDS 30 according to the control signal received from the control unit 60. For example, the first switching unit 41 connects the DDS 30 to either the first narrowband filter 51 or the second narrowband filter 52 according to the input first control signal. Also, the second switching unit 42 connects either the first narrowband filter 51 or the second narrowband filter 52 to the output unit 11 according to the input second control signal.

[0020] The first narrowband filter 51 is a band-pass filter that reduces the spurious components superimposed on the DDS signal while passing the first frequency corresponding to the DDS signal of a predetermined first frequency output by the DDS 30. The second narrowband filter 52 is, similarly to the first narrowband filter 51, a band-pass filter that reduces the spurious components superimposed on the DDS signal while passing the second frequency corresponding to the DDS signal of a predetermined second frequency output by the DDS 30.

[0021] The passband widths of the first narrowband filter 51 and the second narrowband filter 52 are desirably smaller values in order to reduce spurious, for example, desirably about several MHz or less. The first narrowband filter 51 and the second narrowband filter 52 are, for example, SAW (Surface Acoustic Wave) filters, BAW (Bulk Acoustic Wave) filters, etc.

[0022] The control unit 60 controls each part of the frequency synthesizer 10. The control unit 60 supplies, for example, a control signal for designating the frequency of the clock signal of the clock signal source 20 to the clock signal source 20. The control unit 60 supplies setting data for setting the frequency of the DDS signal of the DDS 30 to the DDS 30. The control unit 60 supplies control signals for designating the connections of the first switching unit 41 and the second switching unit 42 to the first switching unit 41 and the second switching unit 42, respectively.

[0023] The control unit 60 causes, for example, a clock signal with a predetermined clock frequency to be output from the clock signal source 20, and causes a DDS signal with a predetermined first frequency to be output from the DDS 30. In this case, the control unit 60 supplies a control signal for connecting the DDS 30 and the first narrowband filter 51 to the first switching unit 41, and supplies a control signal for connecting the first narrowband filter 51 and the output unit 11 to the second switching unit 42.

[0024] Also, the control unit 60 causes a clock signal with a predetermined clock frequency to be output from the clock signal source 20, and causes a DDS signal with a predetermined second frequency to be output from the DDS 30. In this case, the control unit 60 supplies a control signal for connecting the DDS 30 and the second narrowband filter 52 to the first switching unit 41, and supplies a control signal for connecting the second narrowband filter 52 and the output unit 11 to the second switching unit 42.

[0025] Such a control unit 60 may receive an input for designating the frequency of the output signal from a user or the like. In this case, the frequency synthesizer 10 may further include an input unit or the like for the user or the like to input frequency information. Also, the control unit 60 may receive a control signal for designating the frequency of the output signal from an external device or the like. In this case, the frequency synthesizer 10 may further include a receiving circuit, a communication circuit, or the like for receiving the control signal from an external device or the like.

[0026] The control unit 60 is preferably configured by an integrated circuit or the like. The control unit 60 includes, for example, an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor), and / or a CPU (Central Processing Unit). When at least a part of the control unit 60 is configured by a computer or the like, the storage unit 61 includes a ROM (Read Only Memory) for storing a BIOS (Basic Input Output System) or the like of a computer or the like that realizes the control unit 60, and a RAM (Random Access Memory) that serves as a work area.

[0027] In addition, the storage unit 61 may store various information including an OS (Operating System), application programs, and / or a database referred to during the execution of the application programs. The storage unit 61 may include a large-capacity storage device such as an HDD (Hard Disk Drive) and / or an SSD (Solid State Drive). A processor such as a CPU functions as the control unit 60 by executing the programs stored in the storage unit 61.

[0028] The storage unit 61 stores, for example, setting data for outputting a DDS signal of a first frequency and setting data for outputting a DDS signal of a second frequency. In addition, it is desirable that the storage unit 61 stores, in association with the setting data for outputting the DDS signal of the first frequency, a control signal for connecting the DDS 30 and the first narrowband filter 51 and connecting the first narrowband filter 51 and the output unit 11 or information for generating the control signal.

[0029] Similarly, it is desirable that the storage unit 61 stores, in association with the setting data for outputting the DDS signal of the second frequency, a control signal for connecting the DDS 30 and the second narrowband filter 52 and connecting the second narrowband filter 52 and the output unit 11 or information for generating the control signal.

[0030] The amplifier circuit 70 is provided between the second switching unit 42 and the output unit 11 and amplifies the input signal. The amplifier circuit 70 outputs the amplified signal from the output unit 11. Note that the amplifier circuit 70 may not be provided when the signal intensity of the signal output from the second switching unit 42 is greater than or equal to a predetermined intensity level.

[0031] The above-described conventional frequency synthesizer 10 switches a narrowband filter that passes the frequency of the DDS signal according to the frequency of the output DDS signal. In such a configuration, by making the passband width of the narrowband filter smaller, spurs included in the DDS signal can be reduced.

[0032] However, depending on the combination of the frequency of the clock signal and the frequency of the DDS signal to be output, the frequency of the aliasing spurious may be close to the frequency of the DDS signal to be output, and there are cases where the spurious signal intensity cannot be sufficiently reduced even by using a narrow-band filter. Also, when outputting output signals of a plurality of different frequencies from the frequency synthesizer 10, as many narrow-band filters as the number of frequencies to be output are required, resulting in an increase in the circuit scale of the system.

[0033] In addition, narrow-band filters such as SAW filters and BAW filters are expensive, and if narrow-band filters are prepared for as many frequencies as used, the cost of the frequency synthesizer 10 will increase. Therefore, the frequency synthesizer 100 according to the present embodiment is configured to suppress the spurious signal intensity without using a narrow-band filter. Such a frequency synthesizer 100 will be described below.

[0034] <First Configuration Example of Frequency Synthesizer 100> FIG. 2 shows a first configuration example of the frequency synthesizer 100 according to the present embodiment. The frequency synthesizer 100 switches a combination of a plurality of multipliers and filters according to the frequency of the output signal to be output. FIG. 2 shows an example of the frequency synthesizer 100 capable of switching two sets of multipliers and filters.

[0035] The frequency synthesizer 100 includes an output unit 11, a clock signal source 20, a DDS 30, a first switching unit 41, a second switching unit 42, a control unit 60, a storage unit 61, an amplifier circuit 70, a first multiplier 81, a second multiplier 82, a first band-pass filter 91, and a second band-pass filter 92. In the frequency synthesizer 100 shown in FIG. 2, components that operate substantially the same as those of the conventional frequency synthesizer 10 shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0036] The first multiplier 81 outputs a first multiplied signal obtained by multiplying the frequency of the input signal. The second multiplier 82 outputs a second multiplied signal obtained by multiplying the frequency of the input signal. The multiplication factor of the first multiplier 81 is different from the multiplication factor of the second multiplier 82. For example, the multiplication factor of the first multiplier 81 is 3 times, and the multiplication factor of the second multiplier 82 is 4 times.

[0037] The first band-pass filter 91 allows the first multiplied signal output by the first multiplier 81 to pass through. The second band-pass filter 92 allows the second multiplied signal output by the second multiplier 82 to pass through. As will be described later, the first band-pass filter 91 and the second band-pass filter 92 each have a predetermined pass bandwidth.

[0038] The first switching unit 41 of the frequency synthesizer 100 connects either the DDS 30 or one of the multipliers of the first multiplier 81 and the second multiplier 82 according to the input control signal. In this embodiment, the control signal supplied from the control unit 60 to the first switching unit 41 may be referred to as the first control signal.

[0039] The second switching unit 42 of the frequency synthesizer 100 connects either one of the first band-pass filter 91 and the second band-pass filter 92 and the output unit 11 of the frequency synthesizer 100 via the amplifier circuit 70 according to the input control signal. In this embodiment, the control signal supplied from the control unit 60 to the second switching unit 42 may be referred to as the second control signal.

[0040] In other words, the control unit 60 supplies the first switching unit 41 with a first control signal for connecting either the DDS 30 or one of the multipliers of the first multiplier 81 and the second multiplier 82. Further, the control unit 60 supplies the second switching unit 42 with a second control signal for connecting the filter connected to the multiplier connected to the DDS 30 by the first switching unit 41 and the output unit 11.

[0041] For example, in the conventional frequency synthesizer 10 described with reference to FIG. 1, the difference between the frequency of the DDS signal and the spurious frequency closest to the frequency of the DDS signal varies from 0 MHz to about several tens of MHz depending on the setting of the clock frequency and the frequency of the DDS signal. Here, the frequency difference between the frequency of the DDS signal and the spurious frequency is referred to as the offset frequency.

[0042] Here, when the DDS signal is multiplied by a multiplier, not only the frequency of the DDS signal but also the spurious frequency is multiplied, so the offset frequency is also multiplied. In other words, when the DDS signal is passed through a multiplier as in the frequency synthesizer 100 according to the present embodiment, the offset frequency of the spurious closest to the frequency of the DDS signal can be multiplied, and the passband width of the filter can be increased.

[0043] Note that increasing the multiplication factor of the multiplier increases the offset frequency, but depending on the spurious, the folding order may increase, and spurious close to the frequency of the DDS signal may occur. Therefore, it is desirable that a multiplier with an appropriate multiplication factor is set corresponding to the setting of the clock frequency and the frequency of the DDS signal of the frequency synthesizer 100. Further, it is more desirable that the frequency synthesizer 100 includes a plurality of multipliers with different multiplication factors and is configured to be able to switch and select an appropriate multiplier based on the setting of the clock frequency and the frequency of the DDS signal.

[0044] For example, consider a case where it is desired to output a signal of 1689 MHz from the frequency synthesizer 100, and an example in which the control unit 60 sets the clock frequency to 3000 MHz and the DDS signal to 563 MHz. Here, it is assumed that the control unit 60 connects the DDS 30 and the first multiplier 81, and connects the first bandpass filter 91 and the output unit 11.

[0045] As a result, the output signal of the frequency synthesizer 100 becomes a first multiplied signal obtained by multiplying the DDS signal by 3 by the first multiplier 81, and the frequency of the output signal becomes 1689 MHz. In this case, among the frequencies of the 2nd to 10th spurs, the offset frequency of the spur closest to the first multiplied signal is 185 MHz. Therefore, the first band-pass filter 91 can reduce the spur closest to the first multiplied signal by including 1689 MHz in the passband and setting the passband width to about the offset frequency.

[0046] Next, consider the case where it is desired to output a signal of 1803 MHz from the frequency synthesizer 100. For example, when the control unit 60 sets the clock frequency to 3000 MHz and the DDS signal to 601 MHz, the frequency of the first multiplied signal obtained by multiplying the DDS signal by 3 by the first multiplier 81 becomes 1803 MHz. However, in this case, among the frequencies of the 2nd to 10th spurs, the offset frequency of the spur closest to the first multiplied signal is 5 MHz. Therefore, it becomes difficult to reduce the spur closest to the first multiplied signal unless the passband width of the first band-pass filter 91 is a narrow-band filter of about several MHz.

[0047] Therefore, consider an example where the control unit 60 sets the clock frequency to 3000 MHz and the DDS signal to 450.75 MHz. Here, it is assumed that the control unit 60 connects DDS30 and the second multiplier 82, and connects the second band-pass filter 92 and the output unit 11.

[0048] As a result, the output signal of the frequency synthesizer 100 becomes a second multiplied signal obtained by multiplying the DDS signal by 4 by the second multiplier 82, and the frequency of the output signal becomes 1803 MHz. In this case, among the frequencies of the 2nd to 10th spurs, the offset frequency of the spur closest to the second multiplied signal is 155 MHz. Therefore, the second band-pass filter 92 can reduce the spur closest to the second multiplied signal by including 1803 MHz in the passband and setting the passband width to about the offset frequency.

[0049] In this way, when the control unit 60 inputs a DDS signal for outputting a multiplied signal of a predetermined set frequency among the first multiplier 81 and the second multiplier 82, the control unit 60 identifies the multiplier that outputs a multiplied signal in which the frequency difference between the spurious frequency below a predetermined order and the set frequency exceeds a predetermined deviation frequency. Here, it is desirable that the combination of the predetermined set frequency and the multiplier that outputs a multiplied signal exceeding the predetermined deviation frequency is stored in the storage unit 61 in advance.

[0050] In other words, the storage unit 61 stores, in association with the set frequency, the information of the multiplier that has been previously specified corresponding to the set frequency among the first multiplier 81 and the second multiplier 82. The storage unit 61 may further store the information of the multiplier in association with the clock frequency. Note that the predetermined deviation frequency is, for example, a frequency greater than the half-value width of the pass frequency band of the first band-pass filter 91 and the second band-pass filter 92. Also, the predetermined deviation frequency may be a frequency approximately equal to the pass frequency band width of the first band-pass filter 91 and the second band-pass filter 92, or a frequency greater than the pass frequency band width.

[0051] Thereby, the control unit 60 can identify the multiplier that outputs the multiplied signal by reading out the information of the multiplier corresponding to the set frequency from the storage unit 61. Alternatively, the control unit 60 may calculate the frequency at which spurious occurs using an equation, and identify the multiplier corresponding to the set frequency based on the calculated result.

[0052] For example, if the frequency of the DDS signal is F DDS , and the difference between the frequency of the DDS signal and the frequency of the Nth-order spurious is F delta,Np,Fsn (F DDS ), then the difference is calculated as follows. Here, Np is the order of the spurious, F sn is the clock frequency of the clock signal, floor() is a function that truncates the decimal part, and mod(x, y) is a function that obtains the remainder when x is divided by y.

[0053] (Equation 1) F delta,Np,Fsn (FDDS ) = -F DDS + mod{floor(F DDS × Np / (F sn / 2)), 2} × {(F sn / 2) - mod(F DDS × Np, F sn / 2)} + [1 - mod{floor(F DDS × Np / (F sn / 2)), 2}] × mod(F DDS × Np, F sn / 2)

[0054] Then, the control unit 60 sets the clock frequency and the frequency of the DDS signal in order to output an output signal of a predetermined set frequency from the frequency synthesizer 100 corresponding to the multiplication factor of the specified multiplier. Further, the control unit 60 supplies a first control signal for connecting the specified multiplier and the DDS 30 to the first switching unit 41, and supplies a second control signal for connecting the filter connected to the specified multiplier and the output unit 11 to the second switching unit 42.

[0055] As described above, the frequency synthesizer 100 according to the present embodiment selects a multiplier with a larger offset frequency from spurious and outputs an output signal of a predetermined set frequency. Thereby, for example, even a band-pass filter with a pass-band width exceeding about several tens of MHz to about 100 MHz can reduce spurious.

[0056] Therefore, the frequency synthesizer 100 does not have to use expensive narrow-band filters such as SAW filters and BAW filters as the first band-pass filter 91 and the second band-pass filter 92. The first band-pass filter 91 and the second band-pass filter 92 may be, for example, LC filters formed by inductor elements, capacitor elements, etc. In other words, the frequency synthesizer 100 according to the present embodiment can easily suppress the signal intensity of spurious signals included in the output signal of the frequency synthesizer 100 by using an inexpensive filter.

[0057] In addition, since the frequency synthesizer 100 can increase the pass frequency bandwidths of the first band-pass filter 91 and the second band-pass filter 92, the number of settable frequencies that can be set as the output signal of the frequency synthesizer 100 can be increased.

[0058] For example, from equation (1), in a 3000 MHz clock signal, when the first multiplied signal output from the first multiplier 81 is changed from 1664 MHz to 1688 MHz (when the DDS signal of DDS30 is changed from 554.7 MHz to 562.7 MHz), the offset frequency gradually increases from 101 MHz to 187 MHz. Then, when the first multiplied signal is changed from 1688 MHz to 1740 MHz (when the DDS signal of DDS30 is changed from 562.7 MHz to 580 MHz), the offset frequency gradually decreases from 187 MHz to 100 MHz.

[0059] In other words, when the first multiplied signal from 1664 MHz to 1740 MHz is output, the offset frequency is 100 MHz or more. Therefore, for example, when the center frequency of the pass band of the first band-pass filter 91 is about 1702 MHz and the pass bandwidth is about 100 MHz, it can be seen that spurs can be reduced even when the first multiplied signal from about 1664 MHz to about 1740 MHz is output.

[0060] Similarly, in a 3000 MHz clock signal, when the second multiplied signal output from the second multiplier 82 is changed from 1772 MHz to 1846 MHz (when the DDS signal of DDS30 is changed from 443 MHz to 461.5 MHz), the offset frequency gradually increases from 101 MHz to 231 MHz. Then, when the second multiplied signal is changed from 1846 MHz to 1933 MHz (when the DDS signal of DDS30 is changed from 461.5 MHz to 483.3 MHz), the offset frequency gradually decreases from 231 MHz to 101 MHz.

[0061] In other words, when outputting the second harmonic signal from 1772 MHz to 1933 MHz, the offset frequency becomes 100 MHz or higher. Therefore, for example, if the center frequency of the passband of the second band-pass filter 92 is set to about 1853 MHz and the passband width is set to about 100 MHz, it can be understood that spurs can be reduced even when outputting the second harmonic signal from at least about 1803 MHz to about 1903 MHz.

[0062] Note that since the values of the above first harmonic signal and second harmonic signal change with the clock signal, by setting the clock signal to a different frequency, it is also possible to output the first harmonic signal and the second harmonic signal having frequencies different from the above-described frequencies.

[0063] As described above, when the frequency synthesizer 100 according to the present embodiment inputs a DDS signal for outputting an output signal having a set frequency in a predetermined frequency band at a predetermined clock frequency, a multiplier that outputs a harmonic signal in which the frequency difference between the frequency of the spur below a predetermined order and the set frequency exceeds a predetermined offset frequency is specified, and by using the specified multiplier, an output signal with reduced spurs can be output. It is desirable that the information on the set frequency of such a predetermined frequency band is stored in the storage unit 61.

[0064] In the frequency synthesizer 100 according to the above-described embodiment, an example in which two sets of a multiplier and a band-pass filter are provided has been described, but the present invention is not limited thereto. The frequency synthesizer 100 may include three or more sets of a multiplier and a band-pass filter. Needless to say, the multiplication factors of the plurality of multipliers are different from each other, and the plurality of band-pass filters correspond to the same set of multipliers and have different passbands.

[0065] <Second Configuration Example of Frequency Synthesizer 100> FIG. 3 shows a second configuration example of the frequency synthesizer 100 according to the present embodiment. The frequency synthesizer 100 of the second configuration example shows an example including three sets of a multiplier and a band-pass filter. The frequency synthesizer 100 further includes a third multiplier 83 and a third band-pass filter 93. The first switching unit 41 connects either one of the multipliers from the first multiplier 81 to the third multiplier 83 and the DDS 30 in accordance with the first control signal. The second switching unit 42 connects either one of the band-pass filters from the first band-pass filter 91 to the third band-pass filter 93 and the output unit 11 in accordance with the second control signal.

[0066] As described above, the frequency synthesizer 100 may further include one or more multipliers having a multiplication factor different from the multiplication factors of the first multiplier 81 and the second multiplier 82, and one or more band-pass filters respectively connected to the one or more multipliers. In other words, the frequency synthesizer 100 includes N multipliers (N is an integer of 3 or more) that multiply the frequencies of signals input with different multiplication factors, and N band-pass filters respectively connected to each of the plurality of multipliers.

[0067] In this case, the first switching unit 41 connects the DDS 30 and any one of the multipliers from the first multiplier 81 to the Nth multiplier in accordance with the first control signal. Then, the control unit 60 supplies the first switching unit 41 with a first control signal for connecting the multiplier that outputs a signal whose frequency difference exceeds a predetermined detuning frequency among the multipliers from the first multiplier 81 to the Nth multiplier and the DDS 30.

[0068] Similarly, the second switching unit 42 connects any one of the band-pass filters from the first band-pass filter 91 to the Nth band-pass filter and the output unit 11 in accordance with the second control signal. Then, the control unit 60 supplies the second switching unit 42 with a second control signal for connecting the band-pass filter connected to the multiplier connected to the DDS 30 and the output unit 11.

[0069] By adopting such a configuration, the frequency synthesizer 100 can improve the degree of freedom of parameters to be set when outputting an output signal with reduced spurs. Here, the parameters include the clock frequency of the clock signal, the frequency of the DDS signal, a predetermined offset frequency, the multiplication factor of the multiplier to be used, and the like. In addition, the number of settable frequencies that can be set as the output signal of the frequency synthesizer 100 can also be increased.

[0070] In the frequency synthesizer 100 according to the above-described embodiment, among the plurality of multipliers, an example has been described in which the multiplier used corresponding to the frequency of the output signal is specified and switched, and the multiplier corresponding to the frequency of the output signal is specified in advance and stored in the storage unit 61. Therefore, a method for specifying in advance the multiplier corresponding to the frequency of the output signal will be described.

[0071] <The first example of the operation flow for specifying the multiplier connected to DDS30> FIG. 4 shows a first example of an operation flow for specifying the multiplier connected to DDS30 of the frequency synthesizer 100 according to the present embodiment. The operation flow shown in FIG. 4 is executed, for example, in the manufacturing process of the frequency synthesizer 100, during the operation of the frequency synthesizer 100, and the like. The operation flow may be executed by the control unit 60 of the frequency synthesizer 100, or alternatively, may be executed by a computer such as a server separate from the frequency synthesizer 100.

[0072] In the present embodiment, a method for reducing the spurs included in the output signal output by the frequency synthesizer 100 will be described, where the frequency band of the output signal is set to 1500 MHz to 2000 MHz. As shown in FIG. 3, the frequency synthesizer 100 is assumed to include three multipliers. Here, the multiplication factor of the first multiplier 81 is 3, the multiplication factor of the second multiplier 82 is 4, and the multiplication factor of the third multiplier 83 is 5. Also, the spurs to be considered are up to the 10th order spurs.

[0073] First, set the multiplier of the frequency synthesizer 100 as the first multiplier 81 (start with the first multiplier 81 for the multiplier of the frequency synthesizer 100) (S20). Then, generate first spurious characteristic data in which the offset frequency with respect to the frequency of the output signal output from the frequency synthesizer 100 is specified and plotted (S21). Here, the offset frequency is the frequency difference between the frequency of the M-th spurious and the frequency of the output signal. The M-th spurious is a spurious generated in the output signal due to M-th harmonics (where M is an integer of 2 or more and a predetermined number or less) of a predetermined order or less included in the DDS signal output from the DDS 30. In the present embodiment, M is an integer of 2 or more and 10 or less.

[0074] FIG. 5 shows an example of the first spurious data of the frequency synthesizer 100 according to the present embodiment. The horizontal axis of the first spurious data indicates the frequency of the output signal of the frequency synthesizer 100, and the vertical axis indicates the offset frequency. FIG. 5 is a result obtained by calculating the first multiplied signal output from the first multiplier 81 as the output signal when the clock frequency of the clock signal is 3000 MHz. In other words, the frequency obtained by dividing the frequency of the output signal on the horizontal axis by 3 is the frequency of the DDS signal output from the DDS 30.

[0075] FIG. 5 shows an example of the result of plotting the offset frequencies of the second to tenth spurious included in the first multiplied signal. Such an offset frequency with respect to the frequency of the output signal can be calculated using Equation (1).

[0076] Next, in the first spurious characteristic data, extract the data with the smallest offset frequency for each frequency of the output signal, and generate second spurious characteristic data (S22). FIG. 6 shows an example of the second spurious data of the frequency synthesizer 100 according to the present embodiment. FIG. 6 shows the result of extracting the data with the smallest offset frequency for each frequency of the output signal from the first spurious data shown in FIG. 5. In other words, from FIG. 6, when the frequency of the output signal of the frequency synthesizer 100 is determined at a predetermined clock frequency, the offset frequency of the spurious closest to the frequency of the first multiplied signal of the first multiplier 81 can be specified.

[0077] Next, for each of the plurality of multipliers, the step of generating first spurious characteristic data (S21) and the step of generating second spurious characteristic data (S22) are repeated to generate a plurality of second spurious characteristic data corresponding to the plurality of multipliers (S20 to S23). For example, the second multiplier signal output from the second multiplier 82 is used as the output signal of the frequency synthesizer 100 to generate first spurious data and second spurious data. Next, the third multiplier signal output from the third multiplier 83 is used as the output signal of the frequency synthesizer 100 to generate first spurious data and second spurious data.

[0078] Next, frequency characteristic data is generated by drawing a plurality of second spurious characteristic data on the same graph (S24). FIG. 7 shows an example in which a plurality of second spurious data of the frequency synthesizer 100 according to the present embodiment are drawn on the same graph. More specifically, FIG. 7 shows an example in which three second spurious data generated based on three signals, namely, the first multiplier signal, the second multiplier signal, and the third multiplier signal, are drawn on the same graph.

[0079] Next, in the frequency characteristic data obtained by drawing a plurality of second spurious characteristic data on the same graph, data with the largest detuning frequency for each frequency of the output signal is extracted to generate third spurious characteristic data (S25). FIG. 8 shows an example of the third spurious data of the frequency synthesizer 100 according to the present embodiment. FIG. 8 shows the result of extracting data with the largest detuning frequency for each frequency of the output signal from the frequency characteristic data shown in FIG. 7.

[0080] In other words, from FIG. 8, at a predetermined clock frequency, when the frequency of the output signal of the frequency synthesizer 100 is determined, it is possible to identify the multiplier that outputs the multiplier signal including the spurious with the largest detuning frequency. Therefore, next, based on the third spurious characteristic data, among the plurality of multipliers, the multiplier connected to the DDS 30 corresponding to the frequency of the output signal of the frequency synthesizer 100 is identified (S26).

[0081] For example, identify the multiplier that outputs a signal corresponding to the data among the third spurious characteristic data that exhibits the maximum value of the offset frequency as the multiplier connected to DDS30. In the case of the example in FIG. 8, for example, in the range of the output signal of the frequency synthesizer 100 from 1589 MHz to 1661 MHz, since the data plotted as the offset frequency is the offset frequency of the second multiplication signal, the multiplier connected to DDS30 can be identified as the second multiplier 82.

[0082] Also, in the range of the output signal of the frequency synthesizer 100 from 1662 MHz to 1730 MHz, since the data plotted as the offset frequency is the offset frequency of the first multiplication signal, the multiplier connected to DDS30 can be identified as the first multiplier 81. Similarly, in the range of the output signal of the frequency synthesizer 100 from 1731 MHz to 1791 MHz, since the data plotted as the offset frequency is the offset frequency of the third multiplication signal, the multiplier connected to DDS30 can be identified as the third multiplier 83.

[0083] Alternatively, the multiplier that outputs a signal corresponding to the data among the third spurious characteristic data where the frequency difference exceeds a predetermined offset frequency may be identified as the multiplier connected to DDS30. For example, in the example of FIG. 8, identify the multiplier that outputs a multiplication signal with an offset frequency exceeding 100 MHz as the multiplier connected to DDS30.

[0084] For example, in the range of the output signal of the frequency synthesizer 100 from 1551 MHz to 1579 MHz, the offset frequencies of the first to third multiplication signals all exceed 100 MHz. Therefore, any one of the first multiplier 81, the second multiplier 82, and the third multiplier 83 can be identified as the multiplier connected to DDS30.

[0085] In addition, since the offset frequency of the second multiplication signal exceeds 100 MHz in the range of the output signal of the frequency synthesizer 100 from 1580 MHz to 1656 MHz, the second multiplier 82 can be specified as the multiplier connected to the DDS30. Similarly, since the offset frequency of the third multiplication signal exceeds 100 MHz in the range of the output signal of the frequency synthesizer 100 from 1723 MHz to 1812 MHz, the third multiplier 83 can be specified as the multiplier connected to the DDS30.

[0086] As described above, according to the operation flow of the present embodiment, the multiplier connected to the DDS30 of the frequency synthesizer 100 can be specified. It is desirable to store the information of the specified multiplier in the storage unit 61 in association with the clock frequency and the output signal of the frequency synthesizer 100. Thereby, the frequency synthesizer 100 can read the information stored in the storage unit 61 and specify the multiplier to be used corresponding to the frequency of the signal to be output. Therefore, as described above, the frequency synthesizer 100 can easily suppress the spurious signal intensity included in the output signal.

[0087] As described above, in the operation flow according to the present embodiment, an example of specifying the multiplier connected to the DDS30 with a clock frequency of 3000 MHz has been described, but the present invention is not limited thereto. For example, the multiplier connected to the DDS30 may be specified using a plurality of different clock frequencies. The operation of specifying such a multiplier will be described next.

[0088] <Second Example of Operation Flow for Specifying Multiplier Connected to DDS30> FIG. 9 shows a second example of the operation flow for specifying the multiplier connected to the DDS30 of the frequency synthesizer 100 according to the present embodiment. In the operation flow of the second example, the same reference numerals are given to the operations substantially the same as those in the operation flow shown in FIG. 4, and the overlapping description is omitted.

[0089] The operation flow of the second example executes steps S21 to generate first spurious characteristic data, S22 to generate second spurious characteristic data, and steps S23 to S24 to generate third spurious characteristic data for a plurality of predetermined clock frequencies to generate a plurality of third spurious characteristic data (S31 to S32).

[0090] Then, frequency characteristic data is generated by drawing the generated plurality of third spurious characteristic data on the same graph (S33). FIG. 10 shows an example of drawing a plurality of third spurious data of the frequency synthesizer 100 according to the present embodiment on the same graph. More specifically, FIG. 10 shows an example of drawing three third spurious data generated when the clock frequencies are 2000 MHz, 2500 MHz, and 3000 MHz on the same graph.

[0091] Next, in the frequency characteristic data obtained by drawing the plurality of third spurious characteristic data on the same graph, data with the largest detuning frequency for each output signal frequency is extracted to generate fourth spurious characteristic data (S34). FIG. 11 shows an example of the fourth spurious data of the frequency synthesizer 100 according to the present embodiment. FIG. 11 shows the result of extracting data with the largest detuning frequency for each output signal frequency from the frequency characteristic data shown in FIG. 10.

[0092] Then, in S26, based on the fourth spurious characteristic data, among the plurality of multipliers, the multiplier connected to the DDS30 corresponding to the frequency of the output signal of the frequency synthesizer is specified. The operation in S26 of the operation flow of the second example is to change the data used from the third spurious data to the fourth spurious data in the operation in S26 of the operation flow of the first example. Then, for example, the multiplier that outputs a signal corresponding to the data showing the maximum value of the detuning frequency among the fourth spurious characteristic data and the clock frequency are specified as the multiplier connected to the DDS30 and the clock frequency to be used.

[0093] Alternatively, a multiplier that outputs a signal corresponding to data in the fourth spurious characteristic data whose frequency difference exceeds a predetermined detuning frequency and a clock frequency may be specified as the multiplier connected to the DDS30 and the clock frequency used. As described above, also in the operation flow of the second example, the multiplier connected to the DDS30 of the frequency synthesizer 100 can be specified.

[0094] In the operation flow of the second example, by using a plurality of clock frequencies, the operating conditions of the frequency synthesizer 100 are increased, so that the detuning frequency can be increased in a wider band of the output signal. For example, in the band from 1500 MHz to 2000 MHz, in the third spurious characteristic data of FIG. 8, there is a frequency band where the detuning frequency is 100 MHz or less, but it can be seen that in the fourth spurious characteristic data of FIG. 11, all detuning frequencies exceed 100 MHz.

[0095] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of the gist. For example, all or part of the device can be configured by being functionally or physically distributed and integrated in an arbitrary unit. Also, new embodiments generated by any combination of a plurality of embodiments are included in the embodiments of the present invention. The effects of the new embodiments generated by the combination have the effects of the original embodiments combined.

Explanation of Reference Numerals

[0096] 10 Frequency synthesizer 11 Output unit 20 Clock signal source 30 DDS 41 First switching unit 42 Second switching unit 51 First narrowband filter 52 Second narrowband filter 60 Control unit 61 Storage unit 70 Amplification circuit 81 First multiplier 82 Second multiplier 83 Third multiplier 91 First band-pass filter 92 Second band-pass filter 93 Third band-pass filter 100 Frequency synthesizer

Claims

1. A method for reducing spurs of a frequency synthesizer executed by a computer, comprising: The frequency synthesizer includes: A clock signal source that outputs a clock signal; A DDS that outputs a DDS signal based on the clock signal output from the clock signal source; A plurality of multipliers that multiply the frequencies of signals input with different multiplication factors; A plurality of band-pass filters connected to each of the plurality of multipliers; A first switching unit that connects the DDS and any one of the plurality of multipliers in response to a first input control signal; The method for reducing spurs includes: Generating first spur characteristic data by identifying and plotting the frequency difference between the frequency of the output signal generated in the output signal due to Mth-order harmonics (M is an integer of 2 or more and a predetermined number or less) of a predetermined order or less included in the DDS signal with respect to the frequency of the output signal output from the frequency synthesizer; In the first spur characteristic data, extracting data with the smallest frequency difference for each frequency of the output signal to generate second spur characteristic data; Repeating the step of generating the first spur characteristic data and the step of generating the second spur characteristic data for each of the plurality of multipliers to generate a plurality of the second spur characteristic data corresponding to the plurality of multipliers; In the frequency characteristic data obtained by plotting the plurality of the second spur characteristic data on the same graph, extracting data with the largest frequency difference for each frequency of the output signal to generate third spur characteristic data; Based on the third spur characteristic data, identifying the multiplier to be connected to the DDS corresponding to the frequency of the output signal of the frequency synthesizer among the plurality of multipliers; And a method.

2. The method according to claim 1, wherein in the step of identifying the multiplier, the multiplier that outputs a signal corresponding to the data showing the maximum value of the frequency difference in the third spur characteristic data is identified as the multiplier to be connected to the DDS.

3. ​ In the step of identifying the multiplier, the multiplier that outputs a signal corresponding to data among the third spurious characteristic data whose frequency difference exceeds a predetermined detuning frequency is identified as the multiplier connected to the DDS, according to the method of claim 1.

4. The method according to claim 3, wherein the predetermined detuning frequency is a frequency greater than a half-value width of a pass frequency band of the plurality of band-pass filters.

5. The step of generating the first spurious characteristic data, the step of generating the second spurious characteristic data, and the step of generating the third spurious characteristic data are executed for a plurality of predetermined clock frequencies to generate a plurality of the third spurious characteristic data; In the frequency characteristic data obtained by drawing a plurality of the third spurious characteristic data on the same graph, data having the largest frequency difference for each frequency of the output signal is extracted to generate fourth spurious characteristic data; Based on the fourth spurious characteristic data, identifying the multiplier connected to the DDS corresponding to the frequency of the output signal of the frequency synthesizer among the plurality of multipliers; The method according to claim 1, further comprising:

6. A program which, when executed by a computer, causes the computer to execute the method according to any one of claims 1 to 5.

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