Display device

Abstract

SOLUTION: A display device includes: a substrate including a display region, an optical region including a through hole and arranged within the display region, and a non-display region surrounding the display region; a plurality of insulator layers arranged on a substrate; at least one dam arranged on the plurality of insulator layers; and at least one connection prevention part arranged on at least one insulator layer and closer to the through hole than at least one dam. A first trench is arranged in a part of the plurality of insulator layers which overlap at least one connection prevention part in the optical region.EFFECT: It is possible to prevent propagation of a crack generated by external interference in an optical region.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, provides a display device capable of blocking a crack propagation path in an area where a camera or a sensor is disposed.

Background Art

[0002] With the advent of the information age, the field of display devices for visually displaying electrical information signals has been rapidly developing, and research has continued to develop performance such as thinning, weight reduction, and low power consumption for various display devices.

[0003] Typical display devices include a liquid crystal display (LCD), a field emission display (FED), an electro-wetting display (EWD), an organic light emitting display (OLED), and the like.

[0004] The field emission display typified by the organic light emitting display is a self-luminous display device, and unlike the liquid crystal display, it does not require a separate light source and can be manufactured in a lightweight and thin form. In addition, the field emission display is not only advantageous in terms of power consumption due to low voltage driving, but also excellent in hue reproduction, response speed, viewing angle, and contrast ratio (CR), and is expected to be utilized in various fields.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved in one embodiment of this specification is to provide a display device capable of preventing cracks generated from external interference from propagating in an area where a camera or a sensor is disposed.

[0006] Another problem to be solved in other embodiments of the present specification is to provide a display device capable of ensuring product yield and reliability performance.

[0007] The problems of the present specification are not limited to the problems mentioned above, and other problems not mentioned may be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] The display device according to an embodiment of the present specification includes a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area surrounding the display area, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection prevention portion disposed on the plurality of insulating layers and disposed closer to the through hole than the at least one dam, and a first trench is disposed in a part of the plurality of insulating layers that overlaps the at least one connection prevention portion in the optical area.

[0009] Specific matters of other embodiments are included in the detailed description and the drawings.

[0010] The display device according to an embodiment of the present specification can form a plurality of connection prevention portions around the through hole to prevent the penetration of moisture and oxygen entering from the through hole. The prevention portion can cut off the connection of the organic common layer of the light-emitting element disposed on the front surface of the display panel, that is, the light-emitting layer, and block the movement path of moisture and oxygen.

[0011] The display device according to an embodiment of the present specification can dispose a plurality of dams near the plurality of connection prevention portions to prevent the organic insulating layer of the sealing layer from overflowing into the camera hole. The plurality of dams can prevent the contamination of the camera hole area that may occur when the organic insulating layer overflows into the camera hole and the interference with the camera disposed in the through hole.

[0012] The display device according to an embodiment of the present specification can prevent the crack from propagating by arranging trenches by etching a part of a plurality of inorganic insulating layers that overlap a plurality of crack prevention parts, so that even if a crack occurs in the through hole, the path through which the crack propagates is blocked.

[0013] The effects according to the present specification are not limited to the contents exemplified above, and more various effects are included in the present specification.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6a

Figure 6b

Figure 6c

Figure 6d

Figure 6e

Figure 7a

Figure 7b

Figure 7c

Figure 7d

Best Mode for Carrying Out the Invention

[0015] The advantages and features of this specification, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, and can be embodied in various different forms. Merely, these embodiments are provided so that the disclosure of this specification is complete, and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of one embodiment of this specification.

[0016] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so the embodiments of this specification are not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining one embodiment of this specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of one embodiment of this specification, that detailed description will be omitted. When terms such as "including", "having", "being made" are used in this specification, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0017] When interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0018] When it is an explanation of a positional relationship, for example, when the positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., as long as "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0019] An element or layer being referred to as "on" another element or layer includes both the case where there is another layer or another element immediately above the other element or intervening between them.

[0020] Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0021] Throughout the specification, the same reference numerals refer to the same components.

[0022] The areas and thicknesses of the respective configurations shown in the drawings are shown for convenience of explanation, and one embodiment of this specification is not necessarily limited to the areas and thicknesses of the shown configurations.

[0023] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various technical linkages and drives, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0024] Hereinafter, one embodiment of this specification will be described with reference to the drawings.

[0025] FIG. 1 is a block diagram of a display device according to one embodiment of this specification.

[0026] Referring to FIG. 1, a display device 100 of one embodiment of this specification can include a video processing unit 151, a timing controller 152, a data driving unit 153, a gate driving unit 154, and a display panel DP.

[0027] At this time, the video processing unit 151 can output a data signal DATA, a data enable signal DE, etc. supplied from the outside. The video processing unit 151 can output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE.

[0028] The timing controller 152 receives the supply of the data signal DATA together with a data enable signal DE or a drive signal including a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. from the video processing unit 151. The timing controller 152 can output a gate timing control signal GDC for controlling the operation timing of the gate driving unit 154 and a data timing control signal DDC for controlling the operation timing of the data driving unit 153 based on the drive signal.

[0029] Also, the data driving unit 153 can sample, latch, convert to a gamma reference voltage, and output the data signal DATA supplied from the timing controller 152 in response to the data timing control signal DDC supplied from the timing controller 152. The data driving unit 153 can output the data signal DATA through the data wirings DL1 to DLn.

[0030] Also, the gate driving unit 154 can output a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 152. The gate driving unit 154 can output the gate signal through the gate wirings GL1 to GLm.

[0031] The display panel DP can display an image while the pixel P emits light corresponding to the data signal DATA and the gate signal supplied from the data driving unit 153 and the gate driving unit 154. The detailed structure of the pixel P will be described in detail in FIG. 2.

[0032] The display panel DP can include a display area DA, an optical area OA disposed within the display area DA and including a through hole TH, and a non-display area NDA surrounding the display area DA.

[0033] The display area DA is an area where an image is displayed on the display panel DP.

[0034] In the display area DA, a number of pixels P and a circuit for driving the number of pixels P can be arranged. The number of pixels P is the minimum unit that constitutes the display area DA, and a display element can be arranged in each of the number of pixels P. For example, an organic light-emitting element including an anode, a light-emitting layer, and a cathode can be arranged in each of the number of pixels P, but it is not limited thereto. Further, the circuit for driving the number of pixels P may include a driving element, wiring, and the like. For example, the circuit may be composed of a thin-film transistor, a storage capacitor, a gate wiring, a data wiring, etc., but it is not limited thereto.

[0035] The optical area OA is an area that is arranged inside the display area DA and in which the through hole TH is arranged. The display panel DP can reduce the bezel area that is the non-display area (Non-display area) NDA where the through hole TH is arranged inside the display area DA and maximize the display area DA. A product with a design that maximizes the display area DA can maximize the user's sense of immersion in the screen and be more aesthetically pleasing.

[0036] The through hole TH can be formed to correspond to an optoelectronic device such as a camera or a light sensor.

[0037] There may be two through holes TH as shown in FIG. 1, but it is not limited thereto, and they can be arranged in various ways. For example, one or two holes may be arranged inside the display area DA, a camera may be arranged in the first hole, and a distance sensing sensor or a face recognition sensor and a wide-angle camera may be arranged in the second hole.

[0038] The non-display area NDA is an area where an image is not displayed.

[0039] The non-display area NDA can be bent and hidden by a case (not shown) that cannot be seen from the front, and is also called a bezel area.

[0040] In FIG. 1, although the non-display area NDA is shown as surrounding the rectangular display area DA, the form and arrangement of the display area DA and the non-display area NDA are not limited to the example shown in FIG. 1. That is, the display area DA and the non-display area NDA may be in a form suitable for the design of the electronic device equipped with the display device 100. For example, exemplary forms of the display area DA may be pentagonal, hexagonal, circular, elliptical, etc.

[0041] In the non-display area NDA, various wirings and circuits for driving the organic light-emitting elements of the display area DA can be arranged. For example, in the non-display area NDA, link wirings for transmitting signals to a large number of sub-pixels and circuits in the display area DA, GIP (Gate-In-Panel) wirings, or driving ICs such as the gate driving unit 154 and the data driving unit 153 can be arranged, but it is not limited thereto.

[0042] The display device 100 can further include various additional elements for generating various signals or driving the pixels within the display area DA. The additional elements for driving the pixels can include an inverter circuit, a multiplexer, an Electro Static Discharge (ESD) circuit, etc. The display device 100 can also include additional elements related to functions other than driving the pixels. For example, the display device 100 can further include additional elements for providing a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, a tactile feedback function, etc. The above-mentioned additional elements can be located in the non-display area NDA and / or an external circuit connected to the connection interface.

[0043] In the following, FIG. 2 will be referred to together for a more detailed description of the cross-sectional structure of the display area DA of the display device 100.

[0044] FIG. 2 is a cross-sectional view showing the cross-sectional structure of one pixel arranged in the display area according to an embodiment of the present specification.

[0045] The display device 100 according to an embodiment of the present specification may include a substrate 110, a first buffer layer 111, a first thin film transistor TR1, a second thin film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a connection electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode 145, a bank 116a, a spacer 116b, an anode 121, a light emitting layer 122, a cathode 123, a sealing layer 117, and a touch sensing unit.

[0046] The substrate 110 serves to support and protect the components of the flexible display device disposed thereon.

[0047] The substrate 110 is a structure for supporting various components included in the display device 100 and may be made of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. By configuring the substrate 110 in this way with the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c, moisture penetration can be prevented. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates, and the interlayer insulating film 110c may be made of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0048] A light shielding layer 125 may be disposed on the substrate 110.

[0049] The first buffer layer 111 may be disposed on the substrate 110 covering the light shielding layer 125. Specifically, a multi-buffer layer 111a may be disposed on the substrate 110 covering the light shielding layer 125, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0050] The multi-buffer layer 111a can delay the diffusion of moisture or oxygen that has penetrated the substrate 110 and can contain at least one of silicon nitride (SiNx) and silicon oxide (SiOx).

[0051] The active buffer layer 111b can protect the first active layer A1 and block various types of defects flowing in from the substrate 110. For example, the active buffer layer 111b can contain at least one of a-Si, silicon nitride (SiNx), and silicon oxide (SiOx).

[0052] The first thin-film transistor TR1 can be disposed on the first buffer layer 111. The first thin-film transistor TR1 can include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. Here, depending on the design of the pixel circuit, the first source electrode S1 can become the first drain electrode, and the first drain electrode D1 can become the first source electrode.

[0053] The first active layer A1 can be disposed on the first buffer layer 111 so as to overlap with the light-shielding layer 125. The first active layer A1 can contain amorphous silicon or polycrystalline silicon. For example, the first active layer A1 can contain low-temperature polycrystalline silicon (LTPS). For example, the polycrystalline silicon material has a high mobility (100 cm 2Since it has a voltage of / Vs or higher, low energy consumption power, and excellent reliability, it can be applied to a gate driver for a driving element that drives a thin film transistor for a display element and / or a multiplexer (MUX), etc. In the display device 100 according to an embodiment of the present specification, it can be applied to the first active layer A1 of the driving thin film transistor, but is not limited thereto. For example, depending on the characteristics of the display device 100, it can also be applied to the second active layer A2 of the switching thin film transistor. An amorphous silicon (a-Si) material is deposited on the first buffer layer 111, and polysilicon is formed by performing a dehydrogenation process and a crystallization process, and the polysilicon is patterned to form the first active layer A1. Here, the first active layer A1 can include a first channel region where a channel is formed when the first thin film transistor TR1 is driven, a first source region and a first drain region on both sides of the first channel region. The first source region means a portion of the first active layer A1 connected to the first source electrode S1, and the first drain region means a portion of the first active layer A1 connected to the first drain electrode D1. For example, the first source region and the first drain region can be formed by ion doping (impurity doping) of the first active layer A1. The first source region and the first drain region can be generated by ion doping the polysilicon material, and the first channel region can mean the portion left of the polysilicon material without ion doping.

[0054] A first gate insulating layer 112a can be disposed on the first active layer A1. The first gate insulating layer 112a can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. Contact holes can be formed in the first gate insulating layer 112a for connecting the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 to the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1, respectively.

[0055] On the first gate insulating layer 112a, the first gate electrode G1 of the first thin film transistor TR1 and the first capacitor electrode C1 of the storage capacitor Cst can be arranged.

[0056] At this time, the first gate electrode G1 and the first capacitor electrode C1 can be formed of a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The first gate electrode G1 can be formed on the first gate insulating layer 112a so as to overlap with the first channel region of the first active layer A1 of the first thin film transistor TR1.

[0057] The first capacitor electrode C1 may be omitted based on the driving characteristics of the display device 100, the structure and type of the thin film transistor, etc. The first gate electrode G1 and the first capacitor electrode C1 can be formed by the same process. And the first gate electrode G1 and the first capacitor electrode C1 can be formed of the same material and formed on the same layer.

[0058] The first interlayer insulating layer 113a can be arranged on the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. And contact holes for exposing the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1 can be formed in the first interlayer insulating layer 113a.

[0059] The second capacitor electrode C2 of the storage capacitor Cst can be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 can be formed of a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The second capacitor electrode C2 can be formed on the first interlayer insulating layer 113a so as to overlap with the first capacitor electrode C1. Also, the second capacitor electrode C2 can be formed of the same material as the first capacitor electrode C1. The second capacitor electrode C2 may be omitted based on the driving characteristics of the display device 100 and the structure and type of the thin film transistor, etc.

[0060] The second buffer layer 114 can be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. Contact holes may be formed in the second buffer layer 114 to expose the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1. Also, contact holes may be formed in the second buffer layer 114 to expose the second capacitor electrode C2 of the storage capacitor Cst.

[0061] The second buffer layer 114 can also be formed as a multilayer, but is not limited thereto.

[0062] The second active layer A2 of the second thin film transistor TR2 can be disposed on the second buffer layer 114. Here, the second thin film transistor TR2 can include the second active layer A2, the second gate insulating layer 112b, the second gate electrode G2, the second source electrode S2, and the second drain electrode D2. Here, depending on the design of the pixel circuit, the second source electrode S2 can become the drain electrode, and the second drain electrode D2 can become the source electrode.

[0063] Further, the second active layer A2 may include a second channel region where a channel is formed when the second thin film transistor TR2 is driven, a second source region and a second drain region on both sides of the second channel region. The second source region may mean a portion of the second active layer A2 connected to the second source electrode S2, and the second drain region may mean a portion of the second active layer A2 connected to the second drain electrode D2.

[0064] The second active layer A2 may be made of an oxide semiconductor. Since the oxide semiconductor material has a larger bandgap compared to the silicon material, electrons cannot cross the bandgap in the off state, thereby resulting in a low off-current. Therefore, a thin film transistor including an active layer made of an oxide semiconductor may be suitable for a switching thin film transistor having a short on-time and a long off-time, but is not limited thereto. Depending on the characteristics of the display device 100, it may be applied to the driving thin film transistor. And since the off-current is small, the size of the auxiliary capacitor may be reduced, so it is suitable for a high-resolution display element. For example, the second active layer A2 may be made of a metal oxide and may be made of various metal oxides such as IGZO (indium-gallium-zinc-oxide). Here, it has been described assuming that the second active layer A2 of the second thin film transistor TR2 is formed of IGZO among various metal oxides, but it is not limited thereto and may be formed of other metal oxides such as IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), or IGO (indium-gallium-oxide) that are not IGZO.

[0065] The second active layer A2 may be formed by depositing a metal oxide on the second buffer layer 114, performing a heat treatment process for stabilization, and then patterning the metal oxide.

[0066] The second gate insulating layer 112b can be disposed over the entire substrate 110 including the second active layer A2. For example, the second gate insulating layer 112b can be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0067] A second gate electrode G2 can be disposed over the second gate insulating layer 112b.

[0068] The second gate electrode G2 can be formed of a single layer or multiple layers composed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0069] For example, a metal material is formed over the second gate insulating layer 112b, a photoresist pattern is formed over the metal material, and then the metal material is wet-etched using the photoresist pattern as a mask to form the second gate electrode G2. A wet etching solution for etching the metal material can be a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof that constitute the metal material and does not etch insulating materials.

[0070] A second interlayer insulating layer 113b can be disposed over the second gate insulating layer 112b and the second gate electrode G2. Contact holes for exposing the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 can be formed in the second interlayer insulating layer 113b. For example, contact holes for exposing the first source region and the first drain region of the first active layer A1 in the first thin film transistor TR1 can be formed in the second interlayer insulating layer 113b. Contact holes for exposing the second source region and the second drain region of the second active layer A2 in the second thin film transistor TR2 can be formed in the second interlayer insulating layer 113b.

[0071] The second interlayer insulating layer 113b can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of these.

[0072] On the second interlayer insulating layer 113b, a connection electrode CE, a first source electrode S1 and a first drain electrode D1 of the first thin film transistor TR1, and a second source electrode S2 and a second drain electrode D2 of the second thin film transistor TR2 can be arranged.

[0073] The connection electrode CE can be electrically connected to the second drain electrode D2 of the second thin film transistor TR2. And the connection electrode CE can be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through contact holes formed in the second buffer layer 114 and the second interlayer insulating layer 113b. That is, the connection electrode CE can play a role of electrically connecting the second capacitor electrode C2 of the storage capacitor Cst and the second drain electrode D2 of the second thin film transistor TR2.

[0074] Here, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 can be connected to the first active layer A1 of the first thin film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, and the second interlayer insulating layer 113b.

[0075] The second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be connected to the second active layer A2 through contact holes formed in the second interlayer insulating layer 113b.

[0076] The connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be formed of the same material by the same process.

[0077] For example, the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be formed of a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof. For example, the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be formed in a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but is not limited thereto.

[0078] The connecting electrode CE can be formed integrally connected to the second drain electrode D2 of the second thin film transistor TR2, but is not limited thereto.

[0079] The first planarization layer 115a can be disposed on the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2, and the upper portion of the second interlayer insulating layer 113b.

[0080] The first planarization layer 115a may be an organic layer for planarizing and protecting the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2. For example, the first planarization layer 115a can be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0081] The auxiliary electrode 145 can be disposed on the first planarization layer 115a. The auxiliary electrode 145 can be connected to the second drain electrode D2 of the second thin film transistor TR2 through the contact hole of the first planarization layer 115a. The auxiliary electrode 145 can serve to electrically connect the second thin film transistor TR2 and the anode 121. And the auxiliary electrode 145 can be formed of a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The auxiliary electrode 145 can be formed of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2.

[0082] The second planarization layer 115b can be disposed on the auxiliary electrode 145 and the first planarization layer 115a. For example, the second planarization layer 115b can be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0083] The light emitting element 120 can be disposed on the second planarization layer 115b.

[0084] The anode 121 can be disposed on the second planarization layer 115b. At this time, the anode 121 can be electrically connected to the auxiliary electrode 145 through the contact hole provided in the second planarization layer 115b. The anode 121 can be formed of a metallic material.

[0085] When the display device 100 is of the top emission type in which the light emitted by the light-emitting element 120 is emitted above the substrate 110 on which the light-emitting element 120 is disposed, the anode 121 can further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer can be made of a transparent conductive oxide such as ITO, IZO, etc., and the reflective layer can be made of, for example, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof, etc.

[0086] The bank 116a can be disposed while covering the anode 121. A portion of the bank 116a corresponding to the light-emitting region of the sub-pixel can be open. A part of the anode 121 can be exposed in the open portion (hereinafter referred to as the open region) of the bank 116a. At this time, the bank 116a can be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or an organic insulating material such as a benzocyclobutene-based resin, an acrylic-based resin, or an imide-based resin, but is not limited thereto. A spacer 116b can be further disposed on the bank 116a.

[0087] The light-emitting layer 122 can be disposed in the open region of the bank 116a and its periphery. Thereby, the light-emitting layer 122 can be disposed on the anode 121 exposed through the open region of the bank 116a.

[0088] The cathode 123 can be disposed on the light-emitting layer 122.

[0089] The light-emitting element 120 can be formed by the anode 121, the light-emitting layer 122, and the cathode 123. The light-emitting layer 122 can include a number of organic films.

[0090] The sealing layer 117 can be located on the above-described light-emitting element 120.

[0091] The encapsulation layer 117 may have a single-layer structure or a multi-layer structure. For example, the encapsulation layer 117 may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0092] At this time, the first encapsulation layer 117a and the third encapsulation layer 117c may be formed of an inorganic film, and the second encapsulation layer 117b may be formed of an organic film. Among the first encapsulation layer 117a, the second encapsulation layer 117b, and the third encapsulation layer 117c, the second encapsulation layer 117b is the thickest and can serve as a planarization layer.

[0093] The first encapsulation layer 117a is disposed on the cathode 123 and may be disposed so as to be most adjacent to the light-emitting element 120. The first encapsulation layer 117a may be formed of an inorganic insulating material capable of low-temperature evaporation. For example, the first encapsulation layer 117a may be composed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Since the first encapsulation layer 117a is deposited in a low-temperature atmosphere, it is possible to prevent the light-emitting layer 122 containing organic substances, which is vulnerable to a high-temperature atmosphere, from being damaged during the deposition process.

[0094] The second encapsulation layer 117b may be formed in an area smaller than that of the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed so as to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b can serve as a buffer to relieve the stress between layers due to the warpage of the flexible display device and as a role to enhance the planarization performance.

[0095] For example, the second encapsulation layer 117b may be composed of an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or a silicon oxycarbide (SiOC). For example, the second encapsulation layer 117b may be formed through an inkjet method, but is not limited thereto.

[0096] The third encapsulation layer 117c can be formed to cover the upper surfaces and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a on the substrate 110 on which the second encapsulation layer 117b is formed. At this time, the third encapsulation layer 117c can minimize or block the penetration of external moisture and oxygen into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c can be composed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0097] A touch sensing layer can be disposed on the encapsulation layer 117.

[0098] For example, a touch buffer layer 118a can be disposed on the third encapsulation layer 117c, and a touch electrode TE can be disposed on the touch buffer layer 118a.

[0099] The touch electrode TE can include a touch sensor metal TS and a bridge metal BM located in different layers. A touch interlayer insulating layer 118b can be disposed between the touch sensor metal TS and the bridge metal BM.

[0100] The touch buffer layer 118a and the touch interlayer insulating layer 118b can be disposed to eliminate the step at the location where the touch electrode TE is disposed and to be electrically well insulated.

[0101] On the other hand, although not shown in the figure, a polarizing layer can be disposed on the touch sensing layer.

[0102] The polarizing layer suppresses the reflection of external light on the display area DA of the substrate 110. When the display device 100 is used externally, external natural light may flow in and be reflected by the reflective layer included in the anode 121 of the light emitting element 120, or may be reflected by an electrode composed of metal disposed under the light emitting element 120. In this way, the image of the display device 100 may not be visible due to the reflected light. The polarizing layer polarizes the light flowing in from the outside in a specific direction and prevents the reflected light from being emitted outside the display device 100.

[0103] Although not shown, a cover glass may be adhered to the polarizing layer by an adhesive layer. The adhesive layer can serve to adhere the respective components of the display device 100 to each other, and can be formed, for example, using an optically transparent display adhesive such as a pressure-sensitive adhesive, an optical clear adhesive (OCR), an optical clear resin (OCR), etc., but is not limited thereto.

[0104] The cover glass can protect the components of the display device 100 from external impacts and prevent damage such as scratches from occurring.

[0105] FIG. 3 is a plan view showing an enlarged view of region A corresponding to the optical region of FIG. 1.

[0106] Referring to FIG. 3, in the optical region OA, there is a through hole TH for arranging an optoelectronic device in the center, where a camera module or a sensor can be arranged. The optical region OA can include the circular or elliptical through hole TH and all regions where adjacent dam structures 300, connection prevention parts 200, etc. are arranged. The through hole TH can be removed by a laser in the panel completion step. The non-display region NDA can be located between the through hole TH and the display region DA, and high-potential power supply wirings PL, gate wirings SL, etc. can be arranged. A connection prevention part 200 and a dam structure 300 can be arranged around the through hole TH. Referring to FIG. 3, the connection prevention part 200 can be composed of a first prevention part 210 and a second prevention part 220, and the dam structure 300 can be composed of a first dam 301 and a second dam 302. The first prevention part 210, the first dam 301, the second prevention part 220, and the second dam 302 can be sequentially arranged centering on the through hole TH. Generally, the dam structure can be for the purpose of preventing a part of the second sealing layer 117b, which is a part of the sealing layer 117, from slipping down to the end of the outer contour part of the display panel DP, and maintaining the adhesive force between the upper substrate and the lower substrate constituting the display panel DP. The dam structure 300 in the optical region OA can also be formed by a plurality of structures such as the first dam 301 and the second dam 302 to prevent the second sealing layer 117b of the sealing layer 117 for protecting the light-emitting element 120 from invading or leaking into the optical region OA. The connection prevention part 200 can be formed to cut off the connection of the light-emitting layer 122 and prevent the penetration of moisture or oxygen. Although two dams are proposed in this specification, it is not limited thereto, and further dam arrangements are possible depending on the arrangement of the space. Referring to FIG. 3, the first prevention part 210 is arranged near the through hole TH, and then the first dam 301, the second prevention part 220, and the second dam 302 can be sequentially arranged. The first prevention part 210 and the second prevention part 220 can be arranged for the purpose of protecting the light-emitting element 120 in the display region from moisture or oxygen that can flow in from the through hole TH. The light-emitting layer 122 of the light-emitting element 120 can be deposited on the front surface of the display panel DP, but can also be uniformly deposited in the optical region OA. Due to the characteristics of the organic material, the light-emitting layer 122 has high reactivity and propagativeness to moisture and oxygen and can transmit moisture and oxygen to the light-emitting element 120 in the display region DA.To prevent this, the first and second prevention parts 210 and 220 can be configured to partially disconnect the light-emitting layer 122. Although two prevention parts are shown in this specification, the present invention is not limited thereto.

[0107] Although the light-emitting element 120 and the pixel circuit in the corresponding region are removed by the arrangement of the optical region OA, the light-emitting elements 120 and the pixel circuits arranged above, below, left, and right with respect to the optical region OA must be electrically connected. For this purpose, the high-potential power supply wiring PL, the gate wiring SL, etc. can be arranged in the non-display region NDA adjacent to the optical region OA so as to be connected vertically and horizontally by detouring through the through-hole TH.

[0108] FIG. 4 is a plan view showing an enlarged view of the B region in FIG. 3.

[0109] Referring to FIG. 4, the first prevention part 210 is arranged near the through-hole TH, a first dam 301 can be arranged between the first prevention part 210 and the second prevention part 220, and a second dam 302 can be arranged on the right side of the second prevention part 220. The first prevention part 210 includes a first structure 211, a second structure 212, a third structure 213, and a fourth structure 214, and the second prevention part 220 can include a fifth structure 221, a sixth structure 222, a seventh structure 223, and an eighth structure 224. Referring to FIGS. 3 and 4, it can be seen that the first prevention part 210, the first dam 301, the second prevention part 220, and the second dam 302 are arranged in a closed loop shape around the through-hole TH. The reason for arranging the first prevention part 210, the first dam 301, the second prevention part 220, and the second dam 302 in a closed loop shape is that if there is an opening even at one place, moisture and oxygen may penetrate from the outside into the display region DA, or conversely, the second sealing layer 117b may overflow from the inside into the optical region OA and further into the through-hole TH. Referring to FIG. 4, the first prevention part 210 and the second prevention part 220 can be composed of four structures each, but the present invention is not limited thereto. For example, the structure can be composed of three or less or five or more structures, but the present invention is not limited thereto.

[0110] FIG. 5 is a cross-sectional view taken along the line V-V' of the optical region in FIG. 4.

[0111] A first prevention part 210 and a second prevention part 220 are arranged in a closed-loop shape around the through hole TH, a first dam 301 is arranged between the first prevention part 210 and the second prevention part 220, and second dams 302 can be respectively arranged in a closed-loop shape on other side surfaces of the second prevention part 220. Referring to FIG. 5, the through hole TH can be arranged near the first prevention part 210.

[0112] As described with reference to FIG. 4, the first prevention part 210 can include first structures 211 to fourth structures 214. The first structures 211 to fourth structures 214 can be formed in an upper and lower two-stage structure for cutting off the moisture permeation path of the light-emitting layer 122 that can become a moisture permeation path from the region where the through hole TH is arranged, and an undercut structure can be formed on the upper side surface. Specifically, the upper parts of the first structures 211 to fourth structures 214 are arranged to have a trapezoidal cross-section with a positive taper, and the lower parts are arranged to have a rectangular cross-section with a side surface having an inverse taper or a constant height close to vertical, so that a width difference can occur between the lower upper surface and the upper lower surface which is the contact point between the upper and lower parts. Since the lower upper surface can be formed thinner than the upper lower surface, an undercut structure in which a part of the upper lower surface is exposed can be formed. Thereby, the light-emitting layer 122 vapor-deposited on the front surface of the display panel DP can be cut off by the undercut structure on the upper side surface of the first structures 211 to fourth structures 214 described above.

[0113] The first structures to fourth structures 211, 212, 213, 214 constituting the first prevention part 210 can be made of an organic material and an inorganic material. For example, the upper parts of the first structures to fourth structures 211, 212, 213, 214 can be made of the same material as the first planarization layer 115a or the second planarization layer 115b, but are not limited thereto. Also, the lower parts of the first structures to fourth structures 211, 212, 213, 214 can be made of the same material as the second interlayer insulation layer 113b, but are not limited thereto.

[0114] The second prevention part 220 can include a fifth structure 221 to an eighth structure 224. The fifth structure 221 to the eighth structure 224 that constitute the second prevention part 220 can be formed in a two-stage structure of an upper part and a lower part like the first structure 211 to the fourth structure 214. The second sealing layer 117b disposed on the second prevention part 220 makes it difficult for moisture and oxygen to penetrate from above, and in order to block the penetration path mainly on the side where the through holes TH and the first prevention part 210 are disposed, an undercut structure can be formed on the upper side surface in the same manner as the first prevention part 210. By the arrangement of the first prevention part 210 and the second prevention part 220, moisture and oxygen that penetrate through the light-emitting layer 122 to the light-emitting element 120 in the display area DA in the optical area OA can be stopped.

[0115] The fifth structure to the eighth structure 221, 222, 223, 224 that constitute the second prevention part 220 can also be made of an organic material and an inorganic material. For example, the upper part of each of the fifth structure to the eighth structure 221, 222, 223, 224 can be made of the same material as the first planarization layer 115a or the second planarization layer 115b, but is not limited thereto. The lower part of each of the fifth structure to the eighth structure 221, 222, 223, 224 can be made of the same material as the second interlayer insulation layer 113b, but is not limited thereto.

[0116] As shown in FIG. 5, the first dam 301 and the second dam 302 can be formed by laminating the second planarization layer 115b, the bank 116a, and the spacer 116b, but are not limited thereto, and may further include the first planarization layer 115a or other layers.

[0117] Referring to both Fig. 3, the optical region OA can vary depending on the size of the camera applied to the product. Although the corresponding region is shown as an empty space, an insulating film or wiring structure may be partially arranged therein. However, since it is a dummy region that does not remain in the finished product when removing the through-hole TH with a laser, separate representation is omitted. The laser can be irradiated in a circular or elliptical shape along the form of the optical region OA, and all regions above the substrate including the substrate 110 can be removed through the laser irradiation. There may be a difference between the actual optical region OA and the laser irradiation region. For example, in the optical region OA, the laser irradiation region may be an inner region about 100 μm deeper. Only in this way can the insulating layer in the optical region OA be prevented from being damaged during laser irradiation when there is a difference between the laser irradiation region and the optical region OA. The laser can use a picosecond laser or a femtosecond laser, but is not limited thereto. The laser utilizes the light amplified by adding energy to a specific material to generate induced emission, has characteristics like radio waves, has directivity in monochromatic light, and is used for communication, medical, and industrial applications. By using the laser, a pattern can be formed at a desired site or a specific site can be easily removed. The laser forms or removes a pattern using energy. When the energy of the laser is irradiated onto the subject, the thermal energy melts the subject to form a pattern. The longer the time the laser is irradiated, the more likely a thermal effect is generated in the vicinity of the portion where the pattern is formed. Such a thermal effect can cause heat to accumulate around the laser irradiation region of the subject, and the surrounding region larger than the set pattern can be burned or deformed by heat. Due to such characteristics of the laser, if the region irradiated by the laser overlaps or is adjacent to the insulating film, the thermal energy of the laser can also cause deformation in the insulating film. Cracks may occur due to the deformation of the insulating film, and the cracks may propagate through the insulating film, resulting in peeling or penetration of moisture and oxygen due to this.For example, in order to prevent deformation and peeling of insulating films such as the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, all the insulating films can be removed at a distance of about 100 μm from the laser irradiation position.

[0118] Cracks generated during the cutting of the substrate 110 through the laser have a problem of being transmitted through the inorganic insulating layer. While moisture or oxygen is characterized by reacting with the light-emitting layer 122 of the light-emitting element 120 and being transmitted, the cracks can be transmitted through the rigid inorganic insulating layer that is not flexible. Or, cracks due to interference may occur during the assembly of a camera or sensor in the through hole TH formed by the laser. The cracks generated at this time can also be propagated through the inorganic insulating layer. When the cracks generated in the through hole TH are propagated through the inorganic insulating layer, line defects or GDS (growing dark spot) defects may occur.

[0119] Therefore, in the display device 100 according to an embodiment of the present specification, by arranging the first trench T1 in a part of the plurality of insulating layers arranged in the optical region OA, a stepped structure can be formed in the plurality of insulating layers to block the crack propagation path.

[0120] FIG. 6a is a cross-sectional view showing an enlarged view of the C region of FIG. 5 according to an embodiment of the present specification.

[0121] Referring to FIGS. 5 and 6a, according to an embodiment of the present specification, it can include the first trench T1 arranged in a part of the plurality of insulating layers that overlap at least one connection prevention portion 200 in the optical region OA. For example, the plurality of insulating layers may be at least one or more of the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b arranged on the substrate 110, and the first trench T1 may be arranged in a part of the insulating layers arranged at the upper part of the plurality of insulating layers.

[0122] Specifically, referring to both FIGS. 3 and 6a, a plurality of insulating layers that overlap at least one crack prevention portion 200 disposed in the optical region OA, that is, at least a part of the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b can be included in the first trench T1 that is etched.

[0123] A stepped structure can be formed in the plurality of insulating layers by the first trench T1. Thus, even if a crack occurs in the via hole TH, since the inorganic insulating layer in the region where the first trench T1 is formed and through which the crack propagates is removed, the propagation of the crack can be prevented.

[0124] Also, according to an embodiment of the present specification, at least one of the first planarization layer 115a or the second planarization layer 115b can be disposed in the first trench T1 to fill the inside of the first trench T1.

[0125] According to an embodiment of the present specification, by removing a part of the plurality of inorganic insulating layers through which the crack propagates to form the first trench T1 and filling the inside of the first trench T1 with an organic material, when a crack occurs in the via hole TH, the crack does not need to propagate further in the first trench T1.

[0126] Although the first trench disposed in the optical region OA is shown in FIGS. 5 and 6a, the first trench in the optical region OA according to an embodiment of the present specification is not limited thereto.

[0127] FIG. 6b is a cross-sectional view of a display device according to another embodiment of the present specification. FIG. 6c is a cross-sectional view of a display device according to still another embodiment of the present specification. FIG. 6d is a cross-sectional view of a display device according to still another embodiment of the present specification. FIG. 6e is a cross-sectional view of a display device according to still another embodiment of the present specification.

[0128] As shown in FIG. 6b, the display device 1000 according to another embodiment of the present specification may further include a second trench T2 disposed in a part of a plurality of insulating layers that overlap with the dam structure 300, together with a first trench T1 that overlaps with at least one connection prevention portion 200 disposed in the optical region OA.

[0129] Specifically, as shown in FIG. 6b, the optical region OA includes a first trench T1 in which at least a part of the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b that overlap with at least one connection prevention portion 200 is etched, and a first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b that overlap with the dam structure 300. It may include a second trench T2 in which at least a part of the layer 113b is etched.

[0130] Therefore, in the display device 1000 according to another embodiment of the present specification, by disposing the first trench T1 and the second trench T2 in the optical region OA, even if a crack occurs when forming the through hole TH in the optical region OA or when assembling an optoelectronic device in the through hole TH, the first trench T1 and the second trench T2 block the crack propagation path, and defects due to crack propagation can be prevented.

[0131] For example, after forming a plurality of insulating layers, the depths of the first trench T1 and the second trench T2 disposed in a part of the plurality of insulating layers can be adjusted using a mask process. At this time, the first trench T1 and the second trench T2 can be formed by the same mask process.

[0132] The depths of the first trench T1 and the second trench T2 can be adjusted by changing the conditions of the mask process as needed.

[0133] FIG. 6c is a cross-sectional view of a display device according to still another embodiment of the present specification.

[0134] As shown in FIG. 6c, in the display device 1100 according to another embodiment of the present specification, the first trench T1 and the second trench T2 respectively overlap at least one connection prevention part 200 and the dam structure 300, and can be arranged in at least a part of the gate metal GM arranged in the same layer as the gate electrode G1 of the first thin film transistor, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0135] FIG. 6d is a cross-sectional view of a display device according to another embodiment of the present specification. FIG. 6e is a cross-sectional view of a display device according to another embodiment of the present specification.

[0136] As shown in FIG. 6d, in the display device 1200 according to another embodiment of the present specification, the first trench T1 and the second trench T2 respectively overlap at least one connection prevention part 200 and the dam structure 300, and can be arranged in at least a part of the light shielding layer 125, the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0137] FIG. 6e is a cross-sectional view of a display device according to another embodiment of the present specification.

[0138] As shown in FIG. 6e, in the display device 1300 according to another embodiment of the present specification, the first trench T1 and the second trench T2 respectively overlap at least one connection prevention part 200 and the dam structure 300, and can be arranged in at least a part of the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0139] According to still other embodiments of the present specification, by arranging the first trench T1 and the second trench T2 in the optical region OA, even if cracks occur during the formation of the through hole TH in the optical region OA or during the assembly of the optoelectronic device in the through hole TH, the first trench T1 and the second trench T2 block the propagation path of the cracks, and it is possible to prevent defects due to crack propagation.

[0140] Also, according to still other embodiments of the present specification, the first trench T1 and the second trench T2 are arranged so as to overlap at least one crack prevention portion 200 and the dam structure 300 in the optical region OA respectively, so that a separate space for preventing crack propagation is not required, and thus the non-display region NDA adjacent to the optical region OA can be minimized.

[0141] In the following, FIG. 7 will be referred to together for a more detailed description of the optical region OA of the display device according to still other embodiments of the present specification.

[0142] FIG. 7a is a cross-sectional view of a display device according to still other embodiments of the present specification. FIG. 7b is a cross-sectional view of a display device according to still other embodiments of the present specification. FIG. 7c is a cross-sectional view of a display device according to still other embodiments of the present specification. FIG. 7d is a cross-sectional view of a display device according to still other embodiments of the present specification. The cross-sectional views of FIGS. 7a to 7d are substantially the same in other configurations except for the first and second metal layers as compared with the cross-sectional views of FIGS. 6a to 6e. Therefore, for the sake of convenience of explanation, the overlapping explanations except for the first and second metal layers are omitted.

[0143] In the display device 1400 according to still other embodiments of the present specification, the first trench T1 and the second trench T2 may further include a first metal layer 410 disposed along the surface of a part of the plurality of insulating layers respectively.

[0144] For example, the first metal layer 410 may be disposed so as to be in contact with the surfaces of the plurality of insulating layers in the first trench T1 and the second trench T2 respectively.

[0145] As shown in FIG. 7a, a first metal layer 410 can be disposed inside the first trench T1 and inside the second trench T2 so as to be in contact with the surfaces of a plurality of insulating layers. For example, the first metal layer 410 can be made of the same material as the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1.

[0146] In the display device 1400 according to another embodiment of the present specification, the step structure of the plurality of insulating layers formed by the first trench T1 and the second trench T2 blocks the propagation path of cracks. Further, the first metal layer 410 disposed so as to be in contact with the surfaces of the plurality of insulating layers inside the first trench T1 and the second trench T2 further blocks the propagation of cracks. Even if cracks occur when forming the through hole TH in the optical region OA or when assembling an optoelectronic device in the through hole TH, the first trench T1, the second trench T2, and the first metal layer 410 completely block the propagation path of the cracks, thereby preventing defects caused by crack propagation.

[0147] FIG. 7a shows the structure of the first metal layer 410 disposed along the surfaces of some of the plurality of insulating layers in each of the first trench T1 and the second trench T2 in the optical region OA. However, the structure of the optical region OA according to an embodiment of the present specification is not limited thereto.

[0148] FIG. 7b is a cross-sectional view of a display device according to another embodiment of the present specification.

[0149] In the display device 1500 according to another embodiment of the present specification, a second metal layer 520 disposed under each of the first trench T1 and the second trench T2 in the optical region OA can be further included.

[0150] For example, as shown in FIG. 7b, the first metal layer 510 contacts the side surfaces of some of the plurality of insulating layers at the first trench T1 and the second trench T2, respectively, and the first metal layer 510 and the second metal layer 520 can contact each other. For example, the first metal layer 510 is disposed in the same layer as the first source electrode S1 and the first drain electrode D1 and is made of the same material, and the second metal layer 520 can be disposed in the same layer as the first gate electrode G1 and made of the same material.

[0151] In the display device 1500 according to another embodiment of the present specification, the step structure of the plurality of insulating layers formed by the first trench T1 and the second trench T2 blocks the crack propagation path. Further, the first metal layer 510 and the second metal layer 520 respectively disposed inside and below the first trench T1 and the second trench T2 further block the crack propagation path. Even when cracks occur during the formation of the through hole TH in the optical region OA or when assembling the optoelectronic device into the through hole TH, the first trench T1, the second trench T2, the first metal layer 510, and the second metal layer 520 completely block the crack propagation path, and defects caused by crack propagation can be prevented.

[0152] According to another embodiment of the present specification, the depths of the first trench T1 and the second trench T2 disposed in a part of the plurality of insulating layers can be adjusted. At this time, the materials for forming the first metal layer 510 and the second metal layer 520 can be different depending on the depths of the first trench T1 and the second trench T2.

[0153] FIG. 7c is a cross-sectional view of a display device according to another embodiment of the present specification. As shown in FIG. 7c, in the display device 1600 according to another embodiment of the present specification, the first metal layer 610 is made of the same material as the first source electrode S1 and the first drain electrode D1, and the second metal layer 620 can be made of the same material as the light shielding layer 125.

[0154] FIG. 7d is a cross-sectional view of a display device according to still another embodiment of the present specification. As shown in FIG. 7d, in the display device 1700 according to still another embodiment of the present specification, the second metal layer 720 is disposed to contact the surfaces of a plurality of insulating layers at the first trench T1 and the second trench T2, respectively, and the first metal layer 710 may be disposed to contact the surface of the second metal layer 720 at the first trench T1 and the second trench T2, respectively. For example, the first metal layer 710 may be disposed in the same layer as the second source electrode S2 and the second drain electrode D2 and made of the same material, and the second metal layer 720 may be disposed in the same layer as the first source electrode S1 and the first drain electrode D1 and made of the same material.

[0155] According to still another embodiment of the present specification, by disposing the first trench T1 and the second trench T2 in the optical region OA, even if cracks occur during the formation of the through hole TH in the optical region OA or during the assembly of the optoelectronic device in the through hole TH, the first trench T1 and the second trench T2 block the propagation path of the cracks, and defects due to crack propagation can be prevented. Further, the first trench T1 and the second trench T2 are each disposed so as to overlap at least one connection prevention portion 200 and the dam structure 300 in the optical region OA, so that a separate space for preventing crack propagation is not required, and the non-display region NDA adjacent to the optical region OA can be minimized.

[0156] Further, according to still another embodiment of the present specification, by disposing the first metal layers 410, 510, 610, 710 in the first trench T1 and the second trench T2 and disposing the second metal layers 420, 520, 620, 720 so as to contact the first metal layers 410, 510, 610, 710, the propagation of cracks is further blocked, and even if cracks occur during the formation of the through hole TH in the optical region OA or during the assembly of the optoelectronic device in the through hole TH, the first trench T1, the second trench T2, the first metal layers 410, 510, 610, 710, and the second metal layers 420, 520, 620, 720 completely block the propagation path of the cracks, and defects due to crack propagation can be prevented.

[0157] Embodiments of the present invention can also be described as follows.

[0158] According to an aspect of the present invention, a substrate includes a display area, an optical area disposed within the display area and including a through hole, and a non-display area surrounding the display area, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection prevention portion disposed on the plurality of insulating layers and closer to the through hole than the at least one dam. A first trench is disposed in a part of the plurality of insulating layers that overlaps with the at least one connection prevention portion in the optical area. According to other features of the present specification, the plurality of insulating layers includes at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate, and the first trench may be disposed in a part of the insulating layers disposed at the upper part of the plurality of insulating layers.

[0159] According to other features of the present specification, it may further include a second trench disposed in a part of the plurality of insulating layers that overlaps with the at least one dam in the optical area.

[0160] According to other features of the present specification, it may further include a first metal layer disposed along the surface of a part of the insulating layers of the plurality of insulating layers in each of the first trench and the second trench.

[0161] According to other features of the present specification, the first metal layer may be disposed so as to be in contact with the surface of the plurality of insulating layers in each of the first trench and the second trench.

[0162] According to other features of the present specification, it may further include a first thin film transistor disposed on the substrate of the display area and including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, at least one insulating layer disposed on the first gate electrode, and a second thin film transistor disposed on the insulating layer and including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

[0163] According to other features of this specification, the first metal layer can be composed of the same material as the first source electrode and the first drain electrode.

[0164] According to other features of this specification, it can further include a second metal layer disposed under each of the first trench and the second trench.

[0165] According to other features of this specification, the first metal layer is in contact with the side surfaces of some of the plurality of insulating layers in each of the first trench and the second trench, and the first metal layer and the second metal layer can be in contact with each other.

[0166] According to other features of this specification, the first metal layer is disposed in the same layer as the first source electrode and the first drain electrode and is composed of the same material, and the second metal layer can be disposed in the same layer as the first gate electrode and be composed of the same material.

[0167] According to other features of this specification, it further includes a light-shielding layer disposed to overlap with the first gate electrode under the first active layer, the first metal layer is composed of the same material as the first source electrode and the first drain electrode, and the second metal layer can be composed of the same material as the light-shielding layer.

[0168] According to other features of this specification, the second metal layer is disposed to contact the surfaces of the plurality of insulating layers in each of the first trench and the second trench, and the first metal layer can be disposed to contact the surface of the second metal layer in each of the first trench and the second trench.

[0169] According to other features of this specification, the first metal layer is disposed in the same layer as the second source electrode and the second drain electrode and is composed of the same material, and the second metal layer can be disposed in the same layer as the first source electrode and the first drain electrode and be composed of the same material.

[0170] According to other features of this specification, it can further include an optoelectronic device disposed to overlap with the optical region.

[0171] The embodiments of this specification have been described in more detail above with reference to the accompanying drawings. However, this specification is not necessarily limited to such embodiments, and various modifications can be made within the scope not departing from the technical idea of this specification. Therefore, the embodiments disclosed in this specification are not for limiting the technical idea of this specification, but for explanatory purposes, and the scope of the technical idea of this specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. All technical ideas within the scope equivalent to the claims of this specification should be construed as being included in the scope of rights of this specification.

Claims

1. a substrate including a display area, an optical area disposed within the display area and including a through hole, and a non-display area surrounding the display area; a plurality of insulating layers disposed on the substrate; at least one dam disposed on the plurality of insulating layers; and at least one coupling prevention portion disposed on the plurality of insulating layers and disposed closer to the through hole than the at least one dam; A first trench is disposed in a portion of the insulating layers that overlaps the at least one anti-coupling portion in the optical region.

2. the plurality of insulating layers include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate; The display device according to claim 1 , wherein the first trench is disposed in an upper part of the insulating layers.

3. The display device of claim 1 , further comprising a second trench disposed in a portion of the insulating layers overlapping the at least one dam in the optical region.

4. a first thin film transistor disposed on the substrate in the display region, the first thin film transistor including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; at least one insulating layer disposed on the first gate electrode; a second thin film transistor disposed on the at least one insulating layer, the second thin film transistor including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; a first planarization layer disposed on the first source electrode and the first drain electrode of the first thin film transistor and the second source electrode and the second drain electrode of the second thin film transistor; and further comprising a second planarization layer disposed on the first planarization layer; The display device of claim 2 , wherein at least one of the first planarization layer and the second planarization layer is disposed in the first trench to fill the first trench.

5. The display device according to claim 3 , further comprising a first metal layer disposed along a surface of a part of the insulating layers in each of the first trench and the second trench.

6. The display device according to claim 5 , wherein the first metal layer is disposed so as to be in contact with surfaces of the insulating layers in each of the first trench and the second trench.

7. a first thin film transistor disposed on the substrate in the display region, the first thin film transistor including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; at least one insulating layer disposed over the first gate electrode; and 7. The display device of claim 6, further comprising a second thin film transistor disposed on the at least one insulating layer, the second thin film transistor including a second active layer, a second gate electrode, a second source electrode and a second drain electrode.

8. The display device according to claim 7 , wherein the first metal layer is made of the same material as the first source electrode and the first drain electrode.

9. The display device of claim 7 , further comprising a second metal layer disposed beneath each of the first trench and the second trench.

10. the first metal layer contacts side surfaces of some of the insulating layers in each of the first trench and the second trench; The display device of claim 9 , wherein the first metal layer and the second metal layer are in contact with each other.

11. the first metal layer is disposed in the same layer as the first source electrode and the first drain electrode and is made of the same material; The display device according to claim 10 , wherein the second metal layer is disposed in the same layer as the first gate electrode and is made of the same material as the first gate electrode.

12. a light-shielding layer disposed under the first active layer so as to overlap the first gate electrode; the first metal layer is made of the same material as the first source electrode and the first drain electrode; The display device according to claim 10 , wherein the second metal layer is made of the same material as the light-shielding layer.

13. the second metal layer is disposed in contact with surfaces of the insulating layers in each of the first trench and the second trench; The display device according to claim 10 , wherein the first metal layer is disposed so as to be in contact with a surface of the second metal layer in each of the first trench and the second trench.

14. the first metal layer is disposed in the same layer as the second source electrode and the second drain electrode and is made of the same material; The display device according to claim 13 , wherein the second metal layer is disposed in the same layer as the first source electrode and the first drain electrode and is made of the same material as the first source electrode and the first drain electrode.

15. The display device of claim 1 further comprising an optoelectronic device disposed in overlap with the optical region.

16. The display device according to claim 15 , wherein the through-hole is formed to correspond to the optical-electronic device.

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