Phased array antenna device and wireless communication device

Abstract

To reduce the number of lengths of signal line for supplying control signals to the phase shifters of a phased array antenna device.SOLUTION: A plurality of phase shifters 1 changes the phases of a plurality of radio frequency signals transmitted or received via a plurality of antenna elements 104 in accordance with control signals K and D. The control signal K sets the initial phase of a plurality of radio frequency signals. The control signal D sets the phase difference of two radio frequency signals transmitted or received via mutually adjacent two antenna elements among the plurality of antenna elements 104. In each of a plurality of adders 2, the control signal K, or a signal outputted from the output terminal of the other adder 2 among the plurality of adders 2, is inputted to the first input terminal, and the control signal D is inputted to the second input terminal. In each of the plurality of adders 2, the signal outputted from the output terminal is supplied to one of the plurality of phase shifters 1, and the shift amount of the one phase shifter 1 is controlled.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a phased array antenna device and a wireless communication device.

Background Art

[0002] In wireless communication systems after the fifth generation mobile communication system (Beyond 5G), the use of high frequency bands such as millimeter waves and terahertz waves is being considered for increasing communication capacity. Furthermore, in order to increase communication capacity, it is being considered to concentrate radio waves on a communication partner using a phased array antenna device.

[0003] For example, Patent Document 1 discloses a phased array antenna device according to the prior art.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a phased array antenna device, it is known that there is a proportional relationship between the number of antenna elements and the transmission power. Since there is a limit to the maximum saturation output of one power amplifier in a high frequency band, it is possible to increase the transmission power of the phased array antenna device by increasing the number of antenna elements.

[0006] On one hand, in order to precisely control the phase of radio frequency signals transmitted or received through each antenna element of a phased array antenna device, a digitally controlled phase shifter may be used. For example, when 16 antenna elements and 16 phase shifters are used and the phase shifters are controlled according to 8-bit digital control signals, a total of 16×8 = 128 signal lines are required for the entire phase shifters. A significant area on the substrate is occupied to arrange 128 signal lines, which leads to an increase in the substrate size. Although it is also conceivable to reduce the number of signal lines by using a serial interface such as SPI (Serial Peripheral Interface), in this case, there is a problem that the control becomes slow. Therefore, it is required to reduce the number of signal lines for supplying control signals to the phase shifters compared to the conventional case without reducing the operating speed.

[0007] An object of the present disclosure is to provide a phased array antenna device including a digitally controlled phase shifter, which reduces the number of signal lines for supplying control signals to the phase shifters compared to the conventional case without reducing the operating speed. Another object of the present disclosure is to provide a wireless communication device including such a phased array antenna device.

Means for Solving the Problems

[0008] According to a first aspect of the present disclosure, a phased array antenna device includes a plurality of antenna elements arranged at predetermined intervals, a phase shift circuit including a plurality of phase shifters that change the phases of a plurality of radio frequency signals transmitted or received through the plurality of antenna elements according to first and second control signals, and a control circuit that controls the phase shift amounts of the plurality of phase shifters using the second control signal. The first control signal sets the initial phases of the plurality of radio frequency signals, and the second control signal sets the phase difference between two radio frequency signals transmitted or received via two adjacent antenna elements among the plurality of antenna elements. The first and second control signals have digital values consisting of a plurality of bits. The phase shifter circuit further includes a plurality of adders. Each of the plurality of adders has a first input terminal, a second input terminal, and an output terminal. The first control signal is input to the first input terminal, or a signal output from the output terminal of another one of the plurality of adders is input. The second control signal is input to the second input terminal, and the signal output from the output terminal is supplied to one of the plurality of phase shifters to control the phase shift amount of the one phase shifter.

[0009] According to a second aspect of the present disclosure, in the first aspect, The phase shift amounts of the plurality of phase shifters change linearly according to the first and second control signals.

[0010] According to a third aspect of the present disclosure, in the first or second aspect, The first control signal is supplied from the control circuit to the phase shifter circuit.

[0011] According to a fourth aspect of the present disclosure, in the first or second aspect, The phase shifter circuit further includes a storage device that stores the first control signal in advance.

[0012] According to a fifth aspect of the present disclosure, in one of the first to fourth aspects, The first control signal has a value of 0, The second control signal has any one of a positive value, a negative value, and a value of 0, The phase shift amounts of the plurality of phase shifters have any one of a positive value, a negative value, and a value of 0.

[0013] According to a sixth aspect of the present disclosure, in one of the first to fifth aspects, The plurality of antenna elements are arranged as a one-dimensional array.

[0014] According to a seventh aspect of the present disclosure, in one of the first to fifth aspects, the plurality of antenna elements are arranged as a two-dimensional array along first and second directions different from each other, the second control signal is a third control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the first direction among the plurality of antenna elements, and a fourth control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the second direction among the plurality of antenna elements, the plurality of adders include a plurality of first adders to which the third control signal is input, and a plurality of second adders to which the fourth control signal is input, In each of the plurality of second adders, the signal output from the output terminal is input to the first input terminal in one of the plurality of first adders, or is input to the first input terminal in one of the plurality of first adders and the first input terminal in another one of the plurality of second adders.

[0015] According to an eighth aspect of the present disclosure, a phased array antenna device includes a plurality of antenna elements arranged at predetermined intervals, a phase shift circuit including a plurality of phase shifters that change the phases of a plurality of radio frequency signals transmitted or received via the plurality of antenna elements according to first and second control signals, and a control circuit that controls the phase shift amounts of the plurality of phase shifters using the second control signal. The first control signal sets the phase of one of the plurality of radio frequency signals, and the second control signal sets the phase difference between two radio frequency signals transmitted or received via two adjacent antenna elements among the plurality of antenna elements. The first and second control signals have digital values consisting of a plurality of bits. The first control signal is supplied to a first phase shifter among the plurality of phase shifters to control the phase shift amount of the first phase shifter. The second control signal is supplied to one or more second phase shifters among the plurality of phase shifters to control the phase shift amount of the one or more second phase shifters. The phase shift circuit further includes one or more bit shift circuits and one or more adders. Each of the one or more bit shift circuits shifts the bits of the second control signal so as to increase the digital value of the second control signal. The signal output from the bit shift circuit is supplied to one or more third phase shifters among the plurality of phase shifters to control the phase shift amount of the one or more third phase shifters. Each of the one or more adders has a first input terminal, a second input terminal, and an output terminal. The signal output from the bit shift circuit is input to the first input terminal, or the signal output from the output terminal of another one of the plurality of adders is input. The second control signal is input to the second input terminal. The signal output from the output terminal is supplied to one or more fourth phase shifters among the plurality of phase shifters to control the phase shift amount of the one or more fourth phase shifters.

[0016] According to a ninth aspect of the present disclosure, in the eighth aspect, The plurality of antenna elements are arranged as a one-dimensional array.

[0017] According to a tenth aspect of the present disclosure, in the eighth aspect, The plurality of antenna elements are arranged as a two-dimensional array along first and second directions different from each other. The second control signal is A third control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the first direction among the plurality of antenna elements; and a fourth control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the second direction among the plurality of antenna elements. The one or more second phase shifters include a fifth phase shifter to which the third control signal is supplied and a sixth phase shifter to which the fourth control signal is supplied. The one or more bit shift circuits include a first bit shift circuit to which the third control signal is input and a second bit shift circuit to which the fourth control signal is input. The one or more third phase shifters include a seventh phase shifter to which a signal output from the first bit shift circuit is supplied and an eighth phase shifter to which a signal output from the second bit shift circuit is supplied. The one or more adders include a plurality of first adders to which the third control signal is input and one or more second adders to which the fourth control signal is input. In each of the one or more second adders, the signal output from the output terminal is input to the first input terminal in one of the plurality of first adders, or is input to the first input terminal in one of the plurality of first adders and the first input terminal in another one of the plurality of second adders.

[0018] According to an eleventh aspect of the present disclosure, a wireless communication device includes a phased array antenna device according to one of the first to tenth aspects; and a wireless communication circuit.

Advantages of the Invention

[0019] According to one aspect of the present disclosure, it is possible to reduce the number of signal lines for supplying a control signal to a phase shifter as compared with the conventional case without reducing the operating speed.

Brief Description of Drawings

[0020]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0021] Hereinafter, with reference to the drawings, a phased array antenna device and a wireless communication device according to each embodiment of the present disclosure will be described. Throughout the drawings, the same reference numerals denote the same components.

[0022] [First Embodiment] FIG. 1 is a block diagram showing the configuration of a wireless communication device 100 according to the first embodiment. The wireless communication device 100 includes a transmission circuit 101, mixers 102-1 to 102-4, amplifiers 103-1 to 103-4, antenna elements 104-1 to 104-4, a frequency synthesizer 105, a frequency multiplier 106, a phase shifter 107, frequency multipliers 108-1 to 108-4, and a control circuit 109.

[0023] The transmission circuit 101 sends a baseband signal S1 including data to be transmitted to the mixers 102-1 to 102-4.

[0024] The frequency synthesizer 105 generates a high-frequency signal having a predetermined frequency. The frequency multiplier 106 multiplies the frequency of the high-frequency signal generated by the frequency synthesizer 105 and sends a high-frequency signal S2 having the multiplied frequency to the phase shifter 107.

[0025] The phase shift circuit 107 includes at least phase shifters 1-1 to 1-4. The phase shifters 1-1 to 1-4 change the phase of the high-frequency signal S2 input from the frequency multiplier 106, thereby changing the phases of the four radio frequency signals transmitted via the antenna elements 104-1 to 104-4 respectively. Also, control signals K and D are input to the phase shift circuit 107 from the control circuit 109. The control signal K sets an initial phase common to the four radio frequency signals. The control signal D sets the phase difference between two radio frequency signals transmitted via two adjacent antenna elements among the antenna elements 104-1 to 104-4. The control signals K and D have digital values of a predetermined number of bits, for example, 8 bits. The phase shifters 1-1 to 1-4 change the phases of the four radio frequency signals respectively according to the control signals K and D. The phase shifters 1-1 to 1-4 are configured such that their phase shift amounts change linearly according to the control signals K and D. The control circuit 109 controls the phase shift amounts of the phase shifters 1-1 to 1-4 using the control signals K and D.

[0026] The frequency multipliers 108-1 to 108-4 multiply the frequency of the high-frequency signal output from the phase shifters 1-1 to 1-4 and send it to the mixers 102-1 to 102-4.

[0027] The mixers 102-1 to 102-4 modulate the high-frequency signals (radio frequency signals) input from the frequency multipliers 108-1 to 108-4 with the baseband signals input from the transmission circuit 101. The output signals of the mixers 102-1 to 102-4 are amplified by the amplifiers 103-1 to 103-4 respectively, and then radiated from the antenna elements 104-1 to 104-4 respectively.

[0028] The antenna elements 104-1 to 104-4 are arranged at equal intervals, for example, half of the operating wavelength, as a one-dimensional array.

[0029] The antenna elements 104-1 to 104-4 operate as a phased array antenna device by changing the phase of the radio frequency signal to be transmitted by the phase shifters 1-1 to 1-4.

[0030] Figure 2 is a block diagram showing the detailed configuration of the phase shift circuit 107 in FIG. 1. The phase shift circuit 107 includes adders 2-1 to 2-3 in addition to phase shifters 1-1 to 1-4.

[0031] Each of the adders 2-1 to 2-3 is a digital full adder having two input terminals and one output terminal. The adders 2-1 to 2-3 generate control signals A1 to A4 for controlling the phase shift amounts of the phase shifters 1-1 to 1-4 based on the control signals K and D as follows.

[0032] The control signal K is directly supplied to the phase shifter 1-1 as the control signal A1.

[0033] In the adder 2-1, the control signal K is input to the first input terminal, and the control signal D is input to the second input terminal. The adder 2-1 calculates the sum of the control signals K and D. The output signal of the adder 2-1 is supplied to the adder 2-2 and is also supplied to the phase shifter 1-2 as the control signal A2.

[0034] In the adder 2-2, the output signal of the adder 2-1 is input to the first input terminal, and the control signal D is input to the second input terminal. The adder 2-2 calculates the sum of the output signal of the adder 2-1 and the control signal D. The output signal of the adder 2-2 is supplied to the adder 2-3 and is also supplied to the phase shifter 1-3 as the control signal A3.

[0035] In the adder 2-3, the output signal of the adder 2-2 is input to the first input terminal, and the control signal D is input to the second input terminal. The adder 2-3 calculates the sum of the output signal of the adder 2-2 and the control signal D. The output signal of the adder 2-3 is supplied to the phase shifter 1-4 as the control signal A4.

[0036] Therefore, the control signals A1 to A4 are represented by the following equations.

[0037] A1 = K A2 = A1 + D mod(2 8 ) A3 = A2 + D mod(2 8 ) A4 = A3 + D mod(2 8 )

[0038] The phase shifters 1-1 to 1-4 change the phases of the high-frequency signal S2 according to the control signals A1 to A4, respectively, and output high-frequency signals S3(φ1) to S3(φ4) having phases φ1 to φ4. The four high-frequency signals output from the phase shifters 1-1 to 1-4 have a common initial phase φ0 = (K / 2 8 )×360°. Also, among the four high-frequency signals output from the phase shifters 1-1 to 1-4, two high-frequency signals corresponding to two adjacent antenna elements have a phase difference Δφ = (D / 2 8 )×360°. In this case, the phases φ1 to φ4 are represented by the following equations.

[0039] φ1 = (A1 / 2 8 )×360° = φ0 φ2 = (A2 / 2 8 )×360° = φ0 + Δφ φ3 = (A3 / 2 8 )×360° = φ0 + 2Δφ φ4 = (A4 / 2 8 )×360° = φ0 + 3Δφ

[0040] In this specification, the phase shifters 1-1 to 1-4, etc. are collectively referred to as "phase shifter 1", and the adders 2-1 to 2-3, etc. are collectively referred to as "adder 2".

[0041] The configuration of the phase shift circuit 107 may be represented as follows. In each of the plurality of adders 2, the control signal K is input to the first input terminal or the output signal of another one of the adders 2 is input, and the control signal D is input to the second input terminal. Also, in each of the plurality of adders 2, the output signal is supplied to one of the plurality of phase shifters 1 and controls the phase shift amount of the one phase shifter 1.

[0042] Generally, when the antenna elements of a phased array antenna device are arranged at equal intervals, the phase difference of each pair of radio frequency signals transmitted through each pair of adjacent antenna elements is set to be equal to each other. By using the phase shifter circuit 107 of FIG. 2 including the phase shifter 1 having a phase shift amount that linearly changes according to the control signals K and D, the phases of the four radio frequency signals transmitted through the antenna elements 104-1 to 104-4 can be changed so as to direct the beam in a desired direction.

[0043] The phased array antenna device according to the first embodiment may be configured to steer its beam to positive and negative angles with respect to a predetermined reference direction. In this case, the control signal K has, for example, a value of 0. The control signal D has either a positive value, a negative value, or a value of 0. The negative value of the control signal D may be represented, for example, by two's complement. Each phase shifter 1 is configured such that its phase shift amount changes to either a positive value, a negative value, or a value of 0 according to the control signal D. When the phase shift amount of each phase shifter 1 is 0, the beam of the phased array antenna device is in the reference direction. When the phase shift amount has a positive value, the beam has a positive angle with respect to the reference direction. When the phase shift amount has a negative value, the beam has a negative angle with respect to the reference direction.

[0044] In a conventional phased array antenna device, it was necessary to individually provide signal lines for supplying control signals from a control circuit to a plurality of phase shifters for each phase shifter. Therefore, conventionally, for example, when using four phase shifters operating according to an 8-bit control signal, it was necessary to provide 8×4 = 32 signal lines between the control circuit and the phase shifters. On the other hand, according to the phased array antenna device according to the first embodiment, since the 8-bit control signals K and D are supplied from the control circuit 109 to the phase shifter circuit 107, only 8×2 = 16 signal lines are provided between the control circuit 109 and the phase shifter circuit 107. Thus, according to the phased array antenna device according to the first embodiment, the number of signal lines for supplying control signals to each phase shifter 1 can be reduced compared to the prior art.

[0045] The change in the beam direction of the phased array antenna device is executed, for example, on the order of several microseconds. On the other hand, the operation of each adder 2 is executed on the order of 1 / 100 to 1 / 1000 of the time taken for the change in the beam direction. Therefore, according to the phased array antenna device according to the first embodiment, the beam direction can be controlled without substantially reducing the operating speed as compared with the case where signal lines are provided individually for each phase shifter;

[0046] According to the phased array antenna device according to the first embodiment, the number of signal lines for supplying a control signal to the phase shifter 1 can be reduced as compared with the conventional case without reducing the operating speed.

[0047] The signal lines inside the phase shift circuit 107 are partially shared by using the adder 2. Therefore, according to the phased array antenna device according to the first embodiment, the total length of the signal lines is shorter than the case where signal lines are provided individually for each phase shifter.

[0048] According to the phased array antenna device according to the first embodiment, by reducing the number and length of the signal lines for supplying a control signal to each phase shifter 1, the area occupied by the signal lines can be reduced as compared with the conventional case. Therefore, the size of the phased array antenna device can be reduced as compared with the conventional case.

[0049] [Configuration Example of Phase Shifter] As described above, each phase shifter 1 is configured such that its phase shift amount changes linearly according to the control signals K and D. Hereinafter, an exemplary configuration of a phase shifter having linear phase shift characteristics will be described.

[0050] FIG. 3 is a block diagram showing the detailed configuration of the phase shifters 1-1 to 1-4 in FIG. 2. Each phase shifter 1 includes a signal generation circuit 10 and a quadrature modulation circuit 20.

[0051] The signal generation circuit 10 includes a control voltage source circuit 11, a reference voltage source circuit 12, and folding circuits 13 and 14. The control voltage source circuit 11 includes a plurality of resistors and a plurality of N taps, and generates a control voltage Vc(k) having one of a predetermined N voltage values by selecting one of the N taps according to the input control signal k. The control signal k takes an arbitrary value from 1 to N. The control signal k has a size of log2N bits. The reference voltage source circuit 12 includes a plurality of resistors and a plurality of M taps, and generates predetermined M reference voltages Vr1, …, VrM from the M taps. The folding circuit 13 generates an output signal Vsin(k) having a signal level corresponding to a predetermined phase of a sine wave based on the difference between the control voltage Vc(k) and the plurality of reference voltages Vr1, …, VrM. The folding circuit 14 generates an output signal Vcos(k) having a signal level corresponding to a predetermined phase of a cosine wave based on the difference between the control voltage Vc(k) and the plurality of reference voltages Vr1, …, VrM.

[0052] The quadrature modulation circuit 20 includes a quadrature distributor 21, multipliers 22 and 23, and a synthesizer 24. The quadrature distributor 21 distributes the input original frequency signal Vin into an I-component signal VinI and a Q-component signal VinQ. The multiplier 22 multiplies the I-component signal VinI by the signal Vcos(k) output from the folding circuit 14. The multiplier 23 multiplies the Q-component signal VinQ by the signal Vsin(k) output from the folding circuit 13. Each of the multipliers 22 and 23 outputs the product when two analog signals are input. The multipliers 22 and 23 may be, for example, four-quadrant multipliers or variable gain amplifiers. The synthesizer 24 synthesizes the output signals of the multipliers 22 and 23 with each other and outputs a frequency signal Vout with a phase shift.

[0053] Here, the operating principle of the quadrature modulation circuit 20 will be described. The original frequency signal Vin is represented as Vin = sin(ωt) as a sine wave having an angular frequency ω. Also, the following signals Vsin(k) and Vcos(k) are input from the signal generation circuit 10.

[0054]

Number

Number

[0055] The quadrature distributor 21 generates two signals VinI = sin(ωt) and VinQ = cos(ωt) having a phase shift of 90 degrees. Next, the multipliers 22 and 23 multiply the signals Vcos(k) and Vsin(k) input from the signal generation circuit 10 by the signals VinI and VinQ, respectively. The synthesizer 24 synthesizes the output signals of the multipliers 22 and 23 with each other and outputs a frequency signal Vout with a phase shift. Therefore, the frequency signal Vout with a phase shift is represented as follows.

[0056]

Number

[0057] Comparing the original frequency signal Vin and the frequency signal Vout with a phase shift, it can be seen that the phase shifter 1 generates an output signal having a phase shift amount proportional to the value of the control signal k.

[0058] The signal generation circuit 10 operates as a control circuit of the quadrature modulation circuit 20 and controls the phase shift amount of the signal Vin by the quadrature modulation circuit 20.

[0059] FIG. 4 is a circuit diagram showing the configuration of the signal generation circuit 10 in FIG. 3.

[0060] The control voltage source circuit 11 includes a plurality of resistors R10, R11, R12, a plurality of N taps, and a switch SW. The plurality of resistors R10, R11, R12 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee. FIG. 4 shows the case where N = 256. At the N taps between the resistors R10, R11, R12, different predetermined voltage values Vc1, …, Vc256 are generated. The plurality of resistors R10 have the same resistance value as each other. In this case, the potential differences of the voltage values Vc1, …, Vc256 are equal to each other. The switch SW selects one of the plurality of N taps according to the control signal k and outputs the corresponding voltage value Vck as the control voltage Vc(k).

[0061] In the present disclosure, for simplicity, the control voltage Vc(k) may sometimes be simply denoted as the control voltage Vc as well.

[0062] The reference voltage source circuit 12 includes resistors R21 to R28 and a plurality of M taps. FIG. 4 shows the case where M = 6. The resistors R21, R25 to R28 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee and are the first voltage dividing resistors that generate the reference voltages Vr2, Vr4, Vr6 from the power supply voltage. At the M / 2 taps between the resistors R25 to R28, the reference voltages Vr2, Vr4, Vr6 are generated. The resistors R21 to R24, R28 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee and are the second voltage dividing resistors that generate the reference voltages Vr1, Vr3, Vr5 from the power supply voltage. At the M / 2 taps between the resistors R21 to R24, the reference voltages Vr1, Vr3, Vr5 are generated. The resistance values of the resistors R24, R25 are set to be equal to each other. Also, the resistance values of the resistors R22, R23, R26, R27 are equal to each other and are set to be twice the resistance values of the resistors R24, R25. By setting the resistance values of the resistors R22 to R27 in this way, the reference voltages Vr1 to Vr6 for simultaneously generating a sine wave and a cosine wave can be generated.

[0063] In the present disclosure, for simplicity, the reference voltages Vr1 to Vr6 may sometimes be simply denoted as the reference voltage Vr as well.

[0064] The folding circuit 13 includes differential amplifiers 31 to 33 and resistors R31, R32. The differential amplifier 31 compares the control voltage Vc with the reference voltage Vr2 to generate a first differential output signal. The differential amplifier 32 compares the control voltage Vc with a reference voltage Vr4 higher than the reference voltage Vr2 to generate a second differential output signal. The differential amplifier 33 compares the control voltage Vc with a reference voltage Vr6 higher than the reference voltage Vr4 to generate a third differential output signal. The output terminals of the differential amplifiers 31 to 33 are connected to the terminal of the power supply voltage Vcc via the resistors R31, R32. The first output signal Vsin(k) is the sum of the differential output signals of the differential amplifiers 31, 33 and the inverted signal of the differential output signal of the differential amplifier 32.

[0065] The folding circuit 14 includes differential amplifiers 41 to 43 and resistors R41, R42. The differential amplifier 41 compares the control voltage Vc with the reference voltage Vr1 to generate a fourth differential output signal. The differential amplifier 42 compares the control voltage Vc with a reference voltage Vr3 higher than the reference voltage Vr1 to generate a fifth differential output signal. The differential amplifier 43 compares the control voltage Vc with a reference voltage Vr5 higher than the reference voltage Vr3 to generate a sixth differential output signal. The output terminals of the differential amplifiers 41 to 43 are connected to the terminal of the power supply voltage Vcc via the resistors R41, R42. The second output signal Vcos(k) is the sum of the differential output signals of the differential amplifiers 41, 43 and the inverted signal of the differential output signal of the differential amplifier 42.

[0066] FIG. 5 is a circuit diagram showing an example of the configuration of the differential amplifiers 31 to 33, 41 to 43 in FIG. 4. Each of the differential amplifiers 31 to 33, 41 to 43 includes a pair of bipolar transistors Q1, Q2, a constant current source 51, and resistors Ra to Rd. The control voltage Vc is applied to the base of the bipolar transistor Q1, and the reference voltage Vr (any one of the reference voltages Vr1 to Vr6) is applied to the base of the bipolar transistor Q2. According to the potential difference between the control voltage Vc and the reference voltage Vr, an output current Ix flows through the output terminals dout1, dout2.

[0067] The output currents Ix of the differential amplifiers 31 to 33 and 41 to 43 vary approximately with the transmission characteristics of the hyperbolic sine function tanh(Vc) with respect to the control voltage Vc or the transmission characteristics of its inverted signal. When the control voltage Vc is within a predetermined voltage range Vtran centered on the reference voltage Vr, the output current Ix varies according to the control voltage Vc. However, when the control voltage Vc is outside the voltage range Vtran, the output current Ix does not substantially vary even if the control voltage Vc changes.

[0068] By combining the differential amplifiers 31 and 32 each having the characteristics of the hyperbolic sine function, the sum of the output currents of the differential amplifiers 31 and 32 varies with the characteristic obtained by connecting two hyperbolic sine functions with respect to the control voltage Vc. By appropriately setting the difference between the reference voltages Vr2 and Vr4, the sum of the output currents of the differential amplifiers 32 and 33 can be well approximated by the waveform of a sine wave. Similarly, by appropriately setting the difference between the reference voltages Vr4 and Vr6, the sum of the output currents of the differential amplifiers 32 and 33 can also be well approximated by the waveform of a sine wave. Also, by appropriately setting the difference between the reference voltages Vr1 and Vr3, the sum of the output currents of the differential amplifiers 41 and 42 can also be well approximated by the waveform of a sine wave. Further, by appropriately setting the difference between the reference voltages Vr3 and Vr5, the sum of the output currents of the differential amplifiers 42 and 43 can also be well approximated by the waveform of a sine wave.

[0069] The folding circuits 13 and 14 are analog circuits in which the output voltage repeats increases and decreases a plurality of times in response to an increase or decrease in the input voltage.

[0070] The total phase shift amount of the phase shifter 1 becomes ((M - 1) / 4)2π radians. For example, when the control voltage Vc changes over the potential difference between Vr5 - Vr1 (or the potential difference between Vr6 - Vr2), a phase shift amount of 2π is brought about in the quadrature modulation circuit 20.

[0071] The upper and lower limits of the control voltage Vc(k) may be made to coincide with the upper and lower limits of the reference voltage Vr, respectively (Vc1 = Vr1, Vc256 = Vr6). In this case, when the k-th voltage value is selected in the control voltage source circuit 11, the phase shift amount of the phase shifter 1 is represented by the following equation.

[0072]

Equation

[0073] As described above, the parameter M determines the total phase shift amount of the phase shifter 1. When a wide phase shift amount is required, a large M is set at the time of designing the phase shifter 1. Also, the parameter N determines the resolution with which the control signal k can be set. When a fine resolution is required, a large N is set at the time of designing the phase shifter 1.

[0074] As described above, the signal generation circuit 10 includes two folding circuits 13 and 14, and a control voltage source circuit 11 and a reference voltage source circuit 12 that generate the control voltage Vc and the reference voltage Vr used in the folding circuits 13 and 14, respectively. The folding circuits 13 and 14 generate output signals Vsin(k) and Vcos(k) having signal levels corresponding to a predetermined phase of a sine wave or a cosine wave and changing in proportion to the value of the control signal k. The output signals Vsin(k) and Vcos(k) are applied as DC coefficients to the two multipliers 22 and 23 of the quadrature modulation circuit 20. As a result, the phase of the original frequency signal input to the quadrature modulation circuit 20 is shifted by a phase proportional to the control signal k and output as a frequency signal with the phase shifted.

[0075] FIG. 6 is a graph showing the operating characteristics of the phase shifters 1-1 to 1-4 in FIG. 2. When the phase shifter 1 is controlled according to 8-bit control signals A1 to A4, the control signals A1 to A4 have values from 0 to 255, and the phases of the high-frequency signals output from each phase shifter 1 change in the range of 0 to 360°. When the values of the control signals A1 to A4 become 256 or more, the phase shifter 1 operates according to the remainder obtained by dividing the control signal by 256. Mathematically, this is represented by a mod operation.

[0076] Accordingly, it is possible to provide the phase shifter 1 having a phase shift amount that linearly changes according to the control signals K and D.

[0077] Also, according to the phase shifter 1 described with reference to FIGS. 3 to 6, it is possible to provide the phase shifter 1 having a smaller circuit scale and power consumption than before, having resistance to PVT variations, being digitally controllable, and having linear control characteristics with respect to the control signal.

[0078] [Modification of the First Embodiment] FIG. 7 is a block diagram showing the configuration of a wireless communication device 100A according to a modification of the first embodiment. FIG. 8 is a block diagram showing the detailed configuration of the phase shift circuit 107A in FIG. 7. The wireless communication device 100A includes a phase shift circuit 107A and a control circuit 109A instead of the phase shift circuit 107 and the control circuit 109 in FIG. 1.

[0079] The control circuit 109A supplies only the control signal D to the phase shift circuit 107A. The phase shift circuit 107A further includes a storage device 3 that stores the control signal K in advance. The control signal K read from the storage device 3 is supplied to the phase shifter 1-1 and the adder 2-1.

[0080] In a phased array antenna device, generally, only the phase difference between two radio frequency signals transmitted or received via two adjacent antenna elements determines the beam direction, and the initial phase of each phase shifter 1 does not affect the beam direction. Therefore, the control signal K that sets a common initial phase for the radio frequency signals may be any fixed value. In this case, instead of being set by the control circuit 109, the control signal K may be stored in advance inside the phase shift circuit 107A. Accordingly, only eight signal lines are provided between the control circuit 109A and the phase shift circuit 107A, and the number of signal lines for supplying the control signal to each phase shifter 1 can be further reduced compared to the case of FIG. 1. Therefore, the size of the phased array antenna device can be further reduced compared to the case of FIG. 1.

[0081] [Second Embodiment] FIG. 9 is a block diagram showing the configuration of a wireless communication device 100B according to the second embodiment. The wireless communication device 100B includes a transmission circuit 101, mixers 102-1 to 102-16, amplifiers 103-1 to 103-16, antenna elements 104-1 to 104-16, a frequency synthesizer 105, a frequency multiplier 106, a phase shifter circuit 107B, frequency multipliers 108-1 to 108-16, and a control circuit 109B.

[0082] The transmission circuit 101, the frequency synthesizer 105, and the frequency multiplier 106 are configured in the same manner as the corresponding components in FIG. 1. The mixers 102-1 to 102-16, the amplifiers 103-1 to 103-16, and the frequency multipliers 108-1 to 108-16 are configured in the same manner as the corresponding components in FIG. 1, except that the number thereof is increased.

[0083] FIG. 10 is a perspective view showing the arrangement of the antenna elements 104-1 to 104-16 in FIG. 9. The plurality of antenna elements 104-1 to 104-16 are arranged at equal intervals as a two-dimensional array on an antenna substrate 110 along mutually different first and second directions, for example, the X direction and the Y direction orthogonal to each other, at a predetermined interval, for example, half of the operating wavelength.

[0084] The phase shift circuit 107B includes at least phase shifters 1-1 to 1-16. The phase shifters 1-1 to 1-16 change the phase of the high-frequency signal S2 input from the frequency multiplier 106, thereby changing the phases of the 16 radio frequency signals transmitted via the antenna elements 104-1 to 104-16 respectively. Further, control signals K, D1, and D2 are input to the phase shift circuit 107B from the control circuit 109B. The control signal K sets an initial phase common to the 16 radio frequency signals. The control signal D1 sets the phase difference between two radio frequency signals transmitted or received via two adjacent antenna elements among the antenna elements 104-1 to 104-16 in the X direction. The control signal D2 sets the phase difference between two radio frequency signals transmitted or received via two adjacent antenna elements among the antenna elements 104-1 to 104-16 in the Y direction. The control signals K, D1, and D2 have digital values of a predetermined number of bits, for example, 8 bits. The phase shifters 1-1 to 1-16 change the phases of the 16 radio frequency signals respectively according to the control signals K, D1, and D2. The phase shifters 1-1 to 1-16 are configured such that their phase shift amounts change linearly according to the control signals K, D1, and D2. The control circuit 109B controls the phase shift amounts of the phase shifters 1-1 to 1-16 using the control signals K, D1, and D2.

[0085] FIG. 11 is a block diagram showing the detailed configuration of the phase shift circuit 107B in FIG. 9. The phase shift circuit 107B includes adders 2-1 to 2-15 in addition to the phase shifters 1-1 to 1-16.

[0086] Each of the adders 2-1 to 2-15 is a digital full adder having two input terminals and one output terminal. The adders 2-1 to 2-15 generate control signals B1 to B16 for controlling the phase shift amounts of the phase shifters 1-1 to 1-16 respectively based on the control signals K, D1, and D2 as follows.

[0087] The control signal D1 is input to the adders 2-1 to 2-12, and the control signal D2 is input to the adders 2-13 to 2-15.

[0088] Adders 2-1 to 2-3 generate control signals B1 to B4 for controlling the phase shift amounts of phase shifters 1-1 to 1-4 respectively based on control signals K and D1. The control signals B1 to B4 are generated in the same manner as the control signals A1 to A4 in FIG. 2, except that the control signal D1 is used instead of the control signal D in FIG. 2.

[0089] In adder 2-13, the control signal K is input to the first input terminal, and the control signal D2 is input to the second input terminal. Adder 2-13 calculates the sum of the control signals K and D2. The output signal of adder 2-13 is supplied to adders 2-4 and 2-14 and phase shifter 1-5.

[0090] Adders 2-4 to 2-6 generate control signals B5 to B8 for controlling the phase shift amounts of phase shifters 1-5 to 1-8 respectively based on the output signal of adder 2-13 and the control signal D1. The control signals B5 to B8 are generated in the same manner as the control signals B1 to B4, except that the output signal of adder 2-13 is used instead of the control signal K.

[0091] In adder 2-14, the output signal of adder 2-13 is input to the first input terminal, and the control signal D2 is input to the second input terminal. Adder 2-14 calculates the sum of the output signal of adder 2-13 and the control signal D2. The output signal of adder 2-14 is supplied to adders 2-7 and 2-15 and phase shifter 1-9.

[0092] Adders 2-7 to 2-9 generate control signals B9 to B12 for controlling the phase shift amounts of phase shifters 1-9 to 1-12 respectively based on the output signal of adder 2-14 and the control signal D1. The control signals B9 to B12 are generated in the same manner as the control signals B1 to B4, except that the output signal of adder 2-14 is used instead of the control signal K.

[0093] In adder 2-15, the output signal of adder 2-14 is input to the first input terminal, and control signal D2 is input to the second input terminal. Adder 2-15 calculates the sum of the output signal of adder 2-14 and control signal D2. The output signal of adder 2-15 is supplied to adder 2-10 and phase shifter 1-13.

[0094] Adders 2-10 to 2-12 generate control signals B13 to B16 for respectively controlling the phase shift amounts of phase shifters 1-13 to 1-16 based on the output signal of adder 2-15 and control signal D1. Control signals B13 to B16 are generated in the same manner as control signals B1 to B4, except that the output signal of adder 2-15 is used instead of control signal K.

[0095] Therefore, control signals B1 to B16 are represented by the following equations.

[0096] B1 = K B2 = B1 + D1 mod(2 8 ) B3 = B2 + D1 mod(2 8 ) B4 = B3 + D1 mod(2 8 ) B5 = B1 + D2 mod(2 8 ) B6 = B5 + D1 mod(2 8 ) B7 = B6 + D1 mod(2 8 ) B8 = B7 + D1 mod(2 8 ) B9 = B5 + D2 mod(2 8 ) B10 = B9 + D1 mod(2 8 ) B11 = B10 + D1 mod(2 8 ) B12 = B11 + D1 mod(2 8 ) B13 = B9 + D2 mod(2 8 ) B14 = B13 + D1 mod(2 8 ) B15 = B14 + D1 mod(2 8 ) B16 = B15 + D1 mod(2 8 )

[0097] The phase shifters 1-1 to 1-16 change the phases of the high-frequency signal S2 according to the control signals B1 to B16, respectively, and output high-frequency signals S3(θ1) to S3(θ16) having phases θ1 to θ16. The 16 high-frequency signals output from the phase shifters 1-1 to 1-16 have a common initial phase θ0 = (K / 2 8 )×360°. Also, among the 16 high-frequency signals output from the phase shifters 1-1 to 1-16, two high-frequency signals corresponding to two adjacent antenna elements in the X direction have a phase difference Δθx = (D1 / 2 8 )×360°. Also, among the 16 high-frequency signals output from the phase shifters 1-1 to 1-16, two high-frequency signals corresponding to two adjacent antenna elements in the Y direction have a phase difference Δθy = (D2 / 2 8 )×360°. In this case, the phases θ1 to θ16 are represented by the following equations.

[0098] θ1 = (B1 / 2 8 )×360° = θ0 θ2 = (B2 / 2 8 )×360° = θ0 + Δθx θ3 = (B3 / 2 8 )×360° = θ0 + 2Δθx θ4 = (B4 / 2 8 )×360° = θ0 + 3Δθx θ5 = (B5 / 2 8 )×360° = θ0 + Δθy θ6 = (B6 / 2 8 )×360° = θ0 + Δθx + Δθy θ7 = (B7 / 2 8 )×360° = θ0 + 2Δθx + Δθy θ8 = (B8 / 2 8 )×360° = θ0 + 3Δθx + Δθy θ9 = (B9 / 2 8 )×360° = θ0 + 2Δθy θ10 = (B10 / 28 )) × 360° = θ0 + Δθx + 2Δθy θ11 = (B11 / 2 8 )) × 360° = θ0 + 2Δθx + 2Δθy θ12 = (B12 / 2 8 )) × 360° = θ0 + 3Δθx + 2Δθy θ13 = (B13 / 2 8 )) × 360° = θ0 + 3Δθy θ14 = (B14 / 2 8 )) × 360° = θ0 + Δθx + 3Δθy θ15 = (B15 / 2 8 )) × 360° = θ0 + 2Δθx + 3Δθy θ16 = (B16 / 2 8 )) × 360° = θ0 + 3Δθx + 3Δθy

[0099] The configuration of the phase shift circuit 107B may be expressed as follows. In each of the adders 2-1 to 2-15, a control signal K is input to the first input terminal, or an output signal of another adder 2 is input, and a control signal D1 or D2 is input to the second input terminal. Also, in each of the adders 2-13 to 2-15, the output signal is input to one of the first input terminals of the adders 2-1 to 2-12, or is input to one of the first input terminals of the adders 2-1 to 2-12 and to one of the first input terminals of the adders 2-13 to 2-15. Further, in each of the adders 2-1 to 2-15, the output signal is supplied to one of the plurality of phase shifters 1 to control the phase shift amount of the one phase shifter 1.

[0100] The phased array antenna device according to the second embodiment may also be configured to steer its beam to positive and negative angles with respect to a predetermined reference direction. In this case, the control signal K has, for example, a value of 0. Each of the control signals D1 and D2 has either a positive value, a negative value, or a value of 0. The negative values of the control signals D1 and D2 may be represented, for example, by two's complement. Each phase shifter 1 is configured such that its phase shift amount changes to either a positive value, a negative value, or a value of 0 according to the control signals D1 and D2. When the phase difference Δθx is 0, the X component of the beam of the phased array antenna device coincides with the X component of the reference direction. When the phase difference Δθx has a positive value, the X component of the beam has a positive angle with respect to the reference direction. When the phase difference Δθx has a negative value, the X component of the beam has a negative angle with respect to the reference direction. Similarly, when the phase difference Δθy is 0, the Y component of the beam of the phased array antenna device coincides with the Y component of the reference direction. When the phase difference Δθy has a positive value, the Y component of the beam has a positive angle with respect to the reference direction. When the phase difference Δθy has a negative value, the Y component of the beam has a negative angle with respect to the reference direction.

[0101] As described above, in a conventional phased array antenna device, it has been necessary to individually provide signal lines for supplying control signals from a control circuit to a plurality of phase shifters for each phase shifter. Therefore, conventionally, for example, when using 16 phase shifters operating according to an 8-bit control signal, it has been necessary to provide 8 × 16 = 128 signal lines between the control circuit and the phase shifters. On the other hand, according to the phased array antenna device according to the second embodiment, since 8-bit control signals K, D1, and D2 are supplied from the control circuit 109 to the phase shift circuit 107B, only 8 × 3 = 24 signal lines are provided between the control circuit 109 and the phase shift circuit 107. Thus, according to the phased array antenna device according to the second embodiment, the number of signal lines for supplying control signals to each phase shifter 1 can be reduced compared to the conventional case.

[0102] According to the phased array antenna device according to the second embodiment, even when the beam direction is two-dimensionally controlled, the number of signal lines for supplying a control signal to the phase shifter 1 can be reduced as compared with the conventional case without reducing the operation speed. According to the phased array antenna device according to the second embodiment, by reducing the number and length of the signal lines for supplying a control signal to each phase shifter 1, the area occupied by the signal lines can be reduced as compared with the conventional case. Therefore, the size of the phased array antenna device can be reduced as compared with the conventional case.

[0103] Also in the phased array antenna device according to the second embodiment, similar to the cases of FIGS. 7 and 8, instead of being set by the control circuit 109B, the control signal K may be stored in advance inside the phase shift circuit 107B. Thereby, only 16 signal lines are provided between the control circuit 109B and the phase shift circuit 107B, and the number of signal lines for supplying a control signal to each phase shifter 1 can be further reduced as compared with the case of FIG. 9. Therefore, the size of the phased array antenna device can be further reduced as compared with the case of FIG. 9.

[0104] [Third Embodiment] The phased array antenna device according to the third embodiment includes antenna elements 101-1 to 101-4 arranged as a one-dimensional array, similar to the phased array antenna device of FIG. 1.

[0105] FIG. 12 is a block diagram showing the configuration of the phase shift circuit 107C in the phased array antenna device according to the third embodiment. The phase shift circuit 107C includes a bit shift circuit 4 instead of the adders 2-1 and 2-2 of the phase shift circuit 107A in FIG. 8.

[0106] The storage device 3 stores the control signal K = 0 in advance.

[0107] The control signal K is supplied to the phase shifter 1-1 and controls the phase shift amount of the phase shifter 1-1.

[0108] The control signal D is supplied to the phase shifter 1-2 and controls the phase shift amount of the phase shifter 1-2.

[0109] FIG. 13 is a diagram showing the detailed configuration of the bit shift circuit 4 in FIG. 12. d1, d2,..., d8 represent each bit from the least significant bit to the most significant bit of the 8-bit control signal D. s1, s2,..., s8 represent each bit from the least significant bit to the most significant bit of the output signal of the bit shift circuit 4. The bit shift circuit 4 doubles the value of the control signal D by shifting the bits of the control signal D one bit to the left. The output signal of the bit shift circuit 4 is supplied to the phase shifter 1-3 and controls the phase shift amount of the phase shifter 1-3.

[0110] The output signal of the bit shift circuit 4 is further input to the adder 2-3. The adder 2-3 calculates the sum of the output signal of the bit shift circuit 4 and the control signal D. The signal output from the output terminal of the adder 2-3 is supplied to the phase shifter 1-4 and controls the phase shift amount of the phase shifter 1-4.

[0111] In the third embodiment, the control signal K sets the phase of one of the four radio frequency signals, rather than the common initial phase of the four radio frequency signals.

[0112] When the control signal K has a fixed value K = 0, the signal input to one of the input terminals of the adder 2-1 in FIG. 8 is always 0. Therefore, the adder 2-1 in FIG. 8 may be removed and the control signal D may be directly supplied to the phase shifter 1-2. Also, when the control signal K has a fixed value K = 0, the same control signal D is input to the two input terminals of the adder 2-2 in FIG. 8, and a value twice that of the control signal D is supplied to the phase shifter 1-3. The control signal D having a digital value is doubled, for example, by a shift operation. Therefore, the adder 2-2 in FIG. 8 may be replaced with the bit shift circuit 4.

[0113] According to the phased array antenna device according to the third embodiment, by removing the adders 2-1 and 2-2, the circuit scale can be significantly reduced compared to the case of FIG. 8, and the power consumption can be reduced.

[0114] When the phased array antenna device according to the third embodiment includes five or more antenna elements, control signals for controlling the phase shift amounts of the phase shifters after the fifth one can be generated using a plurality of adders, similar to the adders 2-1 to 2-3 in FIG. 8. In this case, the adder that outputs a signal that is 2 n times (n is a positive integer) the control signal D may be replaced with a bit shift circuit that shifts the bits of the control signal D to the left by n bits. In each of the plurality of adders, a signal output from the bit shift circuit is input to one input terminal, or a signal output from the output terminal of another adder is input, and the control signal D is input to the other input terminal.

[0115] Similar to the phased array antenna device according to the first embodiment, the phased array antenna device according to the third embodiment may be configured to steer its beam to positive and negative angles with respect to a predetermined reference direction.

[0116] [Fourth Embodiment] The phased array antenna device according to the fourth embodiment includes antenna elements 101-1 to 101-16 arranged as a two-dimensional array, similar to the cases of FIGS. 9 to 10.

[0117] FIG. 14 is a block diagram showing the configuration of the phase shift circuit 107D in the phased array antenna device according to the fourth embodiment. The phase shift circuit 107D includes bit shift circuits 4-1 and 4-2 instead of the adders 2-1, 2-2, 2-13, and 2-14 in FIG. 11. Also, similar to the phased array antenna device in FIG. 7, the phase shift circuit 107D includes a storage device 3 that stores the control signal K = 0 in advance.

[0118] The bit shift circuits 4-1 and 4-2 are configured in the same manner as the bit shift circuit 4 in FIG. 13.

[0119] The control signal K is supplied to the phase shifter 1-1 and controls the phase shift amount of the phase shifter 1-1.

[0120] The control signal D1 is supplied to the phase shifter 1-2 and controls the phase shift amount of the phase shifter 1-2.

[0121] The bit shift circuit 4-1 doubles the value of the control signal D1 by shifting the bits of the control signal D1 one bit to the left. The output signal of the bit shift circuit 4-1 is supplied to the phase shifter 1-3 and controls the phase shift amount of the phase shifter 1-3.

[0122] The output signal of the bit shift circuit 4-1 is further input to the adder 2-3. The adder 2-3 calculates the sum of the output signal of the bit shift circuit 4-1 and the control signal D1. The signal output from the output terminal of the adder 2-3 is supplied to the phase shifter 1-4 and controls the phase shift amount of the phase shifter 1-4.

[0123] The control signal D2 is supplied to the phase shifter 1-5 and controls the phase shift amount of the phase shifter 1-5.

[0124] The bit shift circuit 4-2 doubles the value of the control signal D2 by shifting the bits of the control signal D2 one bit to the left. The output signal of the bit shift circuit 4-2 is supplied to the phase shifter 1-9 and controls the phase shift amount of the phase shifter 1-9.

[0125] The output signal of the bit shift circuit 4-2 is further input to the adder 2-15. The adder 2-15 calculates the sum of the output signal of the bit shift circuit 4-2 and the control signal D2. The signal output from the output terminal of the adder 2-15 is supplied to the phase shifter 1-13 and controls the phase shift amount of the phase shifter 1-13.

[0126] The control signals D1 and D2 are input to the adder 2-4.

[0127] In the fourth embodiment, the control signal K sets the phase of one of the 16 radio frequency signals instead of the common initial phase for the 16 radio frequency signals.

[0128] When the control signal K has a fixed value K = 0, the signal input to one of the input terminals of the adder 2-1 in FIG. 11 always becomes 0. Therefore, the adder 2-1 in FIG. 11 may be removed, and the control signal D1 may be directly supplied to the phase shifter 1-2. Also, when the control signal K has a fixed value K = 0, the same control signal D is input to the two input terminals of the adder 2-2 in FIG. 11, and a value twice that of the control signal D1 is supplied to the phase shifter 1-3. Therefore, the adder 2-2 in FIG. 11 may be replaced with a bit shift circuit 4-1.

[0129] Similarly, when the control signal K has a fixed value K = 0, the signal input to one of the input terminals of the adder 2-13 in FIG. 11 always becomes 0. Therefore, the adder 2-13 in FIG. 11 may be removed, and the control signal D2 may be directly supplied to the phase shifter 1-5. Also, when the control signal K has a fixed value K = 0, the same control signal D2 is input to the two input terminals of the adder 2-14 in FIG. 11, and a value twice that of the control signal D2 is supplied to the phase shifter 1-9. Therefore, the adder 2-14 in FIG. 11 may be replaced with a bit shift circuit 4-2.

[0130] According to the phased array antenna device according to the fourth embodiment, by removing the adders 2-1, 2-2, 2-13, and 2-14, the circuit scale can be significantly reduced compared to the case of FIG. 11, and the power consumption can be reduced.

[0131] When the phased array antenna device according to the fourth embodiment includes more antenna elements than 4 elements × 4 elements (see FIG. 10), the control signals for controlling the phase shift amounts of the phase shifters corresponding to the fifth and subsequent antenna elements in the X direction and / or the Y direction can be generated using a plurality of adders in the same manner as the adders 2-1 to 2-3 and 2-13 to 2-15 in FIG. 11. In this case, the adder that outputs a signal that is twice (n is a positive integer) the control signal D1 may be replaced with a bit shift circuit that shifts the bits of the control signal D1 n bits to the left. Similarly, twice the control signal D2 n times (n is a positive integer) of the signal may be replaced with a bit shift circuit that shifts the bits of the control signal D2 n bits to the left. nAn adder that outputs a signal multiplied by a factor of n (where n is a positive integer) may be replaced by a bit shift circuit that shifts the bits of the control signal D2 to the left by n bits. In each of a plurality of adders, a signal output from the bit shift circuit or a signal output from the output terminal of another one of the adders is input to one input terminal, and the control signal D is input to the other input terminal.

[0132] The phased array antenna device according to the fourth embodiment may be configured to steer its beam to positive and negative angles with respect to a predetermined reference direction, similarly to the phased array antenna device according to the second embodiment.

[0133] [Other Embodiments] Each of the described embodiments and each modification may be arbitrarily combined.

[0134] In FIG. 1 and elsewhere, the case where the phase shifter 1 is arranged to control the phase of the high-frequency signal (i.e., the local oscillation signal or LO signal) mixed with the baseband signal has been described. However, the phase shifter 1 may be arranged to control the phase of other signals in the wireless communication device. For example, the phase shifter 1 may be arranged to control the phase of the modulated radio frequency signal (RF signal), or may be arranged to control the phase of the baseband signal (BB signal) or the intermediate frequency signal (IF signal). In any case, the phase shifter 1 can change the phase of the radio frequency signal transmitted via the antenna element so as to finally direct the beam in a desired direction by changing the phase of the LO signal, RF signal, BB signal, or IF signal.

[0135] In FIG. 1 and elsewhere, the case where the wireless communication device is configured to transmit a radio frequency signal has been described. However, due to the duality of the antenna device, the wireless communication device may be configured to receive a radio frequency signal, or the wireless communication device may be configured to transmit and receive a radio frequency signal.

[0136] In FIG. 4, the case where both the control voltage source circuit 11 and the reference voltage source circuit 12 are configured as resistor ladders has been described. However, at least one of the control voltage source circuit 11 and the reference voltage source circuit 12 may be configured as a current output type digital / analog converter.

Industrial Applicability

[0137] According to an aspect of the present disclosure, it is applicable to a phased array antenna device including a digitally controlled phase shifter.

[0138] According to an aspect of the present disclosure, for example, a wireless communication device using a high frequency band such as millimeter waves and terahertz waves can be provided.

Explanation of Signs

[0139] 1-1 to 1-16 Phase shifter 2-1 to 2-15 Adder 3 Memory device 4, 4-1, 4-2 Bit shift circuit 10 Signal generation circuit 11 Control voltage source circuit 12 Reference voltage source circuit 13, 14 Folding circuit 20 Quadrature modulation circuit 21 Quadrature distributor 22, 23 Multiplier 24 Combiner 31 to 33 Differential amplifier 41 to 43 Differential amplifier 51 Constant current source 100, 100A, 100B Wireless communication device 101 Transmission circuit 102-1 to 102-4 Mixer 103-1 to 103-4 Amplifier 104-1 to 104-4 Antenna element 105 Frequency synthesizer 106 Frequency multiplier 107, 107A to 107D Phase shift circuit 108-1 to 108-4 Frequency multiplier 109, 109A, 109B control circuits 110 antenna substrate Resistors R10~R14, R21~R28, R31, R32, R41, R42, Ra~Rd Bipolar transistors Q1, Q2 SW switch

Claims

1. A plurality of antenna elements arranged at a predetermined interval, A phase shifter circuit comprising a plurality of phase shifters that change the phases of a plurality of radio frequency signals transmitted or received via the plurality of antenna elements according to first and second control signals, A control circuit that controls the phase shift amounts of the plurality of phase shifters using the second control signal, The first control signal sets an initial phase of the plurality of radio frequency signals, the second control signal sets a phase difference between two radio frequency signals transmitted or received via two adjacent antenna elements among the plurality of antenna elements, and the first and second control signals have digital values consisting of a plurality of bits, The phase shifter circuit further includes a plurality of adders, each of the plurality of adders having a first input terminal, a second input terminal, and an output terminal. The first control signal is input to the first input terminal, or a signal output from an output terminal of another one of the plurality of adders is input. The second control signal is input to the second input terminal, and the signal output from the output terminal is supplied to one of the plurality of phase shifters to control the phase shift amount of the one phase shifter, A phased array antenna device.

2. The phase shift amounts of the plurality of phase shifters change linearly according to the first and second control signals, The phased array antenna device according to Claim 1.

3. The first control signal is supplied from the control circuit to the phase shifter circuit, The phased array antenna device according to Claim 1.

4. The phase shifter circuit further includes a storage device that stores the first control signal in advance, The phased array antenna device according to Claim 1.

5. The first control signal has a value of 0, The second control signal has any one of a positive value, a negative value, and a value of 0, The phase shift amounts of the plurality of phase shifters have any one of a positive value, a negative value, and a value of 0, The phased array antenna device according to Claim 1.

6. The plurality of antenna elements are arranged as a one-dimensional array, The phased array antenna device according to any one of Claims 1 to 5.

7. The plurality of antenna elements are arranged as a two-dimensional array along first and second directions different from each other, The second control signal is, A third control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the first direction among the plurality of antenna elements; A fourth control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the second direction among the plurality of antenna elements, The plurality of adders, A plurality of first adders to which the third control signal is input, Including a plurality of second adders to which the fourth control signal is input, In each of the plurality of second adders, the signal output from the output terminal is input to the first input terminal in one of the plurality of first adders, or the first input terminal in one of the plurality of first adders and the first input terminal in another one of the plurality of second adders, The phased array antenna device according to one of claims 1 to 5.

8. A plurality of antenna elements arranged at predetermined intervals, A phase shift circuit including a plurality of phase shifters that change the phases of a plurality of radio frequency signals transmitted or received via the plurality of antenna elements according to first and second control signals; A control circuit that controls the phase shift amounts of the plurality of phase shifters using the second control signal, The first control signal sets the phase of one of the plurality of radio frequency signals, the second control signal sets the phase difference between two radio frequency signals transmitted or received via two adjacent antenna elements among the plurality of antenna elements, and the first and second control signals have digital values composed of a plurality of bits, The first control signal is supplied to a first phase shifter among the plurality of phase shifters and controls the phase shift amount of the first phase shifter, The second control signal is supplied to one or a plurality of second phase shifters among the plurality of phase shifters and controls the phase shift amounts of the one or plurality of second phase shifters, The phase shift circuit further includes one or more bit shift circuits and one or more adders, Each of the one or more bit shift circuits shifts the bits of the second control signal so as to increase the digital value of the second control signal, and the signal output from the bit shift circuit is supplied to one or more third phase shifters among the plurality of phase shifters to control the phase shift amount of the one or more third phase shifters. Each of the one or more adders has a first input terminal, a second input terminal, and an output terminal. A signal output from the bit shift circuit is input to the first input terminal, or a signal output from the output terminal of another one of the plurality of adders is input. The second control signal is input to the second input terminal, and the signal output from the output terminal is supplied to one or more fourth phase shifters among the plurality of phase shifters to control the phase shift amount of the one or more fourth phase shifters. Phased array antenna device.

9. The plurality of antenna elements are arranged as a one-dimensional array. The phased array antenna device according to claim 8.

10. The plurality of antenna elements are arranged as a two-dimensional array along first and second directions different from each other. The second control signal includes a third control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the first direction among the plurality of antenna elements, and a fourth control signal for setting a phase difference between two radio frequency signals transmitted or received via two antenna elements adjacent to each other in the second direction among the plurality of antenna elements. The one or more second phase shifters include a fifth phase shifter to which the third control signal is supplied and a sixth phase shifter to which the fourth control signal is supplied. The one or more bit shift circuits include a first bit shift circuit to which the third control signal is input and a second bit shift circuit to which the fourth control signal is input. The one or more third phase shifters include a seventh phase shifter to which the signal output from the first bit shift circuit is supplied and an eighth phase shifter to which the signal output from the second bit shift circuit is supplied. The one or more adders include a plurality of first adders to which the third control signal is input and one or more second adders to which the fourth control signal is input. In each of the one or more second adders, the signal output from the output terminal is input to the first input terminal in one of the plurality of first adders, or is input to the first input terminal in one of the plurality of first adders and the first input terminal in another one of the plurality of second adders. The phased array antenna device according to claim 8.

11. The phased array antenna device according to claim 1, and a wireless communication circuit, a wireless communication device.

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