Display device

Abstract

To provide a display device with a light-transmitting structure in which a light-receiving device on the rear side can normally receive light.SOLUTION: A display device includes: a substrate having a display area in which an image can be displayed and a non-display area outside the display area; a plurality of subpixels included in the display area and each including a plurality of light-emitting elements; and a plurality of data lines for supplying data signals for image display to the plurality of subpixels. The display area includes a first area capable of transmitting light and a second area located outside the first area. The second area includes an upper area located above the first area and a lower area located below the first area. The plurality of data lines include a first data line passing through all the upper area, the first area and the lower area, an upper data line arranged in the upper area, a lower data line arranged in the lower area, and a bypass line electrically connecting the upper data line and the lower data line and bypassing the first area.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] With the development of technology, in addition to the image display function, a display device can provide a photographing function and various sensing functions. For this purpose, the display device must be provided with electronic devices (also referred to as light receiving devices or sensors) such as cameras and sensing sensors.

[0003] Since the electronic device needs to receive light from the front of the display device, it must be installed at a position where light is received. Therefore, in a conventional display device, a camera (camera lens) and a sensing sensor had to be exposed on the front surface. As a result, the bezel of the display device became large, or there were significant restrictions on the design of the display device.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present disclosure can provide a display device having a light transmission structure that allows an electronic device that needs to receive light to receive light (for example, visible light, infrared light, or ultraviolet light) normally without being exposed on the front surface.

[0005] Embodiments of the present disclosure can provide a display device that can improve the transmittance of an optical region (first region) through which light can pass.

[0006] Embodiments of the present disclosure can provide a display device having a structure that reduces the metal ratio in an optical region (first region) through which light can pass.

[0007] Embodiments of the present disclosure can provide a display device having a panel structure that can improve the sensing performance of a sensing sensor that uses light transmitted through an optical region (first region).

[0008] Embodiments of the present disclosure can provide a display device having a panel structure capable of improving the camera performance of a camera using light transmitted through an optical region (first region). **Means for Solving the Problems**

[0009] A display device according to an embodiment of the present disclosure can include a substrate including a display region capable of image display and a non-display region outside the display region, a plurality of sub-pixels included in the display region and each including a plurality of light-emitting elements, and a plurality of data lines for supplying data signals for image display to the plurality of sub-pixels.

[0010] The display region can include a first region capable of transmitting light and a second region located outside the first region.

[0011] The second region can include an upper region located above the first region and a lower region located below the first region. The upper region, the first region, and the lower region can be regions that are partitioned when viewed from above.

[0012] The plurality of data lines can include a first data line extending from the upper region through the first region to the lower region, an upper data line disposed in the upper region, a lower data line disposed in the lower region, and a bypass wiring that electrically connects the upper data line and the lower data line and bypasses the first region.

[0013] The bypass wiring can include a first bypass wiring connected to the upper data line, a second bypass wiring connected to the lower data line, and a third bypass wiring connecting the first bypass wiring and the second bypass wiring.

[0014] The bypass wiring can include a horizontally extending horizontal bypass wiring and a vertically extending vertical bypass wiring. The first bypass wiring and the second bypass wiring may be horizontal bypass wirings, and the third bypass wiring may be a vertical bypass wiring.

[0015] The horizontal detour wiring may be disposed on the first metal layer, and the vertical detour wiring may be disposed on a second metal layer different from the first metal layer.

[0016] The plurality of light-emitting elements may each include a plurality of pixel electrodes.

[0017] The plurality of pixel electrodes may be disposed in an upper region, a first pixel electrode included in a first sub-pixel and disposed in the upper region, a second pixel electrode included in a second sub-pixel and disposed in the upper region, a third pixel electrode included in a third sub-pixel and disposed in a first region, a fourth pixel electrode included in a fourth sub-pixel and disposed in the first region, a fifth pixel electrode included in a fifth sub-pixel and disposed in a lower region, and a sixth pixel electrode included in a sixth sub-pixel and disposed in the lower region.

[0018] The first data line can be connected to the first sub-pixel, the third sub-pixel, and the fifth sub-pixel.

[0019] The upper data line can be connected to the second sub-pixel.

[0020] The lower data line can be connected to the sixth sub-pixel.

[0021] In the display device according to the embodiment of the present disclosure, the third pixel electrode and the fourth pixel electrode can be electrically connected.

[0022] The light emission colors of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel may be the same.

[0023] Each of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fifth sub-pixel, and the sixth sub-pixel can include a light-emitting element and a sub-pixel circuit that drives the light-emitting element. The sub-pixel circuit can include two or more transistors.

[0024] The fourth sub-pixel includes a light-emitting element, but may not include a sub-pixel circuit. In this case, the light-emitting element of the fourth sub-pixel can be driven by the sub-pixel circuit of the third sub-pixel.

[0025] The drive current output from the sub-pixel circuit of the third sub-pixel can be supplied to the third pixel electrode and the fourth pixel electrode.

[0026] The display device according to an embodiment of the present disclosure can be arranged in the first region and further include a connection wiring that electrically connects the third pixel electrode and the fourth pixel electrode.

[0027] The third pixel electrode, the connection wiring, and the fourth pixel electrode can be integrally configured.

[0028] The plurality of pixel electrodes can be arranged in the upper region and further include a seventh pixel electrode included in the seventh sub-pixel, an eighth pixel electrode included in the eighth sub-pixel arranged in the second region, and a ninth pixel electrode included in the ninth sub-pixel arranged in the lower region.

[0029] The plurality of data lines can further include a second data line connected to the seventh sub-pixel, the eighth sub-pixel, and the ninth sub-pixel.

[0030] The emission colors of the seventh sub-pixel, the eighth sub-pixel, and the ninth sub-pixel may be different from the emission colors of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel.

[0031] The second data line can intersect and overlap with a portion (i.e., a connection wiring) where the third pixel electrode and the fourth pixel electrode are connected.

[0032] As an example, in the first region and the second region, the first data line and the second data line may be arranged in the same metal layer and spaced apart on the same plane.

[0033] In another example, in the second region, the first data line and the second data line can be arranged in the same metal layer. In at least a part of the first region, the first data line and the second data line may be arranged in different metal layers.

[0034] For example, in the second region, the first data line and the second data line may be arranged in the same metal layer and spaced apart from each other on the same plane. The first region can include a transmissive region and a non - transmissive region. In the transmissive region, the first data line and the second data line are arranged in different metal layers and can overlap in the vertical direction. In the non - transmissive region, the first data line and the second data line may be arranged in the same metal layer and spaced apart from each other on the same plane.

[0035] The display device according to an embodiment of the present disclosure can further include an electronic device that is located below the substrate, overlaps the first region, and performs a predetermined operation using light that passes through the first region.

[0036] The display device according to an embodiment of the present disclosure can include a substrate including a display region capable of image display and a non - display region outside the display region, a plurality of sub - pixels each including a plurality of pixel electrodes included in the display region, and a plurality of data lines for supplying data signals for image display to the plurality of sub - pixels.

[0037] The display area can include a first area capable of transmitting light and a second area located outside the first area.

[0038] The second area can include an upper area located above the first area and a lower area located below the first area.

[0039] The plurality of pixel electrodes can include a first pixel electrode disposed in the upper area and included in the first sub-pixel, a second pixel electrode disposed in the upper area and included in the second sub-pixel, a third pixel electrode disposed in the first area and included in the third sub-pixel, a fourth pixel electrode disposed in the first area and included in the fourth sub-pixel, a fifth pixel electrode disposed in the lower area and included in the fifth sub-pixel, and a sixth pixel electrode disposed in the lower area and included in the sixth sub-pixel.

[0040] The plurality of data lines are arranged to extend from the upper area through the first area to the lower area, and can include a first data line connected to the first sub-pixel, the third sub-pixel, and the fifth sub-pixel, an upper data line disposed in the upper area and connected to the second sub-pixel, and a lower data line disposed in the lower area and connected to the sixth sub-pixel.

[0041] The third pixel electrode and the fourth pixel electrode can be electrically connected.

[0042] The display device according to an embodiment of the present disclosure can further include a connection wiring disposed in the first area and electrically connecting the third pixel electrode and the fourth pixel electrode.

[0043] According to an embodiment of the present specification, a display device having a light-transmitting structure can be provided in which an electronic device to receive light is not entirely exposed and the electronic device can normally receive light (e.g., visible light, infrared light, or ultraviolet light, etc.).

[0044] According to an embodiment of the present disclosure, it is possible to provide a display device capable of improving the transmittance of an optical region (first region) through which light can pass.

[0045] According to an embodiment of the present disclosure, it is possible to provide a display device having a structure that reduces the metal ratio in an optical region (first region) through which light can pass.

[0046] According to an embodiment of the present disclosure, it is possible to provide a display device having a panel structure capable of improving the sensing performance of a sensing sensor that uses light transmitted through an optical region (first region).

[0047] According to an embodiment of the present disclosure, it is possible to provide a display device having a panel structure capable of improving the camera performance of a camera that uses light transmitted through an optical region (first region).

[0048] The effects of the present specification are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

Brief Description of the Drawings

[0049]

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Mode for Carrying Out the Invention

[0050] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, the same components may be denoted by the same numerals as much as possible even if they are shown on other drawings. In the description of the present invention, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case of including a plurality unless otherwise explicitly stated.

[0051] Also, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used. These terms are only for distinguishing the components from other components, and the essence, order, sequence, number, etc. of the components are not limited by these terms.

[0052] In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled", or "joined", it should be understood that two or more components can be directly "connected", "coupled", or "joined", but it is also possible that two or more components and other components are further "interposed" and "connected", "coupled", or "joined". Here, the other components may be included in one or more of the two or more components that are "connected", "coupled", or "joined" to each other.

[0053] In the description of the relationship of the time flow regarding components, operation methods, manufacturing methods, etc., for example, when the time sequence relationship or the flow sequence relationship is described by "after ~", "subsequent to ~", "next ~", "before ~", etc., it may include the case where it is not continuous unless "immediately" or "directly" is used.

[0054] On the one hand, when a numerical value related to a component or its corresponding information (e.g., level, etc.) is mentioned, even without a separate explicit description, the numerical value or its corresponding information can be interpreted as including the range of errors that can occur due to various factors (e.g., process factors, internal or external impacts, noise, etc.).

[0055] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. FIGS. 1a, 1b, and 1c show a display device 100 according to an embodiment of the present disclosure.

[0056] Referring to FIGS. 1a, 1b, and 1c, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 that displays an image, and one or more electronic devices 11, 12.

[0057] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. A plurality of sub-pixels and various signal lines for driving the plurality of sub-pixels may be arranged in the display area. The non-display area NDA may be an outer area of the display area DA. Various signal lines may be arranged in the non-display area NDA, and various driving circuits may be connected to the non-display area NDA. The non-display area NDA is bent and becomes invisible from the front or is covered by a case (not shown). The non-display area NDA is also called a bezel or bezel area.

[0058] The display device 100 according to an embodiment of the present disclosure may include one or more electronic devices 11, 12 located below the display panel 110 (opposite to the viewing surface). Here, the one or more electronic devices 11, 12 may be provided separately from the display panel 110.

[0059] The one or more electronic devices 11, 12 may be devices that receive light transmitted through the display panel 110 and perform a predetermined function using the received light.

[0060] For example, one or more electronic devices 11, 12 can include one or more of an imaging device such as a camera (image sensor), a proximity sensor, and a sensing sensor such as an illuminance sensor. Here, for example, the sensing sensor can be an infrared sensor.

[0061] The light necessary for the operation of one or more electronic devices 11, 12 enters the front (viewing surface) of the display panel 110, passes through the display panel 110, and can be transmitted to one or more electronic devices 11, 12 located below the display panel 110 (on the side opposite to the viewing surface). For example, the light necessary for the operation of one or more electronic devices 11, 12 and passing through the display panel 110 can include one or more of visible light, infrared rays, ultraviolet rays, etc.

[0062] Referring to FIGS. 1a, 1b, and 1c, in the display panel 110 according to an embodiment of the present disclosure, the display area DA can include a general area NA and one or more optical areas OA1, OA2. One or more optical areas OA1, OA2 can be areas that overlap with one or more optoelectronic devices 11, 12.

[0063] According to the example of FIG. 1a, the display area DA can include a general area NA and a first optical area OA1. Here, at least a part of the first optical area OA1 can overlap with the first optoelectronic device 11.

[0064] According to the example of FIG. 1b, the display area DA can include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of FIG. 1b, a general area NA may exist between the first optical area OA1 and the second optical area OA2. Here, at least a part of the first optical area OA1 can overlap with the first electronic device 11, and at least a part of the second optical area OA2 can overlap with the second electronic device 12.

[0065] According to the illustration of FIG. 1c, the display area DA can include a general area NA, a first optical area OA1, and a second optical area OA2. In the illustration of FIG. 1c, there is no general area NA between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 are in contact with each other. Here, at least a part of the first optical area OA1 may overlap with the first electronic device 11, and at least a part of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0066] In one or more optical areas OA1, OA2, both an image display structure and a light transmission structure must be formed. That is, since one or more optical areas OA1, OA2 are partial areas of the display area DA, light-emitting areas of sub-pixels for image display must be arranged in one or more optical areas OA1, OA2. And in one or more optical areas OA1, OA2, a light transmission structure for transmitting light to one or more electronic devices 11, 12 must be formed.

[0067] One or more electronic devices 11, 12 are located behind the display panel 110 (below, on the opposite side of the viewing surface) and are configured to receive light transmitted through the display panel 110.

[0068] One or more optoelectronic devices 11, 12 are not exposed on the front surface (viewing surface) of the display panel 110. Therefore, when the user looks at the front surface of the display device 100, the electronic devices 11, 12 are not visible to the user.

[0069] For example, the first electronic device 11 may be a camera that receives light in the visible light wavelength band (visible light), and the second electronic device 12 may be a sensing sensor such as a proximity sensor or an illuminance sensor. For example, the sensing sensor may be an infrared sensor that senses light in the infrared wavelength band (infrared). Conversely, the first electronic device 11 may be a sensing sensor and the second electronic device 12 may be a camera.

[0070] Hereinafter, for the sake of convenience of explanation, an example will be described in which the first electronic device 11 is a camera and the second electronic device 12 is an infrared-based sensing sensor. Here, the camera can be a camera lens or an image sensor.

[0071] When the first electronic device 11 is a camera, this camera is located behind (lower part) the display panel 110, but it may also be a front camera that captures in the front direction of the display panel 110. Therefore, the user can perform shooting (self-shooting) through a camera that is not visible on the viewing surface while looking at the viewing surface of the display panel 110.

[0072] The general area NA and the one or more optical areas OA1, OA2 included in the display area DA can be areas where image display is possible. However, the general area NA is an area where a light transmission structure does not need to be formed, and the one or more optical areas OA1, OA2 can be areas where a light transmission structure should be formed.

[0073] Therefore, the one or more optical areas OA1, OA2 should have a transmittance of a certain level or higher, and the general area NA can have no light transmittance or a low transmittance of less than a certain level.

[0074] For example, the one or more optical areas OA1, OA2 and the general area NA may differ from each other in terms of resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure, etc.

[0075] For example, the number of sub-pixels per unit area in one or more optical regions OA1 and OA2 may be less than the number of sub-pixels per unit area in the general region NA. That is, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the general region NA. Here, the number of sub-pixels per unit area may have the same meaning as resolution or pixel density or pixel integration. For example, the unit of the number of sub-pixels per unit area can also be said to be PPI (Pixels Per Inch), which means the number of pixels within 1 inch.

[0076] For example, the number of sub-pixels per unit area in the first optical region OA1 may be less than the number of sub-pixels per unit area in the general region NA. The number of sub-pixels per unit area in the second optical region OA2 may be less than the number of sub-pixels per unit area in the general region NA, even if it is equal to or more than the number of sub-pixels per unit area in the first optical region OA1.

[0077] On the other hand, as one method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, as described above, the pixel density difference design method can be applied. According to the pixel density difference design method, the display panel 110 can be designed such that the number of sub-pixels per unit area of at least one of the first optical region OA1 and the second optical region OA2 is less than the number of sub-pixels per unit area of the general region NA.

[0078] However, in some cases, different from this, as another method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, a pixel size difference design method can be applied. According to the pixel size difference design method, although the number of sub-pixels per unit area of at least one of the first optical region OA1 and the second optical region OA2 is the same as or similar to the number of sub-pixels per unit area of the general region NA, the size of each sub-pixel SP (i.e., the light-emitting region size) arranged in at least one of the first optical region OA1 and the second optical region OA2 is designed to be smaller than the size of each sub-pixel SP (i.e., the light-emitting region size) arranged in the general region NA, so that the display panel 110 can be designed.

[0079] Hereinafter, for the convenience of explanation, among the two methods (pixel density difference design method, pixel size difference design method) for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, it is assumed that the pixel density difference design method is applied and the explanation is given. Therefore, hereinafter, the fact that the number of sub-pixels per unit area is small may be an expression corresponding to the fact that the sub-pixel size is small, and the fact that the number of sub-pixels per unit area is large may be an expression corresponding to the fact that the sub-pixel size is large.

[0080] The first optical region OA1 can have various shapes, such as circular, elliptical, square, hexagonal, or octagonal. The second optical region OA2 can have various shapes, such as circular, elliptical, square, hexagonal, or octagonal. The first optical region OA1 and the second optical region OA2 may have the same shape or different shapes.

[0081] Referring to FIG. 1c, when the first optical region OA1 and the second optical region OA2 are in contact, the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes, such as circular, elliptical, square, hexagonal, or octagonal. Hereinafter, for the sake of convenience of explanation, it is assumed that the first optical region OA1 and the second optical region OA2 are each circular.

[0082] In the display device 100 according to an embodiment of the present disclosure, when the first electronic device 11, which is hidden under the display panel 110 and not exposed to the outside, is a camera, the display device 100 according to the embodiment of the present disclosure can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0083] According to this, in the case of the display device 100 according to the embodiment of the present disclosure, since a notch or a camera hole for camera exposure does not have to be formed in the display panel 110, a decrease in the area of the display area DA does not occur. As a result, since a notch or a camera hole for camera exposure does not have to be formed in the display panel 110, the size of the bezel area can be reduced, there are no design constraints, and the degree of freedom in design can be increased.

[0084] In the display device 100 according to an embodiment of the present disclosure, although one or more electronic devices 11, 12 are arranged hidden behind the display panel 110, the one or more electronic devices 11, 12 must be able to receive light normally and execute a predetermined function normally.

[0085] Further, in the display device 100 according to an embodiment of the present disclosure, although one or more electronic devices 11, 12 are arranged hidden behind the display panel 110 and overlap with the display area DA, in the display area DA, normal image display must be possible in one or more optical regions OA1, OA2 that overlap with the one or more electronic devices 11, 12.

[0086] Since the above-described first optical region OA1 is designed as a transmissive region, the image display characteristics in the first optical region OA1 may be different from those in the general region NA.

[0087] In addition, when designing the first optical region OA1 to improve the image display characteristics, there is also a possibility that the transmittance of the first optical region OA1 may decrease.

[0088] Therefore, an embodiment of the present disclosure presents a structure of the first optical region OA1 that can improve the transmittance in the first optical region OA1 without causing image quality variations between the first optical region OA1 and the general region NA.

[0089] In addition, an embodiment of the present disclosure presents a structure of the second optical region OA2 that can improve the image quality and the transmittance in the second optical region OA2 not only for the first optical region OA1 but also for the second optical region OA2.

[0090] Note that in the display device 100 according to the embodiment of the present disclosure, the first optical region OA1 and the second optical region OA2 are similar in that they are regions where light transmission is possible, but their usage examples may be different.

[0091] Therefore, in the display device 100 according to the embodiment of the present disclosure, the structure of the first optical region OA1 and the structure of the second optical region OA2 are basically similar or the same, but the resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure may be different from each other.

[0092] FIG. 2 is a configuration diagram of the system of the display device 100 according to the embodiment of the present disclosure.

[0093] Referring to FIG. 2, the display device 100 can include components for image display, including a display panel 110 and a display driving circuit. The display driving circuit is a circuit for driving the display panel 110 and can include a data driving circuit 220, a gate driving circuit 230, a display controller 240, and the like.

[0094] The display panel 110 can include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The non-display area NDA may be an outer area of the display area DA, which can also be referred to as a bezel area. All or part of the non-display area NDA can be an area visible from the front of the display device 100 or an area that is bent and not visible from the front of the display device 100.

[0095] The display panel 110 can include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. Further, the display panel 110 can further include various types of signal lines for driving the plurality of sub-pixels SP.

[0096] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP can include a light-emitting element. For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting element is realized by an organic light-emitting diode (OLED). As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is realized by an inorganic-based light-emitting diode. As yet another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting element is a quantum dot that is a semiconductor crystal that emits light by itself.

[0097] Depending on the type of the display device 100, the structure of each of the plurality of sub-pixels SP can vary. For example, when the display device 100 is a self-emitting display device that emits light from the sub-pixels SP by itself, each sub-pixel SP can include a light-emitting element that emits light by itself, one or more transistors, and one or more capacitors.

[0098] For example, some types of signal lines can include a plurality of data lines DL that transmit data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL that transmit gate signals (also referred to as scan signals).

[0099] The plurality of data lines DL and the plurality of gate lines GL can intersect with each other. Each of the plurality of data lines DL can be arranged while extending in a first direction. Each of the plurality of gate lines GL can be arranged while extending in a second direction. Here, the first direction can be the column direction, and the second direction can be the row direction. Or, the first direction can be the row direction, and the second direction can be the column direction. Hereinafter, for the sake of convenience of explanation, an example will be given in which each of the plurality of data lines DL is arranged in the column direction and each of the plurality of gate lines GL is arranged in the row direction.

[0100] The data driving circuit 220 is a circuit for driving the plurality of data lines DL, and can output a data signal to the plurality of data lines DL. The gate driving circuit 230 is a circuit for driving the plurality of gate lines GL, and can output a gate signal to the plurality of gate lines GL.

[0101] The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing for the plurality of data lines DL and the driving timing for the plurality of gate lines GL.

[0102] The display controller 240 can supply a data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and can supply a gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0103] The display controller 240 can receive input image data from the host system 250 and supply image data (Data) to the data drive circuit 220 based on the input image data.

[0104] The data drive circuit 220 can receive image data (Data) in digital format from the display controller 240, convert the received image data (Data) into an analog data signal, and output it to a plurality of data lines DL.

[0105] The gate drive circuit 230 is supplied with a first gate voltage corresponding to the turn-on level voltage and a second gate voltage corresponding to the turn-off level voltage together with various gate drive control signals GCS, generates a gate signal, and can supply the generated gate signal to a plurality of gate lines GL.

[0106] For example, the data drive circuit 220 can be connected to the display panel 110 in a tape automated bonding (TAB) method, or can be connected to the bonding pads of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or can be implemented in a chip on film (COF) method and be connected to the display panel 110.

[0107] The gate driving circuit 230 can be connected to the display panel 110 in a tape automated bonding (TAB) method, or connected to the bonding pads of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or can be connected to the display panel 110 according to the chip on film (COF) method. Alternatively, the gate driving circuit 230 may be of a gate in panel (GIP) type and formed in the non-display area NDA of the display panel 110. The gate driving circuit 230 may be disposed on the substrate or connected to the substrate. That is, in the case of the GIP type, the gate driving circuit 230 can be disposed in the non-display area NDA of the substrate. When the gate driving circuit 230 is of the chip on glass (COG) type, chip on film (COF) type, etc., it can be connected to the substrate.

[0108] On the other hand, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed so as not to overlap with the sub-pixel SP, or may be disposed so as to partially or entirely overlap with the sub-pixel SP.

[0109] The data driving circuit 220 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 220 may be entirely connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110.

[0110] The gate driving circuit 230 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 230 may be entirely connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110.

[0111] The display controller 240 can be realized as a component separate from the data driving circuit 220, or can be integrated with the data driving circuit 220 and realized as an integrated circuit.

[0112] The display controller 240 may be a timing controller used in ordinary display technology, or may be a control device that can further execute other control functions including the timing controller, or may be a control device different from the timing controller, or may be a circuit within the control device. The display controller 240 can be realized as various circuits and electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or a processor (Processor).

[0113] The display controller 240 is mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data driving circuit 220 and the gate driving circuit 230 via the printed circuit board, the flexible printed circuit, etc.

[0114] The display controller 240 can transmit and receive signals with the data driving circuit 220 according to one or more predetermined interfaces. For example, the interface can include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Clock Point-Point Interface) interface, an SPI (Serial Peripheral Interface), etc.

[0115] The display device 100 according to an embodiment of the present disclosure can include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch is generated by a touch object such as a finger or a pen, or to detect a touch position, in order to provide not only an image display function but also a touch sensing function.

[0116] The touch sensing circuit can include a touch drive circuit 260 that drives and senses the touch sensor to generate and output touch sensing data, and a touch controller 270 that can sense touch occurrence or detect a touch position using the touch sensing data.

[0117] The touch sensor can include a plurality of touch electrodes. The touch sensor can further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch drive circuit 260.

[0118] The touch sensor may exist in the form of a touch panel outside the display panel 110 or inside the display panel 110. When the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is of the external type, the touch panel and the display panel 110 can be separately manufactured and combined in the assembly process. The external type touch panel can include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0119] When the touch sensor exists inside the display panel 110, the touch sensor can be formed on the substrate SUB together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0120] The touch drive circuit 260 can supply a touch drive signal to at least one of the plurality of touch electrodes, sense at least one of the plurality of touch electrodes, and generate touch sensing data.

[0121] The touch sensing circuit can perform touch sensing in a self - capacitance sensing method or a mutual - capacitance sensing method.

[0122] When the touch sensing circuit performs touch sensing in the self - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (such as a finger, a pen, etc.). According to the self - capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0123] When the touch sensing circuit performs touch sensing in the mutual - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual - capacitance sensing method, the plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0124] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be realized as separate devices or as one device. Also, the touch driving circuit 260 and the data driving circuit 220 may be realized as separate devices or as one device.

[0125] The display device 100 can further include a power supply circuit that supplies various power supplies to the display driving circuit and / or the touch sensing circuit.

[0126] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or a television (TV) of various sizes, and is not limited thereto, and may be a display of various types and various sizes capable of presenting information and images.

[0127] As described above, the display area DA in the display panel 110 can include a general area NA and one or more optical areas OA1, OA2. The general area NA and the one or more optical areas OA1, OA2 are areas where image display is possible. However, the general area NA is an area where a light transmission structure does not need to be formed, and the one or more optical areas OA1, OA2 are areas where a light transmission structure should be formed.

[0128] As described above, in the display panel 110, the display area DA can include one or more optical areas OA1, OA2 together with the general area NA. For the sake of convenience of explanation, it is assumed that the display area DA includes both the first optical area OA1 and the second optical area OA2 (FIGS. 1b and 1c).

[0129] FIG. 3 shows a display panel 110 according to an embodiment of the present disclosure.

[0130] Referring to FIG. 3, a plurality of sub-pixels SP can be arranged in the display area DA of the display panel 110. The plurality of sub-pixels SP can be arranged in the general area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA.

[0131] Referring to FIG. 3, each of the plurality of sub-pixels SP can include a light-emitting element ED and a pixel circuit SPC configured to drive the light-emitting element ED.

[0132] Referring to FIG. 3, the sub-pixel circuit SPC can include a driving transistor DT for driving the light-emitting element ED, a scan transistor ST for transmitting the data voltage VDATA to the driving transistor DT, and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0133] The driving transistor DT can include a first node N1, a second node N2, and a third node N3.

[0134] The first node N1 can be electrically connected to the light-emitting element ED. The second node N2 may be connected to the scan transistor ST. The third node N3 can be connected to the driving voltage line VDDL.

[0135] The first node N1 can be electrically connected to the pixel electrode PE of the light-emitting element ED. The data voltage VDATA can be applied to the second node N2. The driving voltage VDD can be applied to the third node N3.

[0136] The first node N1 is a source node or a drain node, the second node N2 is a gate node, and the third node N3 can be a drain node or a source node. Hereinafter, for convenience of explanation, in the driving transistor DT, the case where the first node N1 is a source node, the second node N2 is a gate node, and the third node N3 is a drain node will be taken as an example.

[0137] The light-emitting element ED can include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0138] The pixel electrode PE may be an electrode disposed in each sub-pixel SP. For example, the pixel electrode PE can be electrically connected directly or indirectly (through other transistors) to the first node N1 of the driving transistor DT of each sub-pixel SP.

[0139] The common electrode CE may be an electrode commonly disposed for a plurality of sub-pixels SP. For example, the common electrode CE can be electrically connected to the base voltage line VSSL. A base voltage VSS, which is a kind of common driving voltage, can be applied to the common electrode CE via the base voltage line VSSL.

[0140] For example, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. Conversely, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode. Hereinafter, for convenience of explanation, it is assumed that the pixel electrode PE is an anode electrode and the common electrode CE is a cathode electrode.

[0141] The intermediate layer EL may include a light-emitting layer EML and a common intermediate layer EL_COM.

[0142] As an example, the light-emitting layer EML may be disposed for each of the plurality of sub-pixels SP, or as another example, may be commonly disposed for the plurality of sub-pixels SP. The common intermediate layer EL_COM can be commonly disposed across the plurality of sub-pixels SP.

[0143] The light-emitting layer EML can be disposed for each light-emitting region EA, and the common intermediate layer EL_COM can be commonly disposed across a plurality of light-emitting regions EA and non-light-emitting regions.

[0144] The common intermediate layer EL_COM may include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 is disposed between the pixel electrode PE and the light-emitting layer EML and can include at least one layer (for example, an organic layer). The second common intermediate layer COM2 is disposed between the light-emitting layer EML and the common electrode CE and can include at least one layer (for example, an organic layer).

[0145] For example, the first common intermediate layer COM1 can include a hole injection layer (HIL, Hole Injection Layer) and a hole transport layer (HTL, Hole Transfer Layer), etc. The second common intermediate layer COM2 can include an electron transport layer (ETL, Electron Transfer Layer) and an electron injection layer (EIL, Electron Injection Layer), etc.

[0146] The hole injection layer injects holes from the pixel electrode PE into the hole transport layer, the hole transport layer transports holes to the light-emitting layer EML, the electron injection layer injects electrons from the common electrode CE into the electron transport layer, and the electron transport layer can transport electrons to the light-emitting layer EML.

[0147] Each light-emitting element ED can be composed of the overlapping portion of the pixel electrode PE, the light-emitting layer EML in the intermediate layer EL, and the common electrode CE. A predetermined light-emitting region EA can be formed by each light-emitting element ED. For example, the light-emitting region EA can be defined as the region where the pixel electrode PE, the light-emitting layer EML of the intermediate layer EL, and the common electrode CE overlap.

[0148] For example, the light-emitting element ED may be an organic-based organic light-emitting diode (OLED: Organic Light Emitting Diode), an inorganic-based inorganic light-emitting diode, or a quantum dot light-emitting element, etc. When the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL in the light-emitting element ED can include an organic layer containing an organic substance.

[0149] The scan transistor ST is turned on and off by a scan signal SC which is a type of gate signal applied via a scan signal line SCL which is a type of gate line GL, and can be electrically connected between the second node N2 of the drive transistor DT and the data line DL.

[0150] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the drive transistor DT.

[0151] As shown in FIG. 3, the sub-pixel circuit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DT and ST and one capacitor Cst. In some cases, it may further include one or more transistors, or may further include one or more capacitors.

[0152] The storage capacitor Cst is not a parasitic capacitor (e.g., Cgs, Cgd), which is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT, but may be an externally designed external capacitor outside the driving transistor DT. The driving transistor DT and the scan transistor ST may each be an n-type transistor or a p-type transistor.

[0153] Circuit elements within each sub-pixel SP (particularly, the light-emitting element ED realized by an organic light-emitting diode OLED containing an organic substance) are vulnerable to external moisture, oxygen, etc. Therefore, a sealing layer ENCAP for preventing external moisture and oxygen from penetrating into the circuit elements (particularly, the light-emitting element ED) may be disposed on the display panel 110. The sealing layer ENCAP can be disposed in a form that covers the light-emitting element ED.

[0154] Referring to FIG. 3, the display device 100 according to an embodiment of the present disclosure may include a touch sensor layer TSL including a plurality of sensor electrodes, a touch driving circuit 260 configured to sense the plurality of sensor electrodes, and a touch controller 270 configured to determine the presence or absence of a touch or the touch coordinates using the sensing result (touch sensing data) of the touch driving circuit 260.

[0155] The touch sensor layer TSL may be built into the display panel 110. For example, the touch sensor layer TSL can be disposed on the sealing layer ENCAP within the display panel 110.

[0156] The display panel 110 may further include a plurality of touch pads TP to which the touch driving circuit 260 is electrically connected, and a plurality of touch routing wirings for electrically connecting the plurality of sensor electrodes included in the touch sensor layer TSL to the plurality of touch pads TP to which the touch driving circuit 260 is connected.

[0157] FIG. 4 shows a general region NA, a first optical region OA1, and a second optical region OA2 in the display panel 110 according to an embodiment of the present disclosure.

[0158] Referring to FIG. 4, the display panel 110 according to an embodiment of the present disclosure may include a display region DA where an image is displayed and a non-display region NDA where an image is not displayed. The display region DA may include a first optical region OA1, a second optical region OA2, and a general region NA.

[0159] Since the first optical region OA1, the second optical region OA2, and the general region NA are included in the display region DA, they can have a display structure. For example, each of the first optical region OA1, the second optical region OA2, and the general region NA may include a plurality of light emitting regions EA.

[0160] Also, the first optical region OA1 and the second optical region OA2 may be regions where light transmission is possible, and the general region NA may be a region where light transmission is impossible or a region where light transmission is minute. The general region NA may mean a region that cannot transmit light and excludes the first optical region OA1 and the second optical region OA2. Here, the fact that light is transmitted may mean that light passes between the front surface and the back surface of the display panel 110.

[0161] The first optical region OA1 may be a region that overlaps with the first electronic device 11. The second optical region OA2 may be a region that overlaps with the second electronic device 12.

[0162] Each of the first optical region OA1 and the second optical region OA2 can have a light transmission structure. However, the first optical region OA1 and the second optical region OA2 can have different structural characteristics from each other. For example, the transmittance of the first optical region OA1 may be higher than that of the second optical region OA2. The resolution or the number of sub-pixels per unit area of the first optical region OA1 may be less than that of the second optical region OA2.

[0163] The first electronic device 11 can perform a defined operation using light in the first wavelength band among the light transmitted through the first optical region OA1. The second electronic device 12 can perform a defined operation using light in a second wavelength band different from the first wavelength band among the light transmitted through the second optical region OA2.

[0164] The first wavelength band can include one or more of the wavelength bands of visible light, infrared light, ultraviolet light, etc. The second wavelength band can include one or more of the wavelength bands of visible light, infrared light, and ultraviolet light, etc., but may be different from the first wavelength band.

[0165] For example, the first electronic device 11 can be a camera, and the second electronic device 12 can be a sensing sensor. The first electronic device 11 can perform a camera operation using light in the wavelength band of visible light corresponding to the first wavelength band among the light transmitted through the first optical region OA1. The second electronic device 12 can perform a sensing operation using light in the wavelength band of infrared light corresponding to the second wavelength band among the light transmitted through the second optical region OA2.

[0166] Referring to FIG. 4, each of the first optical region OA1 and the second optical region OA2 can be circular or octagonal, etc. Without being limited thereto, each of the first optical region OA1 and the second optical region OA2 can have various shapes such as an elliptical shape, a polygonal shape, or an irregular shape.

[0167] The first optical region OA1 and the second optical region OA2 may have the same shape as each other. Alternatively, the first optical region OA1 and the second optical region OA2 may have different shapes from each other.

[0168] Referring to FIG. 4, the display region DA can include a plurality of light-emitting regions EA. Since the general region NA, the first optical region OA1, and the second optical region OA2 are regions included in the display region DA, each of the general region NA, the first optical region OA1, and the second optical region OA2 can include a plurality of light-emitting regions EA.

[0169] The plurality of light-emitting regions EA can include light-emitting regions that emit light of three or more colors. For example, the plurality of light-emitting regions EA can include a first-color light-emitting region that emits light of a first color, a second-color light-emitting region that emits light of a second color, and a third-color light-emitting region that emits light of a third color.

[0170] For example, when the light of the first color is red light, the light of the second color is green light, and the light of the third color is blue light, the first-color light-emitting region may be referred to as a red light-emitting region EA_R, the second-color light-emitting region may be referred to as a green light-emitting region EA_G, and the third-color light-emitting region may be referred to as a blue light-emitting region EA_B.

[0171] The red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B can have the same size (light-emitting area size). Alternatively, at least one of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B can have a size (light-emitting area size) different from the remaining portions.

[0172] As described above, the first color, the second color, and the third color may be various colors as different colors. For example, the first color, the second color, and the third color can include red, green, and blue. Hereinafter, for the sake of convenience of explanation, the case where the first color is red, the second color is green, and the third color is blue will be taken as an example. However, it is not limited thereto.

[0173] When the first color is red, the second color is green, and the third color is blue, the size (emission area size) of the blue light emitting region EA_B among the size (emission area size) of the red light emitting region EA_R, the size (emission area size) of the green light emitting region EA_G, and the size (emission area size) of the blue light emitting region EA_B may be the largest.

[0174] The light emitting element ED disposed in the red light emitting region EA_R may include a light emitting layer EL that emits red light. The light emitting element ED disposed in the green light emitting region EA_G may include a light emitting layer EL that emits green light. The light emitting element ED disposed in the blue light emitting region EA_B may include a light emitting layer EL that emits blue light.

[0175] Among the light emitting layer EL that emits red light, the light emitting layer EL that emits green light, and the light emitting layer EL that emits blue light, the organic substances contained in the light emitting layer EL that emits blue light may be most easily deteriorated materially. Thus, by designing the size of the blue light emitting region EA_B to be the largest, the current density supplied to the light emitting element ED disposed in the blue light emitting region EA_B may be the lowest. Therefore, the degree of deterioration of the light emitting element ED disposed in the blue light emitting region EA_B may be similar to the degree of deterioration of the light emitting element ED disposed in the red light emitting region EA_R and the degree of deterioration of the light emitting element ED disposed in the green light emitting region EA_G.

[0176] Therefore, the variation in deterioration among the light emitting element ED disposed in the red light emitting region EA_R, the light emitting element ED disposed in the green light emitting region EA_G, and the light emitting element ED disposed in the blue light emitting region EA_B is eliminated or reduced, so that the image quality can be improved.

[0177] Referring to FIG. 4, each of the plurality of first transmission regions TA1 included in the first optical region OA1 can have various shapes such as a circular shape, an elliptical shape, a polygonal shape, or an irregular shape. Each of the plurality of second transmission regions TA2 included in the second optical region OA2 can have various shapes such as a circular shape, an elliptical shape, a polygonal shape, or an irregular shape.

[0178] The plurality of first transmission regions TA1 can also have the same shape. Alternatively, some of the plurality of first transmission regions TA1 can have a shape different from the rest. The plurality of second transmission regions TA2 can also have the same shape. Alternatively, some of the plurality of second transmission regions TA2 can have a shape different from the rest.

[0179] The first transmission region TA1 and the second transmission region TA2 can have the same shape as each other. Alternatively, the first transmission region TA1 and the second transmission region TA2 can have different shapes from each other.

[0180] Referring to FIG. 4, the general region NA can correspond to all non-transmission regions. That is, the general region NA can include a non-transmission region NTA including a plurality of light-emitting regions EA. In other words, the whole of the general region NA can be the non-transmission region NTA, and the general region NA may not include the transmission region TA.

[0181] The first optical region OA1 can further include a non-transmission region NTA including a plurality of light-emitting regions EA and a plurality of first transmission regions TA1. The non-transmission region NTA included in the first optical region OA1 may be a region where light is not transmitted at all, or may be a region where light is transmitted at a transmittance lower than that of the first transmission region TA1.

[0182] The second optical region OA2 can further include a non-transmission region NTA including a plurality of light-emitting regions EA and a plurality of second transmission regions TA2. The non-transmission region NTA included in the second optical region OA2 may be a region where light is not transmitted at all, or may be a region where light is transmitted at a transmittance lower than that of the second transmission region TA2.

[0183] On the one hand, the common electrode CE can include a plurality of common electrode holes CH corresponding to the plurality of openings. The plurality of common electrode holes CH can be formed in the first optical region OA1 and the second optical region OA2. That is, the positions where the plurality of common electrode holes CH are formed may be the first optical region OA1 and the second optical region OA2.

[0184] Referring to FIG. 4, in the common electrode CE, the positions where the plurality of common electrode holes CH are formed can respectively correspond to the plurality of first transmission regions TA1 included in the first optical region OA1. And in the common electrode CE, the positions where the plurality of common electrode holes CH are formed can respectively correspond to the plurality of second transmission regions TA2 included in the second optical region OA2. Thereby, the transmittance of each of the first optical region OA1 and the second optical region OA2 can be improved.

[0185] FIG. 5 shows the signal lines SL arranged on the display panel 110 according to an embodiment of the present disclosure.

[0186] Referring to FIG. 5, the display panel 110 according to an embodiment of the present disclosure can include a plurality of sub-pixels SP and a plurality of signal lines SL for driving the plurality of sub-pixels SP.

[0187] Referring to FIG. 5, each of the plurality of sub-pixels SP can include a light-emitting element ED and a sub-pixel circuit SPC for driving it. A light-emitting region EA can be formed by the light-emitting element ED.

[0188] Referring to FIG. 5, the plurality of signal lines SL can supply various driving signals necessary for driving the plurality of sub-pixels SP to the plurality of sub-pixels SP.

[0189] For example, various drive signals can include a data signal VDATA for driving a data line DL, a scan signal SC for driving a gate line GL, and the like. The various drive signals can further include a drive voltage VDD for driving a drive voltage line VDDL and a base voltage VSS for driving a base voltage line VSSL connected to a common electrode CE.

[0190] Therefore, the plurality of signal lines can include a plurality of data lines DL for supplying the data signal VDATA and a plurality of gate lines GL for supplying gate signals such as the scan signal SC. The plurality of signal lines can further include a drive voltage line VDDL for supplying the drive voltage VDD and a base voltage line VSSL for supplying the base voltage VSS.

[0191] Referring to FIG. 5, the display area DA can include a general area NA, a first optical area OA1, and a second optical area OA2.

[0192] Referring to FIG. 5, each of the general area NA, the first optical area OA1, and the second optical area OA2 can include a plurality of light-emitting areas EA. A plurality of light-emitting elements ED and a plurality of sub-pixel circuits SPC can be arranged in each of the general area NA, the first optical area OA1, and the second optical area OA2.

[0193] Referring to FIG. 5, the plurality of signal lines SL can include a plurality of general signal lines SL_NA and a plurality of specific signal lines SL_OA.

[0194] The plurality of general signal lines SL_NA may be signal lines arranged only in the general area NA without passing through the first optical area OA1 and the second optical area OA2.

[0195] The plurality of specific signal lines SL_OA may be signal lines passing through at least one of the first optical area OA1 and the second optical area OA2.

[0196] For example, the plurality of general signal lines SL_NA can include a plurality of data lines DL_NA and a plurality of gate lines GL_NA that do not pass through the first optical region OA1 and the second optical region OA2.

[0197] For example, the plurality of specific signal lines SL_OA can include a plurality of data lines DL_OA and a plurality of gate lines GL_OA that pass through at least one of the first optical region OA1 and the second optical region OA2.

[0198] As described above, as the plurality of specific signal lines SL_OA pass through at least one of the first optical region OA1 and the second optical region OA2, the transmission characteristics of the first optical region OA1 and the second optical region OA2 can be affected by the plurality of specific signal lines SL_OA.

[0199] On the other hand, in the common electrode CE, the positions where the plurality of common electrode holes CH are formed can respectively correspond to the plurality of first transmission regions TA1 included in the first optical region OA1. And in the common electrode CE, the positions where the plurality of common electrode holes CH are formed can respectively correspond to the plurality of second transmission regions TA2 included in the second optical region OA2. Thereby, the transmittance of each of the first optical region OA1 and the second optical region OA2 can be improved.

[0200] In order to further increase the transmittance of the first optical region OA1, when the plurality of specific signal lines SL_OA pass through the first optical region OA1, the plurality of specific signal lines SL_OA can be arranged to bypass the plurality of common electrode holes CH corresponding to the plurality of first transmission regions TA1. Similarly, in order to further increase the transmittance of the second optical region OA2, when the plurality of specific signal lines SL_OA pass through the second optical region OA2, the plurality of specific signal lines SL_OA can be arranged to bypass the plurality of common electrode holes CH corresponding to the plurality of second transmission regions TA2.

[0201] In this case, a plurality of specific signal lines SL_OA passing through at least one of the first optical region OA1 and the second optical region OA2 can have a wiring length longer than that of a plurality of general signal lines SL_NA not passing through the first optical region OA1 and the second optical region OA2.

[0202] Thereby, the plurality of specific signal lines SL_OA and the plurality of general signal lines SL_NA can have different electrical characteristics (e.g., different wiring resistances, different signal transmission delays, etc.). As a result, a change in the driving characteristics between the sub-pixels SP connected to the plurality of specific signal lines SL_OA and the sub-pixels SP connected to the plurality of general signal lines SL_NA may cause a deterioration in image quality.

[0203] On the other hand, during the manufacture of the display panel 110, a process for patterning the common electrode CE having a plurality of common electrode holes CH can proceed. At this time, if variations occur in the patterning process of the common electrode CE, variations in the transmittance of the plurality of common electrode holes CH of the common electrode CE may occur, and a transmittance deviation between the plurality of common electrode holes CH may also occur.

[0204] Therefore, the display panel 110 according to the embodiment of the present disclosure can have a structure for reducing wiring characteristic deviations.

[0205] According to the wiring characteristic deviation reduction structure according to the embodiment of the present disclosure, electrical characteristic deviations (e.g., wiring resistance deviation, signal transmission delay deviation, etc.) between a plurality of specific signal lines SL_OA passing through at least one of the first optical region OA1 and the second optical region OA2 and a plurality of general signal lines SL_NA not passing through the first optical region OA1 and the second optical region OA2 can be reduced.

[0206] In addition, the display panel 110 according to the embodiment of the present disclosure can have a structure for reducing the transmittance variation range.

[0207] According to the structure for reducing the transmittance variation range according to an embodiment of the present disclosure, even when process variations occur, the transmittance variation range between a plurality of common electrode holes CH can be reduced. Here, the plurality of common electrode holes CH can respectively correspond to a plurality of first transmission regions TA1 in the first optical region OA1 or a plurality of second transmission regions TA2 in the second optical region OA2.

[0208] Hereinafter, for convenience of explanation, the first optical region OA1 and the second optical region OA2 are described as the optical region OA, and the first transmission region TA1 in the first optical region OA1 and the second transmission region TA2 in the second optical region OA2 are described as the transmission region TA.

[0209] Hereinafter, an improvement structure of the transmittance characteristics of the optical region OA of the display panel 110 according to an embodiment of the present disclosure will be described with reference to various exemplary drawings.

[0210] FIGS. 6 and 7 are plan views of the optical region OA of the display panel 110 according to an embodiment of the present disclosure.

[0211] The display panel 110 according to an embodiment of the present disclosure can include a substrate SUB including a display region DA where an image is displayed, a plurality of signal lines SL disposed on the substrate SUB, and a common electrode CE disposed on the substrate SUB.

[0212] The display region DA can include an optical region OA through which light passes and a general region NA located on the outer periphery of the optical region OA. The general region NA can include a plurality of light emitting regions EA.

[0213] The optical region OA can include a plurality of transmission regions TA and a non-transmission region NTA excluding the plurality of transmission regions TA.

[0214] The non-transmission region NTA included in the optical region OA can include a plurality of light emitting regions EA formed by a plurality of light emitting elements ED. Also, a plurality of sub-pixel circuits SPC can be disposed in the non-transmission region NTA included in the optical region OA.

[0215] The common electrode CE can include a plurality of common electrode holes CH. The positions where the plurality of common electrode holes CH are formed may be in the optical region OA. That is, the plurality of common electrode holes CH may exist within the optical region OA.

[0216] The plurality of common electrode holes CH can be positioned so as to respectively correspond to the plurality of transmission regions TA.

[0217] As described above, the plurality of signal lines SL can include a plurality of general signal lines SL that do not pass through the optical region OA and a plurality of specific signal lines SL_OA that pass through the optical region OA.

[0218] For example, the plurality of specific signal lines SL_OA that pass through the optical region OA can include a plurality of data lines DL. The plurality of specific signal lines SL_OA that pass through the optical region OA can include a plurality of gate lines GL.

[0219] Referring to FIG. 6, the plurality of data lines DL that pass through the optical region OA can be arranged while bypassing the plurality of transmission regions TA.

[0220] Thereby, the transmittance of the optical region OA can be improved.

[0221] Referring to FIG. 7, the plurality of data lines DL that pass through the optical region OA can be arranged without bypassing the plurality of transmission regions TA and across at least one of the plurality of transmission regions TA.

[0222] Thereby, by reducing the length deviation between the plurality of data lines DL that pass through the optical region OA and the plurality of data lines DL that do not pass through the optical region OA, the signal transmission characteristic deviation (wiring characteristic deviation) can be reduced.

[0223] Referring to FIG. 7, each of the plurality of common electrode holes CH can overlap with a plurality of data lines DL passing through the optical region OA.

[0224] Each of the plurality of common electrode holes CH illustrated in FIGS. 6 and 7 can be triangular. This is an example, and the common electrode holes CH can have various shapes.

[0225] FIGS. 8 and 9 are cross-sectional views of a partial region within the optical region of a display panel according to an embodiment of the present disclosure. FIG. 8 is a cross-sectional view taken along line A-B of FIG. 6, and FIG. 9 is a cross-sectional view taken along line C-D of FIG. 7.

[0226] Referring to FIGS. 8 and 9, a display panel 110 according to an embodiment of the present disclosure can include a substrate SUB including a display region DA where an image is displayed, a plurality of signal lines SL disposed on the substrate SUB, and a common electrode CE disposed on the substrate SUB.

[0227] Referring to FIGS. 8 and 9, the optical region OA can include a plurality of light-emitting regions EA and a plurality of transmissive regions TA.

[0228] Referring to FIGS. 8 and 9, the common electrode CE can include a plurality of common electrode holes CH. The plurality of common electrode holes CH can be positioned to respectively correspond to the plurality of transmissive regions TA.

[0229] Referring to FIGS. 8 and 9, a display panel 110 according to an embodiment of the present disclosure further can include a pixel electrode PE disposed in one of the plurality of light-emitting regions EA included in the optical region OA, a driving transistor DT disposed in the optical region OA for supplying a driving current to the pixel electrode PE, a capacitor Cst disposed in the optical region OA, a bank 833 disposed on the pixel electrode (PE) and having an opening, and an intermediate layer EL disposed between the bank 833 and the common electrode CE and positioned on a part of the pixel electrode PE through the opening of the bank 833.

[0230] The region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE are superimposed can form one light-emitting element ED and can correspond to one light-emitting region EA.

[0231] The driving transistor DT and the capacitor Cst may be arranged in a non-transmissive region NTA other than the plurality of transmissive regions TA in the optical region OA.

[0232] Referring to FIGS. 8 and 9, the display panel 110 according to an embodiment of the present disclosure may further include a scan transistor ST arranged in a region other than the plurality of transmissive regions TA in the optical region OA.

[0233] Referring to FIGS. 8 and 9, the scan transistor ST can be connected to a data line DL which is one of the plurality of specific signal lines SL_OA.

[0234] Referring to FIGS. 8 and 9, the data line DL, which is one of the plurality of specific signal lines SL_OA connected to the scan transistor ST, can be arranged in a metal layer located between the source electrode and the drain electrode of the driving transistor DT and the pixel electrode PE.

[0235] Referring to FIGS. 8 and 9, the display panel 110 according to an embodiment of the present disclosure may further include a sealing layer ENCAP arranged on the common electrode CE, and a touch sensor metal TSM arranged on the sealing layer ENCAP and arranged in the general region NA and the optical region OA.

[0236] Referring to FIGS. 8 and 9, the touch sensor metal TSM can overlap with the bank 833. The touch sensor metal TSM arranged in the optical region OA among the touch sensor metals TSM can be located in a non-transmissive region NTA excluding the plurality of light-emitting regions EA and the plurality of transmissive regions TA in the optical region OA.

[0237] Hereinafter, with reference to FIGS. 8 and 9, the vertical structure of the display panel 110 will be described in more detail.

[0238] Referring to FIGS. 8 and 9, the display panel 110 according to an embodiment of the present disclosure may include a transistor forming portion, a light emitting element forming portion, and a sealing portion when viewed from the vertical structure, and may further include a touch sensor portion.

[0239] Referring to FIGS. 8 and 9, the display panel 110 according to an embodiment of the present disclosure may include a substrate SUB, a first buffer layer 811 on the substrate SUB, a first gate insulating layer 812 on the first buffer layer 811, a first interlayer insulating layer 813 on the first gate insulating layer 812, a second buffer layer 821 on the first interlayer insulating layer 813, a second gate insulating layer 822 on the second buffer layer 821, a second interlayer insulating layer 823 on the second gate insulating layer 822, a first planarization layer 831 on the second interlayer insulating layer 823, and a second planarization layer 832 on the first planarization layer 831.

[0240] The display panel 110 according to an embodiment of the present disclosure may further include a first gate metal layer located between the first gate insulating layer 812 and the first interlayer insulating layer 813, a first source-drain metal layer located between the second interlayer insulating layer 823 and the first planarization layer 831, and a second source-drain metal layer located between the first planarization layer 831 and the second planarization layer 832.

[0241] The display panel 110 according to an embodiment of the present disclosure may further include a second gate metal layer between the first interlayer insulating layer 813 and the second buffer layer 821, and a third gate metal layer between the second gate insulating layer 822 and the second interlayer insulating layer 823.

[0242] The display panel 110 according to an embodiment of the present disclosure may further include a first active layer ACT1 between the first buffer layer 811 and the first gate insulating layer 812, and a second active layer ACT2 between the second buffer layer 821 and the second gate insulating layer 822.

[0243] Referring to FIGS. 8 and 9, the transistor forming portion may include a substrate SUB, a first buffer layer 811 on the substrate SUB, and various transistors DT, ST, a storage capacitor Cst, and various electrodes or signal wirings formed on the first buffer layer BUF.

[0244] Referring to FIGS. 8 and 9, the substrate SUB may include a first substrate SUB1 and a second substrate SUB2, and may include a substrate intermediate layer IPD between the first substrate SUB1 and the second substrate SUB2. For example, each of the first substrate SUB1 and the second substrate SUB2 may include polyimide (PI). For example, the substrate intermediate layer IPD may be an inorganic layer and can block moisture penetration.

[0245] Referring to FIGS. 8 and 9, the first buffer layer 811 may be a single layer or a multilayer. When the first buffer layer 811 is a multilayer, the first buffer layer 811 may include a multi-buffer layer 811a and an active buffer layer 811b.

[0246] Various transistors DT, ST, a storage capacitor Cst, and various electrodes or signal wirings can be formed on the first buffer layer 811.

[0247] For example, the transistors DT, ST formed on the first buffer layer 811 may be composed of the same material and can be located in the same layer with each other. In contrast, as shown in FIGS. 8 and 9, the driving transistor DT and the scan transistor ST may be composed of different materials and arranged in different layers.

[0248] Referring to FIGS. 8 and 9, the driving transistor DT, the scan transistor ST, and the storage capacitor Cst may be included in a sub-pixel circuit portion SPC for driving a light-emitting element ED included in an optical region OA.

[0249] The scan transistor ST can include an active layer ACT1, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1.

[0250] The drive transistor DT can include an active layer ACT2, a gate electrode GE2, a source electrode SE2, and a second drain electrode DE2.

[0251] The active layer ACT2 of the drive transistor DT can be positioned higher than the active layer ACT1 of the scan transistor ST. Depending on the height of the active layer, the upper transistor and the lower transistor can be distinguished. The drive transistor DT is called the "upper transistor", and the scan transistor ST may also be called the "lower transistor".

[0252] The source electrode SE1 and the drain electrode DE1 of the scan transistor ST, which is the lower transistor, can be located in the "first source-drain metal layer". The gate electrode GE1 of the scan transistor ST, which is the lower transistor, can be located in the "first gate metal layer".

[0253] The source electrode SE2 and the drain electrode DE1 of the drive transistor DT, which is the upper transistor, can be located in the "first source-drain metal layer". The gate electrode GE2 of the drive transistor DT, which is the upper transistor, can be located in another "third gate metal layer" that is above the first gate metal layer and the second gate metal layer.

[0254] Under the active layer ACT1 of the scan transistor ST, a first buffer layer 811 may be disposed, and under the active layer ACT2 of the drive transistor DT, a second buffer layer 821 may be disposed. That is, the active layer ACT1 of the scan transistor ST can be located on the first buffer layer 811, and the active layer ACT2 of the drive transistor DT can be located on the second buffer layer 821. Here, the second buffer layer 821 can be located higher than the first buffer layer 811.

[0255] The active layer ACT1 of the scan transistor ST is disposed on the first buffer layer 811, and a first gate insulating layer 812 may be disposed on the active layer ACT1 of the scan transistor ST. The gate electrode GE1 of the scan transistor ST can be disposed on the first gate insulating layer 812, and a first interlayer insulating layer 813 can be disposed on the gate electrode GE1 of the scan transistor ST.

[0256] Here, the active layer ACT1 of the scan transistor ST can include a channel region overlapping with the gate electrode GE1, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0257] The second buffer layer 821 can be disposed on the first interlayer insulating layer 813.

[0258] The active layer ACT2 of the drive transistor DT can be disposed on the second buffer layer 821, and a second gate insulating layer 822 can be disposed on the active layer ACT2 of the drive transistor DT. The gate electrode GE2 of the drive transistor DT can be disposed on the second gate insulating layer 822, and a second interlayer insulating layer 823 can be disposed on the gate electrode GE2 of the drive transistor DT.

[0259] Here, the active layer ACT2 of the driving transistor DT can include a channel region overlapping with the gate electrode GE2, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0260] The source electrode SE2 and the drain electrode DE2 of the driving transistor DT can be disposed on the second interlayer insulating layer 823. Also, the source electrode SE1 and the drain electrode DE1 of the scan transistor ST may be disposed on the second interlayer insulating layer 823.

[0261] The source electrode SE1 and the drain electrode DE1 of the scan transistor ST can be connected to the source connection region and the drain connection region of the active layer ACT1 of the scan transistor ST respectively through the through holes of the second interlayer insulating layer 823, the second gate insulating layer 822, the second buffer layer 821, the first interlayer insulating layer 813, and the first gate insulating layer 812.

[0262] The source electrode SE2 and the drain electrode DE2 of the driving transistor DT can be connected to the source connection region and the drain connection region of the active layer ACT2 of the driving transistor DT respectively through the through holes of the second interlayer insulating layer 823 and the second gate insulating layer 822.

[0263] The storage capacitor Cst can include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0264] The first capacitor electrode PLT1 of the storage capacitor Cst is electrically connected directly or indirectly to the gate electrode GE2 of the driving transistor DT, and the second capacitor electrode PLT2 of the storage capacitor Cst can be electrically connected directly or indirectly to the source electrode SE2 of the driving transistor DT.

[0265] The first capacitor electrode PLT1 of the storage capacitor Cst can be located within the first gate metal layer composed of the first gate metal. The second capacitor electrode PLT2 of the storage capacitor Cst can be located within the second gate metal layer composed of the second gate metal.

[0266] On the other hand, the lower metal BML can be disposed under the active layer ACT2 of the drive transistor DT. The lower metal BML can overlap all or part of the active layer ACT2 of the drive transistor DT. The lower metal BML can include the second gate metal of the second gate metal layer.

[0267] For example, the lower metal BML can be electrically connected to the gate electrode GE2 of the drive transistor DT. As another example, the lower metal BML can also serve as a light shield that blocks light incident from below. In this case, the lower metal BML may be electrically connected to the source electrode SE2 of the drive transistor DT.

[0268] Referring to FIGS. 8 and 9, a first planarization layer 831 can be disposed on the drive transistor DT and the scan transistor ST. That is, the first planarization layer 831 can be disposed on the source electrode SE2 and the drain electrode DE2 of the drive transistor DT and on the source electrode SE1 and the drain electrode DE1 of the scan transistor ST.

[0269] Referring to FIGS. 8 and 9, a second source-drain metal layer can exist between the first planarization layer 831 and the second planarization layer 832.

[0270] The source electrode SE2 of the drive transistor DT and the pixel electrode PE of the light-emitting element ED can be electrically connected via a relay pattern formed in the second source-drain metal layer.

[0271] Referring to FIGS. 8 and 9, the data line DL passing through the transmission region TA can be formed in the second source-drain metal layer. That is, the data line DL passing through the transmission region TA can include the second source-drain metal.

[0272] Referring to FIGS. 8 and 9, the active layer ACT2 of the driving transistor DT which is the upper transistor and the active layer ACT1 of the scan transistor ST which is the lower transistor can include different semiconductor materials.

[0273] For example, the active layer ACT2 of the driving transistor DT which is the upper transistor can include an oxide semiconductor material. For example, the oxide semiconductor material can include IGZO (Indium gallium zinc oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), etc.

[0274] For example, the active layer ACT1 of the scan transistor ST which is the lower transistor can include a semiconductor material different from the active layer ACT2 of the driving transistor DT which is the upper transistor.

[0275] For example, the active layer ACT1 of the scan transistor ST which is the lower transistor can include a silicon-based semiconductor material. For example, the silicon-based semiconductor material can include low-temperature polycrystalline silicon (LTPS), etc.

[0276] Referring to FIGS. 8 and 9, the light emitting element forming part can be positioned on the second planarization layer PNL2.

[0277] The light-emitting element forming portion can include a light-emitting element ED formed on the second planarization layer PNL2. The light-emitting element ED can be disposed in the optical region OA.

[0278] Referring to FIGS. 8 and 9, the light-emitting element ED can be configured by the superposition of a pixel electrode PE, an intermediate layer EL, and a common electrode CE. That is, the light-emitting element ED may be a portion where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap.

[0279] The pixel electrode PE can be disposed on the second planarization layer 832.

[0280] A bank 833 can be disposed on the pixel electrode PE.

[0281] The bank 833 can include a plurality of bank holes, and a part of the pixel electrode PE can be exposed through the plurality of bank holes. That is, the plurality of bank holes formed in the bank 833 can overlap a part of the pixel electrode PE.

[0282] The intermediate layer EL can be disposed on the bank 833. The intermediate layer EL can contact a part of the pixel electrode PE through the bank hole.

[0283] At least one spacer may exist between the intermediate layer EL and the bank 833. The spacer can include the same material as the bank 833.

[0284] The common electrode CE can be disposed on the intermediate layer EL. The common electrode CE can include a plurality of common electrode holes CH. The plurality of common electrode holes CH formed in the common electrode CE can be disposed in the optical region OA.

[0285] The common electrode hole CH can correspond in position to the transmission region TA.

[0286] Referring to FIG. 8, the data line DL can be arranged to avoid the transmission region TA. Therefore, the data line DL does not exist in the transmission region TA.

[0287] Referring to FIG. 9, the data line DL can be arranged while passing through the transmission region TA. Therefore, the data line DL exists in the transmission region TA. For example, the data line DL may be a transparent wiring including a transparent material.

[0288] Referring to FIGS. 8 and 9, the sealing portion can be arranged on the cathode electrode CE. The sealing portion can include a sealing layer ENCAP formed on the common electrode CE.

[0289] The sealing layer ENCAP may be a layer that prevents moisture and oxygen from penetrating into the light-emitting element ED disposed under the sealing layer ENCAP. In particular, the sealing layer ENCAP can prevent moisture or oxygen from penetrating into the intermediate layer EL that can include an organic layer. Here, the sealing layer ENCAP may be composed of a single layer or multiple layers.

[0290] The sealing layer ENCAP can include a first sealing layer 841, a second sealing layer 842, and a third sealing layer 843.

[0291] For example, the sealing layer ENCAP can include alternating inorganic and organic layers. In this case, for example, the first sealing layer 841 and the third sealing layer 843 may be inorganic layers, and the second sealing layer 842 may be an organic layer. When the second sealing layer 842 is composed of an organic layer, the second sealing layer 842 can serve as a planarization layer.

[0292] On the other hand, the display panel 110 according to the embodiment of the present disclosure may embed a touch sensor. In this case, the display panel 110 according to the embodiment of the present disclosure can include a touch sensor layer TSL on the sealing layer ENCAP.

[0293] The touch sensor layer TSL can include a touch sensor metal TSM and a bridge metal BRG, and can further include an insulating layer structure such as a sensor buffer layer 851, a sensor interlayer insulating layer 852, and a sensor protection layer 853.

[0294] The sensor buffer layer 851 can be disposed on the encapsulation layer ENCAP.

[0295] The bridge metal BRG can be disposed on the sensor buffer layer 851, and the sensor interlayer insulating layer 852 can be disposed on the bridge metal BRG.

[0296] The touch sensor metal TSM can be disposed on the sensor interlayer insulating layer 852. A part of the touch sensor metal TSM can be connected to the corresponding bridge metal BRG through the holes of the sensor interlayer insulating layer 852.

[0297] The touch sensor metal TSM and the bridge metal BRG are disposed in the general area NA and can be disposed in the non-transmissive area NTA within the optical area OA.

[0298] When the display panel 110 has an upper light-emitting structure, when the touch sensor metal TSM and the bridge metal BRG are disposed in the non-transmissive area NTA within the optical area OA, the touch sensor metal TSM and the bridge metal BRG can be disposed so as not to overlap the light-emitting area EA of the non-transmissive area NTA.

[0299] A plurality of touch sensor metals TSM can form one touch electrode (or one touch electrode line), are arranged in a mesh shape, and can be electrically connected. A part of the touch sensor metal TSM and another part of the touch sensor metal TSM can be electrically connected through the bridge metal BRG to form one touch electrode (or one touch electrode line).

[0300] The sensor protection layer 853 can be disposed while covering the touch sensor metal TSM and the bridge metal BRG.

[0301] On the other hand, when the display panel 110 is of a type incorporating a touch sensor, at least a part of the touch sensor metal TSM located on the encapsulation layer ENCAP in the display area DA extends and can be arranged along the outer inclined surface of the encapsulation layer ENCAP and electrically connected to pads located outside the outer inclined surface of the encapsulation layer ENCAP. Here, the pads may be arranged in the non-display area NDA or may be metal patterns to which the touch drive circuit 260 is electrically connected.

[0302] Referring to FIGS. 8 and 9, the display device 100 according to an embodiment of the present disclosure can include an electronic device 800 located under the substrate SUB and overlapping the optical area OA. The electronic device 800 can be one of the first electronic device 11 and the second electronic device 12 (see FIGS. 1a, 1b, and 1c).

[0303] The electronic device 800 can perform a defined operation in response to the first light in the first wavelength band among the light received through the optical area OA. For example, the first wavelength band can correspond to the wavelength band of visible light or the wavelength band of infrared light.

[0304] FIG. 10 shows the signal intensity during reception processing of the light passing through the optical area OA of the display panel 110 according to an embodiment of the present disclosure.

[0305] Referring to FIG. 10, the light incident on the upper surface of the display panel 110 passes through (transmits through) the optical area OA of the display panel 110 and is received by the electronic device 800 located below the display panel 110 and overlapping the optical area OA.

[0306] The electronic device 800 can execute a predetermined operation using the received light.

[0307] Depending on the amount of light received by the electronic device 800, the performance and quality of the operation executed by the electronic device 800 can vary.

[0308] As an example, in the case where the electronic device 800 is an infrared sensor that senses a nearby object, the performance and quality of the sensing operation performed using infrared rays may change according to the amount of infrared rays transmitted through the optical region OA of the display panel 110.

[0309] The amount of infrared rays transmitted through the optical region OA of the display panel 110 can correspond to the value (Intensity) of the point spread function (PSF: Point Spread Function). Here, the value (Intensity) of the point spread function can correspond to the signal intensity of infrared rays during the reception process of the electronic device 800. The value of the point spread function can be an indicator of the sensing performance of the infrared sensor.

[0310] When the metal ratio in the optical region OA increases, that is, when the transmittance of the optical region OA decreases, the value of the point spread function, which is an indicator of the sensing performance of the infrared sensor, may decrease.

[0311] When the metal ratio in the optical region OA decreases, that is, when the transmittance of the optical region OA increases, the value of the point spread function, which is an indicator of the sensing performance of the infrared sensor, may increase.

[0312] As another example, when the electronic device 800 is an image sensor (camera), the performance and quality of the camera operation performed using visible light may change according to the amount of visible light transmitted through the optical region OA of the display panel 110.

[0313] The amount of visible light transmitted through the optical region OA of the display panel 110 can correspond to the value (Intensity) of the modulation transfer function (MTF: Modulation Transfer Function). Here, the value of the modulation transfer function can correspond to the signal intensity (Intensity) of visible light during the reception process of the electronic device 800. Here, the value of the modulation transfer function is an indicator of camera performance and can represent the sharpness level.

[0314] When the metal ratio in the optical region OA increases, that is, when the transmittance of the optical region OA decreases, the value of the modulation transfer function, which is an index of camera performance, may decrease.

[0315] When the metal ratio in the optical region OA decreases, that is, when the transmittance of the optical region OA increases, the value of the modulation transfer function, which is an index of camera performance, may increase.

[0316] Hereinafter, a structure for improving the transmittance of the optical region OA of the display panel 110 according to an embodiment of the present disclosure will be described. The structure for improving the transmittance of the optical region OA can include a structure capable of reducing the metal ratio in the optical region OA.

[0317] Hereinafter, for convenience of explanation, the optical region OA will be described as the first region OA, and the general region NA will be described as the second region NA.

[0318] FIG. 11 is a plan view of a display panel 110 according to an embodiment of the present disclosure.

[0319] Referring to FIG. 11, a display panel 110 according to an embodiment of the present disclosure includes a substrate SUB including a display region DA capable of displaying an image and a non-display region NDA outside the display region DA, a plurality of sub-pixels SP each including a plurality of light-emitting elements ED included in the display region DA, and a plurality of data lines DL for supplying data signals for image display to the plurality of sub-pixels SP.

[0320] Referring to FIG. 11, the display region DA can include a first region OA capable of transmitting light and a second region NA located outside the first region OA. The second region NA can include an upper region NA1 located above the first region OA and a lower region NA2 located below the first region OA.

[0321] In FIG. 11, as an example, the first region OA is shown by a dotted circle, and it may be the second region NA which is the region outside the dotted circle. The upper region NA1 of the second region NA may be the region located above the first region OA among the outer regions of the first region OA. The lower region NA2 of the second region NA may be the region located below the first region OA among the outer regions of the first region OA.

[0322] Referring to FIG. 11, the plurality of sub-pixels SP arranged in the display area DA can include the first to twelfth sub-pixels (SP1 to SP12).

[0323] Referring to FIG. 11, the plurality of sub-pixels SP arranged in the upper region NA1 of the second region NA can include the first sub-pixel SP1, the second sub-pixel SP2, the seventh sub-pixel SP7, and the tenth sub-pixel SP10.

[0324] Referring to FIG. 11, the plurality of sub-pixels SP arranged in the lower region NA2 of the second region NA can include the fifth sub-pixel SP5, the sixth sub-pixel SP6, the ninth sub-pixel SP9, and the twelfth sub-pixel SP12.

[0325] Referring to FIG. 11, the plurality of sub-pixels SP arranged in the first region OA can include the third sub-pixel SP3, the fourth sub-pixel SP4, the eighth sub-pixel SP8, and the eleventh sub-pixel SP11.

[0326] Referring to FIG. 11, for example, the plurality of sub-pixels SP arranged in the display area DA can include a red sub-pixel that emits red light, a green sub-pixel that emits green light, and a blue sub-pixel that emits blue light.

[0327] Referring to FIG. 11, a plurality of sub-pixels SP arranged in the display area DA can each include a plurality of pixel electrodes PE. For example, the plurality of pixel electrodes PE can include a red pixel electrode PE(R) included in the red sub-pixel, a green pixel electrode PE(G) included in the green sub-pixel, and a blue pixel electrode PE(B) included in the blue sub-pixel.

[0328] Referring to FIG. 11, a plurality of data lines DL arranged in the display area DA can include a red data line DL(R) that supplies a data signal to the red sub-pixel, a green data line DL(G), DL(G)_U, DL(G)_D that supply data signals to the green sub-pixel, and a blue data line DL(B) that supplies a data signal to the blue sub-pixel.

[0329] Referring to FIG. 11, a plurality of data lines DL arranged in the display area DA can be arranged in a second area NA that is a general area NA.

[0330] Referring to FIG. 11, a part DL(R), DL(G), DL(B) of the plurality of data lines DL arranged in the second area NA can pass through a first area OA that is an optical area OA.

[0331] However, among the plurality of data lines DL arranged in the second area NA, another part DL(G)_U, DL(G)_D can be arranged while bypassing the first area OA without passing through the first area OA that is the optical area OA.

[0332] For example, the upper data line DL(G)_U can be arranged in the upper region NA1 of the second region NA, and the lower data line DL(G)_D can be arranged in the lower region NA2 of the second region NA. The upper data line DL(G)_U and the lower data line DL(G)_D can be electrically connected via a detour wiring BW that detours around the first region OA. The upper data line DL(G)_U, the lower data line DL(G)_D, and the detour wiring BW are electrically connected to correspond to one data line, and such one data line can detour around the first region OA without passing through the first region OA.

[0333] For example, referring to FIG. 11, the plurality of data lines DL can include a first data line DL1 that passes through all of the upper region NA1, the first region OA, and the lower region NA2.

[0334] In the example of FIG. 11, the first data line DL1 may be a green data line DL(G) for supplying a data signal to the green sub-pixels arranged in each of the upper region NA1, the first region OA, and the lower region NA2. However, this is merely an example and is not limited thereto.

[0335] The plurality of data lines DL can further include an upper data line DL(G)_U arranged in the upper region NA1 of the second region NA, a lower data line DL(G)_D arranged in the lower region NA2 of the second region NA, and a detour wiring BW that electrically connects the upper data line DL(G)_U and the lower data line DL(G)_D and detours around the first region OA. Here, the upper data line DL(G)_U, the lower data line DL(G)_D, and the detour wiring BW are electrically connected to play the role of one data line.

[0336] In the example of FIG. 11, the upper data line DL(G)_U may be the green data line DL(G)_U for supplying a data signal to the green sub-pixels arranged in the upper region NA1, and the lower data line DL(G)_D may be the green data line DL(G)_D for supplying a data signal to the green sub-pixels arranged in the lower region NA2. However, this is merely an example and is not limited thereto.

[0337] Referring to FIG. 11, the detour wiring BW can include a first detour wiring BW1 connected to the upper data line DL(G)_U, a second detour wiring BW2 connected to the lower data line DL(G)_D, and a third detour wiring BW3 connecting the first detour wiring BW1 and the second detour wiring BW2.

[0338] Referring to FIG. 11, the detour wiring BW can include a horizontal detour wiring H_BW extending in the horizontal direction and a vertical detour wiring V_BW extending in the vertical direction. Referring to FIG. 11, the horizontal detour wiring H_BW, the upper data line DL(G)_U, and the lower data line DL(G)_D can form a mesh configuration.

[0339] Referring to FIG. 11, the intersection of the detour wiring BW and the upper data line DL(G)_U and the intersection of the detour wiring BW and the lower data line DL(G)_D can have connection points. For example, the first connection point can be formed at the intersection of the upper data line DL(G)_U and the first detour wiring BW1 which is the horizontal detour wiring H_BW, and the second connection point can be formed at the intersection of the lower data line DL(G)_D and the second detour wiring BW2 which is the horizontal detour wiring H_BW. The third connection point can be formed at the intersection of the first detour wiring BW1 which is the horizontal detour wiring H_BW and the third detour wiring BW3 which is the vertical detour wiring V_BW. The fourth connection point can be formed at the intersection of the second detour wiring BW2 which is the horizontal detour wiring H_BW and the third detour wiring BW3 which is the vertical detour wiring V_BW.

[0340] Referring to FIG. 11, the horizontal bypass wiring H_BW can include a first bypass wiring BW1 and a second bypass wiring BW2, and the vertical bypass wiring V_BW can include a third bypass wiring BW3.

[0341] The horizontal bypass wiring H_BW and the vertical bypass wiring V_BW intersect and can overlap in the vertical direction.

[0342] Therefore, the horizontal bypass wiring H_BW and the vertical bypass wiring V_BW can be arranged in different metal layers. For example, the horizontal bypass wiring H_BW may be arranged in the first metal layer, and the vertical bypass wiring V_BW may be arranged in a second metal layer different from the first metal layer. For example, the first metal layer can be the first source-drain metal layer, and the second metal layer can be the second source-drain metal layer.

[0343] Referring to FIG. 11, a plurality of pixel electrodes PE included in a plurality of light-emitting elements ED are arranged in the upper region NA1, a first pixel electrode PE1 included in the first sub-pixel SP1 and arranged in the upper region NA1, a second pixel electrode PE2 included in the second sub-pixel SP2 and arranged in the upper region NA1, a third pixel electrode PE3 included in the third sub-pixel SP3 and arranged in the first region OA, a fourth pixel electrode PE4 included in the fourth sub-pixel SP4 and arranged in the first region OA, a fifth pixel electrode PE5 included in the fifth sub-pixel SP5 and arranged in the lower region NA2, and a sixth pixel electrode PE6 included in the sixth sub-pixel SP6 and arranged in the lower region NA2 can be included.

[0344] Referring to FIG. 11, the first data line DL1 can be connected to the first sub-pixel SP1 in the upper region NA1, the third sub-pixel SP3 in the first region OA, and the fifth sub-pixel SP5 in the lower region NA2.

[0345] The first data line DL1 can supply a data signal to the first sub-pixel SP1 in the upper region NA1, the third sub-pixel SP3 in the first region OA, and the fifth sub-pixel SP5 in the lower region NA2.

[0346] Referring to FIG. 11, the upper data line DL(G)_U can be connected to the second sub-pixel SP2 disposed in the upper region NA1, and the lower data line DL(G)_D can be connected to the sixth sub-pixel SP6 disposed in the lower region NA2.

[0347] Referring to FIG. 11, the display panel 110 according to an embodiment of the present disclosure can further include a connection wiring CW that electrically connects the third pixel electrode PE3 and the fourth pixel electrode PE4.

[0348] The connection wiring CW can be disposed in the first region OA which is the optical region OA.

[0349] Referring to FIG. 11, the emission colors of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fourth sub-pixel SP4, the fifth sub-pixel SP5, and the sixth sub-pixel SP6 can be the same.

[0350] In the example of FIG. 11, the emission colors of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fourth sub-pixel SP4, the fifth sub-pixel SP5, and the sixth sub-pixel SP6 can be green light, but this is merely an example and is not limited thereto.

[0351] Referring to FIG. 11, a part of the plurality of sub-pixels SP3, SP4 disposed in the first region OA (for example, the third sub-pixel SP3) can include a light-emitting element ED and a sub-pixel circuit SPC.

[0352] The sub-pixel circuit SPC included in a part of the plurality of sub-pixels SP3, SP4 disposed in the first region OA (for example, the third sub-pixel SP3) can include a driving transistor DT, a scan transistor ST, a storage capacitor Cst, etc. (see FIG. 3).

[0353] Referring to FIG. 11, the sub-pixel circuit SPC included in a part of a plurality of sub-pixels SP3, SP4 arranged in the first region OA (for example, the third sub-pixel SP3) can include a red sub-pixel circuit SPC(R) included in a red sub-pixel, a green sub-pixel circuit SPC(G) included in a green sub-pixel, and a blue sub-pixel circuit SPC(B) included in a blue sub-pixel.

[0354] Referring to FIG. 11, another part of the plurality of sub-pixels SP arranged in the first region OA (for example, the fourth sub-pixel SP4) includes a light-emitting element ED but does not include a sub-pixel circuit SPC.

[0355] Referring to the example of FIG. 11, the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fifth sub-pixel SP5, and the sixth sub-pixel SP6 can each include a light-emitting element ED and a sub-pixel circuit SPC(G) that drives the light-emitting element ED. Here, the sub-pixel circuit SPC(G) can include two or more transistors DT, ST.

[0356] Referring to the example of FIG. 11, the fourth sub-pixel SP4 includes a light-emitting element ED but may not include a sub-pixel circuit SPC(G). The light-emitting element ED of the fourth sub-pixel SP4 can be driven by the sub-pixel circuit SPC(G) of the third sub-pixel SP3.

[0357] Thereby, the drive current output from the sub-pixel circuit SPC(G) of the third sub-pixel SP3 is supplied to the third pixel electrode PE3 and can also be supplied to the fourth pixel electrode PE4 via the connection wiring CW.

[0358] Referring to FIG. 11, a plurality of pixel electrodes PE are arranged in the upper region NA1, including the seventh pixel electrode PE7 included in the seventh sub-pixel SP7, arranged in the first region OA, the eighth pixel electrode PE8 included in the eighth sub-pixel SP8, and arranged in the lower region NA2, and may further include the ninth pixel electrode PE9 included in the ninth sub-pixel SP9.

[0359] The plurality of data lines DL may further include a second data line DL2 connected to the seventh sub-pixel SP7 in the upper region NA1, the eighth sub-pixel SP8 in the first region OA, and the ninth sub-pixel SP9 in the lower region NA2.

[0360] In the example of FIG. 11, the second data line DL2 may be a blue data line DL(B) for supplying a data signal to the blue sub-pixels arranged in each of the upper region NA1, the first region OA, and the lower region NA2. However, this is merely an example and is not limited thereto.

[0361] The emission colors of each of the seventh sub-pixel SP7 in the upper region NA1, the eighth sub-pixel SP8 in the first region OA, and the ninth sub-pixel SP9 in the lower region NA2 may be different from the emission colors of each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fourth sub-pixel SP4, the fifth sub-pixel SP5, and the sixth sub-pixel SP6.

[0362] For example, the emission colors of each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fourth sub-pixel SP4, the fifth sub-pixel SP5, and the sixth sub-pixel SP6 are green light, and the emission colors of each of the seventh sub-pixel SP7 in the upper region NA1, the eighth sub-pixel SP8 in the first region OA, and the ninth sub-pixel SP9 in the lower region NA2 may be blue light. However, this is merely an example and is not limited thereto.

[0363] Referring to FIG. 11, the second data line DL2 can intersect and overlap with the connection wiring CW. The first data line DL1 can also intersect and overlap with the connection wiring CW.

[0364] Referring to FIG. 11, a plurality of pixel electrodes PE can be arranged in the upper region NA1, including the tenth pixel electrode PE10 included in the tenth sub-pixel SP10, arranged in the first region OA, the eleventh pixel electrode PE11 included in the eleventh sub-pixel SP11, and arranged in the lower region NA2, and can further include the twelfth pixel electrode PE12 included in the twelfth sub-pixel SP12.

[0365] Referring to FIG. 11, a plurality of data lines DL can further include a third data line DL3 connected to the tenth sub-pixel SP10 in the upper region NA1, the eleventh sub-pixel SP11 in the first region OA, and the twelfth sub-pixel SP12 in the lower region NA2.

[0366] In the example of FIG. 11, the third data line DL3 may be a red data line DL(R) for supplying a data signal to the red sub-pixels arranged in each of the upper region NA1, the first region OA, and the lower region NA2. However, this is merely an example and is not limited thereto.

[0367] Referring to FIG. 11, the emission colors of the tenth sub-pixel SP10, the eleventh sub-pixel SP11, and the twelfth sub-pixel SP12 may be different from the emission colors of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fourth sub-pixel SP4, the fifth sub-pixel SP5, and the sixth sub-pixel SP6.

[0368] For example, the emission colors of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fourth sub-pixel SP4, the fifth sub-pixel SP5, and the sixth sub-pixel SP6 can be green light, and the emission colors of the tenth sub-pixel SP10, the eleventh sub-pixel SP11, and the twelfth sub-pixel SP12 can be red light. However, the present invention is not limited thereto.

[0369] Referring to FIG. 11, a display panel 110 according to an embodiment of the present disclosure may further include a common electrode CE disposed on a plurality of pixel electrodes PE.

[0370] Referring to FIG. 11, within the first region OA, the common electrode CE may have a plurality of common electrode holes CH. For example, within the first region OA, the common electrode CE may have a common electrode hole CH between the first data line DL1 and the third data line DL3.

[0371] A display panel 110 according to an embodiment of the present disclosure may include a substrate SUB including a display area DA capable of displaying an image and a non-display area NDA outside the outline of the display area DA, a plurality of sub-pixels SP each including a plurality of light-emitting elements ED included in the display area DA, and a plurality of data lines DL for supplying data signals for image display to the plurality of sub-pixels SP.

[0372] The display area DA may include a first area OA that is an optical area capable of transmitting light and a second area NA that is a general area located outside the first area OA.

[0373] The second area NA may include an upper area NA1 located above the first area OA and a lower area NA2 located below the first area OA.

[0374] The plurality of light-emitting elements ED may each include a plurality of pixel electrodes PE.

[0375] A plurality of pixel electrodes PE are arranged in the first region OA and can include two pixel electrodes PE3 and PE4 that are electrically connected to each other.

[0376] The display panel 110 according to an embodiment of the present disclosure can further include a connection wiring CW that is arranged in the first region OA and electrically connects two pixel electrodes PE3 and PE4.

[0377] The plurality of data lines DL can include a first data line DL1 connected to one of two sub-pixels including two pixel electrodes PE3 and PE4 (for example, the sub-pixel including PE3). The remaining one of the two sub-pixels including two pixel electrodes PE3 and PE4 (for example, the sub-pixel including PE4) is not connected to a data line.

[0378] FIGS. 12 and 13 are plan views of a partial region within a first region OA1 that is an optical region OA of the display panel 110 according to an embodiment of the present disclosure.

[0379] Referring to FIGS. 12 and 13, the first region OA1 that is the optical region OA of the display panel 110 can include a transmissive region TA and a non-transmissive region NTA.

[0380] Referring to FIGS. 12 and 13, the non-transmissive region NTA can include a circuit region CA in which a plurality of sub-pixel circuits respectively included in a plurality of sub-pixels are arranged. For example, the plurality of sub-pixel circuits can include a red sub-pixel circuit included in a red sub-pixel, a green sub-pixel circuit included in a green sub-pixel, and a blue sub-pixel circuit included in a blue sub-pixel.

[0381] Referring to FIGS. 12 and 13, the non-transmissive region NTA can include a plurality of light-emitting regions respectively corresponding to a plurality of sub-pixels. Thereby, a plurality of pixel electrodes PE(R), PE(G), PE(B) can be arranged in the non-transmissive region NTA.

[0382] Referring to FIGS. 12 and 13, a plurality of pixel electrodes PE(R), PE(G), PE(B) can be disposed in a non-transmissive region NTA with a plurality of contact holes CNT(R), CNT(G), CNT(B) respectively connected to a plurality of sub-pixel circuits.

[0383] For example, the plurality of pixel electrodes PE(R), PE(G), PE(B) can include a red pixel electrode PE(R) included in a red sub-pixel, a green pixel electrode PE(G) included in a green sub-pixel, and a blue pixel electrode PE(B) included in a blue sub-pixel. For reference, the arrangements of the red pixel electrode PE(R), the green pixel electrode PE(G), and the blue pixel electrode PE(B) in FIGS. 12 and 13 are different from the arrangements of the red pixel electrode PE(R), the green pixel electrode PE(G), and the blue pixel electrode PE(B) in FIG. 11.

[0384] For example, the plurality of contact holes CNT(R), CNT(G), CNT(B) can include a contact hole CNT(R) between the red pixel electrode PE(R) and the red sub-pixel circuit, a contact hole CNT(G) between the green pixel electrode PE(G) and the green sub-pixel circuit, and a contact hole CNT(B) between the blue pixel electrode PE(B) and the blue sub-pixel circuit.

[0385] Referring to FIGS. 12 and 13, two green pixel electrodes PE(G) can be connected by a connection wiring CW. The two green pixel electrodes PE(G) connected by the connection wiring CW can correspond to the third pixel electrode PE3 and the fourth pixel electrode PE4 in FIG. 11.

[0386] Referring to FIGS. 12 and 13, the blue pixel electrode PE(B) can correspond to the eighth pixel electrode PE8 in FIG. 11.

[0387] Referring to FIG. 11, in the second region NA which is the general region NA, four data lines (red data line, green data line, blue data line, green data line) can be repeatedly arranged.

[0388] In the upper region NA1 of the second region NA which is the general region NA, a red data line DL(R), a green data line DL(G)_U which is the upper data line, a blue data line DL(B), and a green data line DL(G) can be arranged in order.

[0389] Referring to FIG. 11, in the lower region NA2 of the second region NA which is the general region NA, a red data line DL(R), a green data line DL(G)_D which is the lower data line, a blue data line DL(B), and a green data line DL(G) can be arranged in order.

[0390] Referring to FIGS. 12 and 13, in the first region OA which is the optical region OA, three data lines (red data line DL(R), blue data line DL(B), green data line DL(G)) can be repeatedly arranged.

[0391] Referring to FIGS. 12 and 13, in the first region OA, the green data line is omitted in the region 1200 between the red data line DL(R) and the blue data line DL(B). Therefore, the metal can be reduced in the first region OA which is the optical region OA. Thereby, the metal ratio in the first region OA which is the optical region OA can be lowered and the transmittance can be increased.

[0392] In FIGS. 12 and 13, the green data line DL(G) can correspond to the first data line DL1 in FIG. 11, in FIGS. 12 and 13, the blue data line DL(B) can correspond to the second data line DL2 in FIG. 11, and in FIGS. 12 and 13, the red data line DL(R) can correspond to the third data line DL3 in FIG. 11.

[0393] Referring to FIGS. 12 and 13, the red data line DL(R), which is the third data line DL3, can overlap with the red pixel electrode PE(R).

[0394] The region 1200 where the green data line is omitted is an area directly adjacent to the red data line DL(R), which is the third data line DL3, and can overlap with the red pixel electrode PE(R).

[0395] In the upper region NA1 of the second region NA, which is the general region NA, the red pixel electrode PE(R) overlaps with two data lines DL(R) and DL(G)_U. Also, in the lower region NA2 of the second region NA, which is the general region NA, the red pixel electrode PE(R) can overlap with two data lines DL(R) and DL(G)_D.

[0396] However, as described above, in the first region OA, which is the optical region OA, the red pixel electrode PE(R) only overlaps with one data line DL(R). As a result, the light emission characteristics of the red sub-pixels in the first region OA may be different from those of the red sub-pixels in the second region NA.

[0397] In order to reduce such variations in light emission characteristics, as shown in FIGS. 12 and 13, the red data line DL(R), which is the third data line DL3, can include a protrusion 1210. The protrusion 1210 can overlap with the red pixel electrode PE(R) within the first region OA.

[0398] That is, referring to FIGS. 12 and 13, the red data line DL(R), which is the third data line DL3, can overlap with the red sub-pixel PE(R), which is the 11th sub-pixel PE11 in FIG. 11. The red data line DL(R), which is the third data line DL3, can include a protrusion 1210 that protrudes into the region 1200 where the green data line is omitted.

[0399] The protrusion 1210 can overlap with the red sub-pixel PE(R), which is the 11th sub-pixel PE11 in FIG. 11, in the direction of the data line length (column direction, data line extension direction).

[0400] Referring to FIGS. 12 and 13, the third pixel electrode PE3, the connection wiring CW, and the fourth pixel electrode PE4 can be integrally formed. That is, the connection wiring CW can be formed of a pixel electrode material.

[0401] Referring to FIG. 12, in the first region OA, the first data line DL1 and the second data line DL2 may be arranged in the same metal layer (the second metal layer) and spaced apart on the same plane. Similarly, in the second region NA, the first data line DL1 and the second data line DL2 may be arranged in the same metal layer (the second metal layer) and spaced apart on the same plane.

[0402] Referring to FIG. 13, in at least a part of the first region OA, the first data line DL1 and the second data line DL2 can be arranged in different metal layers (the first metal layer, the second metal layer). In contrast, in the second region NA, the first data line DL1 and the second data line DL2 may be arranged in the same metal layer (the second metal layer).

[0403] In other words, in the second region NA, the first data line DL1 and the second data line DL2 may be arranged in the same metal layer and spaced apart from each other on the same plane. Among the transmission region TA and the non-transmission region NTA included in the first region OA, in the transmission region TA, the first data line DL1 and the second data line DL2 may be arranged in different metal layers (the first metal layer, the second metal layer) and may overlap in the vertical direction. Among the transmission region TA and the non-transmission region NTA included in the first region OA, in the non-transmission region NTA, the first data line DL1 and the second data line DL2 may be arranged in the same metal layer (the second metal layer) and spaced apart from each other on the same plane.

[0404] Referring to FIG. 13, for example, the first metal layer is a metal layer between the second interlayer insulating layer 823 and the first planarization layer 831, and can be the first source-drain metal layer. The second metal layer is a metal layer between the first planarization layer 831 and the second planarization layer 832, and can be the second source-drain metal layer. For example, the blue data line DL(B), which is the second data line DL2, may be disposed within the first metal layer, and the green data line DL(G), which is the first data line DL1, may be disposed within the second metal layer.

[0405] FIGS. 14 to 18 are cross-sectional views of a display panel 110 having a transmittance improvement structure according to an embodiment of the present disclosure. However, the stacked structure in the cross-sectional views of FIGS. 14 to 18 is the same as that in FIGS. 8 and 9. Therefore, the description of the stacked structure is omitted. In the following description, FIGS. 11 to 13 are also referred to.

[0406] FIG. 14 is a cross-sectional view taken along the X1-X2 line of FIGS. 12 and 13, FIG. 15 is a cross-sectional view taken along the X3-X4 line of FIGS. 12 and 13, FIG. 16 is a cross-sectional view taken along the X5-X6 line of FIG. 13, FIG. 17 is a cross-sectional view taken along the X7-X8 line of FIG. 13, and FIG. 18 is a cross-sectional view taken along the X9-X10 line of FIG. 13.

[0407] Referring to FIG. 14, in the region where the X1-X2 line of FIGS. 12 and 13 is shown, there are a blue light-emitting region EA_B of a blue sub-pixel and a red light-emitting region EA_R of a red sub-pixel. That is, a blue pixel electrode PE(B) and a red pixel electrode PE(R) can be disposed in the region where the X1-X2 line of FIGS. 12 and 13 is shown.

[0408] Referring to FIG. 14, in the region where the X1-X2 line of FIGS. 12 and 13 is displayed, transistors TFT included in the green sub-pixel circuit SPC(G), transistors TFT included in the blue sub-pixel circuit SPC(B), and transistors TFT included in the red sub-pixel circuit SPC(R) can be arranged.

[0409] These transistors TFT can include a first active layer ACT1 and a first gate electrode GE1 on the first active layer ACT1. The first active layer ACT1 can include a silicon-based semiconductor material as the active layer of the lower transistor. For example, the silicon-based semiconductor material can include low-temperature polycrystalline silicon (LTPS).

[0410] A shield metal SM overlapping the first active layer ACT1 can be arranged below the transistor TFT. The shield metal SM can be arranged between the multi-buffer layer 811a and the active buffer layer 811b.

[0411] A first upper metal TM1 overlapping the first gate electrode GE1 can be arranged above the transistor TFT. The first upper metal TM1 can be arranged between the first interlayer insulating layer 813 and the second buffer layer 821.

[0412] Referring to FIG. 14, the metal layer between the second interlayer insulating layer 823 and the first planarization layer 831 is called the first metal layer, and the metal layer between the first planarization layer 831 and the second planarization layer 832 is called the second metal layer. As shown in FIG. 14, the second metal layer can be a metal layer above the first metal layer.

[0413] Various horizontal wirings extending in the horizontal direction may be arranged in the first metal layer, and various vertical wirings extending in the vertical direction may be arranged in the second metal layer.

[0414] Referring to FIG. 14, data lines DL(R), DL(G), DL(B), which are a kind of vertical wiring, can be arranged in the second metal layer. Also, a power supply wiring PWL, which is another kind of vertical wiring, can be arranged in the second metal layer.

[0415] Referring to FIG. 14, the power supply wiring PWL may be a wiring to which a power supply voltage that does not change in voltage level due to a frame change is applied, unlike the data lines DL(R), DL(G), DL(B). For example, the power supply wiring PWL can include at least one of a drive voltage line VDDL and a base voltage line VSSL.

[0416] As described above, the power supply wiring PWL can be arranged in the same metal layer (the second metal layer) as the vertical detour wiring V_BW.

[0417] Referring to FIG. 14, one of the two red data lines DL(R) that overlap with the red pixel electrode PE(R) corresponds to a protruding portion 1210 protruding from the red data line DL(R) which is the third data line DL3 in FIGS. 12 and 13.

[0418] Referring to FIG. 15, the third pixel electrode PE3 and the fourth pixel electrode PE4, which are two green pixel electrodes PE(G), can be connected to each other via a connection wiring CW.

[0419] Referring to FIG. 15, the third pixel electrode PE3 and the fourth pixel electrode PE4 can be integrally formed with the connection wiring CW.

[0420] Referring to FIG. 15, below the fourth pixel electrode PE4, a second active layer ACT2 on the second buffer layer 821 and a second gate metal GM2 corresponding to the second gate electrode GE2 on the second active layer ACT2 can be arranged.

[0421] Referring to FIG. 15, a first upper metal TM1 can be disposed between the first interlayer insulating layer 813 and the second buffer layer 821, and a first gate metal GM1 can be disposed between the first gate insulating layer 812 and the first interlayer insulating layer 813.

[0422] Referring to FIG. 16, the region where the X5-X6 line is displayed is a boundary region between the transmission region TA and the non-transmission region NTA.

[0423] Referring to FIG. 16, in the region where the X5-X6 line is displayed, the second data line DL2 can include an upper portion disposed in the same second metal layer as the first data line DL1, a lower portion disposed in a first metal layer lower than the second metal layer, a connecting portion connecting the upper portion and the lower portion, and an extension portion extending under the first data line DL1.

[0424] Referring to FIG. 16, in the region where the X5-X6 line is displayed, the second data line DL2 descends in the vertical direction and shifts in the horizontal direction so as to overlap the first data line DL1. Here, the first data line DL1 may be a green data line DL(G), and the second data line DL2 may be a blue data line DL(B).

[0425] Referring to FIG. 16, in the region where the X5-X6 line is displayed, the first data line DL1 may be a first upper data line DL(G)_ML2 disposed in the second metal layer. The second data line DL2 can include a second lower data line DL(B)_ML1 disposed in the first metal layer and a second upper data line DL(B)_ML2 disposed in the second metal layer.

[0426] Referring to FIG. 16, the upper blue data line DL(B)_ML2 can be connected to the lower blue data line DL(B)_ML1 through a hole in the first planarization layer 831. The lower blue data line DL(B)_ML1 can extend slightly in the horizontal direction and overlap the upper green data line DL(G)_ML2.

[0427] Referring to FIG. 17, the region where the X7-X8 line is displayed is a region included in the transmission region TA. In the region where the X7-X8 line is displayed, the first data line DL1 and the second data line DL2 can be vertically overlapped.

[0428] Referring to FIG. 17, in the region where the X7-X8 line is displayed, the first data line DL1 may be the first upper data line DL(G)_ML2 disposed in the second metal layer, and the second data line DL2 may be the second lower data line DL(B)_ML1 disposed in the first metal layer.

[0429] Referring to FIG. 17, the region where the X7-X8 line is displayed is a region included in the transmission region TA. In the region where the X7-X8 line is displayed, the first data line DL1 and the second data line DL2 can significantly improve the transmittance of the transmission region TA by overlapping in the vertical direction.

[0430] Referring to FIG. 18, the region where the X9-X10 line is displayed is a region included in the non-transmission region NTA and may be a sub-pixel circuit region.

[0431] Referring to FIG. 18, in the non-transmission region NTA, the first data line DL1 can include the first lower data line DL(G)_ML1 disposed in the first metal layer and the first upper data line DL(G)_ML2 disposed in a second metal layer different from the first metal layer.

[0432] The first lower data line DL(G)_ML1 and the first upper data line DL(G)_ML2 can be electrically connected to each other through a hole in the first planarization layer 831, which is an insulating layer between the first metal layer and the second metal layer.

[0433] Referring to FIG. 18, in the non-transmissive region NTA, the second data line DL2 can include a second lower data line DL(B)_ML1 disposed in the first metal layer and a second upper data line DL(B)_ML2 disposed in the second metal layer.

[0434] The second lower data line DL(B)_ML1 and the second upper data line DL(B)_ML2 can be electrically connected to each other through other holes in the first planarization layer 831 which is an insulating layer.

[0435] FIG. 19 is a cross-sectional view of a connection region between a vertical bypass wiring V_BW and a horizontal bypass wiring H_BW in the display panel 110 according to an embodiment of the present disclosure. However, the stacked structure in the cross-sectional view of FIG. 19 is the same as that in FIGS. 8 and 9. Therefore, the description of the stacked structure is omitted. In the following description, FIGS. 11 to 13 are also referred to together.

[0436] Referring to FIG. 19, the horizontal bypass wiring H_BW can be disposed in the first metal layer, and the vertical bypass wiring V_BW can be disposed in a second metal layer different from the first metal layer.

[0437] Referring to FIG. 19, the vertical bypass wiring V_BW can be connected to the horizontal bypass wiring H_BW through a hole in the first planarization layer 831 which is an insulating layer disposed between the first metal layer and the second metal layer.

[0438] Referring to FIG. 19, the region where the horizontal bypass wiring H_BW and the vertical bypass wiring V_BW are disposed may be a second region NA which is a general region NA.

[0439] Referring to FIG. 19, in the second region NA, there is a light-emitting region EA of the sub-pixel, and a pixel electrode PE therefor can be disposed. Also, in the second region NA, a transistor TFT included in the sub-pixel circuit of the sub-pixel may be disposed.

[0440] For example, each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, the fifth sub-pixel SP5, and the sixth sub-pixel SP6 shown in FIG. 11 includes a light-emitting element ED and a sub-pixel circuit SPC(G), and the sub-pixel circuit SPC(G) can include two or more transistors (TFT; DT, ST).

[0441] The fourth sub-pixel SP4 includes a light-emitting element ED and does not include a sub-pixel circuit SPC(G). The source electrode and drain electrode of each of the two or more transistors TFT can be arranged in the same first metal layer as the horizontal bypass wiring H_BW.

[0442] The first data line DL1, the upper data line DL(G)_U, and the lower data line DL(G)_D can be arranged in the same second metal layer as the vertical bypass wiring V_BW.

[0443] Referring to FIGS. 14 to 19, a display device 100 according to an embodiment of the present disclosure is located below a substrate SUB, overlaps a first region OA, and can further include an electronic device 800 that performs a predetermined operation using light that passes through the first region OA.

[0444] Briefly explaining the embodiments of the present disclosure described above, it is as follows.

[0445] A display device according to an embodiment of the present disclosure includes a substrate including a display area capable of displaying an image and a non-display area outside the display area, a plurality of sub-pixels included in the display area and each including a plurality of light-emitting elements, and a plurality of data lines for supplying data signals for image display to the plurality of sub-pixels.

[0446] The display area can include a first area that can transmit light and a second area located outside the first area. The second area can include an upper area located above the first area and a lower area located below the first area.

[0447] A plurality of data lines can include a first data line that passes through all of an upper region, a first region, and a lower region, an upper data line disposed in the upper region, a lower data line disposed in the lower region, and a detour wiring that electrically connects the upper data line and the lower data line and detours around the first region.

[0448] The detour wiring can include a first detour wiring connected to the upper data line, a second detour wiring connected to the lower data line, and a third detour wiring that connects the first detour wiring and the second detour wiring.

[0449] The detour wiring can include a horizontally extending horizontal detour wiring and a vertically extending vertical detour wiring. The first detour wiring and the second detour wiring may be horizontal detour wirings, and the third detour wiring may be a vertical detour wiring.

[0450] The horizontal detour wiring may be disposed in a first metal layer, and the vertical detour wiring may be disposed in a second metal layer different from the first metal layer.

[0451] The display device according to an embodiment of the present disclosure can further include a power supply wiring to which a power supply voltage that does not change in voltage level due to a change in the frame is applied. The power supply wiring may be disposed within the second metal layer.

[0452] The power supply wiring can be disposed in the same metal layer as the vertical detour wiring.

[0453] The plurality of light-emitting elements can each include a plurality of pixel electrodes.

[0454] A plurality of pixel electrodes can include a first pixel electrode disposed in an upper region and included in a first sub-pixel, a second pixel electrode disposed in the upper region and included in a second sub-pixel, a third pixel electrode disposed in a first region and included in a third sub-pixel, a fourth pixel electrode disposed in the first region and included in a fourth sub-pixel, a fifth pixel electrode disposed in a lower region and included in a fifth sub-pixel, and a sixth pixel electrode disposed in the lower region and included in a sixth sub-pixel.

[0455] The first data line can be connected to the first sub-pixel, the third sub-pixel, and the fifth sub-pixel.

[0456] The upper data line can be connected to the second sub-pixel.

[0457] The lower data line can be connected to the sixth sub-pixel.

[0458] In the display device according to an embodiment of the present disclosure, the third pixel electrode and the fourth pixel electrode can be electrically connected.

[0459] The emission colors of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel may be the same.

[0460] Each of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fifth sub-pixel, and the sixth sub-pixel can include a light-emitting element and a sub-pixel circuit for driving the light-emitting element. The sub-pixel circuit can include two or more transistors.

[0461] The fourth sub-pixel includes a light-emitting element, but may not include a sub-pixel circuit. In this case, the light-emitting element of the fourth sub-pixel can be driven by the sub-pixel circuit of the third sub-pixel.

[0462] The drive current output from the sub-pixel circuit of the third sub-pixel can be supplied to the third pixel electrode and the fourth pixel electrode.

[0463] The display device according to an embodiment of the present disclosure may further include a connection wiring disposed in the first region and electrically connecting the third pixel electrode and the fourth pixel electrode.

[0464] The third pixel electrode, the connection wiring, and the fourth pixel electrode may be integrally formed.

[0465] The plurality of pixel electrodes may further include a seventh pixel electrode disposed in the upper region and included in the seventh sub-pixel, an eighth pixel electrode disposed in the second region and included in the eighth sub-pixel, and a ninth pixel electrode disposed in the lower region and included in the ninth sub-pixel.

[0466] The plurality of data lines may further include a second data line connected to the seventh sub-pixel, the eighth sub-pixel, and the ninth sub-pixel.

[0467] The emission colors of the seventh sub-pixel, the eighth sub-pixel, and the ninth sub-pixel may be different from the emission colors of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel.

[0468] The second data line may intersect and overlap with a portion (i.e., the connection wiring) to which the third pixel electrode and the fourth pixel electrode are connected.

[0469] In one example, in the first region and the second region, the first data line and the second data line may be disposed in the same metal layer and spaced apart on the same plane.

[0470] In another example, in the second region, the first data line and the second data line can be arranged within the same metal layer. In at least a partial region of the first region, the first data line and the second data line may be arranged in different metal layers.

[0471] For example, in the second region, the first data line and the second data line can be arranged within the same metal layer and may be arranged spaced apart from each other on the same plane. The first region can include a transmissive region and a non-transmissive region. In the transmissive region, the first data line and the second data line are arranged in different metal layers and can overlap in the vertical direction. In the non-transmissive region, the first data line and the second data line can be arranged within the same metal layer and may be arranged spaced apart from each other on the same plane.

[0472] The plurality of pixel electrodes are arranged in the upper region, and can further include a tenth pixel electrode included in the tenth sub-pixel, an eleventh pixel electrode arranged in the first region and included in the eleventh sub-pixel, and a twelfth pixel electrode arranged in the lower region and included in the twelfth sub-pixel.

[0473] The plurality of data lines can further include a third data line connected to the tenth sub-pixel, the eleventh sub-pixel, and the twelfth sub-pixel.

[0474] The third data line can overlap with the tenth pixel electrode.

[0475] The third data line includes a protruding portion, and the protruding portion can overlap with the eleventh pixel electrode in the direction of the data line length. The emission color of each of the tenth sub-pixel, the eleventh sub-pixel, and the twelfth sub-pixel may be different from the emission color of each of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel.

[0476] The display device according to an embodiment of the present disclosure may further include a common electrode disposed on a plurality of pixel electrodes.

[0477] Within the first region, the common electrode may have a plurality of common electrode holes.

[0478] The display device according to an embodiment of the present disclosure may further include an electronic device that is located below the substrate, overlaps the first region, and performs a predetermined operation using light that passes through the first region.

[0479] The display device according to an embodiment of the present disclosure may include a second interlayer insulating layer on the substrate; a first planarization layer on the second interlayer insulating layer; and a second planarization layer on the first planarization layer. The first metal layer is located between the second interlayer insulating layer and the first planarization layer, and the second metal layer may be located between the first planarization layer and the second planarization layer.

[0480] The display device according to an embodiment of the present disclosure may include a substrate including a display region capable of image display and a non-display region outside the display region, a plurality of sub-pixels included in the display region, each including a plurality of pixel electrodes, and a plurality of data lines for supplying data signals for image display to the plurality of sub-pixels.

[0481] The display region may include a first region capable of transmitting light and a second region located outside the first region.

[0482] The second region may include an upper region located above the first region and a lower region located below the first region.

[0483] The plurality of pixel electrodes can include a first pixel electrode disposed in the upper region and included in the first sub-pixel, a second pixel electrode disposed in the upper region and included in the second sub-pixel, a third pixel electrode disposed in the first region and included in the third sub-pixel, a fourth pixel electrode disposed in the first region and included in the fourth sub-pixel, a fifth pixel electrode disposed in the lower region and included in the fifth sub-pixel, and a sixth pixel electrode disposed in the lower region and included in the sixth sub-pixel.

[0484] The plurality of data lines are arranged to extend from the upper region through the first region to the lower region, and can include a first data line connected to the first sub-pixel, the third sub-pixel, and the fifth sub-pixel, an upper data line disposed in the upper region and connected to the second sub-pixel, and a lower data line disposed in the lower region and connected to the sixth sub-pixel.

[0485] The third pixel electrode and the fourth pixel electrode may be electrically connected.

[0486] The display device according to an embodiment of the present disclosure can further include a connection wiring disposed in the first region and electrically connecting the third pixel electrode and the fourth pixel electrode.

[0487] The display device according to an embodiment of the present invention can include a substrate including a display region capable of image display and a non-display region outside the display region, a plurality of sub-pixels included in the display region, and a plurality of data lines for supplying data signals for image display to the plurality of sub-pixels. The display region can include a first region capable of transmitting light and a second region located outside the first region. A part of the plurality of data lines can pass through the first region, and another part of the plurality of data lines can bypass the first region.

[0488] According to the embodiments of the present disclosure described above, a display device having a light transmission structure can be provided in which an electronic device to receive light is not exposed on the front surface, and the electronic device can normally receive light (e.g., visible light, infrared light, or ultraviolet light, etc.).

[0489] According to the embodiments of the present disclosure, a display device can be provided that can improve the transmittance of an optical region (first region) through which light can pass.

[0490] According to the embodiments of the present disclosure, a display device having a structure that reduces the metal ratio in an optical region (first region) through which light can pass can be provided.

[0491] According to the embodiments of the present disclosure, a display device having a panel structure that can improve the sensing performance of a sensing sensor using light transmitted through an optical region (first region) can be provided.

[0492] According to the embodiments of the present disclosure, a display device having a panel structure that can improve the camera performance of a camera using light transmitted through an optical region (first region) can be provided.

[0493] The above description merely exemplarily explains the technical idea of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure pertains can make various modifications and variations without departing from the essential characteristics of the present disclosure. Also, the embodiments of the present disclosure do not limit the technical idea of the present disclosure but are for explanatory purposes, and the scope of the technical idea of the present disclosure is not limited by such embodiments.

Claims

1. A substrate including a display area capable of image display and a non-display area outside the display area, a plurality of sub-pixels included in the display area and each including a plurality of light-emitting elements, and a plurality of data lines for supplying data signals for image display to the plurality of sub-pixels, wherein the display area includes a first area capable of transmitting light and a second area located outside the first area, and the second area includes an upper area located above the first area and a lower area located below the first area, wherein the plurality of data lines include upper data lines arranged in the upper area, lower data lines arranged in the lower area, and a display device including a detour wiring that electrically connects the upper data lines and the lower data lines and detours around the first area.

2. The display device according to claim 1, wherein the plurality of data lines further include a first data line extending from the upper area to the lower area.

3. The detour wiring includes a first detour wiring connected to the upper data line, a second detour wiring connected to the lower data line, and a third detour wiring connecting the first detour wiring and the second detour wiring, according to the display device of claim 1.

4. The display device according to claim 1, wherein an intersection between the detour wiring and the upper data line and an intersection between the detour wiring and the lower data line have connection points.

5. A first connection point is formed at an intersection between the upper data line and the first detour wiring, a second connection point is formed at an intersection between the lower data line and the second detour wiring, a third connection point is formed at an intersection between the first detour wiring and the third detour wiring, and a fourth connection point is formed at an intersection between the second detour wiring and the third detour wiring, according to the display device of claim 3.

6. The detour wiring includes a horizontal detour wiring extending in the horizontal direction, and a vertical detour wiring extending in the vertical direction, according to the display device of claim 1.

7. A first connection point is formed at an intersection between the upper data line and the horizontal detour wiring, a second connection point is formed at an intersection between the lower data line and the horizontal detour wiring, and a third connection point and a fourth connection point are respectively formed at an intersection between the horizontal detour wiring and the vertical detour wiring, according to the display device of claim 6.

8. The horizontal detour wiring is arranged in a first metal layer, The vertical detour wiring is arranged in a second metal layer different from the first metal layer, and the display device according to claim 6.

9. The second metal layer is above the first metal layer, and the display device according to claim 8.

10. The horizontal detour wiring, the upper data line, and the lower data line form a mesh form, and the display device according to claim 6.

11. Further includes a power supply wiring to which a power supply voltage whose voltage level does not change due to a frame change is applied, The power supply wiring is arranged in the second metal layer, and the display device according to claim 8.

12. The plurality of light emitting elements each include a plurality of pixel electrodes, The plurality of pixel electrodes are A first pixel electrode arranged in the upper region and included in the first sub-pixel, A second pixel electrode arranged in the upper region and included in the second sub-pixel, A third pixel electrode arranged in the first region and included in the third sub-pixel, A fourth pixel electrode arranged in the first region and included in the fourth sub-pixel, A fifth pixel electrode arranged in the lower region and included in the fifth sub-pixel, and A sixth pixel electrode arranged in the lower region and included in the sixth sub-pixel, The upper data line is connected to the second sub-pixel, The lower data line is connected to the sixth sub-pixel, The third pixel electrode and the fourth pixel electrode are electrically connected to each other, and the display device according to claim 1.

13. The plurality of data lines further include a first data line extending from the upper region to the lower region, The first data line is connected to the first sub-pixel, the third sub-pixel, and the fifth sub-pixel, and the display device according to claim 12.

14. The emission colors of each of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel are the same, and the display device according to claim 13.

15. Each of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fifth sub-pixel, and the sixth sub-pixel includes a light emitting element and a sub-pixel circuit for driving the light emitting element, and the sub-pixel circuit includes two or more transistors. The fourth sub-pixel includes a light-emitting element but does not include a sub-pixel circuit, and the light-emitting element of the fourth sub-pixel is driven by the sub-pixel circuit of the third sub-pixel. The display device according to claim 13.

16. The driving current output from the sub-pixel circuit of the third sub-pixel is supplied to the third pixel electrode and the fourth pixel electrode. The display device according to claim 15.

17. The display device according to claim 12, further comprising a connection wiring disposed in the first region and electrically connecting the third pixel electrode and the fourth pixel electrode.

18. The plurality of pixel electrodes include a seventh pixel electrode disposed in the upper region and included in a seventh sub-pixel, an eighth pixel electrode disposed in the second region and included in an eighth sub-pixel, and a ninth pixel electrode disposed in the lower region and included in a ninth sub-pixel, wherein the emission colors of the seventh sub-pixel, the eighth sub-pixel, and the ninth sub-pixel are different from the emission colors of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel respectively. The display device according to claim 12.

19. The plurality of data lines further include a second data line connected to the seventh sub-pixel, the eighth sub-pixel, and the ninth sub-pixel. The display device according to claim 18.

20. The second data line intersects and overlaps a portion where the third pixel electrode and the fourth pixel electrode are connected. The display device according to claim 19.

21. The plurality of data lines further include a first data line extending from the upper region to the lower region, wherein in the first region and the second region, the first data line and the second data line are disposed in the same metal layer and are spaced apart on the same plane. The display device according to claim 19.

22. The plurality of data lines further include a first data line extending from the upper region to the lower region, wherein in the second region, the first data line and the second data line are disposed in the same metal layer, The display device according to claim 19, wherein in at least a partial region of the first region, the first data line and the second data line are disposed in different metal layers from each other.

23. In the second region, the first data line and the second data line are disposed within the same metal layer and are spaced apart from each other on the same plane. The first region includes a transmissive region and a non-transmissive region. In the transmissive region, the first data line and the second data line are disposed in different metal layers from each other and are superimposed in the vertical direction. The display device according to claim 22, wherein in the non-transmissive region, the first data line and the second data line are disposed within the same metal layer and are spaced apart from each other on the same plane.

24. The plurality of pixel electrodes include a tenth pixel electrode disposed in the upper region and included in a tenth sub-pixel, an eleventh pixel electrode disposed in the first region and included in an eleventh sub-pixel, and a twelfth pixel electrode disposed in the lower region and included in a twelfth sub-pixel. The emission color of each of the tenth sub-pixel, the eleventh sub-pixel, and the twelfth sub-pixel is different from the emission color of each of the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel. The display device according to claim 12.

25. The plurality of data lines further include a third data line connected to the tenth sub-pixel, the eleventh sub-pixel, and the twelfth sub-pixel. The third data line is superimposed on the tenth pixel electrode. The third data line includes a protruding portion, and the protruding portion is superimposed on the eleventh pixel electrode in the direction of the data line length. The display device according to claim 24.

26. further includes a common electrode disposed on the plurality of pixel electrodes. In the first region, the common electrode has a plurality of common electrode holes. The display device according to claim 1.

27. An electronic device located below the substrate and overlapping the first region, the display device according to claim 1, further including an electronic device that performs a predetermined operation using light transmitted through the first region.

28. The second interlayer insulating layer on the substrate, the first planarization layer on the second interlayer insulating layer, and further includes a second planarization layer on the first planarization layer, The first metal layer is located between the second interlayer insulating layer and the first planarization layer, and the second metal layer is located between the first planarization layer and the second planarization layer. The display device according to claim 8.

29. A substrate including a display area capable of image display and a non-display area outside the display area, a plurality of sub-pixels included in the display area, each including a plurality of pixel electrodes, and a plurality of data lines for supplying data signals for image display to the plurality of sub-pixels, The display area includes a first area capable of transmitting light and a second area located outside the first area, The second area includes an upper area located above the first area and a lower area located below the first area, The plurality of pixel electrodes are a first pixel electrode disposed in the upper area and included in the first sub-pixel, a second pixel electrode disposed in the upper area and included in the second sub-pixel, a third pixel electrode disposed in the first area and included in the third sub-pixel, a fourth pixel electrode disposed in the first area and included in the fourth sub-pixel, a fifth pixel electrode disposed in the lower area and included in the fifth sub-pixel, and a sixth pixel electrode disposed in the lower area and included in the sixth sub-pixel, The plurality of data lines are an upper data line disposed in the upper area and connected to the second sub-pixel, and a lower data line disposed in the lower area and connected to the sixth sub-pixel, The third pixel electrode and the fourth pixel electrode are electrically connected to each other. The display device.

30. The plurality of data lines are extends from the upper area to the lower area, and further includes a first data line connected to the first sub-pixel, the third sub-pixel, and the fifth sub-pixel. The display device according to claim 29.

31. The display device according to claim 29, further including a connection wiring disposed in the first area and electrically connecting the third pixel electrode and the fourth pixel electrode.

32. A substrate including a display area capable of image display and a non-display area outside the display area, a plurality of sub-pixels included in the display area, and a plurality of data lines for supplying data signals for image display to the plurality of sub-pixels, the display area includes a first area that can transmit light and a second area located outside the first area, the plurality of data lines bypass the first area, a display device.

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