Global sensing current generating circuit and display device including the same

Abstract

To improve luminance degradation due to accumulation of usage time of a display device.SOLUTION: There are provided a global sensing current generating circuit which senses a global current in a display region and a display device which compensates for fluctuation in the global current based on a current value of the sensed global current. The global sensing current generating circuit includes a plurality of sensing current generating circuits. The sensing current generating circuit includes: a driving transistor configured to generate the sensing current based on its gate-source voltage; a capacitor configured to charge the gate-source voltage of the driving transistor; and a plurality of switch transistors electrically connected to the driving transistor and the capacitor and configured to sample a threshold voltage of the driving transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This embodiment relates to a global sensing current generation circuit and a display device including the same.

Background Art

[0002] The drive circuit of a display device includes a data drive circuit that supplies a data voltage to a data line, a gate drive circuit that supplies a scan signal (or a gate signal) to a gate line (or a scan line), and the like. The gate drive circuit can be directly formed on the same substrate together with the circuit elements of the pixel array that constitutes the screen.

[0003] The circuit elements of the pixel array constitute pixel circuits formed in each pixel defined in a matrix form by the data lines and gate lines of the pixel array.

[0004] Here, each of the circuit elements of the pixel array includes a plurality of transistors. In other words, a plurality of transistors are included in one pixel circuit.

[0005] Generally, as the drive time of the display device accumulates, electrical characteristics such as the threshold voltage of the transistors change.

[0006] When the electrical characteristics of the transistors change, the global current, which is the total current flowing through the pixel array, fluctuates, and thereby the luminance of the display device may decrease.

Summary of the Invention

Problems to be Solved by the Invention

[0007] The present invention provides a global sensing current generation circuit that senses the global current in a display area and a display device that compensates for fluctuations in the global current based on the sensed current value of the global current.

[0008] The problems to be solved in this embodiment are not limited to the problems mentioned above, and other problems not mentioned here will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0009] One aspect of the present invention provides a global sensing current generation circuit including a plurality of sensing current generation circuits; and a single current sensing line connected to the plurality of sensing current generation circuits through which sensing currents respectively generated from the plurality of sensing current generation circuits flow during a current sensing period, wherein each sensing current generation circuit includes a driving transistor that generates the sensing current based on a gate-source voltage, a capacitor that charges the gate-source voltage of the driving transistor, and a plurality of switch transistors electrically connected to the driving transistor and the capacitor to sample the threshold voltage of the driving transistor.

[0010] Another aspect of the present invention provides a display device including an integrated circuit including a plurality of sensing current generation circuits arranged adjacent to one side of a display area; a single current sensing line connected to the plurality of sensing current generation circuits through which sensing currents respectively generated from the plurality of sensing current generation circuits flow during a current sensing period; and a current summing circuit that receives the sensing currents generated by the plurality of sensing current generation circuits through the single current sensing line during the current sensing period and outputs a global current sensing value obtained by summing the current values of the sensing currents; and a timing controller that receives the global current sensing value output by the current summing circuit, checks a global current variation amount of the display area using the global current sensing value, and compensates for the global current variation amount.

[0011] As described above, according to this embodiment, since the display device senses the global current flowing through the pixel array and compensates for the variation in the global current based on the sensed current value of the global current, it is possible to improve the luminance degradation due to the accumulation of the usage time of the display device.

[0012] Although the various beneficial advantages and effects of the embodiment are not limited to the above-described content, they will be more easily understood in the process of explaining the specific embodiments of the embodiment.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] The advantages and features of the present invention, and the method for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and can be embodied in various different forms, provided that the embodiments make the disclosure of the present invention complete and are provided to inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention in its entirety, and the present invention is defined only by the scope of the claims.

[0015] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, so the present invention is not limited to the matters illustrated in the drawings. The same reference numerals throughout the specification refer to substantially the same components. Also, in explaining the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

[0016] When terms such as "comprising", "including", "having", "consisting of", etc. mentioned in the present invention are used, other parts may be added as long as "only" is not used. When a component is expressed in the singular, it can be interpreted as plural unless otherwise explicitly stated.

[0017] In interpreting a component, it is interpreted as including an error range even without separate explicit description.

[0018] In the case of an explanation of a positional relationship, for example, when the positional relationship and the mutual connection relationship between two components are explained by "on", "above", "below", "next to", "connected or coupled (connect, couple)", "crossing, intersecting", etc., one or more other components may be interposed between the components unless there is a reference such as "immediately" or "directly".

[0019] First, second, etc. may be used to distinguish components, but the functions and structures of these components are not limited by the ordinal numbers attached to the components or the names of the components. Since the claims are described centered around essential components, the ordinal numbers attached to the names of the components in the claims do not have to match the ordinal numbers attached to the names of the components in the embodiments.

[0020] The following embodiments can be partially or entirely combined or combined with each other, enabling various technical linkages and drives. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0021] The display panel driving circuit, pixel circuit, level shifter, etc. in the display device of the present invention can include transistors. The transistors can be embodied as oxide thin film transistors containing oxides including oxide semiconductors, polycrystalline thin film transistors containing low temperature poly silicon (LTPS), etc.

[0022] A transistor is a three-terminal device that includes a Gate, a Source, and a Drain. The Source is the terminal that supplies carriers to the transistor. In the transistor, carriers start to flow from the Source. The Drain is the terminal through which carriers exit the transistor to the outside. In the transistor, the flow of carriers is from the Source to the Drain. In the case of an N-channel transistor, since the carriers are electrons, the Source voltage has a lower voltage than the Drain voltage so that electrons can flow from the Source to the Drain. In an N-channel transistor, the direction of the current is from the Drain to the Source side. In the case of a P-channel transistor, since the carriers are holes, the Source voltage is higher than the Drain voltage so that holes can flow from the Source to the Drain. In a P-channel transistor, since holes flow from the Source to the Drain side, the current flows from the Source to the Drain side. It should be noted that the Source and Drain of the transistor are not fixed. For example, the Source and Drain can be changed by the applied voltage. Therefore, the invention is not limited by the Source and Drain of the transistor. In the following description, the Source and Drain of the transistor will be referred to as the first terminal and the second terminal.

[0023] The scan signal swings between a Gate On Voltage and a Gate Off Voltage. The Gate Off Voltage can be interpreted as the first voltage, and the Gate On Voltage can be interpreted as the second voltage. The transistor is turned on in response to the Gate On Voltage and turned off in response to the Gate Off Voltage. In the case of an N-channel transistor, the Gate On Voltage can be a Gate High Voltage (VGH), and the Gate Off Voltage can be a Gate Low Voltage (VGL). In the case of a P-channel transistor, the Gate On Voltage can be the Gate Low Voltage VGL, and the Gate Off Voltage can be the Gate High Voltage VGH.

[0024] The present invention is applicable to any flat panel display device that does not require an integrated circuit and a power supply circuit for driving a pixel circuit such as an Organic Light Emitting Display (OLED Display).

[0025] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0026] FIG. 1 and FIG. 2 are block diagrams showing a display device according to an embodiment of the present invention.

[0027] Referring to FIGS. 1 and 2, a display device according to an embodiment includes a display panel 100 and a display panel driving circuit.

[0028] The display area AA of the display panel 100 includes a pixel array for displaying an image. A data voltage corresponding to video data is input to the pixel circuit P of the pixel array. The pixel array includes data lines DL, a number of gate lines GL intersecting the data lines DL, and pixel circuits P arranged in a matrix form. The display panel 100 may further include a power supply line commonly connected to the pixel circuits P. Here, the power supply line may include a low voltage power supply line LVL that supplies a low voltage power supply ELVSS and a high voltage power supply line (not shown) that supplies a high voltage power supply ELVDD.

[0029] When the resolution of the pixel array is n (n is a natural number) × m (m is a natural number), the pixel array includes n pixel columns and m pixel lines intersecting the pixel columns. The pixel lines include pixel circuits P arranged along the first direction X. The pixel columns include pixel circuits P arranged along the second direction Y. Generally, one horizontal period 1H can be the time obtained by dividing one frame period by the number of pixel lines, which is m. A data voltage can be input to the pixel circuit P of one pixel line in one horizontal period 1H.

[0030] The pixel circuit P can be divided into two or more sub-pixel circuits for color representation. For example, three pixel circuits sequentially arranged in the first direction X can be divided into a red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit.

[0031] Also, four pixel circuits sequentially arranged in the first direction X may be divided into a red sub-pixel circuit, a green sub-pixel circuit, a blue sub-pixel circuit, and a white sub-pixel circuit.

[0032] The pixel circuit P as described above is connected to the data line DL and the gate line GL. In one embodiment, when the display device is an organic light-emitting display device, the pixel circuit P is as shown in FIG. 7.

[0033] Referring to FIG. 7, the pixel circuit P includes a light-emitting element EL, a driving transistor DT that generates a driving current by a gate-source voltage and supplies the driving current to the light-emitting element EL, a capacitor Cst connected between a node on a power line to which a high-voltage power supply ELVDD is supplied and a second node n2, and charges the gate-source voltage of the driving transistor DT, a plurality of switch transistors (for example, ST1, ST2) electrically connected to the driving transistor DT and the capacitor Cst to sample the threshold voltage of the driving transistor DT, and other switch transistors for driving the pixel. In the drawings of the present invention, the pixel circuit P is illustrated as being composed of eight transistors and one capacitor, but the present invention is not limited thereto. In other words, the pixel circuit P can include three or more transistors and one or more capacitors.

[0034] In FIG. 7, the light-emitting element EL can be embodied as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode terminal and the cathode terminal of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML to form excitons, and visible light is emitted in the emission layer EML. The OLED used as a light-emitting element may have a tandem structure in which a plurality of emission layers are stacked. The tandem-structured OLED can improve the luminance and lifespan of pixels.

[0035] On the other hand, the display panel 100 may further include a touch sensor. Here, the touch sensor may be of an on-cell type or an add-on type and disposed on the screen of the display panel 100.

[0036] Also, the touch sensor may be embodied as an in-cell type built into the pixel array.

[0037] In the present invention, the display panel driving circuit writes video data to the pixel circuit P of the display panel 100 under the control of the timing controller 130. Such a display panel driving circuit may include a data driving circuit 110, a gate driving circuit 120, a timing controller 130 for controlling the operation timing of the driving circuits 110 and 120, and a level shifter 140 connected between the timing controller 130 and the gate driving circuit 120. And the display panel driving circuit may further include a power supply unit (not shown) that outputs a low voltage power supply ELVSS, a high voltage power supply ELVDD, etc. Here, the level shifter 140 may be included in the timing controller 130.

[0038] The data driving circuit 110 converts the video data received from the timing controller 130 in digital signal for each frame into an analog gamma compensation voltage and outputs a data voltage. The data voltage output from the data driving circuit 110 is supplied to the corresponding data line. The data driving circuit 110 outputs a data voltage by using a digital-to-analog converter (DAC) that converts a digital signal into an analog gamma compensation voltage.

[0039] Such a data driving circuit 110 can be integrated into a source driver integrated circuit (SDIC). The source driver IC can be connected to the bonding pads of the display panel 100 by a tape automated bonding (TAB) method or a chip on glass (COG) method. Also, the source driver IC may be implemented by a chip on film (COF) method.

[0040] When the display panel 100 further includes a touch sensor, the source driver IC may incorporate a touch sensor driving circuit for driving the touch sensor.

[0041] The gate driving circuit 120 may be formed in a non-display area (e.g., bezel area) where video is not displayed on the display panel 100, or at least a part thereof may be arranged in the display area AA. The gate driving circuit 120 receives the input of the clock signal received from the level shifter 140 and outputs a scan signal to the gate line GL.

[0042] The switch transistor of the pixel circuit P connected to the gate line GL can be turned on in response to the gate-on voltage of the scan signal and turned off in response to the gate-off voltage.

[0043] Such a gate drive circuit 120 can include a configuration as shown in FIG. 3.

[0044] Referring to FIG. 3, the gate drive circuit 120 includes a light emission control signal drive circuit 310 and a scan drive circuit 320. The scan drive circuit 320 can be composed of a first scan drive circuit to a fourth scan drive circuit 321, 322, 323, 324. Further, the second scan drive circuit 322 can be composed of an odd-numbered second scan drive circuit 322_O and an even-numbered second scan drive circuit 322_E, respectively.

[0045] The gate drive circuit 120 can be symmetrically configured with shift registers on both sides of the display area AA. Also, the shift register on one side of the display area AA of the gate drive circuit 120 includes the second scan drive circuits 322_O, 322_E, the fourth scan drive circuit 324, and the light emission control signal drive circuit 310, respectively, and the shift register on the other side of the display area AA can be configured to include the first scan drive circuit 321, the second scan drive circuits 322_O, 322_E, and the third scan drive circuit 323, respectively. However, it is not limited thereto, and the light emission control signal drive circuit 310 and the first to fourth scan drive circuits 321, 322, 323, 324 can be arranged differently according to the embodiment.

[0046] Each of the stages STG1 to STGn of the shift register can include a first scan signal generation circuit SC1(1) to SC1(n), a second scan signal generation circuit SC2_O(1) to SC2_O(n), SC2_E(1) to SC2_E(n), a third scan signal generation circuit SC3(1) to SC3(n), a fourth scan signal generation circuit SC4(1) to SC4(n), and a light emission control signal generation circuit EM(1) to EM(n), respectively.

[0047] The first scan signal generation circuits SC1(1) to SC1(n) output first scan signals SC1(1) to SC1(n) through the first gate lines of the display panel 100. The second scan signal generation circuits SC2(1) to SC2(n) output second scan signals SC2(1) to SC2(n) through the second gate lines of the display panel 100. The third scan signal generation circuits SC3(1) to SC3(n) output third scan signals SC3(1) to SC3(n) through the third gate lines of the display panel 100. The fourth scan signal generation circuits SC4(1) to SC4(n) output fourth scan signals SC4(1) to SC4(n) through the fourth gate lines of the display panel 100. The light emission control signal generation circuits EM(1) to EM(n) output light emission control signals EM(1) to EM(n) through the light emission control lines of the display panel 100.

[0048] The first scan signals SC1(1) to SC1(n) can be used as signals for driving the first transistors (e.g., compensation transistors, etc.) included in the pixel circuits. The second scan signals SC2(1) to SC2(n) can be used as signals for driving the second transistors (e.g., data gong emergency transistors, etc.) included in the pixel circuits. The third scan signals SC3(1) to SC3(n) can be used as signals for driving the third transistors (e.g., bias transistors, etc.) included in the pixel circuits. The fourth scan signals SC4(1) to SC4(n) can be used as signals for driving the fourth transistors (e.g., initialization transistors, etc.) included in the pixel circuits. The light emission control signals EM(1) to EM(n) can be used as signals for driving the fifth transistors (e.g., light emission control transistors, etc.) included in the pixel circuits. For example, if the light emission control transistors of the pixels are controlled using the light emission control signals EM(1) to EM(n), the light emission time of the light emitting elements can be varied.

[0049] Referring to FIG. 3, a bias voltage bus line VobsL, a first initialization voltage bus line VarL, and a second initialization voltage bus line ViniL can be arranged between the gate driving circuit 120 and the display area AA.

[0050] The bias voltage bus line VobsL, the first initialization voltage bus line VarL, and the second initialization voltage bus line ViniL can supply the bias voltage Vobs, the first initialization voltage Var, and the second initialization voltage Vini from the power supply circuit of the display device to the pixel circuit, respectively.

[0051] In the drawings, the bias voltage bus line VobsL, the first initialization voltage bus line VarL, and the second initialization voltage bus line ViniL are illustrated as being located only on one side, either the left or the right, of the display area AA. However, the present invention is not limited thereto, and they may be located on both sides, or the position on one side, either the left or the right, is not limited.

[0052] Referring to FIG. 3, one or more optical areas OA1, OA2 may be arranged in the display area AA.

[0053] One or more optical areas OA1, OA2 may be arranged to overlap one or more optoelectronic devices such as imaging devices (image sensors) like cameras, proximity sensors, and illuminance sensors.

[0054] For the operation of the optoelectronic device, a light transmission structure may be formed in one or more optical areas OA1, OA2 to have a transmittance of a certain level or higher. In other words, the number of pixels per unit area in one or more optical areas OA1, OA2 may be smaller than the number of pixels per unit area in the general area excluding the optical areas OA1, OA2 in the display area AA. That is, the resolution of one or more optical areas OA1, OA2 may be lower than the resolution of the general area in the display area AA.

[0055] In one or more optical areas OA1, OA2, the light transmission structure may be formed by patterning the cathode electrode in a portion where no pixel is arranged. At this time, the patterned cathode electrode may be removed using a laser, or the cathode electrode may be selectively formed and patterned by using the same material as the cathode evaporation prevention layer.

[0056] Further, in one or more optical regions OA1, OA2, the light transmission structure may be configured by separating the light emitting element EL and the pixel circuit in a pixel. In other words, the light emitting element EL of the pixel is located on the optical regions OA1, OA2, a plurality of transistors TFTs constituting the pixel circuit are arranged around the optical regions OA1, OA2, and the light emitting element EL and the pixel circuit can be electrically connected through a transparent metal layer.

[0057] The timing controller 130 can multiply the input frame frequency by i and control the operation timing of the display panel driving circuits 110, 120 at a frame frequency of input frame frequency × i (i is a natural number) Hz. The input frame frequency can be 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Phase - Alternating Line) system.

[0058] The timing controller 130 receives video data and a timing signal synchronized therewith from the host system 200. The video data received by the timing controller 130 is a digital signal. The timing controller 130 can convert the video data into a data format suitable for use by the data driving circuit 110 and transmit it to the data driving circuit 110. Here, the timing signal can include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, a data enable signal, etc. Here, the data enable signal has a period of 1 horizontal period 1H.

[0059] The timing controller 130 can generate a data timing control signal for controlling the data driving circuit 110 and a gate timing control signal for controlling the gate driving circuit 120 based on the timing signal received from the host system 200. The gate timing control signal can be generated by a clock of a digital signal voltage level.

[0060] The host system 200 can be any one of a TV (Television), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In mobile and wearable devices, the data driving circuit 110, the timing controller 130, the level shifter 140, etc. can be integrated into one drive IC (not shown). In a mobile system, the host system 200 can be implemented by an AP (Application Processor). The host system 200 can transmit video data to the drive IC through the MIPI (Mobile Industry Processor Interface). The host system 200 can be connected to the drive IC through a flexible printed circuit board (FPCB).

[0061] On the other hand, in the present invention, the switching transistor of the pixel circuit P can be implemented by an N-channel oxide thin film transistor.

[0062] Also, some of the switching transistors of the pixel circuit P can be implemented by oxide thin film transistors with low off current, and the rest can be implemented by polycrystalline thin film transistors with high on-current characteristics.

[0063] For example, in FIG. 7, ST1 and ST2 (indicated by the dotted rectangle), which are switching transistors electrically connected to the driving transistor DT and the capacitor Cst, can be implemented by oxide thin film transistors, and the remaining transistors ST3 to ST7 can be implemented by polycrystalline thin film transistors.

[0064] Here, the off current can mean the leakage current of the transistor. And the oxide thin film transistor can be N-channel, and the polycrystalline thin film transistor can be P-channel or N-channel.

[0065] The gate-on voltage of an N-channel oxide thin-film transistor or an N-channel polycrystalline thin-film transistor can be a gate-high voltage, and the gate-off voltage can be a gate-low voltage.

[0066] And the gate-on voltage of a P-channel polycrystalline thin-film transistor can be a gate-low voltage, and the gate-off voltage can be a gate-high voltage.

[0067] When the switching transistor is composed of an oxide thin-film transistor and a polycrystalline thin-film transistor as described above, the display panel 100 can have the following cross-sectional structure.

[0068] FIG. 4 is a cross-sectional view showing a stacked form of a display panel according to an embodiment of the present invention.

[0069] In FIG. 4, the switching transistor will be referred to as a switching thin-film transistor.

[0070] Referring to FIG. 4, it is a cross-sectional view including two switching thin-film transistors TFT1, TFT2 and one capacitor CST. The two switching thin-film transistors TFT1, TFT2 include a polycrystalline thin-film transistor TFT1 containing a polycrystalline semiconductor material and an oxide thin-film transistor TFT2 containing an oxide semiconductor material.

[0071] The polycrystalline thin-film transistor TFT1 illustrated in FIG. 4 is an emission switching thin-film transistor connected to the light-emitting element EL, and the oxide thin-film transistor TFT2 is any one of the switching thin-film transistors connected to the capacitor CST.

[0072] In FIG. 4, one pixel includes a light-emitting element EL and a pixel driving circuit that applies a driving current to the light-emitting element EL. The pixel driving circuit is disposed on the substrate 411, and the light-emitting element EL is disposed on the pixel driving circuit. And a sealing layer 420 is disposed on the light-emitting element EL. The sealing layer 420 protects the light-emitting element EL.

[0073] The pixel driving circuit may refer to a pixel array portion including a driving thin film transistor, a switching thin film transistor, and a capacitor. And the light-emitting element EL may refer to an array portion for light emission including an anode electrode, a cathode electrode, and a light-emitting layer disposed therebetween.

[0074] The substrate 411 may be embodied as a multi-layer in which an organic film and an inorganic film are alternately laminated. For example, the substrate 411 may be alternately laminated with an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2).

[0075] A lower buffer layer 412a is formed on the substrate 411. The lower buffer layer 412a is for blocking moisture and the like that may penetrate from the outside, and a silicon oxide (SiO2) film or the like can be laminated in multiple layers and used. An auxiliary buffer layer 412b may be further disposed on the lower buffer layer 412a to protect the element from moisture permeation.

[0076] A polycrystalline thin film transistor TFT1 is formed on the substrate 411. The polycrystalline thin film transistor TFT1 can use a polycrystalline semiconductor as an active layer. The polycrystalline thin film transistor TFT1 includes a first active layer ACT1 including a channel through which electrons or holes move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0077] The first active layer ACT1 includes a first channel region, a first source region disposed on one side sandwiching the first channel region, and a first drain region disposed on the other side.

[0078] The first source region and the first drain region are regions in which a group-V or group-III impurity ion, such as indium (P) or boron (B), is doped into a pure polycrystalline semiconductor material at a predetermined concentration to be made conductive. The first channel region maintains the polycrystalline semiconductor material in a pure state and provides a path for electrons and holes to move.

[0079] On one hand, the polycrystalline thin film transistor TFT1 includes a first gate electrode GE1 overlapping with a first channel region in the first active layer ACT1. A first gate insulating layer 413 is disposed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 413 can be formed by laminating a single or multiple inorganic layers such as a silicon oxide (SiO2) film or a silicon nitride (SiNx) film.

[0080] In one embodiment, the polycrystalline thin film transistor TFT1 has a top gate structure in which the first gate electrode GE1 is located above the first active layer ACT1. Accordingly, the first electrode CST1 included in the capacitor CST and the light shielding layer LS included in the oxide thin film transistor TFT2 can be formed of the same material as the first gate electrode GE1. By forming the first gate electrode GE1, the first electrode CST1, and the light shielding layer LS through a single mask process, the number of mask processes can be reduced. However, it is not limited thereto, and the light shielding layer LS may be formed through a separate mask process on the lower buffer layer 412a and the auxiliary buffer layer 412b. In this case, the light shielding layer LS is not limited to the oxide thin film transistor TFT2 and can be formed under all transistors. Also, the light shielding layer LS may be disposed to overlap the lower part of the capacitor CST to form a double capacitor.

[0081] The first gate electrode GE1 is composed of a metal material. For example, the first gate electrode GE1 can be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0082] A first interlayer insulating layer 414 is disposed on the first gate electrode GE1. The first interlayer insulating layer 414 can be implemented with silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0083] The display panel 100 may further include an upper buffer layer 415, a second gate insulating layer 416, and a second interlayer insulating layer 417 that are sequentially disposed on the first interlayer insulating layer 414. The polycrystalline thin film transistor TFT1 is formed on the second interlayer insulating layer 417 and includes a first source electrode SD1 and a first drain electrode SD2 that are respectively connected to the first source region and the first drain region.

[0084] The first source electrode SD1 and the first drain electrode SD2 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0085] The upper buffer layer 415 separates the first active layer ACT1 embodied by a polycrystalline semiconductor material from the second active layer ACT2 of the oxide thin film transistor TFT2 embodied by an oxide semiconductor material, and provides a substrate on which the second active layer ACT2 can be formed.

[0086] The second gate insulating layer 416 covers the second active layer ACT2 of the oxide thin film transistor TFT2. Since the second gate insulating layer 416 is formed on the second active layer ACT2 embodied by an oxide semiconductor material, it is embodied by an inorganic film. For example, the second gate insulating layer 416 may be silicon oxide (SiO2), silicon nitride (SiNx), or the like.

[0087] The second gate electrode GE2 is made of a metal material. For example, the second gate electrode GE2 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0088] On one hand, the oxide thin film transistor TFT2 is formed on the upper buffer layer 415 and includes a second active layer ACT2 embodied with an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 416, and a second source electrode SD3 and a second drain electrode SD4 disposed on the second interlayer insulating layer 417.

[0089] The second active layer ACT2 is embodied with an oxide semiconductor material and includes an intrinsic second channel region not doped with impurities and a second source region and a second drain region doped with impurities and made conductive.

[0090] The oxide thin film transistor TFT2 is located below the upper buffer layer 415 and further includes a light shielding layer LS overlapping with the second active layer ACT2. The light shielding layer LS can block the light incident on the second active layer ACT2 to ensure the reliability of the oxide thin film transistor TFT2. The light shielding layer LS is formed of the same material as the first gate electrode GE1 and can be formed on the upper surface of the first gate insulating layer 413. The light shielding layer LS may be electrically connected to the second gate electrode GE2 to form a dual gate.

[0091] The second source electrode SD3 and the second drain electrode SD4 can be formed simultaneously of the same material on the second interlayer insulating layer 417 together with the first source electrode SD1 and the first drain electrode SD2, thereby reducing the number of mask processes.

[0092] On the other hand, a second electrode CST2 can be disposed on the first interlayer insulating layer 414 so as to overlap with the first electrode CST1 to embody a capacitor CST. The second electrode CST2 can be a single layer or a multilayer made of, for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0093] The capacitor CST stores the data voltage applied through the data line DL for a certain period and then provides it to the light-emitting element EL. The capacitor CST includes two electrodes corresponding to each other and a dielectric disposed therebetween. A first interlayer insulating layer 414 is located between the first electrode CST1 and the second electrode CST2.

[0094] Of the capacitor CST, the first electrode CST1 or the second electrode CST2 can be electrically connected to the oxide thin film transistor TFT2, the second source electrode SD3, or the second drain electrode SD4. However, it is not limited thereto, and the connection relationship of the capacitor CST can be changed by the pixel driving circuit.

[0095] On the other hand, on the pixel driving circuit, a first planarization layer 418 and a second planarization layer 419 are sequentially disposed to planarize the upper end of the pixel driving circuit. The first planarization layer 418 and the second planarization layer 419 can be organic films such as polyimide and acrylic resin.

[0096] And, the light-emitting element EL is formed on the second planarization layer 419.

[0097] The light-emitting element EL includes an anode electrode ANO, a cathode electrode CAT, and a light-emitting layer LEL disposed between the anode electrode ANO and the cathode electrode CAT. When implemented with a pixel driving circuit that commonly uses a low potential voltage connected to the cathode electrode CAT, the anode electrode ANO is disposed as a separate electrode for each sub-pixel. If implemented with a pixel driving circuit that commonly uses a high potential voltage, the cathode electrode CAT may be disposed as a separate electrode for each sub-pixel.

[0098] The light-emitting element EL is electrically connected to the driving element through an intermediate electrode CNE disposed on the first planarization layer 418. Specifically, the anode electrode ANO of the light-emitting element EL and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the pixel driving circuit are connected by the intermediate electrode CNE.

[0099] The anode electrode ANO is connected to the intermediate electrode CNE exposed through a contact hole penetrating the second planarization layer 419. Further, the intermediate electrode CNE is connected to the first source electrode SD1 exposed through a contact hole penetrating the first planarization layer 418.

[0100] The intermediate electrode CNE serves as a medium connecting the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE can be formed of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0101] The anode electrode ANO can be formed in a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film is made of a material with a relatively large work function value such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), and the opaque conductive film can be composed of a single-layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode electrode ANO can be formed in a structure where a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially laminated, or in a structure where a transparent conductive film and an opaque conductive film are sequentially laminated.

[0102] The light-emitting layer LEL is formed by laminating a hole-related layer, an organic light-emitting layer, and an electron-related layer in this order or in the reverse order on the anode electrode ANO.

[0103] The bank layer BNK can be a pixel-defining film that exposes the anode electrode ANO of each pixel. The bank layer BNK may be formed of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer BNK contains a light-shielding substance composed of at least one of a color pigment, organic black, and carbon. A spacer can be further disposed on the bank layer BNK.

[0104] The cathode electrode CAT is formed on the upper surface and the side surface of the light-emitting layer LEL so as to face the anode electrode ANO with the light-emitting layer LEL interposed therebetween. The cathode electrode CAT can be integrally formed over the entire display area AA. When the cathode electrode CAT is applied to a front emission type organic light-emitting display device, it can be made of a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

[0105] A sealing layer 420 for suppressing moisture penetration may be further disposed on the cathode electrode CAT.

[0106] The sealing layer 420 can block the penetration of external moisture and oxygen into the light-emitting element EL that is vulnerable to external moisture and oxygen. For this purpose, the sealing layer 420 can include at least one inorganic sealing layer and at least one organic sealing layer, but is not limited thereto. In the present invention, the structure of the sealing layer 420 in which the first sealing layer 421, the second sealing layer 422, and the third sealing layer 423 are sequentially laminated will be described as an example.

[0107] The first sealing layer 421 is formed on the substrate 411 on which the cathode electrode CAT is formed. The third sealing layer 423 is formed on the substrate 411 on which the second sealing layer 422 is formed, and can be formed so as to surround the upper surface, the lower surface, and the side surface of the second sealing layer 422 together with the first sealing layer 421. Such first sealing layer 421 and third sealing layer 423 can minimize or prevent the penetration of external moisture and oxygen into the light-emitting element EL. The first sealing layer 421 and the third sealing layer 423 can be formed of an inorganic insulating material capable of low-temperature vapor deposition such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first sealing layer 421 and the third sealing layer 423 are vapor-deposited in a low-temperature atmosphere, it is possible to prevent damage to the light-emitting element EL that is vulnerable to a high-temperature atmosphere during the vapor deposition process of the first sealing layer 421 and the third sealing layer 423.

[0108] The second encapsulation layer 422 serves as a buffer to relieve the stress between layers due to the bending of the display device 40 and can planarize the step between layers. This second encapsulation layer 422 can be formed on the substrate 411 on which the first encapsulation layer 421 is formed with a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as photoacrylic, but is not limited thereto. When the second encapsulation layer 422 is formed through an inkjet method, a dam DAM can be disposed to prevent the liquid-form second encapsulation layer 422 from spreading to the edge of the substrate 411. The dam DAM can be disposed closer to the edge of the substrate 411 than the second encapsulation layer 422. Such a dam DAM can prevent the second encapsulation layer 422 from spreading to the pad region where the conductive pads disposed at the outermost contour of the substrate 411 are located.

[0109] The dam DAM is designed to prevent the diffusion of the second encapsulation layer 422. However, if the second encapsulation layer 422 is formed to exceed the height of the dam DAM during the process, since the second encapsulation layer 422, which is an organic layer, can be exposed to the outside, moisture and the like can easily penetrate into the interior of the light-emitting element. Therefore, the dam DAM can be formed in at least 10 or more layers overlappingly to prevent this.

[0110] The dam DAM can be disposed on the second interlayer insulating layer 417 in the non-display area NA.

[0111] Also, the dam DAM can be formed simultaneously with the first planarization layer 418 and the second planarization layer 419. When the first planarization layer 418 is formed, the lower layer of the dam DAM is formed together, and when the second planarization layer 419 is formed, the upper layer of the dam DAM is formed together and can be formed by being laminated in a double structure.

[0112] Therefore, the dam DAM can be made of the same material as the first planarization layer 418 and the second planarization layer 419, but is not limited thereto.

[0113] The dam DAM can be formed overlapping with the low-voltage power line LVL. For example, the low-voltage power line LVL can be formed in the lower layer of the region where the dam DAM is located in the non-display region NA.

[0114] The gate driving circuit 120 configured in the form of the low-voltage power line LVL and GIP (Gate In Panel) is formed to surround the outer contour of the display panel, and the low-voltage power line LVL can be located outside the outer contour of the gate driving circuit 120. Also, the low-voltage power line LVL can be connected to the cathode electrode CAT to apply a common voltage. Although the gate driving circuit 120 is simply represented in the planar and cross-sectional drawings, it can be configured using thin-film transistors having the same structure as those of the thin-film transistors in the display area AA.

[0115] The low-voltage power line LVL is disposed outside the gate driving circuit 120. The low-voltage power line LVL is disposed outside the gate driving circuit 120 and surrounds the display area AA. For example, the low-voltage power line LVL may be made of the same material as the first gate electrode GE1, but is not limited thereto, and may be made of the same material as the second electrode CST2 or the first source and drain electrodes SD1, SD2, but is not limited thereto.

[0116] Also, the low-voltage power line LVL can be electrically connected to the cathode electrode CAT. The low-voltage power line LVL can supply the low-voltage power ELVSS to the pixels in the display area AA.

[0117] A touch layer can be disposed on the sealing layer 420. In the touch layer, the touch buffer film 451 can be located between the touch electrode connection lines 452, 454 and the touch sensor metal including the touch electrodes 455, 456 and the cathode electrode CAT of the light-emitting element EL.

[0118] The touch buffer film 451 can block the penetration of chemical solutions (such as developers or etchants, etc.) or external moisture used during the manufacturing process of the touch sensor metal disposed on the touch buffer film 451 into the light-emitting layer LEL containing organic substances. Accordingly, the touch buffer film 451 can prevent damage to the light-emitting layer LEL that is vulnerable to chemical solutions or moisture.

[0119] The touch buffer film 451 can prevent damage to the light-emitting layer LEL containing organic substances that is vulnerable to high temperatures, and can be formed at a certain temperature (for example, a low temperature of 100 degrees Celsius (°C) or less), and is formed of an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer film 451 can be formed of a material such as an acrylic series, an epoxy series, or a siloxane series. The touch buffer film 451 having planarization performance with an organic insulating material can prevent damage to the sealing layer 420 due to bending of the organic light-emitting display device and the phenomenon that the touch sensor metal formed on the touch buffer film 451 breaks.

[0120] According to the touch sensor structure of the mutual capacitance substrate, touch electrodes 455 and 456 are disposed on the touch buffer film 451, and the touch electrodes 455 and 456 can be disposed so as to cross each other.

[0121] The touch electrode connection lines 452 and 454 can electrically connect between the touch electrodes 455 and 456. The touch electrode connection lines 452 and 454 and the touch electrodes 455 and 456 can be located in different layers with the touch insulating film 453 interposed therebetween.

[0122] The touch electrode connection lines 452 and 454 are disposed so as to overlap the bank layer BNK, and it is possible to prevent a decrease in the aperture ratio.

[0123] On the other hand, a part of the touch electrode connection line 452 of the touch electrodes 455 and 456 can be electrically connected to a touch drive circuit (not shown) through the touch pad through the upper and side surfaces of the sealing layer 420 and the upper and side surfaces of the dam DAM.

[0124] A part of the touch electrode connection line 452 can receive the supply of a touch driving signal from the touch driving circuit and transmit it to the touch electrodes 455 and 456, and the touch sensing signals at the touch electrodes 455 and 456 may be transmitted to the touch driving circuit.

[0125] A touch protection film 457 can be disposed on the touch electrodes 455 and 456. Although the touch protection film 457 is illustrated as being disposed only on the touch electrodes 455 and 456 in the drawing, it is not limited thereto, and the touch protection film 457 can be extended to before or after the dam DAM and also be disposed on the touch electrode connection line 452.

[0126] And a color filter (not shown) can be further disposed on the sealing layer 420. The color filter may be located on the touch layer or may be located between the sealing layer 420 and the touch layer.

[0127] On the other hand, since an oxide thin film transistor receives more stress due to temperature, light, etc. than a polycrystalline thin film transistor, electrical characteristics such as the threshold voltage of the oxide thin film transistor change as the usage time of the display device accumulates.

[0128] When the electrical characteristics of the oxide thin film transistor change, the global current, which is the total current flowing through the pixel array in the display area AA, decreases, and thereby the luminance of the display device may decrease as a whole. Here, the stress can be one or more of positive bias temperature stress (PBTS), negative bias temperature stress (NBTS), and negative bias temperature and illumination stress (NBTiS).

[0129] In the present invention, a plurality of sensing current generation circuits CG for sensing the global current of the pixel array, that is, the global current of the display area AA, are arranged on one side of the display area AA, so that the global current of the display area AA can be sensed. Here, the global current of the display area AA may gradually decrease as the usage time of the display device accumulates. Therefore, by repeatedly sensing the global current with a time difference, it is possible to confirm the change in the global current of the display area AA and also compensate for the change in the global current.

[0130] Specifically, a display device according to an embodiment of the present invention can include a global sensing current generation circuit capable of sensing the global current of the display area AA.

[0131] Referring to FIG. 1, the global sensing current generation circuit can include a plurality of sensing current generation circuits CG, a single current sensing line GCL_S, a switch circuit SW_sel, a data line DL_S for current sensing, and a current summing circuit 112.

[0132] A sensing area SA, which is an area where a plurality of sensing current generation circuits CG are arranged in an embodiment of the present invention, may be located on one side of the display area AA as shown in FIGS. 1 and 5, or may also be located on the other side of the display area AA as shown in FIGS. 2 and 6.

[0133] When the sensing area SA is located on one side and the other side of the display area AA, the plurality of sensing current generation circuits CG, the single current sensing line GCL_S, the switch circuit SW_sel, and the data line DL_S for current sensing can be respectively arranged on both sides of the display area AA as shown in FIG. 2.

[0134] The plurality of sensing current generation circuits CG are arranged adjacent to one side of the display area AA and may receive the supply of the data voltage for current sensing during the current sensing period.

[0135] A plurality of sensing current generation circuits CG are arranged adjacent to both side edges of the display area AA and may receive supply of a data voltage for current sensing during a current sensing period. Here, the plurality of sensing current generation circuits CG may be arranged in the second direction Y on one side edge or both side edges of the display area AA. In other words, the plurality of sensing current generation circuits CG may be arranged in a pixel column form. In FIGS. 1 and 2, the plurality of sensing current generation circuits CG are illustrated as being arranged in one pixel column form on one side edge or both side edges of the display area AA, but the present invention is not limited thereto, and the plurality of sensing current generation circuits CG may be arranged in two or more pixel column forms.

[0136] When the display area AA in the present invention includes m pixel lines, since one or more sensing current generation circuits CG may be arranged on one side or both sides of each pixel line, the number of the plurality of sensing current generation circuits CG may be an integral multiple of m.

[0137] Here, a plurality of pixel circuits P are arranged in the display area AA. And the pixel circuit P can include a light emitting element EL, a capacitor Cst, a driving transistor DT, a plurality of switch transistors (for example, ST1, ST2) and the remaining switch transistors ST3 to ST7 as shown in FIG. 7.

[0138] The sensing current generation circuit CG includes a sensing driving transistor DT_S that generates a sensing current by a gate-source voltage as shown in FIG. 8, a sensing capacitor Cst_S that charges the gate-source voltage of the sensing driving transistor DT_S, a plurality of sensing switch transistors (for example, ST1_S, ST2_S) that are electrically connected to the sensing driving transistor DT_S and the sensing capacitor Cst_S and sample the threshold voltage of the sensing driving transistor, and the remaining sensing switch transistors ST3_S to ST7_S. And the sensing current generation circuit CG does not include a light emitting element.

[0139] The driving transistor DT_S for sensing is the same type of transistor as the driving transistor DT, and the plurality of switching transistors ST1_S, ST2_S for sensing are the same type of transistors as the plurality of switching transistors ST1, ST2. And the remaining sensing switching transistors ST3_S to ST7_S are also the same type of transistors as the remaining switching transistors ST3 to ST7.

[0140] The number of the plurality of sensing switching transistors ST1_S, ST2_S is the same as the number of the plurality of switching transistors ST1, ST2, and the number of the remaining sensing switching transistors ST3_S to ST7_S is also the same as the number of the remaining switching transistors ST3 to ST7.

[0141] Also, the plurality of switching transistors ST1, ST2 and one or more sensing switching transistors ST1_S, ST2_S can be oxide thin film transistors, and the remaining switching transistors ST3 to ST7 and the remaining sensing switching transistors ST3_S to ST7_S can be polycrystalline thin film transistors.

[0142] In other words, in the sensing current generation circuit CG, the remaining components excluding the light emitting element are the same as those in the pixel circuit P.

[0143] In FIG. 1, the single current sensing line GCL_S is commonly connected to a plurality of sensing current generation circuits CG.

[0144] And a switch circuit SW_sel is arranged at one end of the single current sensing line GCL_S.

[0145] The switch circuit SW_sel electrically connects the single current sensing line GCL_S and the current summing circuit 112 during the current sensing period, and electrically connects the low voltage power supply line LVL commonly connected to a plurality of pixel circuits and the single current sensing line GCL_S during periods other than the current sensing period. Here, the low voltage power supply line LVL is a line that supplies the low voltage power supply ELVSS. The low voltage power supply ELVSS can be set to -5 [V], but is not limited thereto.

[0146] Although not shown in FIG. 1, a gate line GL that supplies a scan signal, a high voltage power supply line (not shown) that supplies the high voltage power supply ELVDD, etc. are identically connected to the pixel circuit P and the sensing current generation circuit CG.

[0147] Therefore, when a plurality of pixel circuits P are driven with the switch circuit SW_sel electrically connecting the low voltage power supply line LVL and the single current sensing line GCL_S, the transistors of the plurality of sensing current generation circuits CG arranged adjacent to the display area AA and the transistors of the plurality of pixel circuits P can operate identically.

[0148] Accordingly, the oxide thin film transistors of the sensing current generation circuit CG also receive stress at the same level as the stress received by the oxide thin film transistors of the pixel circuit P.

[0149] In other words, when a plurality of pixel circuits P are driven with the low voltage power supply line LVL and the single current sensing line GCL_S electrically connected by the switch circuit SW_sel, one or more of the positive bias stress and the negative bias stress can be accumulated in the plurality of switch transistors ST1, ST2 and the plurality of sensing switch transistors ST1_S, ST2_S. Here, the positive bias stress can be, for example, positive bias temperature stress PBTS, positive bias temperature and light stress PBTiS, etc., and the negative bias stress can be, for example, negative bias temperature stress NBTS, negative bias temperature and light stress NBTiS, etc.

[0150] On the other hand, the data line DL_S for current sensing is commonly connected to a plurality of sensing current generation circuits CG, and supplies a data voltage for current sensing to the plurality of sensing current generation circuits CG during a current sensing period. Here, the data voltage for current sensing can be output by the data driving circuit 110.

[0151] The current summing circuit 112 receives the sensing currents generated by the respective plurality of sensing current generation circuits CG through a single current sensing line GCL_S during a current sensing period, and outputs a global current sensing value obtained by summing the current values of the sensing currents.

[0152] Here, the plurality of sensing current generation circuits CG are arranged in a pixel column form and are connected to the corresponding gate line GL, so that sensing currents can be sequentially generated and output in the upward or downward direction of the display panel 100 from the upper side to the lower side or from the lower side to the upper side. And the current summing circuit 112 can sequentially receive the sensing currents through a single current sensing line GCL_S.

[0153] Such a current summing circuit 112 can include an ADC (Analog-to-Digital Converter) circuit that sums the current values of the sensing currents, which are analog values, and outputs a global current sensing value, which is a digital value, during a current sensing period. Here, the ADC circuit can be a single slope ADC (Single Slope Analog-to-Digital Converter) circuit, which is an integrating type ADC circuit. And the sensing current can be the drive current of the sensing current generation circuit CG in which the stress accumulated in one or more sensing switch transistors, that is, one or more oxide thin film transistors, is reflected.

[0154] In the global sensing current generation circuit described above, a plurality of sensing current generation circuits CG, a single current sensing line GCL_S, and a current sensing data line DL_S are arranged in a display panel 100 including a display area AA, and the switch circuit SW_sel and the current summing circuit 112 can be arranged in a data driving circuit 110 that supplies a data voltage to a plurality of pixel circuits P.

[0155] On the other hand, the global current sensing value output by the current summing circuit 112 can be received by the timing controller 130.

[0156] The timing controller 130 that has received the global current sensing value can confirm the global current variation amount in the display area AA using the global current sensing value. And the timing controller 130 can compensate for the global current variation amount. A detailed description thereof will be given in the descriptions of FIGS. 12 and 13.

[0157] Hereinafter, the driving method of the global sensing current generation circuit will be described.

[0158] FIG. 9 is a drawing for explaining the driving method of the global sensing current generation circuit according to an embodiment of the present invention.

[0159] Referring to FIG. 9, during a normal period (Normal Timing), which is a period other than the current sensing period (GC Sensing Timing), a switching signal of a first voltage level Lv1 can be input to the switch circuit SW_sel of the global sensing current generation circuit. The switch circuit SW_sel that has received the input of the switching signal of the first voltage level Lv1 can electrically connect the single current sensing line GCL_S and the low voltage power supply line LVL.

[0160] And during the normal period (Normal Timing), the current sensing data voltage Vdata_S is not supplied to the plurality of sensing current generation circuits CG.

[0161] However, when a plurality of pixel circuits P are driven, the scan signal, high voltage power supply ELVDD, etc. supplied to the plurality of pixel circuits P are also supplied to the plurality of sensing current generation circuits CG. Therefore, when the plurality of pixel circuits P are driven during the normal period (Normal Timing), the transistors of the plurality of sensing current generation circuits CG arranged adjacent to the display area AA and the transistors of the plurality of pixel circuits P can operate identically.

[0162] Accordingly, stress at the same level as the positive bias stress or negative bias stress accumulated in the oxide thin film transistors of the pixel circuit P is also accumulated in the oxide thin film transistors of the sensing current generation circuit CG. Here, during the normal period (Normal Timing), the data voltage Vdata is supplied to the plurality of pixel circuits P, and the current sensing data voltage Vdata_S is not supplied to the plurality of sensing current generation circuits CG. However, the presence or absence of the supply of the data voltage may not significantly affect the stress of the oxide thin film transistors.

[0163] The reason is that since the oxide thin film transistor is sensitive to the negative bias stress received in the state where the transistor is turned off, the electrical characteristic change due to the negative bias stress mainly occurs.

[0164] As described above, by electrically connecting the switch circuit SW_sel to the single current sensing line GCL_S and the low voltage power line LVL during the normal period (Normal Timing), stress at the same level as that of the plurality of pixel circuits P can be accumulated in the plurality of sensing current generation circuits CG.

[0165] On one hand, during the current sensing period (GC Sensing Timing), a switching signal with a second voltage level Lv2 can be input to the switch circuit SW_sel. The switch circuit SW_sel that receives the input of the switching signal with the second voltage level Lv2 can electrically connect the single current sensing line GCL_S and the current summing circuit 112.

[0166] And during the current sensing period (GC Sensing Timing), the data voltage for current sensing Vdata_S can be supplied to a plurality of sensing current generation circuits CG. Here, the data voltage for current sensing Vdata_S supplied to each of the plurality of sensing current generation circuits CG can have the same voltage value. For example, the data voltage for current sensing Vdata_S can have a voltage value corresponding to a luminance of 600 nits (Nit).

[0167] Then, the data voltage for current sensing Vdata_S can be sequentially supplied to the plurality of sensing current generation circuits CG by the scan signals sequentially output by the gate driving circuit 120.

[0168] The plurality of sensing current generation circuits CG that receive the supply of the data voltage for current sensing Vdata_S can each generate a sensing current.

[0169] The sensing currents respectively generated by the plurality of sensing current generation circuits CG are input to the current summing circuit 112 through the single current sensing line GCL_S. Here, the plurality of sensing current generation circuits CG can sequentially generate and output the sensing current, and the current summing circuit 112 can sequentially receive the input of the sensing current through the single current sensing line GCL_S. Here, the sensing current can be the driving current of the sensing current generation circuit CG in which the stress accumulated in one or more sensing switch transistors included in the sensing current generation circuit CG, that is, one or more oxide thin film transistors, is reflected.

[0170] The current summing circuit 112 that receives the input of the sensing current sums the current values of the sensing current and outputs them as the global current sensing value GC Sen. Here, since the sensing current is sequentially input, the global current sensing value GC Sen can increase linearly during the current sensing period (GC Sensing Timing).

[0171] Then, at the end of the current sensing period (GC Sensing Timing) when all the sensing currents are input to the current summing circuit 112, the global current sensing value GC Sen output by the current summing circuit 112 can be used as the global current sensing value in the display area AA.

[0172] In other words, since the pixel circuits P and the sensing current generation circuits CG included for each pixel line have the same transistor configuration and the stress is accumulated at the same level, the drive currents generated by the plurality of pixel circuits P and the sensing currents generated by the plurality of sensing current generation circuits CG can be the same or very similar. Therefore, the global current value of the display area AA can be replaced with the value obtained by summing all the sensing currents generated by the plurality of sensing current generation circuits CG.

[0173] The global sensing current generation circuit can sense the global current value of the display area AA through the above-described method. And the global sensing current generation circuit can repeat the current sensing period (GC Sensing Timing) with a time difference. Here, the time difference can be a constant period or a non-constant period such as the turn-on or turn-off time of the display device.

[0174] On the other hand, since the plurality of sensing current generation circuits CG do not include the light-emitting element EL, they do not emit light by the data voltage for current sensing. Therefore, the current sensing period (GC Sensing Timing) can proceed regardless of the driving of the plurality of pixel circuits P.

[0175] In other words, as shown in FIG. 9, during the period when the plurality of pixel circuits P are being driven by the data voltage Vdata, the current sensing period (GC Sensing Timing) can progress, or the current sensing period (GC Sensing Timing) can progress when the plurality of pixel circuits P are not being driven.

[0176] FIGS. 10 and 11 are diagrams for explaining the amount of variation in the global current due to the cumulative use of the display device.

[0177] Referring to FIG. 10, generally, the global current value can be the best at T1, which is the initial use time point of the display device. And as the use time of the display device accumulates, the global current can decrease.

[0178] Therefore, the global current value at T2, which is the time point when the cumulative use time of the display device has passed a certain time or more, can be smaller than the global current value at T1.

[0179] Since the global sensing current generation circuit of the display device repeats and progresses the current sensing period with a time difference, it can output the global current sensing value GC Sen at time point T1 as shown in FIG. 11, and can also output the global current sensing value GC Sen at time point T2. Here, the global current sensing value at time point T2 may be smaller than the global current sensing value at time point T1.

[0180] In other words, as the use time of the display device accumulates, the global current sensing value can gradually decrease.

[0181] The timing controller 130 of the display device receives the global current sensing value according to the cumulative use time from the global sensing current generation circuit, confirms the amount of variation in the global current in the display area AA as follows, and can compensate for the amount of variation in the global current.

[0182] FIG. 12 is a diagram for explaining a method of compensating for the variation in the global current in the display device according to an embodiment of the present invention.

[0183] The timing controller 130 can store the best global current value of the display device as a reference value.

[0184] Then, the timing controller 130 can compare the global current sensing value received by the global sensing current generation circuit with the reference value to confirm the global current variation amount of the display area AA.

[0185] Thereafter, the timing controller 130 can compensate for the global current variation amount of the display area AA by using a compensation gain corresponding to the global current variation amount. Therefore, the global current of the display area AA can be maintained as a reference value regardless of the cumulative usage time of the display device.

[0186] Here, the timing controller 130 can store a look-up table as shown in FIG. 13, and can compensate for the global current variation amount by using the look-up table.

[0187] Specifically, the timing controller 130 can calculate a global current reduction ratio, which is the global current variation amount, by using the reference value and the global current sensing value.

[0188] Then, the timing controller 130 can increase the luminance value of the video data as a whole by using a compensation gain corresponding to the calculated global current reduction ratio.

[0189] Thereafter, the timing controller 130 can transmit the video data with the luminance value increased as a whole, that is, the compensated video data, to the data driving circuit 110.

[0190] The data driving circuit 110 can raise the data voltage according to the compensated video data. Therefore, the global current of the display area AA can be maintained as a reference value.

[0191] For example, when the global current reduction ratio is 40%, the timing controller 130 can increase the luminance value of the video data as a whole by using a compensation gain of 1.67, which corresponds to a 40% global current reduction ratio, in a look-up table as shown in FIG. 13.

[0192] As a result, the global current in the display area AA can be maintained at 100%.

[0193] Hereinafter, the driving method of the sensing current generation circuit CG will be described.

[0194] FIG. 14 is a drawing showing waveforms of a scan signal and an EM signal generated for driving the sensing current generation circuit. FIGS. 15 to 19 are circuit diagrams stepwise showing the operation of the sensing current generation circuit during the driving period of the sensing current generation circuit.

[0195] Referring to FIG. 14, the driving period of the sensing current generation circuit CG can be divided into an initialization period INI, a sampling period SAM, an on-bias period OBS, a holding period HOLD, and an emission period EMI.

[0196] During the initialization period INI, the voltages of the scan signals SC1, SC2, SC3(n), SC3(n + 1), SC4 and the EM signal EM are the gate high voltage VGH. Therefore, as shown in FIG. 15 during the initialization period INI, the first sensing switch transistor ST1_S and the second sensing switch transistor ST2_S are turned on, and the initialization voltage Vinit is applied to the second node n2 and the third node n3. Then, the initialization voltage Vinit can also be applied to the first node n1 through the sensing driving transistor DT_S that maintains the on state.

[0197] During the initialization period INI, the voltages of the second node n2, the third node n3, and the first node n1 are the initialization voltage Vinit. During the initialization period INI, since the fifth sensing switch transistor ST5_S and the sixth sensing switch transistor ST6_S are in the off state, the fourth node n4 is floated to maintain the previous state. Here, the first sensing switch transistor ST1_S and the second sensing switch transistor ST2_S can be N-channel transistors turned on by the gate high voltage VGH. And the initialization voltage Vinit can be set to -5 [V], but is not limited thereto.

[0198] During the sampling period SAM, the voltage of the second scan signal SC2 is inverted from the gate high voltage VGH to the gate low voltage VGL.

[0199] During the sampling period SAM, the voltages of the first scan signal SC1 and the EM signal EM are the gate high voltage VGH, and the voltage of the fourth scan signal SC4 is the gate low voltage VGL. When the third sensing switch transistor ST3_S is turned on during the sampling period SAM in response to the gate low voltage VGL of the second scan signal SC2, as shown in FIG. 16, the current sensing data voltage Vdata_S is applied to the first node n1, and the current sensing data voltage Vdata_S is also applied to the third node n3 and the second node n2 through the on-state sensing drive transistor DT_S. At this time, the voltage of the first node n1 is the current sensing data voltage Vdata_S, and the voltages of the third node n3 and the second node n2 are each Vdata_S + Vth + α, where Vth is the threshold voltage of the drive element DT and α is the threshold voltage change value of the oxide thin film transistor. Here, the threshold voltage change value α of the oxide thin film transistor can be the amount of decrease in the threshold voltage of the oxide thin film transistor due to the stress accumulated in the oxide thin film transistor. The threshold voltage change value α can be a negative number.

[0200] On the other hand, during the sampling period SAM, the fourth node n4 is in a floating state. Here, the third sensing switch transistor ST3_S can be a P-channel transistor turned on by the gate low voltage VGL. And the current sensing data voltage Vdata_S can be set to a voltage between 0 [V] and 4 [V], but is not limited thereto.

[0201] During the on-bias period OBS, the voltages of the third (n) scan signal SC3(n) and the third (n + 1) scan signal SC3(n + 1) are inverted from the gate high voltage VGH to the gate low voltage VGL.

[0202] The fourth sensing switch transistor ST4_S is turned on during the on-bias period OBS in response to the gate low voltage VGL of the third (n) scan signal SC3(n).

[0203] And the fifth sensing switch transistor ST5_S is turned on during the on-bias period OBS in response to the gate low voltage VGL of the third (n + 1) scan signal SC3(n + 1). As a result, as shown in FIG. 17, the first compensation voltage VOBS is applied to the first node n1 and the third node n3, and the second compensation voltage VAR is applied to the fourth node n4.

[0204] At this time, the voltages of the first node n1 and the third node n3 are the first compensation voltage VOBS, and the voltage of the fourth node n4 is the second compensation voltage VAR. The voltage of the second node n2 can maintain the previous state and be Vdata_S + Vth + α. Here, the fourth sensing switch transistor ST4_S and the fifth sensing switch transistor ST5_S can be P-channel transistors turned on by the gate low voltage VGL. And the first compensation voltage VOBS and the second compensation voltage VAR can be set to -4.5 [V] respectively, but are not limited thereto.

[0205] During the HOLD period, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the gate low voltage VGL, and the voltages of the second scan signal SC2, the third(n) scan signal SC3(n), and the third(n + 1) scan signal SC3(n + 1) are the gate high voltage VGH. The voltage of the EM signal EM is the gate high voltage VGH during the HOLD period. Therefore, as shown in FIG. 18, since all of the first sensing switch transistors ST1_S to the seventh sensing switch transistors ST7_S are in the off state, the first node n1 to the fourth node n4 are floated to maintain the previous state.

[0206] During the EMI period, the voltages of the first scan signal SC1 and the fourth scan signal SC4 and the EM signal EM are the gate low voltage VGL, and the voltages of the second scan signal SC2, the third(n) scan signal SC3(n), and the third(n + 1) scan signal SC3(n + 1) are the gate high voltage VGH. As shown in FIG. 19, the sixth sensing switch transistor ST6_S and the seventh sensing switch transistor ST7_S are turned on in response to the gate low voltage VGL of the EM signal EM. Therefore, a current path is formed between the high voltage power supply ELVDD and the fourth node n4 during the EMI period.

[0207] During the EMI period, the sensing current generated by the gate-source voltage Vdata_S + Vth + α of the sensing drive transistor DT_S can be output on the single current sensing line GCL_S. Here, the sixth sensing switch transistor ST6_S and the seventh sensing switch transistor ST7_S can be P-channel transistors turned on by the gate low voltage VGL. And the high voltage power supply ELVDD can be set to 6 [V], but is not limited thereto.

[0208] Through the operation of the sensing current generation circuit CG as described above, a sensing current reflecting the stress accumulated in the plurality of sensing switch transistors, which are oxide thin film transistors, can be generated in the sensing current generation circuit CG.

[0209] As described above, in one embodiment of the present invention, a plurality of sensing current generation circuits CG are arranged so as to receive the same level of stress as the plurality of pixel circuits P, and the sensing currents output by the plurality of sensing current generation circuits CG are combined to derive the global current value of the display area AA.

[0210] In one embodiment of the present invention, the sensing current generation circuit has been described as performing only the function of generating a sensing current. However, the present invention is not limited to this, and the sensing current generation circuit may further perform other functions. In other words, the sensing current generation circuit can be used for other purposes as well.

[0211] FIG. 20 is a block diagram showing a global sensing current generation circuit according to another embodiment of the present invention. FIGS. 21 and 22 are drawings exemplarily showing the sensing current generation circuit according to another embodiment of the present invention.

[0212] Referring to FIG. 20, in another embodiment of the present invention, the global sensing current generation circuit can include a plurality of repair / current generation circuits R / CG that are also used as repair pixel circuits for repairing defective pixel circuits DP included in the plurality of pixel circuits P. In FIG. 20, the plurality of repair / current generation circuits R / CG are illustrated as being arranged in the form of one pixel column on one side of the display area AA, but the present invention is not limited to this, and the plurality of repair / current generation circuits R / CG may be arranged in the form of two or more pixel columns. And the plurality of repair / current generation circuits R / CG may be arranged on both sides of the display area AA.

[0213] The repair / current generation circuit R / CG, which is a sensing current generation circuit according to another embodiment of the present invention, is composed of the same transistors as the pixel circuit. In other words, the repair / current generation circuit R / CG can include one or more oxide thin film transistors (e.g., ST1, ST2).

[0214] The light-emitting element EL is not connected to the fourth node n4 side, and the single current sensing line GCL_S is connected to the fourth node n4 side.

[0215] In the current sensing data line DL_S, a current sensing data voltage Vdata_S can be supplied as shown in FIG. 21, or a repair data voltage Vdata_re can be supplied as shown in FIG. 22.

[0216] A repair wiring can be arranged between one or more pixel circuits P forming one pixel line and the repair / current generation circuit R / CG.

[0217] As shown in FIG. 21, the normal pixel circuit (Normal Pixel), which is a normal pixel circuit, and the repair / current generation circuit R / CG are not electrically connected by a repair wiring (Repair Wire).

[0218] During the current sensing period of the global sensing current generation circuit, a current sensing data voltage Vdata_S can be supplied to the repair / current generation circuit R / CG.

[0219] On the other hand, as shown in FIG. 22, the defective pixel circuit (Defect Pixel), which is a defective pixel circuit, and the repair / current generation circuit R / CG are electrically connected by a repair wiring (Repair Wire). Here, the fourth node n4 of the repair / current generation circuit R / CG and the repair wiring (Repair Wire) are electrically connected by welding or the like, and the fourth node n4 of the defective pixel circuit (Defect Pixel) and the repair wiring (Repair Wire) are electrically connected by welding or the like.

[0220] Then, the repair / current generation circuit R / CG and the single current sensing line GCL_S are disconnected. Also, the power supply line to which the high-voltage power supply ELVDD is supplied in the defective pixel circuit (Defect Pixel), the line connecting the fourth node n4 and the fifth switch transistor ST5, and the line connecting the fourth node n4 and the sixth switch transistor ST6 are also disconnected.

[0221] When the repair / current generation circuit R / CG is electrically connected to the defective pixel circuit (Defect Pixel) as shown in FIG. 22, the data voltage Vdata_re for repair is supplied to the data line DL_S for current sensing. Here, the data voltage Vdata_re for repair is the data voltage supplied to the defective pixel circuit (Defect Pixel).

[0222] For example, when the defective pixel circuit DP is located on the third line as shown in FIG. 20, the data voltage Vdata_3rd of the third line can be supplied to the data voltage Vdata_re for repair.

[0223] Through this, the drive current corresponding to the video data data_3rd of the third line flows through the repair wiring (Repair Wire) to the light-emitting element EL of the defective pixel circuit (Defect Pixel).

[0224] As described above, the data voltage Vdata_S for current sensing is not supplied to the repair / current generation circuit R / CG that is electrically connected to the defective pixel circuit (Defect Pixel).

[0225] For example, when the repair / current generation circuit R / CG of the third line (3rd Line) is connected to the defective pixel circuit DP of the third line (3rd Line) as shown in FIG. 20, the repair / current generation circuit R / CG of the third line (3rd Line) is not supplied with the data voltage Vdata_S for current sensing during the current sensing timing (GC Sensing Timing) as shown in FIG. 23. Therefore, the light-emitting element EL of the defective pixel circuit (Defect Pixel) electrically connected to the repair / current generation circuit R / CG of the third line (3rd Line) does not emit light due to the data voltage Vdata_S for current sensing.

[0226] Here, the global current sensing value GC Sen is a value obtained by summing the sensing currents output by a plurality of repair / current generation circuits R / CG. Therefore, even if a small number of repair / current generation circuits R / CG among the plurality of repair / current generation circuits R / CG are used as repair pixel circuits, the reliability of the global current sensing value GC Sen does not significantly decrease.

[0227] FIG. 24 is a block diagram showing a global sensing current generation circuit according to still another embodiment of the present invention. And FIG. 25 is a drawing exemplarily showing a sensing current generation circuit according to still another embodiment of the present invention.

[0228] Referring to FIG. 24, in still another embodiment of the present invention, the global sensing current generation circuit can include a dummy / current generation circuit D / CG that is also used as a dummy pixel circuit driven during the orbit drive of the display device. Here, the orbit drive means a drive method for relaxing the deterioration and afterimage of a plurality of pixel circuits P by moving the entire display image in accordance with a predetermined period.

[0229] In FIG. 24, a plurality of dummy / current generation circuits D / CG are illustrated as being arranged in the form of two pixel columns on one side of the display area AA. However, the present invention is not limited to this, and the plurality of dummy / current generation circuits D / CG may be arranged in the form of one or three or more pixel columns. And the plurality of dummy / current generation circuits D / CG may be arranged on both sides of the display area AA.

[0230] As shown in FIG. 25, a dummy / current generation circuit D / CG, which is a sensing current generation circuit according to still another embodiment of the present invention, is composed of the same transistors as the pixel circuit. In other words, the dummy / current generation circuit D / CG can include one or more oxide thin film transistors (for example, ST1, ST2).

[0231] And the light emitting element EL is connected to the fourth node n4 side, and the single current sensing line GCL_S is connected to the cathode side of the light emitting element EL.

[0232] A current sensing data voltage Vdata_S or an orbit drive data voltage Vdata_O can be supplied to the current sensing data line DL_S. Here, the current sensing data voltage Vdata_S is supplied during the current sensing period, and the orbit drive data voltage Vdata_O is supplied during the orbit drive.

[0233] In still another embodiment of the present invention, since the dummy / current generation circuit D / CG includes the light emitting element EL, when the current sensing data voltage Vdata_S is supplied to the dummy / current generation circuit D / CG during the current sensing period, the light emitting element EL of the dummy / current generation circuit D / CG can emit light.

[0234] Therefore, in still another embodiment of the present invention, the current sensing period can be the turn-on time, turn-off time, or screensaver operation time of the display device. And during the current sensing period, an image compatible with the light emission patterns of the plurality of dummy / current generation circuits D / CG can be displayed in the display area AA.

[0235] Since the contents of the specification describing the problems to be solved, the means for solving the problems, and the effects do not specify the essential features of the claims, the scope of the claims is not limited by the matters described in the contents of the specification.

[0236] As described above, the embodiments of the present invention have been described in more detail with reference to the accompanying drawings. However, the present invention is not necessarily limited to such embodiments, and can be variously modified and implemented without departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the present invention are for explaining the present invention, not for limiting the technical idea of the present invention, and the scope of the technical idea of the present invention is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative and not restrictive in all respects. The protection scope of the present invention should be construed according to the scope of the claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

Description of Reference Numerals

[0237] 100: Display panel 110: Data driving circuit 112: Current summing circuit 120: Gate driving circuit 130: Timing controller 200: Host system

Claims

1. A plurality of sensing current generation circuits, and a single current sensing line connected to the plurality of sensing current generation circuits, through which sensing currents respectively generated from the plurality of sensing current generation circuits flow during a current sensing period, wherein the sensing current generation circuit includes a driving transistor that generates the sensing current based on a gate-source voltage, a capacitor that charges the gate-source voltage of the driving transistor, and a plurality of switch transistors electrically connected to the driving transistor and the capacitor to sample the threshold voltage of the driving transistor, an integrated circuit.

2. The integrated circuit according to claim 1, further comprising a current summing circuit that receives, during the current sensing period, the sensing currents generated by the plurality of sensing current generation circuits through the single current sensing line and outputs a global current sensing value obtained by summing the current values of the sensing currents.

3. The integrated circuit according to claim 2, further comprising a switch circuit that electrically connects the single current sensing line and the current summing circuit during the current sensing period, and electrically connects a low-voltage power supply line commonly connected to a plurality of pixel circuits and the single current sensing line during a period other than the current sensing period.

4. The integrated circuit according to claim 3, further comprising a data line for current sensing that is connected to the plurality of sensing current generation circuits and supplies a data voltage for current sensing to the plurality of sensing current generation circuits during the current sensing period.

5. The integrated circuit according to claim 3, wherein the driving transistor is the same type of transistor as the driving transistor included in the pixel circuit, and the plurality of switch transistors are the same type of transistors as the plurality of switch transistors included in the pixel circuit.

6. The integrated circuit according to claim 5, wherein the plurality of switch transistors of the sensing current generation circuit and the plurality of switch transistors of the pixel circuit are oxide transistors.

7. The integrated circuit according to claim 6, wherein the number of the plurality of switch transistors of the sensing current generation circuit is the same as the number of the plurality of switch transistors of the pixel circuit.

8. When the pixel circuit is driven with the low-voltage power supply line and the single current sensing line electrically connected by the switch circuit, one or more stresses among positive bias stress and negative bias stress are accumulated in the plurality of switch transistors of the sensing current generation circuit and the plurality of switch transistors included in the pixel circuit. The integrated circuit according to claim 6.

9. The integrated circuit according to claim 1, wherein the sensing current generation circuit does not include a light-emitting element.

10. The integrated circuit according to claim 9, wherein the sensing current generation circuit is also used as a repair pixel circuit for repairing a defective pixel circuit included in a display area.

11. The integrated circuit is further includes a current sensing data line connected to the plurality of sensing current generation circuits and supplying a current sensing data voltage to the plurality of sensing current generation circuits during the current sensing period, When the Nth (N is a natural number of 1 or more) sensing current generation circuit among the plurality of sensing current generation circuits is used as the repair pixel circuit, the current sensing data voltage is not supplied to the Nth sensing current generation circuit during the current sensing period. The integrated circuit according to claim 10.

12. The integrated circuit according to claim 2, wherein the current summing circuit includes an analog-to-digital converter (ADC) circuit that sums the current values of the sensing current, which is an analog value, during the current sensing period and outputs a sum value as the global current sensing value, which is a digital value.

13. further includes a dummy / current generation circuit including a light-emitting element (EL), The integrated circuit according to claim 1, wherein the dummy / current generation circuit is used as a dummy pixel circuit.

14. An integrated circuit including a plurality of sensing current generation circuits arranged adjacent to one side of a display area, a single current sensing line connected to the plurality of sensing current generation circuits and through which sensing currents respectively generated from the plurality of sensing current generation circuits flow during a current sensing period, and a current summing circuit that receives the sensing currents generated by the plurality of sensing current generation circuits through the single current sensing line during the current sensing period and outputs a global current sensing value obtained by summing the current values of the sensing currents, and A display device including a timing controller that receives the global current sensing value output by the current summing circuit, checks the global current fluctuation amount in the display area using the global current sensing value, and compensates for the global current fluctuation amount.

15. The display device according to claim 14, wherein the timing controller compensates for the global current fluctuation amount by increasing the luminance value of the video data displayed in the display area as a whole.

16. The display device according to claim 15, wherein the timing controller increases the luminance value of the video data as a whole using a gain value corresponding to the global current sensing value in a pre-stored look-up table.

17. The display device according to claim 14, wherein the current summing circuit includes an analog-to-digital converter (ADC) circuit that sums the current values of the sensing current, which is an analog value, during the current sensing period and outputs a sum value as the global current sensing value, which is a digital value.

18. The display device according to claim 17, wherein the ADC circuit is a single-slope ADC circuit.

19. The display device according to claim 14, further including a plurality of pixel circuits included in the display area in a driving state during the current sensing period.

20. The sensing current generation circuit includes a driving transistor that generates the sensing current based on a gate-source voltage, a capacitor that charges the gate-source voltage of the driving transistor, and a plurality of switch transistors electrically connected to the driving transistor and the capacitor to sample the threshold voltage of the driving transistor. The display device according to claim 14.

21. The display device according to claim 20, wherein the driving transistor is the same type of transistor as the driving transistor included in the pixel circuit, and the plurality of switch transistors are the same type of transistors as the plurality of switch transistors included in the pixel circuit.

22. The display device according to claim 21, wherein the plurality of switch transistors of the sensing current generation circuit and the plurality of switch transistors of the pixel circuit are oxide transistors.

23. The display device according to claim 22, wherein the plurality of switch transistors of the sensing current generation circuit and the plurality of switch transistors of the pixel circuit are the same in number.

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