Pixel circuit and display device including the same

Abstract

To provide a pixel circuit and a display device including the same.SOLUTION: A pixel circuit includes: a driving element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a light-emitting element connected to the second electrode of the driving element; a first capacitor disposed between the first node and a fourth node; a second capacitor disposed between the fourth node and the second node; a first switch element disposed between the first node and the third node; a second switch element disposed between the fourth node and a reference voltage supply line; and a third switch element disposed between the first node and an initialization voltage supply line. A display device including the pixel circuit is disclosed.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments relate to a pixel circuit and a display device including the same.

Background Art

[0002] In the information society, many technologies in the field of display devices for displaying visual information as video or images have been developed. Among display devices, an organic light-emitting display device uses an organic light-emitting diode, which is a self-luminous element that emits light from a light-emitting layer by recombination of electrons and holes. Therefore, it has a fast response speed, high brightness, low driving voltage, can be made ultrathin, and can be realized in a free form. It is attracting attention as a next-generation display in color.

[0003] Generally, an organic light-emitting display device corrects the characteristics of a driving transistor (Thin Film Transistor) that controls the driving current flowing through the organic light-emitting diode to reduce luminance unevenness.

[0004] The content described in the background art should not be regarded as prior art only because its description is mentioned in the background art or is related to the background art. The background art may include content that explains one or more aspects of the technology of the embodiments.

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the inventors have focused on the following fact. With the trend of high resolution and high-speed driving of organic light-emitting display devices in color, it is difficult to sufficiently compensate for differences in pixel driving characteristics with known compensation methods.

[0006] For example, as the resolution and / or driving frequency increases, the 1 horizontal period (H) for writing data to the pixels in one line on the display panel becomes shorter. The 1 horizontal period (H) is the time for writing data to the pixels arranged in one horizontal line on the screen.

[0007] The driving circuit of the organic light-emitting display device samples the threshold voltage Vth of the driving transistor within one horizontal period (H), compensates the data voltage with the threshold voltage Vth, and writes the data to the pixel. Therefore, when one horizontal period (H) becomes shorter, the time available for sampling the threshold voltage Vth of the driving transistor becomes shorter.

[0008] When the time required for sampling the threshold voltage Vth of the driving transistor becomes insufficient, the threshold voltage Vth of the driving transistor may be inaccurately sensed, which may cause differences in driving characteristics between pixels.

[0009] One aspect of the present embodiment can provide a pixel circuit for improving one or more problems due to the limitations and demerits of related technologies, and a display device including the same.

[0010] The embodiment provides a pixel circuit and a display device including the same that can ensure sufficient sampling time even during high-speed driving.

[0011] The embodiment provides a display device that prevents a short circuit between the pixel driving voltage and the initialization voltage during the initial period.

[0012] The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0013] A pixel circuit according to one feature of an embodiment includes a driving element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a light-emitting element connected to the second electrode of the driving element; a first capacitor disposed between the first node and a fourth node; a second capacitor disposed between the fourth node and the second node; a first switch element disposed between the first node and the third node; a second switch element disposed between the fourth node and a reference voltage supply line; and a third switch element disposed between the first node and an initialization voltage supply line.

[0014] The reference voltage applied to the reference voltage supply line may be greater than the initialization voltage applied to the initialization voltage supply line.

[0015] The first capacitor can be individually initialized with the reference voltage and the initialization voltage applied across its terminals.

[0016] The second capacitor can be individually initialized with the reference voltage and the pixel driving voltage applied across its terminals.

[0017] A fifth switch element connecting the initialization voltage supply line and the anode of the light-emitting element, and a first gate line connected to the third switch element and the fifth switch element may be included.

[0018] It may include a fourth switch element disposed between the fourth node and a data voltage supply line.

[0019] It may include a first gate line for applying a first gate voltage to the gate electrode of the third switch element, a second gate line for applying a second gate voltage to the gate electrode of the second switch element, a third gate line for applying a third gate voltage to the gate electrode of the first switch element, and a fourth gate line for applying a fourth gate voltage to the gate electrode of the fourth switch element.

[0020] The pixel circuit is driven in an initial period, a sampling period, a programming period, and an emission period. In the initial period, the second switch element, the third switch element, and the driving element are turned on, and the first switch element and the fourth switch element are turned off. In the sampling period, the first switch element and the second switch element are turned on, and the level of the fourth node is fixed to a reference voltage, and the level of the first node changes by a difference between an initialization voltage, a color pixel driving voltage, and a threshold voltage of the driving element. In the programming period, the fourth switch element is turned on, and the first to third switch elements are turned off, and the level of the first node changes by a difference between a pixel driving voltage and a threshold voltage of the driving element. In the emission period, the current flowing through the driving element may have no relation with a pixel driving voltage or a threshold voltage of the driving element.

[0021] The reference voltage may be larger than the data voltage supplied from the data voltage supply line, color.

[0022] The initialization voltage supply line may be electrically insulated from the second electrode of the driving element.

[0023] The pixel circuit is driven in an initial period, a sampling period, a programming period, and an emission period. In the initial period, the first capacitor is initialized by applying a reference voltage applied from a reference voltage supply line, color, and an initialization voltage applied from an initialization voltage supply line, color, to both ends of the first capacitor, respectively. In the sampling period, the threshold voltage of the driving element is sampled using the reference voltage and the pixel driving voltage. In the programming period, the data voltage may be applied to the pixel circuit and stored in the second capacitor.

Advantages of the Invention

[0024] According to the embodiment, it is possible to secure a sampling time longer than one horizontal period, and accurate sampling is possible even during high-speed driving. Therefore, there is an advantage that the driving characteristics between pixels are uniform even during high-speed driving.

[0025] In addition, since the pixel driving voltage and the initialization voltage are not short-circuited during initialization, damage applied to the pixel circuit is minimized, and low-power control becomes possible.

[0026] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0027] The accompanying drawings, which may be included to assist in a further understanding of the present invention and which can be incorporated into the present invention to form a part of the present invention, illustrate embodiments of the present invention and can serve to explain various principles of the present invention together with the description.

Brief Description of the Drawings

[0028]

Figure 1

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Figure 14

[0029] Advantages and features of the present invention, and methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but can be embodied in various different forms. The embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention. The present invention is only defined by the scope of the claims.

[0030] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary. The present invention is not limited to the illustrated matters. Throughout the specification, the same reference numerals indicate the same components. Further, when explaining the present invention, if it is determined that the specific description of related known technologies will obscure the gist of the present invention, the detailed description thereof will be omitted.

[0031] When terms such as "comprising", "including", "having", "being" mentioned in this specification are used, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it can be interpreted as plural unless there are special explicit descriptions.

[0032] When interpreting a component, even without a separate explicit description, it is interpreted as including an error range.

[0033] When the positional relationship and the mutual connection relationship are described between two components, such as "on", "above", "below", "sideways", "connect or couple", "crossing", "intersecting", etc., one or more other components can be interposed between those components unless there is a reference such as "immediately" or "directly".

[0034] When the temporal sequence is described, such as "after", "subsequent to", "next to", "before", etc., it may not be continuous on the time axis unless "immediately" or "directly" is used.

[0035] First, second, etc. may be used to distinguish components, but the functions and structures of these components are not limited by the ordinal numbers attached to the components or the names of the components.

[0036] The following embodiments can be partially or entirely combined or combined with each other, and various linkages and drives are technically possible. Each embodiment can be implemented independently of each other or can be implemented together with a correlation relationship.

[0037] In the display device of the present invention, the pixel circuit and the gate drive circuit may include a plurality of transistors. The transistor may be an Oxide TFT (Thin Film Transistor) including an oxide semiconductor, or an LTPS TFT including low temperature poly silicon (LTPS).

[0038] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. Inside the transistor, carriers flow out from the source. The drain is an electrode through which the transistor carriers exit to the outside. In the transistor, the flow of carriers is from the source to the drain. In the case of an n - channel transistor, since the carrier is an electron, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n - channel transistor, the direction of the current is from the drain to the source side. In the case of a p - channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain side in a p - channel transistor, the current flows from the source to the drain side. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first and second electrodes.

[0039] The gate signal can swing between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage VGH, and the gate-off voltage can be a gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage can be a gate low voltage VGL, and the gate-off voltage can be a gate high voltage VGH.

[0040] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0041] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1. FIG. 3 is a diagram schematically showing the display device.

[0042] Referring to FIGS. 1 to 3, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to the pixels of the display panel 100, and a power supply unit 140 that generates a power supply necessary for driving the pixels and the display panel driving circuit.

[0043] The display panel 100 can be color-formed with a plastic substrate, a thin glass substrate, a metal substrate, or the like. The pixel 101 is implemented on the display panel 100.

[0044] The display panel 100 may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but is not limited thereto. The display area AA of the display panel 100 includes a pixel array for displaying an input video. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may further include a power line commonly connected to the pixels 101. The power line is connected to a constant voltage node of the pixel circuit to supply a constant voltage required for driving the pixels 101 to the pixels 101.

[0045] Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for realizing a color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels includes a pixel circuit for driving a light-emitting element. Each of the pixel circuits is connected to a data line, a gate line, and a power line. Hereinafter, "pixel" may be interpreted as "sub-pixel".

[0046] The pixels may be arranged as real color pixels and pentile pixels. The pentile pixels can utilize a preset pixel rendering algorithm to drive two sub-pixels with different colors by one pixel 101 to realize a higher resolution than real color pixels. The pixel rendering algorithm can compensate for the lack of color representation in each pixel with the color of the light emitted from adjacent pixels.

[0047] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel line share the gate line 103. The sub-pixels arranged in the color column direction Y along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0048] The display panel 100 can be embodied as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device where an image is displayed on the screen and the real object in the background can be seen. The display panel 100 can be fabricated as a flexible display panel in color.

[0049] As shown in FIG. 2, the cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light-emitting element layer EMIL, and an encapsulation layer ENC laminated on a substrate SUBS.

[0050] The circuit layer CIR may include a TFT array including pixel circuits connected to wirings such as data lines, gate lines, and power lines, a demultiplexer array, a gate driver unit 120, etc. The circuit layer CIR includes a plurality of metal layers insulated with an insulating layer interposed therebetween and a semiconductor material layer.

[0051] The light-emitting element layer EMIL may include light-emitting elements driven by pixel circuits. The light-emitting elements may include light-emitting elements of red sub-pixels, light-emitting elements of green sub-pixels, and light-emitting elements of blue sub-pixels. The light-emitting element layer EMIL may further include light-emitting elements of white sub-pixels. In each of the sub-pixels, the light-emitting element layer EMIL may have a structure in which a light-emitting element and a color filter are laminated. The light-emitting element EL of the light-emitting element layer EMIL may be covered with a multiple protection layer including an organic film and an inorganic film.

[0052] The encapsulation layer ENC covers the light-emitting element layer EMIL so as to seal the circuit layer CIR and the light-emitting element layer EMIL. The encapsulation layer ENC may also have a structure of a multilayer insulating film in which an organic film and an inorganic film are alternately laminated. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are laminated in multiple layers, the migration path of moisture and oxygen becomes longer compared to a single layer, and the penetration of moisture and oxygen that affects the light-emitting element layer EMIL can be effectively blocked.

[0053] On the encapsulation layer ENC, a touch sensor layer (omitted in the drawing) may be formed, and a polarizing plate and a color filter layer may be disposed thereon. The touch sensor layer may include a capacitance-type touch sensor that senses touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film can insulate the intersecting portions of the metal wiring pattern and planarize the surface of the touch sensor layer. The polarizing plate can convert the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer, improving visibility and contrast ratio. The polarizing plate can be embodied as a polarizing plate in which a linear polarizing plate and a retardation film are joined or a circular polarizing plate. A cover glass may be adhered onto the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer can absorb a part of the wavelength of the light color-reflected by the circuit layer and the touch sensor layer, substituting for the role of the polarizing plate and enhancing the color purity of the video reproduced in the pixel array.

[0054] The power supply unit 140 uses a DC-DC converter to generate a constant voltage (or DC voltage, DC) required for driving the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 can adjust the level of the DC input voltage applied by the host system 200 and output constant voltages such as a gamma reference voltage, a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, and an initialization voltage. The gamma reference voltage is supplied to the data driving unit 110. The dynamic range of the data voltage output by the data driving unit 110 is determined according to the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest gradation voltage and the lowest gradation voltage.

[0055] The gate high voltage and the gate low voltage are supplied to the level shifter 150 and the gate driving unit 120. Constant voltages such as the pixel driving voltage, the cathode voltage, and the initialization voltage are supplied to the pixel 101 through a power supply line commonly connected to the pixel 101.

[0056] The pixel driving voltage can be output from the main power supply of the host system 200 and supplied to the display panel 100. In this case, the power supply unit 140 does not need to output the pixel driving voltage.

[0057] The display panel driving circuit writes pixel data of the input video to the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driving unit 110 and a gate driving unit 120.

[0058] The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensor. The touch sensor driving unit is omitted in FIG. 1. The data driving unit 110 and the touch sensor driving unit may be integrated into one node drive IC (Integrated Circuit). In a mobile terminal or a wearable terminal, the timing controller 130, the power supply unit 140, the level shifter 150, the data driving unit 110, the touch sensor driving unit, etc. may be integrated into one node drive IC (DIC) as shown in FIG. 3.

[0059] The data driving unit 110 receives the pixel data of the input video received as a timing controller 130 color digital signal and outputs a data voltage. The data driving unit 110 uses a DAC (Digital to Analog Converter) to convert the pixel data of the input video into a gamma compensation voltage and outputs a data voltage. The gamma reference voltage VGMA is divided into gradation-specific gamma compensation voltages through the voltage dividing circuit of the data driving unit 110 and provided to the DAC. The DAC generates a data voltage with a gamma compensation voltage corresponding to the gradation value of the pixel data. The data voltage output in color by the DAC is output to the data line 102 through each channel of the data driving unit 110 in color and an output buffer, or may be output to the data line 102 through a demultiplexer array.

[0060] The gate driving unit 120 may be formed on the circuit layer CIR on the display panel 100 together with the TFT array and wiring of the pixel array. The gate driving unit 120 may be disposed in the non-display area BZ outside the display area AA in the display panel 100, or at least a part thereof may be disposed in the display area AA.

[0061] The gate driving unit 120 may include a plurality of shift registers for sequentially shifting the pulses of the gate signal. The gate driving unit 120 is disposed on either the left non-display area BZ or the right non-display area BZ outside the display area AA in the display panel 100, and can supply the gate signal to the gate line 103 in a single feeding manner. In the single feeding method, the color gate signal at one end of the gate line 103 is applied. The gate driving unit 120 is disposed in the left non-display area BZ and the right non-display area BZ of the display panel 100, and can apply the gate signal to the gate line 103 by double feeding. In the double feeding method, the color gate signals at both ends of the gate line 103 are applied simultaneously. At least a part of the circuit of the gate driving unit 120 may be disposed within the display area AA.

[0062] The gate driving unit 120 sequentially outputs the pulses of the gate signal to the gate line under the control of the timing controller 130. The gate driving unit 120 can sequentially supply those signals to the gate line 103 by shifting the pulses of the gate signal using a shift register. The gate driving unit 120 can output a plurality of gate signals having different phases and pulse widths, etc. using a plurality of shift registers. The gate signal can be divided into a scan signal and a light emission control signal (hereinafter referred to as "EM signal").

[0063] The timing controller 130 receives the digital video data of the host system 200 color input video and the timing signal synchronized with the data. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of 1 horizontal period (1H).

[0064] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driving unit 110, a MUX control signal for controlling the operation timing of the demultiplexer array, and a gate timing control signal for controlling the operation timing of the gate driving unit 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 controls the operation timing of the display panel driving circuit to synchronize the data driving unit 110, the demultiplexer array, the touch sensor driving unit, and the gate driving unit 120.

[0065] The generated gate timing control signal of the timing controller 130 can be input to the shift register of the gate driving unit 120 through the level shifter 150. The level shifter 150 can generate a start pulse and a shift clock when the gate timing control signal is input, and provide them to the gate driving unit 120 through the clock line CLk. The level shifter 150 can supply the MUX control signal to the demultiplexer array. The input signal of the level shifter 150 is a signal with a digital signal voltage level, and the output signal of the level shifter 150 can be an analog voltage signal that swings between the gate high voltage VGH and the gate low voltage VGL.

[0066] The host system 200 may include a main board of any one of a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system can scale the video signal of the video source according to the resolution of the display panel 100 and transmit it to the timing controller 130 together with the timing signal.

[0067] In a mobile system, the host system 200 can be implemented by an AP (Application Processor). The host system 200 can transmit pixel data of input video to the drive IC (DIC) shown in FIG. 3 via MIPI (Mobile Industry Processor Interface). The host system 200 can be connected to the drive IC (DIC) through a flexible printed circuit, such as an FPC (Flexible Printed Circuit), as shown in FIG. 3. The drive IC can be adhered onto the display panel 100 in a COG (Chip on glass) process. The drive IC can be mounted on a flexible circuit film and electrically connected to the wiring on the display panel 100.

[0068] Each sub-pixel includes a drive element for driving a light-emitting element and a pixel circuit including a capacitor connected to the drive element. Each pixel circuit of each sub-pixel includes an internal compensation circuit and can compensate the data voltage by the threshold voltage of the drive element.

[0069] FIG. 4 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.

[0070] Referring to FIG. 4, the pixel circuit according to the embodiment includes a light-emitting element EL, a drive element DT for driving the light-emitting element EL, a plurality of switch elements T1 to T6, and capacitors C1 and C2. The drive element DT and the switch elements T1 to T6 can be implemented by transistors. The drive element DT and the switch elements T1 to T6 can all be p-channel transistors, but are not necessarily limited thereto.

[0071] The drive element DT generates a current for driving the light-emitting element EL according to the gate-source voltage Vgs. The drive element DT includes a gate electrode G connected to the first node n1, a first electrode S connected to the second node n2, and a second electrode D connected to the third node n3. The pixel drive voltage ELVDD is applied to the second node n2. The pixel drive voltage ELVDD is also referred to as a high-potential power supply voltage.

[0072] The light-emitting element EL can be implemented as an OLED or an inorganic LED. The OLED includes an anode electrode, a cathode electrode, and an organic compound layer interposed therebetween. The anode electrode of the light-emitting element EL is electrically connected to the fifth node n5, and a cathode voltage ELVSS is applied to the cathode electrode. The cathode voltage ELVSS is also referred to as a low-potential power supply voltage or a ground voltage.

[0073] The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode electrode and the cathode electrode of the light-emitting element EL, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light emission layer EML to form excitons. At this time, color visible light is emitted from the light emission layer EML. The OLED can be implemented as an OLED having a tandem structure in which a plurality of light emission layers are stacked. The tandem structure OLED can improve the luminance and lifespan of the pixel.

[0074] The first switch element T1 may have its first electrode connected to the first node n1 and its second electrode connected to the third node n3. The gate electrode of the first switch element T1 may be connected to a third gate line GL3 to which a third scan signal Scan3 is applied. One side (e.g., the first electrode) of the first switch element T1 is connected to the gate electrode of the driving element DT, and the other side (e.g., the second electrode) of the first switch element T1 may be connected to the second electrode of the driving element DT and the sixth switch element T6.

[0075] The first switch element T1 is turned on or off in response to the third scan signal Scan3 applied through the third gate line GL3, and can connect the first node n1 and the third node n3 when turned on.

[0076] The second switch element T2 may have its first electrode connected to the fourth node n4 and its second electrode connected to the reference voltage supply line PL4. The gate electrode of the second switch element T2 is connected to a second gate line GL2 that provides a second scan signal Scan2.

[0077] The second switch element T2 is turned on or off according to the second scan signal Scan2 supplied through the second gate line GL2, and can supply a reference voltage Vref to the fourth node n4 when turned on.

[0078] The third switch element T3 may have its first electrode connected to the first node n1 and its second electrode connected to the initialization voltage supply line PL3. The gate electrode of the third switch element T3 is connected to a first gate line GL1 that provides a first scan signal Scan1.

[0079] The third switch element T3 is turned on or off according to the first scan signal Scan1 supplied through the first gate line GL1, and can supply an initialization voltage Vinit to the first node n1 when turned on.

[0080] The fourth switch element T4 may have its first electrode connected to the data voltage supply line PL5 and its second electrode connected to the fourth node n4. The gate electrode of the fourth switch element T4 is connected to a fourth gate line GL4 that provides a fourth scan signal Scan4.

[0081] The fourth switch element T4 is turned on or off according to the fourth scan signal Scan4 supplied through the fourth gate line GL4, and can supply a data voltage Vdata to the fourth node n4 when turned on.

[0082] The fifth switch element T5 may have its first electrode connected to the initialization voltage supply line PL3 and its second electrode connected to the fifth node n5. The gate electrode of the fifth switch element T5 is connected to the first gate line GL1 that provides the first scan signal Scan1.

[0083] The fifth switch element T5 is turned on or off according to the first scan signal Scan1 supplied through the first gate line GL1, and can supply the initialization voltage Vinit to the anode electrode of the light emitting element EL when turned on.

[0084] The sixth switch element T6 may have its first electrode connected to the third node n3 and its second electrode connected to the fifth node n5. The gate electrode of the sixth switch element T6 is connected to the fifth gate line GL5. The sixth switch element T6 is turned on or off according to the signal EM(n) applied through the fifth gate line GL5, and can connect the third node n3 and the fifth node n5 when turned on.

[0085] The first capacitor C1 and the second capacitor C2 can keep the gate-source voltage Vgs of the driving element DT constant during one frame. The first capacitor C1 can store the threshold voltage Vth of the driving element DT, and the second capacitor C2 can store the data voltage Vdata.

[0086] The first terminal of the first capacitor C1 may be connected to the first node n1 and the second terminal may be connected to the fourth node n4. The first terminal of the first capacitor C1 may be connected to the gate electrode of the driving element DT, the first electrode of the first switch element T1, and the first electrode of the third switch element T3.

[0087] The first terminal of the second capacitor C2 can be connected to the fourth node n4, and the second terminal can be connected to the second node n2. The fourth node n4 is disposed between the first capacitor C1 and the second capacitor C2, and can be connected to the second switch element T2 and the fourth switch element T4. The other side of the second capacitor C2 (e.g., the second terminal of the second capacitor) can be connected to the drive voltage supply line PL1.

[0088] The first capacitor C1 and the second capacitor C2 can be configured as parasitic capacitors of an internal capacitor (Internal Capacitor), but are not limited thereto, and can be external capacitors (External Capacitor) intentionally designed outside the drive element DT.

[0089] Figures 5a to 9b are diagrams showing the operation of the pixel circuit.

[0090] The refresh frame may include an initial period INI, a sampling period SAM, a programming period PRO, and an emission period EMI. The initial period INI is a period for initializing the capacitor and the gate electrode of the drive element DT, the sampling period SAM is a period for sensing the threshold voltage of the drive element DT, the programming period PRO is a period for storing the data voltage Vdata, and the emission period EMI is a period when the light emitting element EL is turned on.

[0091] Referring to FIGS. 5a and 5b, in the initial period INI, the first scan signal Scan1 and the second scan signal Scan2 output by the first gate line GL1 and the second gate line GL2 are the gate-on voltages VGL and VEL, and the scan signals output by the third gate line GL3, the fourth gate line GL4, and the fifth gate line GL5 can be the gate-off voltages VGH and VEH. Since the drive element DT and the plurality of switch elements T1 to T6 according to the embodiment are P-channel transistors, they can be turned off when a high gate voltage is applied and turned on when a low gate voltage is applied.

[0092] Specifically, the third switch element T3 can be turned on by the gate-on voltages VGL and VEL output from the first gate line GL1, and the initialization voltage Vinit can be applied to the first node n1. Therefore, the initialization voltage Vinit can be applied to one end of the first capacitor C1 connected to the first node n1 and the gate electrode G of the drive element DT.

[0093] The initialization voltage Vinit can be a sufficiently low voltage so as to saturate the drive element DT. Therefore, when the initialization voltage Vinit is applied to the gate electrode G of the drive element DT, the drive element DT can be turned on in advance before the sampling period, and a channel between the source and drain can be formed. Therefore, the pixel drive voltage ELVDD can be applied to the third node n3. Therefore, when sampling starts, the voltage applied to the third node n3 can be quickly applied to the gate electrode of the drive element DT, and the threshold voltage can be sampled quickly.

[0094] In the initial period INI, the fifth switch element T5 connected to the first gate line GL1 can be turned on, and the initialization voltage Vinit can be applied to the fifth node n5. The initialization voltage Vinit can be set to a sufficiently low voltage so that the light-emitting element EL does not emit light during the initial period INI.

[0095] Exemplarily, when the pixel drive voltage ELVDD is set to 4.6V and the cathode voltage ELVSS is set to -6.0V, the initialization voltage Vinit can be set to -3.5V in order to make the drive element DT fully in the saturation region during initialization. However, this is exemplary and can be appropriately adjusted according to the characteristics of each element and the pixel circuit.

[0096] According to the embodiment, when an initialization voltage Vinit is applied to the first node n1, no short circuit occurs between the pixel driving voltage ELVDD applied to the second electrode D of the driving element DT. Therefore, since the voltage Vgs between the gate and the source of the driving element becomes exactly Vinit - ELVDD, the on bias voltage increases, and the OBS effect can be improved. OBS (on bias stress) is an abbreviation for on bias stress, and refers to an operation of applying stress to a transistor in order to prevent or reduce fluctuations in the threshold voltage of the transistor.

[0097] When the gradation value of the pixel data changes significantly, the response time can be lengthened during the first frame period when the input video starts to be reproduced, depending on the time required for the hysteresis characteristic of the driving element DT to change. As a result, the FFR (First Frame Response) can deteriorate. However, according to the embodiment, in the initial period INI, the hysteresis of the driving element DT is relaxed by a high OBS voltage, so the FFR can be improved.

[0098] Since a gate-on voltage is applied to the second gate line GL2, the second switch element T2 is driven, and a reference voltage Vref can be applied to the fourth node n4. Therefore, the first capacitor C1 can be initialized with Vinit - Vref, and the second capacitor C2 can be initialized with Vref - ELVDD.

[0099] In the emission period EMI, in order to apply a current to the light emitting element EL, the driving element DT needs to be in the saturation stage. In order for the driving element DT to be saturated, the voltage Vsg between the source and the gate needs to be greater than the threshold voltage Vth. That is, it is required that the reference voltage Vref be greater than the data voltage Vdata (see the following relational expression 1). When a negative voltage such as the initialization voltage Vinit is used as the reference voltage Vref, the driving element DT may not be saturated.

[0100] The reference voltage Vref can be set to a predetermined voltage level in order to serve the role of fixing the fourth node n4 so that it is not affected by the previous data voltage during the initial period, and also to serve the role of maintaining the voltage of the fourth node n4 constant regardless of the change in the gate voltage of the driving element DT due to diode connection during the sampling period. The initialization voltage Vinit can be set low so that the driving element is sufficiently saturated during initialization. Therefore, since the reference voltage Vref and the initialization voltage Vinit have different roles, they can have different voltage levels.

[0101] Exemplarily, the reference voltage Vref can be set to 2V or more so that the data voltage Vdata has a range of 0V (White) to 2V (Black). However, the range of each voltage is not necessarily limited to this and can be variously deformed. The reference voltage Vref can be appropriately determined within a range that is greater than the initialization voltage Vinit and the data voltage Vdata and smaller than the pixel driving voltage ELVDD.

[0102] Referring to FIGS. 6a and 6b, during the sampling period SAM, the gate high voltages VGH and VEH are applied to the first gate line GL1, the fourth gate line GL4, and the fifth gate line GL5, and the gate on voltages VGL and VEL can be applied to the second gate line GL2 and the third gate line GL3.

[0103] Therefore, when the first switch element T1 is turned on by the gate on voltages VGL and VEL applied to the third gate line GL3, the voltage charged in the third node n3 is charged to the first node n1.

[0104] The gate-on voltages VGL and VEL applied to the second gate line GL2 turn on the second switching element T2 in the sampling stage, allowing the reference voltage Vref to be applied to the fourth node n4. Therefore, even if the voltage of the gate electrode of the driving element DT changes from the initialization voltage Vinit to ELVDD-Vth while changing from the initial period INI to the color sampling period SAM, the voltage of the fourth node n4 can be maintained constant.

[0105] In the sampling period SAM, ELVDD - |Vth| can be applied to the first node n1 connected to one end of the first capacitor C1, and the reference voltage Vref can be applied to the fourth node n4 connected to the other end. Therefore, the voltage charged in the first capacitor C1 can be the difference between ELVDD - Vth and Vref. For example, the voltage charged in the first capacitor C1 can be Vref - (ELVDD - Vth).

[0106] The reference voltage Vref can be applied to the fourth node n4 to which one end of the second capacitor C2 is connected, and the pixel driving voltage ELVDD can be applied to the other end. The voltage charged in the second capacitor C2 can be the difference between ELVDD and Vref. For example, the voltage charged in the second capacitor C2 can be ELVDD - Vref. Therefore, when the voltages stored in the first capacitor C1 and the second capacitor C2 are combined, the pixel driving voltage ELVDD and the reference voltage Vref may be canceled out, leaving only the threshold voltage Vth. In the sampling period SAM, the threshold voltage Vth of the driving element DT can be stored in the first capacitor C1.

[0107] According to the embodiment, since sampling is performed using the reference voltage Vref instead of the data voltage Vdata, the sampling period SAM can be set longer or shorter than one horizontal period (1H). Therefore, it is possible to secure sufficient sampling time without the constraint of one horizontal period even during high-speed driving, and there is an advantage that the threshold voltage can be accurately sensed. Referring to FIG. 7, by controlling the second scan signal Scan2 and the third scan signal Scan3, the sampling time can be set longer than one horizontal period (1H).

[0108] Also, since the threshold voltage is sensed using the pixel driving voltage ELVDD, the voltage of the gate electrode is quickly charged by the driving element DT that has already been saturated in the initial period INI, so the sampling time can be shortened. Therefore, sampling can be performed quickly, which can be advantageous for high-speed driving. In this case, the sampling time can also be set shorter than one horizontal period.

[0109] Referring to FIGS. 8A and 8B, in the programming period PRO, gate high voltages VGH and VEH are applied to the first to third gate lines GL1 to GL3 and the fifth gate line GL5, and gate on voltages VGL and VEL can be applied to the fourth gate line GL4. Therefore, only the fourth switch element T4 to which the fourth scan signal Scan4 is applied is turned on, and the data voltage Vdata can be applied to the fourth node n4.

[0110] At this time, since the first switch element T1 is turned off, the first node n1 is floated, and thus, by capacitive coupling, the voltage of the first node n1 can be (Vdata - Vref + ELVDD - Vth).

[0111] The first capacitor C1 can be charged with a voltage corresponding to the difference between Vdata - Vref + ELVDD - Vth and Vdata. For example, the voltage charged in the first capacitor C1 can be Vdata - (Vdata - Vref + ELVDD - Vth).

[0112] The second capacitor C2 can be charged with a voltage corresponding to the difference between Vdata and ELVDD. For example, the voltage charged to the second capacitor C2 can be ELVDD - Vdata. Therefore, when the voltages stored in the first capacitor C1 and the second capacitor C2 are combined, the pixel driving voltage ELVDD is erased, and Vref - Vdata + Vth may remain. During the programming period PRO, the data voltage Vdata can be charged to the second capacitor C2. The voltages stored in the first capacitor C1 and the second capacitor C2 can be the source-gate voltage Vsg.

[0113] At this time, since the first capacitor C1 and the second capacitor C2 are connected in parallel, the data voltage Vdata is not distributed. Therefore, the data voltage Vdata can be applied to both ends of the first capacitor C1 and the second capacitor C2, respectively. If the first capacitor C1 and the second capacitor C2 are connected in series and the data voltage is distributed, a wider range of the data voltage has to be used, the distribution ratio is affected by the capacitance size, and there is a problem that accurate control becomes difficult.

[0114] Referring to FIGS. 9a and 9b, during the emission period EMI, the gate full voltages VGH and VEH are applied to all of the first to fourth gate lines GL1 to GL4, and the gate on voltages VGL and VEL can be applied to only the fifth gate line. Therefore, the remaining switch elements except for the sixth switch element T6 can be turned off.

[0115] At this time, the current I flowing through the light emitting element EL OLED , the source-gate voltage Vsg of the driving element, and the threshold voltage Vth of the driving element can satisfy the following relational expression 1.

[0116] [Relational Expression 1] I OLED = k(Vsg - |Vth|) 2 =k{ELVDD - (Vdata - Vref + ELVDD - |Vth|) - |Vth|} 2 =k(Vref - Vdata) 2

[0117] Therefore, the current flowing through the light-emitting element EL is determined by the difference between the reference voltage Vref and the data voltage Vdata, and it becomes such that it has no influence on the threshold voltage of the driving element DT, and the driving elements DT of each pixel can have uniform characteristics. Also, the influence of the pixel driving voltage ELVDD is removed, and the influence of the IR drop (voltage drop) can also be reduced.

[0118] Also, during the emission period EMI, even if the pixel driving voltage ELVDD fluctuates, the gate voltage of the driving element DT can also be changed by α. Therefore, as the pixel driving voltage ELVDD changes by α, the gate voltage of the driving element DT can also change by α.

[0119] Substituting this into the above relational expression 1, we get k{(ELVDD + α) - (Vdata - Vref + ELVDD - |Vth| + α) - |Vth|} 2 and thus it can be seen that the expression of k(Vref - Vdata) 2 also holds. Therefore, it is possible to prevent or reduce the change in luminance due to the IR drop of the pixel driving voltage ELVDD.

[0120] In FIGS. 4 to 9B, the specific structure and detailed operation of the pixel circuit are shown, but it should be noted that the present invention is not limited thereto. For example, the pixel circuit of the present invention may include more or fewer transistors or capacitors, and the gate signal can be variously changed by those skilled in the art as needed.

[0121] FIG. 10 is a diagram schematically showing a pixel circuit according to the first embodiment of the present invention.

[0122] Referring to FIG. 10, the pixel circuit according to the first embodiment can include a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements T1 to T4, and capacitors C1 and C2.

[0123] In the initialization stage, the second switching element T2 and the third switching element T3 can be turned on, and a reference voltage Vref and an initialization voltage Vinit can be applied to both ends of the first capacitor C1, respectively. At this time, the initialization voltage Vinit can be applied to the gate electrode of the driving element DT, and the driving element DT can be saturated.

[0124] Thereafter, in the sampling stage, the reference voltage Vref is applied to the fourth node n4, the first switching element T1 is turned on, and the voltage of the first node n1 can become ELVDD - Vth. Therefore, the threshold voltage Vth of the driving element DT can be stored in the first capacitor C1.

[0125] Thereafter, in the programming stage, when the fourth switching element T4 is turned on and the data voltage Vdata is applied to the first node n1, due to capacitive coupling, the voltage of the fourth node n4 can become Vdata - Vref + ELVDD - |Vth|. At this time, the data voltage Vdata can be stored in the second capacitor C2.

[0126] Therefore, in the emission stage, a current can flow through the light-emitting element EL in proportion to Vref - Vdata without being affected by the threshold voltage of the driving element.

[0127] According to the embodiment, there is a feature of initializing a capacitor by using a reference voltage Vref and an initialization voltage Vinit which are different voltages from each other. It is advantageous that the initialization voltage Vinit is set low so as to quickly saturate the driving element and increase the OBS effect. The reference voltage Vref is required to be larger than the data voltage Vdata in order to satisfy the condition for saturating the driving element. That is, in order for the driving element to be saturated, the source-gate voltage Vsg must be larger than the threshold voltage Vth. Therefore, according to Equation 1, the reference voltage Vref is required to be larger than the data voltage Vdata.

[0128] FIG. 11 is a diagram showing an example of a pixel circuit that samples using a data voltage. FIG. 12 is a waveform diagram of the circuit of FIG. 11.

[0129] Referring to FIGS. 11 and 12, in the 6T1C pixel circuit, during the initial period INI, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be turned on by applying the gate-on voltages VGL and VEL.

[0130] The reference voltage Vref can be applied to the A node and the B node at both ends of the capacitor Cst, respectively. Therefore, the capacitor Cst can be initialized with the same reference voltage Vref applied to both ends. At this time, the reference voltage Vref can be applied to the B node through the third transistor M3, the fourth transistor M4, and the first transistor M1.

[0131] In the case of an initialization voltage where the reference voltage Vref is sufficiently low, the driving element DT may be saturated and the source-drain channel may be opened. Therefore, there is a problem that the reference voltage Vref and the pixel driving voltage ELVDD are short-circuited at the C node, and continuous damage occurs to the pixel circuit. However, according to the embodiment, since the initialization voltage does not pass through the node to which the driving element node drain electrode is connected, a short circuit between the initialization voltage and the pixel driving voltage can be prevented.

[0132] Also, in the 6T1C pixel circuit, during the sampling period SAM, the fifth transistor M5 is turned on, and the data voltage Vdata is applied to the A node. Also, the first transistor M1 is turned on, and the voltage of the B node can be ELVDD - Vth.

[0133] At this time, since the input and sampling of the data voltage Vdata are driven simultaneously, the sampling period SAM is limited to one horizontal period (1H) during which the data voltage Vdata is applied. Therefore, during high-speed driving, one horizontal period becomes short, and it is impossible to secure sufficient sampling time. As a result, it is difficult to accurately sense the threshold voltage.

[0134] However, according to the embodiment, since sampling is performed using the reference voltage Vref instead of the data voltage Vdata, there is an advantage that sufficient sampling time can be secured without being restricted by one horizontal period.

[0135] FIG. 13 is a diagram showing a pixel circuit according to another embodiment of the present invention. FIG. 14 is a waveform diagram of the pixel circuit.

[0136] The pixel circuit according to the embodiment includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switch elements, and a capacitor. The driving element DT and the switch elements can be implemented by transistors. The driving element DT and the switch elements can all be p-channel transistors, but are not necessarily limited thereto.

[0137] The driving element DT generates a current for driving the light-emitting element EL according to the voltage between the gate and the source. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The pixel driving voltage ELVDD is applied to the second node n2.

[0138] According to an embodiment, a first scan signal Scan1(N+1) of a (N+1)-th line may be applied to a third gate line GL3, and a first scan signal Scan1(N+2) of a (N+2)-th line may be applied to a fourth gate line GL4. According to such a configuration, the number of sub-stages for outputting a scan signal to one pixel can be reduced, and the size of the gate driving unit can be reduced.

[0139] In this case, in order to sufficiently secure a sampling time at the N-th line, when the width of the first scan signal Scan1(N+1) of the (N+1)-th line is changed, the initial period INI of the (N+1)-th pixel may also be changed to the same period. That is, the initial time and the sampling time may be the same and adjusted to be longer or shorter than one horizontal period.

[0140] A first switch element T1 may have a first electrode connected to a first node n1 and a second electrode connected to a third node n3. A gate electrode of the first switch element T1 may be connected to a third gate line GL3 that applies the first scan signal Scan1(N+1) of the (N+1)-th line. One side of the first switch element T1 may be connected to a gate electrode of a driving element DT, and the other side of the first switch element T1 may be connected to a second electrode of the driving element DT and a sixth switch element T6.

[0141] The first switch element T1 is turned on or off according to the first scan signal Scan1(N+1) of the (N+1)-th line applied through the third gate line GL3, and can connect between the first node n1 and the third node n3 when turned on.

[0142] A second switch element T2 may have a first electrode connected to a fourth node n4 and a second electrode connected to a reference voltage supply line PL4. A gate electrode of the second switch element T2 is connected to a second gate line GL2 that provides the second scan signal Scan2(N).

[0143] The second switch element T2 is turned on or off according to the second scan signal Scan2(N) supplied through the second gate line GL2, and can supply the reference voltage Vref to the fourth node n4 when it is turned on.

[0144] The first electrode of the third switch element T3 can be connected to the first node n1, and the second electrode can be connected to the initialization voltage supply line PL3. The gate electrode of the third switch element T3 is connected to the first gate line GL1 that provides the first scan signal Scan1(N).

[0145] The third switch element T3 is turned on or off according to the first scan signal Scan1(N) supplied through the first gate line GL1, and can supply the initialization voltage Vinit to the first node n1 when it is turned on.

[0146] The first electrode of the fourth switch element T4 can be connected to the data voltage supply line PL5, and the second electrode can be connected to the fourth node n4. The gate electrode of the fourth switch element T4 is connected to the fourth gate line GL4 that provides the first scan signal Scan1(N + 2) of the N + 2 line.

[0147] The fourth switch element T4 is turned on or off according to the first scan signal Scan1(N + 2) of the N + 2 line supplied through the fourth gate line GL4, and can supply the data voltage Vdata to the fourth node n4 when it is turned on.

[0148] The first electrode of the fifth switch element T5 can be connected to the initialization voltage supply line PL3, and the second electrode can be connected to the fifth node n5. The gate electrode of the fifth switch element T5 is connected to the first gate line GL1 that provides the first scan signal Scan1(N).

[0149] The fifth switch element T5 is turned on or off according to the first scan signal Scan1(N) supplied through the first gate line GL1, and can supply the initialization voltage Vinit to the anode electrode of the light-emitting element EL when turned on.

[0150] The sixth switch element T6 may have its first electrode connected to the third node n3 and its second electrode connected to the fifth node n5. The gate electrode of the sixth switch element T6 is connected to the fifth gate line GL5. The sixth switch element T6 is turned on or off according to the signal EN(n) applied through the fifth gate line GL5, and can connect the third node n3 and the fifth node n5 when turned on.

[0151] The first capacitor C1 and the second capacitor C2 can keep the gate-source voltage Vgs of the driving element DT constant during one frame. The first capacitor C1 can store the threshold voltage Vth of the driving element DT, and the second capacitor C2 can store the data voltage Vdata.

[0152] The first terminal of the first capacitor C1 may be connected to the first node n1, and the second terminal may be connected to the fourth node n4. The first terminal of the first capacitor C1 may be connected to the gate electrode of the driving element DT, the first electrode of the first switch element T1, and the first electrode of the third switch element T3.

[0153] The first terminal of the second capacitor C2 is connected to the fourth node n4, and the second terminal may be connected to the second node n2. The fourth node n4 is disposed between the first capacitor C1 and the second capacitor C2 and may be connected to the second switch element T2 and the fourth switch element T4. The other side of the second capacitor C2 may be connected to the driving voltage supply line PL1.

[0154] Since the content of the specification describing the problems to be solved, the means for solving the problems, and the effects does not specify the essential features of the claims, the scope of the claims is not limited by the matters described in the content of the specification.

[0155] The embodiments of the present invention have been described in more detail above with reference to the accompanying drawings. However, the present invention is not necessarily limited to such embodiments, and can be implemented in various modifications without departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the present invention are not for limiting the technical idea of the present invention, but for explaining it, and the scope of the technical idea of the present invention is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. The protection scope of the present invention should be interpreted by the scope of the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

Description of Reference Numerals

[0156] 100: Display panel 102, DL: Data line 103, GL1~GL5: Gate line 110: Data driving unit 120: Gate driving unit 130: Timing controller DT: Driving element EL: Light emitting element T1~T7: Switching element

Claims

1. A driving element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A light-emitting element connected to the second electrode of the driving element; A first capacitor disposed between the first node and a fourth node; A second capacitor disposed between the fourth node and the second node; A first switch element disposed between the first node and the third node; A second switch element disposed between the fourth node and a reference voltage supply line; A pixel circuit including a third switch element disposed between the first node and an initialization voltage supply line.

2. The pixel circuit according to claim 1, wherein a reference voltage applied to the reference voltage supply line is greater than an initialization voltage applied to the initialization voltage supply line.

3. The pixel circuit according to claim 2, wherein the first capacitor is initialized by applying the reference voltage and the initialization voltage to both ends thereof, respectively.

4. The pixel circuit according to claim 3, wherein the second capacitor is initialized by applying the reference voltage and a pixel driving voltage to both ends thereof, respectively.

5. A fifth switch element connecting the initialization voltage supply line and an anode of the light-emitting element; The pixel circuit according to claim 1, further including a first gate line connected to gate electrodes of the third switch element and the fifth switch element.

6. The pixel circuit according to claim 2, further including a fourth switch element disposed between the fourth node and a data voltage supply line.

7. A first gate line for applying a first gate voltage to a gate electrode of the third switch element; A second gate line for applying a second gate voltage to a gate electrode of the second switch element; A third gate line for applying a third gate voltage to a gate electrode of the first switch element; The pixel circuit according to claim 6, further including a fourth gate line for applying a fourth gate voltage to a gate electrode of the fourth switch element.

8. The pixel circuit is driven in an initial period, a sampling period, a programming period, and an emission period. In the initial period, the second switch element, the third switch element, and the driving element are turned on, and the first switch element and the fourth switch element are turned off. During the sampling period, the first switching element and the second switching element are turned on, the level of the fourth node is fixed to the reference voltage, and the level of the first node changes by the difference between the initialization voltage color pixel driving voltage and the threshold voltage of the driving element. During the programming period, the fourth switching element is turned on, the first to third switching elements are turned off, and the level of the first node changes by the difference between the pixel driving voltage and the threshold voltage of the driving element. The pixel circuit according to claim 6, wherein in the emission period, the current flowing through the driving element has no relation with the pixel driving voltage or the threshold voltage of the driving element.

9. The pixel circuit according to claim 6, wherein the reference voltage is larger than the data voltage supplied to the data voltage supply line color.

10. The pixel circuit according to claim 6, wherein the driving element and the first to fourth switching elements are P-channel transistors.

11. The pixel circuit according to claim 1, wherein the initialization voltage supply line is electrically insulated from the second electrode color of the driving element.

12. A data driving circuit; A gate driving circuit; A display device including the pixel circuit according to any one of claims 3, 6, 7, 9, and 10.

13. The pixel circuit is driven in an initial period, a sampling period, a programming period, and an emission period. In the initial period, the first capacitor is initialized by applying the reference voltage applied to the reference voltage supply line color and the initialization voltage applied to the initialization voltage supply line color to both ends of the first capacitor, respectively. In the sampling period, the threshold voltage of the driving element is sampled using the reference voltage and the pixel driving voltage. The display device according to claim 12, wherein in the programming period, a data voltage is applied to the pixel circuit and stored in the second capacitor.

14. The display device according to claim 13, wherein the sampling period is longer or shorter than one horizontal period.

15. The display device according to claim 13, wherein the initial period and the sampling period have the same length, and the initial period and the sampling period are adjusted identically.

Images